JP2004194124A - Hysteresis comparator circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To create a hysteresis comparator circuit capable of adjusting a hysteresis width of high precision without being affected by a power source voltage and requiring a large resistance ratio. <P>SOLUTION: By serially connecting a circuitry consisting of resistors 13 and 14 and switches 5 and 6 for short-circuiting both ends of the resistors to each circuit of a differential pair and controlling them on the basis of comparator output signals Vp and Vo, the hysteresis width is adjusted. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【００８８】
ＮＭＯＳＦＥＴ６１のＶ_ｇｓをＶ_ｇｓ１とおき、ＮＭＯＳＦＥＴ７１のＶ_ｇｓをＶ_ｇｓ２とおくと、ＮＭＯＳＦＥＴ６１，ＮＭＯＳＦＥＴ７１に電流Ｉが流れたときは、
【００８９】
【数２】

【００９０】
今Ｉ_１＝Ｉ_２＝Ｉより
【００９１】
【数３】

【００９２】
上式より
【００９３】
【数４】

【００９４】
よって、入力電圧差は
【００９５】
【数５】

【００９６】
従って、ヒステリシス幅は、差動対１１０の構成は左右対称なので、
【００９７】
【数６】

【００９８】
となる。
【００９９】
図７は、上記計算により求めた、ヒステリシス特性を示すものである。
従って、ヒステリシス幅は、電源電圧の影響を受けることなく、ＭＯＳサイズを可変にすることによって、ヒステリシス幅も可変にすることができる。
【０１００】
（数値例）
ここで、数値例を挙げて説明する。
図５の回路に示すように、ＮＭＯＳＦＥＴを並列接続した場合は、ＮＭＯＳＦＥＴ１，ＮＭＯＳＦＥＴ２，ＮＭＯＳＦＥＴ６１，ＮＭＯＳＦＥＴ７１のＷ／Ｌを１６０μ／１．２μ、電流Ｉを８００μＡに設定したものとする。
【０１０１】
出力信号の電位ＶｏがＬｏｗ→Ｈｉｇｈになるとき（スイッチ６２はＯＮ、スイッチ７２はＯＦＦ）、ＮＭＯＳＦＥＴ２に４００μＡが流れたとき、Ｖ_ｇｓ２＝６７５ｍＶ、ＭＯＳ１，２，３，４のＶ_ｔｂ＝５００ｍＶとすると、スイッチ６２がＯＮのため電位Ｖａをゲート入力とするＭＯＳはＮＭＯＳＦＥＴ１とＮＭＯＳＦＥＴ６１になり、電位Ｖｂをゲート入力とするＮＭＯＳＦＥＴ２よりもゲート幅（Ｗ）は２倍になる。ゲート長（Ｌ）は同じである。
【０１０２】
従って、ヒステリシス幅は、
【０１０３】
【数７】

【０１０４】
となる。
【０１０５】
［第４の例］
次に、本発明の第４の実施の形態を、図８に基づいて説明する。なお、前述した各例と同一部分についてはその説明を省略し、同一符号を付す。
【０１０６】
本例は、前述した第３の例の変形例であり、第１および第２の電位差可変手段をＭＯＳトランジスタにより構成し、該可変手段を差動対１１０の各回路に対して直列に接続して構成した場合の例である。なお、その他の回路構成は、図６と同様である。
【０１０７】
＜構成＞
本回路の構成について説明する。
第１の電位差可変手段は、ＮＭＯＳＦＥＴ８１と、スイッチ８２（ＭＯＳトランジスタ等からなる）とが並列接続された回路８０から構成される。この回路８０は、差動対１１０の一方の回路を構成するＮＭＯＳＦＥＴ１のソースＳ側で直列に接続されている。ここで、ＮＭＯＳＦＥＴ８１は、差動対１１０を構成するＮＭＯＳＦＥＴ１の一部でもある。
【０１０８】
第２の電位差可変手段は、ＮＭＯＳＦＥＴ９１と、スイッチ９２（ＭＯＳトランジスタ等からなる）とが直列接続された回路９０から構成される。この回路９０は、差動対１１０の他方の回路を構成するＮＭＯＳＦＥＴ２のソースＳ側で直列に接続されている。ここで、ＮＭＯＳＦＥＴ９１は、差動対１１０を構成するＮＭＯＳＦＥＴ２の一部でもある。
【０１０９】
つまり、差動対１１０は、４つのＮＭＯＳトランジスタ１，２，８１，９１を有している。ＮＭＯＳＦＥＴ１とＮＭＯＳＦＥＴ８１とは直列に接続され、差動対１１０の一方の入力端子１１１は共通接続されたＮＭＯＳＦＥＴ１，８１のゲートと接続されている。ＮＭＯＳＦＥＴ２とＮＭＯＳＦＥＴ９１とは直列に接続され、差動対１１０の他方の入力端子１１２は共通接続されたＮＭＯＳＦＥＴ２，９２のゲートとなっている。
【０１１０】
差動対１１０に所定の電流を供給する電流源３００を構成するＮＭＯＳＦＥＴ８は、ＮＭＯＳＦＥＴ８１，９１の各ソースに共通接続点２０（共通電位Ｖｍ）を介して接続されている。
【０１１１】
スイッチ８２は、ＮＭＯＳＦＥＴ８１のソースＳとドレインＤとを短絡するように並列に接続されている。スイッチ９２は、ＮＭＯＳＦＥＴ９１のソースＳとドレインＤとを短絡するように並列に接続されている。
【０１１２】
＜動作＞
回路動作について説明する。
スイッチ８２，９２は、出力段２００から出力される出力値に応じてオン又はオフする。すなわち、スイッチ８２はインバータ１１の出力値である電位Ｖｐに応じて、スイッチ９２はインバータ１２の出力値である電位Ｖｏに応じてそれぞれオン、オフされる。
【０１１３】
この場合、スイッチ８２がオンのとき、スイッチ９２はオフとなる。スイッチ８２がオフのとき、スイッチ９２はオンとなる。
ヒステリシス幅の調整は、前述した第３の例と同様にして行うことができる。
【０１１４】
（比較例）
以上説明した第１の例〜第４の例を参考にして、実際にヒステリシスコンパレータ回路を作成した例を、従来回路と比較して説明する。
【０１１５】
図９は、従来のヒステリシスコンパレータ回路４００と、本願発明のヒステリシスコンパレータ回路４０１〜４０３との比較例を示す。
【０１１６】
比較条件は、回路素子はＭＯＳトランジスタとし、また、製造プロセスが０．５μｍダブルポリダブルメタルプロセス、電源電圧が５Ｖ、ヒステリシス幅が２０ｍＶとした。
【０１１７】
比較対象の要素は、差動対サイズ４１０、スイッチサイズ４２０、該スイッチに接続された付随ＭＯＳサイズ４３０、抵抗サイズ４４０、レイアウト面積４５０、面積比４６０とした。Ｗはチャネル幅、Ｌはチャネル長である。
【０１１８】
例えば、スイッチサイズ４２０は、図１ではＮＭＯＳＦＥＴ５，６、図５ではＮＭＯＳＦＥＴ６２，７２、図８ではＮＭＯＳＦＥＴ８２，９２である。付随ＭＯＳサイズ４３０は、図５ではＮＭＯＳＦＥＴ６１，７１、図８ではＮＭＯＳＦＥＴ８１，９１である。面積比４６０は、レイアウト面積４５０の従来回路４００の値１００００を１００％として規格化した値である。
【０１１９】
そして、図９からわかるように、ヒステリシス幅を全て同一として構成した場合、面積比４６０は、従来のヒステリシスコンパレータ回路４００に比べて本願発明のヒステリシスコンパレータ回路４０１〜４０３をいずれも１／２以下に設定することができ、レイアウト面積４５０を半減することができ、これにより、小型で安価な回路を作成することができる。
【０１２０】
特に、本願発明４０２（図５の第３の例）、および、本願発明の（図８の第４の例）では、抵抗器を用いずに、ＭＯＳトランジスタのみによって、スイッチ機能、すなわち、第１の電位差可変手段６０，８０および第２の電位差可変手段７０，９０を構成しているので、製造プロセスのばらつきを一段と削減することが可能となり、ひいては、ヒステリシス幅のばらつきを抑えて高精度な回路を作成することができる。
【０１２１】
【発明の効果】
以上説明したように、本発明によれば、出力段のコンパレータ出力信号に基づいて差動対の各電位差が変化するスイッチ機能を有し、かつ、差動対を構成する各回路に対して直列又は並列に接続された電位差可変手段を設けたので、例えば、該電位差可変手段を抵抗器と該抵抗器の両端を短絡するスイッチとから構成して、該可変手段を差動対の各回路に対して直列に接続してコンパレータ出力信号に基づいて制御したり、或いは、電位差可変手段を差動対の一部でもあるＭＯＳトランジスタと該ＭＯＳトランジスタの両端を短絡するスイッチとから構成して、該可変手段を差動対の各回路に対して並列又は直列に接続してコンパレータ出力信号に基づいて制御することが可能となり、これにより、電源電圧や環境温度に影響を受けることなく、大きな抵抗比を必要とせずに、広範囲に渡り高精度なヒステリシス幅の調整を行うことができる。
【０１２２】
また、本発明によれば、従来回路に比べてレイアウト面積を半減することができるので、製造プロセスのばらつきを大幅に削減することができ、これにより、ヒステリシス幅のばらつきを抑えると共に、小型で安価なヒステリシスコンパレータ回路を作成することができる。
【図面の簡単な説明】
【図１】本発明の第１の実施の形態である、ヒステリシスコンパレータ回路の構成を示す回路図である。
【図２】ヒステリシス特性を示す特性図である。
【図３】電流源の構成を示す回路図である。
【図４】本発明の第２の実施の形態である、ヒステリシスコンパレータ回路の構成を示す回路図である。
【図５】本発明の第３の実施の形態である、ヒステリシスコンパレータ回路の構成を示す回路図である。
【図６】ヒステリシス幅の調整方法を説明するための回路図である。
【図７】ヒステリシス特性を示す特性図である。
【図８】本発明の第４の実施の形態である、ヒステリシスコンパレータ回路の構成を示す回路図である。
【図９】ヒステリシスコンパレータ回路の回路特性を示す説明図である。
【図１０】従来のヒステリシスコンパレータ回路の構成を示す回路図である。
【図１１】従来のヒステリシスコンパレータ回路におけるヒステリシス特性を示す特性図である。
【符号の説明】
１，２ ＮＭＯＳＦＥＴ
３，４ ＰＭＯＳＦＥＴ
５，６ スイッチ
７，８ ＮＭＯＳＦＥＴ
９ ＰＭＯＳＦＥＴ
１０ ＮＭＯＳＦＥＴ
１１，１２ インバータ
１３，１４ 抵抗器
１５ 電流源
２０ 共通接続点
３０ アンプ
３１ ＮＭＯＳＦＥＴ
３２，３３ ＰＭＯＳＦＥＴ
３４ 抵抗器
６０ 回路（第１の電位差可変手段）
６１ ＮＭＯＳＦＥＴ
６２ スイッチ
７０ 回路（第２の電位差可変手段）
７１ ＮＭＯＳＦＥＴ
７２ スイッチ
８０ 回路（第１の電位差可変手段）
８１ ＮＭＯＳＦＥＴ
８２ スイッチ
９０ 回路（第２の電位差可変手段）
９１ ＮＭＯＳＦＥＴ
９２ スイッチ
１００ 差動入力段
１１０ 差動対
１１１，１１２ 入力端子
１３０ 出力端子
２００ 出力段
３００ 電流源
４００ 従来のヒステリシスコンパレータ回路
４０１ 本願発明のヒステリシスコンパレータ回路
４０２ 本願発明のヒステリシスコンパレータ回路
４０３ 本願発明のヒステリシスコンパレータ回路[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a comparator circuit with hysteresis.
[0002]
[Prior art]
FIG. 10 shows a conventional hysteresis comparator (see FIGS. 1 and 2 of JP-A-2002-135090).
[0003]
1 is an input resistance Ri and 2 is a feedback resistance Rf. Va is an input signal, and Vb is a reference voltage. V _OH Is the output high level, which is almost the power supply voltage Vdd. V _OL Is the output low level, which is the ground voltage Vss. The non-inverted output is fed back to the input terminal to realize the comparator operation. The comparator circuit compares an input potential applied to one input terminal with a reference potential applied to the other input terminal, and generates an output according to the comparison result. Hysteresis characteristics can be obtained by the resistors Ri and Rf.
[0004]
FIG. 11 shows the hysteresis characteristics.
[0005]
When the output of the hysteresis comparator changes from High to Low, the input voltage can be expressed by the following equation.
Va (H → L) = ｛Ri (Vb−V _OH ) + Rf · Vb｝ / Rf (1)
[0006]
When the output of the comparator changes from Low to High, the input voltage can be expressed by the following equation.
Va (L → H) = ｛Ri (Vb−V _OL ) + Rf · Vb｝ / Rf (2)
[0007]
Accordingly, the hysteresis width is represented by the difference between the above equations (1) and (2), and is therefore represented by the following equation.
Va (L → H) −Va (H → L) = (V _OH -V _OL ) × (Ri / Rf) (3)
[0008]
[Patent Document 1]
JP 2002-135090 A
[0009]
[Problems to be solved by the invention]
However, as shown in equation (3), the hysteresis width depends on the power supply voltage (V _OH , V _OL ), There is a problem that the hysteresis width also changes when the power supply voltage changes. Further, when it is necessary to reduce the hysteresis width, it is necessary to increase the ratio between Rf and Ri.
[0010]
For example, if Vdd = 5V and the hysteresis width is to be 10 mV,
Ri: Rf = 1: 500
Need to be
[0011]
Therefore, if Ri = 200Ω, Rf needs a large resistance of 100 kΩ, and as a result, the layout area of the circuit increases.
[0012]
When the layout area is increased as described above, the manufacturing process varies, and accompanying this, the ratio of Ri to Rf also varies.
[0013]
When the ratio between Ri and Rf varies, the hysteresis width depending on the ratio is also affected by the variation, and there is a problem that high-precision adjustment cannot be performed.
[0014]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a hysteresis comparator circuit capable of adjusting a hysteresis width without being affected by a power supply voltage and without requiring a large resistance ratio.
[0015]
Another object of the present invention is to provide a small-sized and inexpensive hysteresis comparator circuit while obtaining high-precision hysteresis characteristics.
[0016]
[Means for Solving the Problems]
The present invention compares an input signal input to one input terminal of a differential pair with a reference signal which is a reference input to the other input terminal of the differential pair, and outputs the comparison result from an output stage. A hysteresis comparator circuit that outputs a signal, wherein the differential pair changes a potential difference between a common potential at a common connection point where the differential pair is connected to a current source and a potential of one input terminal of the differential pair. 1 potential difference varying means, a second potential difference varying means for changing a potential difference between a common potential at the common connection point and a potential at the other input terminal of the differential pair, and the potential differences are different from each other. And a control means for controlling the first potential difference varying means and the second potential difference varying means based on an output signal output from the output stage, thereby constituting a hysteresis comparator circuit.
[0017]
Here, the first and second potential difference varying means have a switch function of changing each potential difference based on an output signal output from the output stage, and each circuit constituting the differential pair May be connected in series or in parallel.
[0018]
The differential pair has first and second MOS transistors, one input terminal of the differential pair is a gate of the first MOS transistor, and the other input terminal of the differential pair is A gate of a second MOS transistor, wherein the first potential difference varying means includes a first resistor and a first switch, and wherein the second potential difference varying means includes a second resistor and a second resistor. Two switches, wherein the first resistor is connected in series between the source of the first MOS transistor and the current source that supplies a predetermined current to the differential pair; The first switch is connected in parallel to the first resistor so as to short-circuit both ends of the first resistor, and the second resistor is connected to a source of the second MOS transistor and the current source. And the second switch is connected to the second It may be connected in parallel with the second resistor to short-circuit both ends of the resistor.
[0019]
The first and second switches are turned on or off based on an output signal output from the output stage. If the first switch is on, the second switch is turned off, and the first and second switches are turned off. If the second switch is off, the second switch may be on.
[0020]
The first and second resistors may be variable resistors.
[0021]
The current source that supplies a predetermined current to the differential pair has a voltage source and a third resistor, and is proportional to a current flowing through the third resistor according to a voltage supplied from the voltage source. May be generated.
[0022]
The differential pair has first, second, third, and fourth MOS transistors, the first MOS transistor and the second MOS transistor are connected in parallel, and one of the differential pairs Are the gates of the first and second MOS transistors connected in common, the third MOS transistor and the fourth MOS transistor are connected in parallel, and the other input terminal of the differential pair A terminal is a gate of the third and fourth MOS transistors connected in common, and the current source that supplies a predetermined current to the differential pair is the first, second, third, and fourth MOS transistors. Connected to each source of a transistor, the first potential difference varying means has a first switch, and the second potential difference varying means has a second switch, wherein the first switch Is the current source Connected in series with the second MOS transistor so as to cut off the current supplied to the second MOS transistor, and the second switch is connected to the current supplied from the current source to the third MOS transistor. May be connected in series to the third MOS transistor.
[0023]
The first and second switches are turned on or off based on an output signal output from the output stage. If the first switch is on, the second switch is turned off, and the first and second switches are turned off. If the second switch is off, the second switch may be on.
[0024]
The differential pair has first, second, third, and fourth MOS transistors, the first MOS transistor and the second MOS transistor are connected in series, and one of the differential pairs Are the gates of the first and second MOS transistors connected in common, the third MOS transistor and the fourth MOS transistor are connected in series, and the other input terminal of the differential pair A terminal is a gate of the third and fourth MOS transistors connected in common, and the current source for supplying a predetermined current to the differential pair is connected to each source of the second and third MOS transistors. The first potential difference varying means has a first switch, and the second potential difference varying means has a second switch, wherein the first switch is the first or the second switch. 2 M Connected in parallel so as to short-circuit the source and drain of the S transistor, the second switch may be connected in parallel so as to short-circuit the source and drain of the third or fourth MOS transistors.
[0025]
The first and second switches are turned on or off based on an output signal output from the output stage. If the first switch is on, the second switch is turned off, and the first and second switches are turned off. If the second switch is off, the second switch may be on.
[0026]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[First example]
A hysteresis comparator circuit according to a first embodiment of the present invention will be described with reference to FIGS.
(Overview)
First, an outline of the present invention will be described.
The hysteresis comparator circuit according to the present invention includes, for example, a differential input stage (differential amplifier) 100 and an output stage 200 connected to the differential input stage 100 and outputting an output signal Vo, as shown in the circuit of FIG. It is characterized by having first and second potential difference varying means and control means as described below.
[0027]
The first potential difference varying unit includes a common potential Vm at the common connection point 20 where the differential pair 110 is connected to the current source 300 and one of the differential pair 110 based on the output signal Vo output from the output stage 200. Has a function of changing a potential difference between the input signal 111 and the input signal 111 input to the input terminal 111.
[0028]
The second potential difference varying means has a function of changing the potential difference between the common potential Vm of the common connection point 20 and the reference potential Vb of the reference signal input to the other input terminal 112 of the differential pair 110.
[0029]
In this case, a specific configuration of the first and second potential difference varying means includes, for example, a function (a combination circuit of a resistor and a switch) in which each potential difference changes based on the output result of the output stage 200. Or a MOS transistor having an operation control terminal). The connection configuration of the circuits may be connected to each circuit of the differential pair 110 in series or in parallel.
[0030]
The control means has a function of performing control based on the output result of the output stage 200 such that each potential difference generated by the first and second potential difference variable functions has a different value. In this case, a specific configuration of the control circuit may be, for example, the inverters 11 and 12 directly connected.
[0031]
(Concrete example)
Hereinafter, a specific example will be described.
FIG. 1 shows a configuration example of a hysteresis comparator circuit according to the present invention.
[0032]
In this example, the first and second potential difference varying means are configured by a combination circuit of a resistor and a switch, and these variable means are connected in series to each circuit (NMOSFETs 1 and 2) of the differential pair 110. An example in the case of the configuration will be described.
[0033]
<Structure>
In FIG. 1, the circuit includes a differential input stage 100 and an output stage 200.
[0034]
The differential input stage 100 has a differential pair 110 and a current source 300 connected to the differential pair 110 and supplying a predetermined current.
[0035]
The differential pair 110 includes an NMOSFET 1 to which an input voltage Va is applied, and an NMOSFET 2 to which a reference potential Vb is applied.
[0036]
The output Vc of the differential input stage 100 is inverted by an output stage (amplification stage) composed of a PMOSFET 9 and an NMOSFET 10 serving as a current source, and is output via inverters 11 and 12. The output of the inverter 11 is Vp, and the output of the inverter 12 is the output signal Vo.
[0037]
Further, the differential input stage 100 includes a current mirror circuit composed of PMOSFETs 3 and 4.
[0038]
Further, resistors 13 and 14 are connected in series to the sources S of the NMOSFETs 1 and 2 as the differential pair 110, and switches 5 and 6 are connected to both ends of the resistors 13 and 14, respectively. As a result, the switches 5 and 6 perform opening and closing operations between the resistors 13 and 14, respectively. That is, here, the resistors 13 and 14 and the switches 5 and 6 constitute first and second potential difference varying means.
[0039]
The switches 5 and 6 may be composed of, for example, NMOSFETs or PMOSFETs. In the case of this MOSFET configuration, a path from the source S to the drain D is provided at both ends of the resistors 13 and 14, and a signal from the output stage 200 is applied to the gate G to perform an opening / closing operation. That is, here, the output Vp of the inverter 11 is applied to the gate G of the switch 5, and the output signal Vo of the inverter 12 is applied to the gate G of the switch 6. That is, here, the inverters 11 and 12 constitute control means for controlling the first and second potential difference varying means.
[0040]
The other terminals of the resistors 13 and 14 are connected to each other at a common connection point 20, and the common connection point 20 is connected to the drain D of the NMOSFET 8 which is a part of the constant current source 300. The NMOSFETs 7, 8, and 10 constitute a current mirror circuit, and the drain D of the NMOSFET 7 is connected to the current source 15.
[0041]
<Operation>
Next, the operation of the hysteresis comparator circuit will be described.
[0042]
In FIG. 1, the circuit compares an input signal Va input to one input terminal 111 of a differential pair 110 with a reference signal Vb serving as a reference input to the other input terminal 112 of the differential pair 110. Then, the comparison result is output as an output signal Vo from the output stage 200 connected to the differential input stage 100.
(Input voltage: Va≫Vb)
As an initial state, consider a case where the input voltage Va is sufficiently higher than the reference voltage Vb (Va≫Vb).
[0043]
When Va≫Vb, the drain D side of the NMOSFET 1 becomes L level → the drain D side of the NMOSFET 2 becomes H level → the drain D side of the PMOSFET 9 becomes L level. As a result, the potential Vp, which is the output value of the inverter 11, becomes the Vdd level (H level), and the potential Vo of the output signal of the output terminal 130 via the inverter 12 becomes the Vss level (L level).
[0044]
At this time, the switches 5 and 6 open and close according to the values of the potentials Vp and Vo of the output stage 200. That is, the switch 5 is closed because the potential Vp is at the H level, and the resistor 13 is short-circuited. On the other hand, the switch 6 opens without operating because the potential Vo is in the L level state, and does not short-circuit the resistor 14 (resistance value R). In this case, the switches 5 and 6 are NMOSFETs.
[0045]
The current flowing through the resistor 14 and the NMOSFET 2 on one side of the differential pair 110 is represented by I ₂ Then, the potential V2 on the source S side of the NMOSFET 2 constituting the differential pair 110 is compared with the potential V1 on the source S side of the NMOSFET 1 by I ₂ × R higher by the potential.
[0046]
Therefore, as shown in FIG. 2, to change the output voltage Vo from the Vss level (L level) to the Vdd level (H level), the input voltage Va is represented by the following equation.
Va (H → L) = Vb-I ₂ × R… (4)
[0047]
(Input voltage: Va≪Vb)
Next, a case where the input voltage Va is sufficiently lower than the reference voltage Vb (VaＶVb) will be considered as an initial state.
[0048]
When Va≪Vb, the drain D side of the NMOSFET 1 becomes H level → the drain D side of the NMOSFET 2 becomes L level → the drain D side of the PMOSFET 9 becomes H level. As a result, the Vd potential output from the inverter 11 becomes the Vss level (L level), and the output potential of the output terminal 130 via the inverter 12 becomes the Vdd level (H level).
[0049]
At this time, the switches 5 and 6 open and close according to the values of the potentials Vp and Vo of the output stage 200. That is, the switch 5 is opened without operating because the potential Vp is in the L level state, and does not short-circuit the resistor 13 (resistance value R). On the other hand, the switch 6 is closed because the potential Vo is at the H level, and the resistor 14 is short-circuited.
[0050]
The current flowing through the resistor 13 and the NMOSFET 1 on one side of the differential pair 110 is represented by I ₁ Then, the potential V1 on the source S side of the NMOSFET 1 forming the differential pair 110 is compared with the potential V2 on the source S side of the NMOSFET 2 by I ₁ × R higher by the potential.
[0051]
Therefore, as shown in FIG. 2, to change the output voltage Vo from the Vdd level (H level) to the Vss level (L level), the input voltage Va is represented by the following equation.
Va (L → H) = I ₁ × R + Vb (5)
[0052]
Thus, the hysteresis width is represented by the difference between the expressions (4) and (5), and is expressed by the following expression.
Va (L → H) −Va (H → L) = 2 × I × R (6)
Where I = I ₁ = I ₂ And
[0053]
Therefore, the hysteresis width is determined by the resistance value R and the current value I flowing through the MOSFET on one side of the differential pair, and does not depend on the power supply voltage.
[0054]
For example, when I = 10 μA and R = 1 kΩ, the hysteresis width is 20 mV, and when R = 10 kΩ, the hysteresis width is 200 mV.
When Vdd = 5V and a hysteresis width of 10 mV is required, I = 50 μA and R = 100Ω.
By adjusting the current value I in this manner, the resistance can be reduced.
[0055]
The hysteresis width can be changed by changing the resistance value R of the resistors 13 and 14. The same applies to the case where the reference voltage is input to the Va side.
[0056]
(Adjustment of hysteresis width)
Next, another method for adjusting the hysteresis width will be described using the current source 15.
FIG. 3 shows a configuration example of the current source 15 used in the present circuit.
[0057]
Reference numeral 30 denotes an amplifier connected to the gate G of the NMOSFET 31. V _in Is the reference voltage V _ref Is a reference voltage input terminal of the amplifier 30 for inputting the reference voltage. I _out Is an output current terminal for outputting the output current i.
[0058]
Here, the output current i is represented by the following equation.
i = V _ref / R '... (7)
[0059]
The resistance value 34 (resistance value R ′) is usually formed of polysilicon or a diffusion layer in an LSI. The resistance value R ′ shows a behavior that the resistance value increases on the high temperature side.
[0060]
Therefore, for example, the output current i decreases on the high temperature side and increases on the low temperature side. However, a current source having such a temperature characteristic is used as the current source 15 of the hysteresis comparator circuit in FIG. The resistors 13 and 14 of FIG. 1 are manufactured from the same material as the resistor 34 of FIG. 1, and the hysteresis width when the resistance value in the circuit of FIG. It is represented by an equation.
Hysteresis width = V _ref × (R / R ′)… (8)
[0061]
Therefore, according to equation (8), the hysteresis width is equal to the reference voltage V _ref And the resistance ratio of the resistors R and R ', the fluctuation of the resistance value of the resistor due to the temperature is canceled, and the desired hysteresis width can be kept constant over the entire temperature range.
[0062]
Also, V _ref By changing the voltage, the hysteresis width can be made variable.
[0063]
Further, the hysteresis width can be made variable by changing the resistance R ′ or R of the resistor of the current source 15.
[0064]
[Second example]
Next, a second embodiment of the present invention will be described with reference to FIG. The description of the same parts as those in the first example is omitted, and the same reference numerals are given.
[0065]
This example is a modification of the above-described first example, and is an example in which the configuration of the first and second potential difference varying means is changed.
[0066]
The first potential difference varying means is composed of, for example, switches 40 and 41 and three resistors 50 (R1, R2, R3) connected in series, and is a source of the NMOSFET 1 constituting one circuit of the differential pair 110. It is connected in series to the S side.
[0067]
The second potential difference varying means includes, for example, switches 42 and 43 and three resistors 51 (R1, R2, R3) connected in series. It is connected in series to the source S of the NMOSFET 2 constituting the other circuit of the differential pair 110.
[0068]
The switches 40 and 42 are configured using MOS transistors and the like, like the switches 5 and 6. The switch 40 receives the potential Vp which is the output value of the inverter 11, and the switch 42 receives the potential Vo which is the output value of the inverter 12.
[0069]
The switches 41 and 43 may be similarly configured by MOS transistors. The switches 41 and 43 are turned on / off by inputting an adjustment signal Vh for adjusting the hysteresis width from the outside, thereby changing the resistance value. To The number of resistors and switches may be any number, and any configuration may be used as long as the resistance value is variable.
[0070]
With the above circuit configuration, the current value I flowing on one side of the differential pair 110 ₁ , I ₂ Is controlled by the current source 300 of the differential pair 110. Since the NMOSFETs 7 and 8 are current mirror circuits, the NMOSFETs 7 and 8 control the current value of the current source 15 flowing through the NMOSFET 7; The hysteresis width can be adjusted.
[0071]
Therefore, by switching with the switches 41 and 43 using the plurality of resistance values 50 and 51, the hysteresis width can be more easily changed over a wider range.
[0072]
[Third example]
Next, a third embodiment of the present invention will be described with reference to FIGS. The description of the same parts as those in the above-described examples is omitted, and the same reference numerals are given.
[0073]
This example is an example in which the first and second potential difference varying means are configured by MOS transistors, and the variable means is connected in parallel to each circuit of the differential pair 110.
[0074]
<Structure>
The configuration of this circuit will be described.
[0075]
The first potential difference varying means includes a circuit 60 in which an NMOSFET 61 and a switch 62 (made of a MOS transistor or the like) are connected in series. This circuit 60 is connected in parallel between the drain D and the source S of the NMOSFET 1 constituting one circuit of the differential pair 110. Further, the NMOSFET 61 is also a part of the NMOSFET 1 forming the differential pair 110.
[0076]
The second potential difference varying means is composed of a circuit 70 in which an NMOSFET 71 and a switch 72 (comprising a MOS transistor or the like) are connected in series. This circuit 70 is connected in parallel between the drain D and the source S of the NMOSFET 2 constituting the other circuit of the differential pair 110. Further, the NMOSFET 71 is also a part of the NMOSFET 2 forming the differential pair 110.
[0077]
That is, the differential pair 110 has four NMOS transistors 1, 2, 61, and 71. The NMOSFET 1 and the NMOSFET 61 are connected in parallel, and one input terminal 111 of the differential pair 110 is connected to the gates of the commonly connected NMOSFETs 1 and 61. The NMOSFET 2 and the NMOSFET 71 are connected in parallel, and the other input terminal 112 of the differential pair 110 is the gate of the commonly connected NMOSFETs 2 and 72.
[0078]
The NMOSFET 8 constituting the current source 300 for supplying a predetermined current to the differential pair 110 is connected to each source of the NMOSFETs 1, 61, 2 and 71 via a common connection point 20 (common potential Vm).
[0079]
The switch 62 is connected in series with the NMOSFET 61 so as to cut off the current supplied from the current source 300 to the NMOSFET 61. The switch 72 is connected in series with the NMOSFET 71 so as to cut off the current supplied from the current source 300 to the NMOSFET 71.
[0080]
<Operation>
The circuit operation will be described.
Switches 62 and 72 are turned on or off according to the output value output from output stage 200. That is, the switch 62 is turned on and off according to the potential Vp which is the output value of the inverter 11, and the switch 72 is turned on and off according to the potential Vo which is the output value of the inverter 12.
[0081]
In this case, when the switch 62 is on, the switch 72 is off. When the switch 62 is off, the switch 72 is on.
That is, the channel width of the MOS of each circuit of the differential pair is changed.
[0082]
(Adjustment of hysteresis width)
A method of adjusting the hysteresis width will be described with reference to FIGS.
[0083]
In general, the on-resistance of a MOS transistor (here, the NMOSFETs 61 and 71) when the MOS transistor is on can be defined by using a relationship between a channel width W and a channel length L indicating MOS characteristics. In this example, it is assumed that the on-resistance is defined by the value of W / L.
[0084]
In FIG. 6, when the NMOSFET 71 of FIG. 5 is not connected in parallel with the NMOSFET 2, the MOS size is W ₂ / L ₂ The MOS size when the NMOSFET 61 of FIG. ₁ / L ₁ And
[0085]
When the Vout potential operates from High to Low or from Low to High, the potential Vc operates from Low to High and from High to Low. I becomes Vc high ₁ > I ₂ , Vc goes low by I ₁ <I ₂ Needs to be
Therefore, I ₁ = I ₂ The input voltage at which = I becomes the threshold value of the comparator.
[0086]
Here, the current I in the MOS saturation region is expressed by the following equation.
[0087]
(Equation 1)

[0088]
V of NMOSFET 61 _gs To V _gs1 And V of NMOSFET 71 _gs To V _gs2 If the current I flows through the NMOSFET 61 and the NMOSFET 71,
[0089]
(Equation 2)

[0090]
Now I ₁ = I ₂ = I
[0091]
[Equation 3]

[0092]
From the above formula
[0093]
(Equation 4)

[0094]
Therefore, the input voltage difference is
[0095]
(Equation 5)

[0096]
Accordingly, the hysteresis width is symmetric since the configuration of the differential pair 110 is symmetrical.
[0097]
(Equation 6)

[0098]
It becomes.
[0099]
FIG. 7 shows the hysteresis characteristics obtained by the above calculation.
Accordingly, the hysteresis width can be varied by varying the MOS size without being affected by the power supply voltage.
[0100]
(Numerical example)
Here, a description will be given with a numerical example.
As shown in the circuit of FIG. 5, when NMOSFETs are connected in parallel, it is assumed that the W / L of NMOSFET1, NMOSFET2, NMOSFET61, and NMOSFET71 is set to 160 μ / 1.2 μ and the current I is set to 800 μA.
[0101]
When the potential Vo of the output signal changes from Low to High (the switch 62 is turned on and the switch 72 is turned off), when 400 μA flows through the NMOSFET 2, V _gs2 = 675mV, V of MOS1,2,3,4 _tb = 500 mV, since the switch 62 is ON, the MOS having the gate input of the potential Va is the NMOSFET 1 and the NMOSFET 61, and the gate width (W) is twice as large as that of the NMOSFET 2 having the gate input of the potential Vb. The gate length (L) is the same.
[0102]
Therefore, the hysteresis width is
[0103]
(Equation 7)

[0104]
It becomes.
[0105]
[Fourth example]
Next, a fourth embodiment of the present invention will be described with reference to FIG. The description of the same parts as those in the above-described examples is omitted, and the same reference numerals are given.
[0106]
This example is a modification of the above-described third example. The first and second potential difference varying means are constituted by MOS transistors, and the variable means is connected in series to each circuit of the differential pair 110. This is an example in the case of a configuration. The other circuit configuration is the same as that of FIG.
[0107]
<Structure>
The configuration of this circuit will be described.
The first potential difference varying means includes a circuit 80 in which an NMOSFET 81 and a switch 82 (made of a MOS transistor or the like) are connected in parallel. This circuit 80 is connected in series on the source S side of the NMOSFET 1 constituting one circuit of the differential pair 110. Here, the NMOSFET 81 is also a part of the NMOSFET 1 forming the differential pair 110.
[0108]
The second potential difference varying means includes a circuit 90 in which an NMOSFET 91 and a switch 92 (made of a MOS transistor or the like) are connected in series. This circuit 90 is connected in series on the source S side of the NMOSFET 2 constituting the other circuit of the differential pair 110. Here, the NMOSFET 91 is also a part of the NMOSFET 2 forming the differential pair 110.
[0109]
That is, the differential pair 110 has four NMOS transistors 1, 2, 81, and 91. The NMOSFET 1 and the NMOSFET 81 are connected in series, and one input terminal 111 of the differential pair 110 is connected to the gates of the commonly connected NMOSFETs 1 and 81. The NMOSFET 2 and the NMOSFET 91 are connected in series, and the other input terminal 112 of the differential pair 110 is the gate of the commonly connected NMOSFETs 2 and 92.
[0110]
The NMOSFET 8 configuring the current source 300 that supplies a predetermined current to the differential pair 110 is connected to the sources of the NMOSFETs 81 and 91 via a common connection point 20 (common potential Vm).
[0111]
The switch 82 is connected in parallel so that the source S and the drain D of the NMOSFET 81 are short-circuited. The switch 92 is connected in parallel so that the source S and the drain D of the NMOSFET 91 are short-circuited.
[0112]
<Operation>
The circuit operation will be described.
Switches 82 and 92 are turned on or off according to the output value output from output stage 200. That is, the switch 82 is turned on and off according to the potential Vp which is the output value of the inverter 11, and the switch 92 is turned on and off according to the potential Vo which is the output value of the inverter 12.
[0113]
In this case, when the switch 82 is on, the switch 92 is off. When the switch 82 is off, the switch 92 is on.
The adjustment of the hysteresis width can be performed in the same manner as in the third example described above.
[0114]
(Comparative example)
With reference to the first to fourth examples described above, an example in which a hysteresis comparator circuit is actually created will be described in comparison with a conventional circuit.
[0115]
FIG. 9 shows a comparative example of the conventional hysteresis comparator circuit 400 and the hysteresis comparator circuits 401 to 403 of the present invention.
[0116]
The comparison conditions were as follows. The circuit element was a MOS transistor, the manufacturing process was a 0.5 μm double poly double metal process, the power supply voltage was 5 V, and the hysteresis width was 20 mV.
[0117]
Elements to be compared were a differential pair size 410, a switch size 420, an associated MOS size 430 connected to the switch, a resistor size 440, a layout area 450, and an area ratio 460. W is the channel width and L is the channel length.
[0118]
For example, the switch sizes 420 are NMOSFETs 5 and 6 in FIG. 1, NMOSFETs 62 and 72 in FIG. 5, and NMOSFETs 82 and 92 in FIG. The associated MOS size 430 is the NMOSFETs 61 and 71 in FIG. 5, and the NMOSFETs 81 and 91 in FIG. The area ratio 460 is a value obtained by standardizing the value 10000 of the conventional circuit 400 having the layout area 450 as 100%.
[0119]
As can be seen from FIG. 9, when all the hysteresis widths are configured to be the same, the area ratio 460 of each of the hysteresis comparator circuits 401 to 403 of the present invention is １ ／ or less as compared with the conventional hysteresis comparator circuit 400. Can be set, and the layout area 450 can be halved, whereby a small and inexpensive circuit can be created.
[0120]
In particular, in the present invention 402 (third example in FIG. 5) and the present invention (fourth example in FIG. 8), the switch function, that is, the first function, is achieved only by the MOS transistor without using the resistor. Of the potential difference varying means 60, 80 and the second potential difference varying means 70, 90, it is possible to further reduce the variation in the manufacturing process, and furthermore, to suppress the variation in the hysteresis width to achieve a highly accurate circuit. Can be created.
[0121]
【The invention's effect】
As described above, according to the present invention, a switch function is provided in which each potential difference of a differential pair changes based on a comparator output signal of an output stage, and in series with each circuit constituting a differential pair. Or, since the potential difference varying means connected in parallel is provided, for example, the potential difference varying means is constituted by a resistor and a switch for short-circuiting both ends of the resistor, and the variable means is connected to each circuit of the differential pair. The potential difference varying means is composed of a MOS transistor that is also a part of a differential pair and a switch that short-circuits both ends of the MOS transistor. The variable means can be connected to each circuit of the differential pair in parallel or in series, and can be controlled based on the comparator output signal, thereby not being affected by the power supply voltage or the environmental temperature. , Without requiring a large resistance ratio, it can be adjusted with high precision hysteresis width over a wide range.
[0122]
Further, according to the present invention, the layout area can be halved as compared with the conventional circuit, so that the variation in the manufacturing process can be greatly reduced, thereby suppressing the variation in the hysteresis width and reducing the size and cost. A hysteresis comparator circuit can be created.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of a hysteresis comparator circuit according to a first embodiment of the present invention.
FIG. 2 is a characteristic diagram showing hysteresis characteristics.
FIG. 3 is a circuit diagram showing a configuration of a current source.
FIG. 4 is a circuit diagram showing a configuration of a hysteresis comparator circuit according to a second embodiment of the present invention.
FIG. 5 is a circuit diagram showing a configuration of a hysteresis comparator circuit according to a third embodiment of the present invention.
FIG. 6 is a circuit diagram for explaining a method of adjusting a hysteresis width.
FIG. 7 is a characteristic diagram showing hysteresis characteristics.
FIG. 8 is a circuit diagram showing a configuration of a hysteresis comparator circuit according to a fourth embodiment of the present invention.
FIG. 9 is an explanatory diagram illustrating circuit characteristics of a hysteresis comparator circuit.
FIG. 10 is a circuit diagram showing a configuration of a conventional hysteresis comparator circuit.
FIG. 11 is a characteristic diagram showing hysteresis characteristics in a conventional hysteresis comparator circuit.
[Explanation of symbols]
1,2 NMOSFET
3,4 PMOSFET
5,6 switch
7,8 NMOSFET
9 PMOSFET
10 NMOSFET
11,12 Inverter
13,14 resistor
15 Current source
20 common connection points
30 amplifier
31 NMOSFET
32,33 PMOSFET
34 resistor
60 circuits (first potential difference varying means)
61 NMOSFET
62 switch
70 circuits (second potential difference varying means)
71 NMOSFET
72 switch
80 circuits (first potential difference varying means)
81 NMOSFET
82 switch
90 circuits (second potential difference varying means)
91 NMOSFET
92 switch
100 differential input stage
110 differential pair
111, 112 input terminal
130 output terminal
200 output stage
300 current source
400 Conventional hysteresis comparator circuit
401 Hysteresis comparator circuit of the present invention
402 Hysteresis comparator circuit of the present invention
403 Hysteresis comparator circuit of the present invention

Claims (10)

An input signal input to one input terminal of the differential pair is compared with a reference signal input to the other input terminal of the differential pair as a reference, and the comparison result is output as an output signal from an output stage. A hysteresis comparator circuit,
First potential difference varying means for changing a potential difference between a common potential at a common connection point at which the differential pair is connected to a current source and a potential at one input terminal of the differential pair;
Second potential difference varying means for changing a potential difference between a common potential at the common connection point and a potential at the other input terminal of the differential pair;
Control means for controlling the first potential difference varying means and the second potential difference varying means based on an output signal output from the output stage so that the potential differences are different from each other. Hysteresis comparator circuit. The first and second potential difference varying means include:
It has a switch function of changing each of the potential differences based on an output signal output from the output stage, and is connected in series or parallel to each circuit constituting the differential pair. The hysteresis comparator circuit according to claim 1. The differential pair has first and second MOS transistors, one input terminal of the differential pair is a gate of the first MOS transistor, and the other input terminal of the differential pair is A gate of the second MOS transistor,
The first potential difference varying means has a first resistor and a first switch,
The second potential difference varying means has a second resistor and a second switch,
here,
The first resistor is connected in series between the source of the first MOS transistor and the current source that supplies a predetermined current to the differential pair, and the first switch is connected to the first resistor. Connected in parallel with said first resistor so as to short-circuit both ends of the device;
The second resistor is connected in series between the source of the second MOS transistor and the current source, and the second switch is connected to the second resistor so as to short-circuit both ends of the second resistor. 3. The hysteresis comparator circuit according to claim 1, wherein said hysteresis comparator circuit is connected in parallel to said resistor. The first and second switches are turned on or off based on an output signal output from the output stage;
4. The method of claim 3, wherein the second switch is off if the first switch is on, and the second switch is on if the first switch is off. Hysteresis comparator circuit. 5. The hysteresis comparator circuit according to claim 3, wherein said first and second resistors are variable resistors. The current source that supplies a predetermined current to the differential pair,
6. The power supply circuit according to claim 1, further comprising a voltage source and a third resistor, wherein the current source generates a current proportional to a current flowing through the third resistor in accordance with a voltage supplied from the voltage source. The hysteresis comparator circuit according to any one of the above. The differential pair has first, second, third, and fourth MOS transistors,
The first MOS transistor and the second MOS transistor are connected in parallel, and one input terminal of the differential pair is a gate of the commonly connected first and second MOS transistors. 3 MOS transistors and the fourth MOS transistor are connected in parallel, and the other input terminal of the differential pair is a gate of the commonly connected third and fourth MOS transistors;
The current source that supplies a predetermined current to the differential pair is connected to each source of the first, second, third, and fourth MOS transistors;
The first potential difference varying means has a first switch,
The second potential difference varying means has a second switch,
here,
The first switch is connected in series to the second MOS transistor so as to cut off a current supplied from the current source to the second MOS transistor, and the second switch is connected to the second MOS transistor from the current source. 3. The hysteresis comparator circuit according to claim 1, wherein the third MOS transistor is connected in series so as to cut off a current supplied to the third MOS transistor. The first and second switches are turned on or off based on an output signal output from the output stage;
8. The system of claim 7, wherein the second switch is off if the first switch is on, and the second switch is on if the first switch is off. Hysteresis comparator circuit. The differential pair has first, second, third, and fourth MOS transistors,
The first MOS transistor and the second MOS transistor are connected in series, and one input terminal of the differential pair is a gate of the commonly connected first and second MOS transistors. 3 MOS transistors and the fourth MOS transistor are connected in series, and the other input terminal of the differential pair is a gate of the commonly connected third and fourth MOS transistors,
The current source that supplies a predetermined current to the differential pair is connected to each source of the second and third MOS transistors;
The first potential difference varying means has a first switch,
The second potential difference varying means has a second switch,
here,
The first switch is connected in parallel to short-circuit the source and drain of the first or second MOS transistor, and the second switch is connected to the source and drain of the third or fourth MOS transistor. The hysteresis comparator circuit according to claim 1 or 2, wherein the hysteresis comparator circuit is connected in parallel so as to short-circuit. The first and second switches are turned on or off based on an output signal output from the output stage;
10. The system of claim 9, wherein the second switch is off if the first switch is on, and the second switch is on if the first switch is off. Hysteresis comparator circuit.

Images