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JP2004193886A - Bias t - Google Patents

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Publication number
JP2004193886A
JP2004193886A JP2002358463A JP2002358463A JP2004193886A JP 2004193886 A JP2004193886 A JP 2004193886A JP 2002358463 A JP2002358463 A JP 2002358463A JP 2002358463 A JP2002358463 A JP 2002358463A JP 2004193886 A JP2004193886 A JP 2004193886A
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Prior art keywords
capacitor
conductor pattern
bias
frequency
terminal
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JP2002358463A
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Japanese (ja)
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JP4159346B2 (en
Inventor
Yoshikimi Tanii
義公 谷為
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Okaya Electric Industry Co Ltd
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Okaya Electric Industry Co Ltd
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Priority to JP2002358463A priority Critical patent/JP4159346B2/en
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Abstract

<P>PROBLEM TO BE SOLVED: To realize a bias T having proper productivity, a small size and stable characteristics. <P>SOLUTION: In the bias T 10, a capacitor C in which a pair of high frequency capacitors 12a, 12b and a low frequency capacitor 14 connected in series are connected in parallel, is connected between a first terminal 1 and a second terminal 2, and a coil L is connected between the second terminal 2 and a third terminal 3. Further, a first conductor pattern 32 and a second conductor pattern 33 are oppositely disposed on the surface of a dielectric substrate 30, an internal electrode 34 superposed with the first and second conductor patterns is disposed in the dielectric substrate 30, and the pair of the high frequency capacitors 12a, 12b are formed between the first conductor pattern 32 and the internal electrode 34, and between the second conductor pattern 33 and the internal electrode 34. One electrode 14a of the low frequency capacitor 14 made of a ceramic capacitor is connected to the first conductor pattern 32, and the other electrode 14b is connected to the second conductor pattern 33 to constitute the capacitor C, and a lead wire 20 is wound on the outer peripheral surface of the winding 24 of a conical core 22 to constitute the coil L. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【0001】
【発明の属する技術分野】
この発明は、高周波信号に影響を与えずに直流電流や直流電圧といった直流成分を重畳して供給するバイアスTに関する。
【0002】
【従来の技術】
高周波信号に影響を与えずに、直流電流や直流電圧といった直流成分を重畳して供給する電子部品としてのバイアスTが、特開平9−8583号に開示されているように、従来から用いられている。
図8に示すように、バイアスT70は、端子a−b間にコンデンサC’を接続すると共に、端子a−c間にコイルL’を接続することにより構成されている。
上記バイアスT70は、高周波信号は端子a−b間を通過させて、コンデンサC’によって低域成分を除去し、また、直流成分は端子cから入力し、コイルL’によって高域成分を除去して高周波信号に重畳している。
【0003】
図9及び図10は、バイアスT70に用いられるコイルL’の一例を示すものであり、このコイル74は、銅線76の表面にポリエステル、ポリウレタン等の高分子絶縁材料より成る絶縁被膜78を形成した導線80を、誘電体セラミックや、フェライト等の磁性材料より成る円柱状のコア82の外周面に巻回して成る。また、導線80の両端は、上記絶縁被膜78を剥離して銅線76を露出させることにより、端子部84と成されている。
上記コイル74にあっては、コア82が円柱状であり、該コア82に巻回された導線80の巻線径はどの部分でも一定となるため、一つの自己共振周波数だけを持つこととなる。その結果、図11のグラフに示すように、上記コイル74は、その自己共振周波数においてインピーダンスが最大となり、上記自己共振周波数以上の周波数ではインピーダンスが急激に低下し、コイルの機能を発揮しなくなるため、単一のコイル74では、広帯域において使用することはできなかった。
【0004】
このため上記コイル74を、広帯域用のバイアスT70に使用する場合には、図12のグラフに示す如く、自己共振周波数の異なる複数個のコイル74a,74b,74c,74dを直列接続することにより、図12のグラフの実線部分で示すような広帯域で使用可能なコイルを構成していた。
【0005】
また、広帯域用のバイアスT70に使用するコンデンサC’は、図13に示すように、高周波用コンデンサ86と低周波用コンデンサ88とを並列接続することにより、広帯域で使用可能なコンデンサを構成していた。
上記高周波用コンデンサ86及び低周波用コンデンサ88は、例えばセラミックチップコンデンサで構成される。
そして、図14に示すように、高周波用コンデンサ86の一方の電極86aを、回路基板90表面の導体パターン92aに接続すると共に、他方の電極86bを、銅箔等より成る外部電極端子94を介して、回路基板90表面の導体パターン92bに接続し、また、低周波用コンデンサ88の一方の電極88aを、上記外部電極端子94を介して、回路基板90表面の導体パターン92bに接続すると共に、他方の電極88bを、銅等より成る導電性の台座96を介して、回路基板90表面の導体パターン92aに接続することにより、高周波用コンデンサ86及び低周波用コンデンサ88の回路基板90への実装が行われている。
【特許文献1】
特開平9−8583号
【0006】
【発明が解決しようとする課題】
上記の通り、従来は、自己共振周波数の異なる複数個のコイル74を直列接続することにより、広帯域用のバイアスT70に使用可能なコイルを構成していたが、この場合、複数個のコイル74を接続して安定的な特性を備えたコイルを得るための接続作業が煩雑であると共に、部品点数の増加、形状の大型化をもたらしていた。
【0007】
また、従来は、セラミックチップコンデンサで構成された高周波用コンデンサ86と低周波用コンデンサ88とを並列接続して広帯域で使用可能なコンデンサを構成し、これら高周波用コンデンサ86及び低周波用コンデンサ88を、外部電極端子94や台座96を介して回路基板90へ実装(図14)していたが、この場合、外部電極端子94のインダクタンス成分が高周波用コンデンサ86の高周波特性に大きく影響を与えることから、特性劣化をできるだけ防止するために外部電極端子94の長さや取付位置等を微調整しながら接続作業を行う必要があり、接続作業が煩雑であった。さらに、個別の部品として完成された高周波用コンデンサ86及び低周波用コンデンサ88を、外部電極端子94や台座96を用いて回路基板90への実装を行っていたため、部品点数の増加、形状の大型化をもたらしていた。
【0008】
本発明は、従来の上記問題を解決するために案出されたものであり、その目的とするところは、生産性が良く、小型で特性の安定したバイアスTの実現にある。
【0009】
【課題を解決するための手段】
上記の目的を達成するために、本発明に係るバイアスTにあっては、第1乃至第3の端子を有し、第1の端子と第2の端子との間に、高周波用コンデンサと低周波用コンデンサとを並列接続して構成したコンデンサを接続すると共に、第2の端子と第3の端子との間、又は、第1の端子と第3の端子との間に、コイルを接続して成るバイアスTであって、誘電体基板の表面に導体パターンを配置すると共に、誘電体基板内部に上記導体パターンと重なる内部電極を配置することにより、上記導体パターンと内部電極との間に上記高周波用コンデンサを形成し、また、コアの巻線部に他の部分と径の異なる部分を少なくとも1箇所以上形成すると共に、該コアの外周面に導線を巻回することにより、上記コイルを形成したことを特徴とする。
【0010】
本発明のバイアスTを構成するコイルは、コアの巻線部に、他の部分と径の異なる部分を少なくとも1箇所以上形成したので、径の異なる部分に巻回された導線の巻線径と、それ以外の部分に巻回された導線の巻線径とが相違し、複数の自己共振周波数を持つこととなる。その結果、単一のコイルでありながら、広帯域において使用することが可能である。従って、該コイルを用いた本発明のバイアスTにあっては、従来の広帯域用のバイアスT70の如く複数個のコイル74の煩雑な接続作業が不要となり、生産性及び特性が向上すると共に、部品点数の減少、形状の小型化を実現できる。
【0011】
また、本発明のバイアスTを構成するコンデンサは、誘電体基板表面に配置された導体パターンと、誘電体基板内部に配置され、上記導体パターンと重なる内部電極との間に、高周波用コンデンサを形成しているので、従来の広帯域用のバイアスT70の如く、導体パターン92bと高周波用コンデンサ86とを接続する外部電極端子94を設ける必要がない。従って、該コンデンサを用いた本発明のバイアスTにあっては、従来のバイアスT70の如く高周波特性の劣化防止のための外部電極端子94の煩雑な接続作業が不要となり、生産性及び特性が向上すると共に、部品点数の減少、形状の小型化を実現できる。
【0012】
誘電体基板の表面に、第1の導体パターンと第2の導体パターンとを所定の間隙を設けて対向配置すると共に、誘電体基板内部に、上記第1の導体パターン及び第2の導体パターンと重なる内部電極を配置することにより、第1の導体パターンと内部電極との間、第2の導体パターンと内部電極との間に、直列接続された第1の高周波用コンデンサ及び第2の高周波用コンデンサを形成しても良い。この場合、上記低周波用コンデンサをチップコンデンサで構成すると共に、該低周波用コンデンサの一方の電極を、第1の高周波用コンデンサを構成する第1の導体パターンに接続すると共に、他方の電極を、第2の高周波用コンデンサを構成する第2の導体パターンに接続することにより、低周波用コンデンサと、第1の高周波用コンデンサ及び第2の高周波用コンデンサとが並列接続できるので、更に、生産性が向上すると共に、部品点数の減少、形状の小型化を実現できる。
【0013】
上記コイルのコアの巻線部は、円錐状又は角錐状と成すのが望ましい。
このように、コアの巻線部を円錐状又は角錐状にした場合、該巻線部に巻回された導線の巻線径は、その一端から他端に向かって徐々に小さく、又は大きくなっていくことから、広い周波数帯域に亘って連続的に多数の自己共振周波数を持つこととなり、単一のコイルでありながら、広帯域において使用することができる。
【0014】
【発明の実施の形態】
以下、添付図面に基づいて、本発明に係るバイアスTの実施形態を説明する。図1は、本発明に係るバイアスT10の回路図であり、該バイアスT10は、第1の端子1、第2の端子2及び第3の端子3を有しており、第1の端子1と第2の端子2との間に、直列接続された一対の高周波用コンデンサ12a,12bと低周波用コンデンサ14とを並列接続して構成したコンデンサCを接続すると共に、第2の端子2と第3の端子3との間に、コイルLを接続することにより構成されている。尚、コイルLは、第1の端子1と第3の端子3との間に接続することもできる。
【0015】
上記コイルLは、図2乃至図4に示すように、銅線16の表面にポリエステル、ポリウレタン等の高分子絶縁材料より成る絶縁被膜18を形成した導線20を、誘電体セラミックや、フェライト等の磁性材料より成る円錐状のコア22の巻線部24外周面に巻回して成る。
また、導線20の両端は、上記絶縁被膜18を剥離して銅線16を露出させることにより、端子部26と成されている。
【0016】
本発明のコイルLにあっては、上記の通り、コア22の巻線部24が、その一端(図2の右端)から他端(図2の左端)に向かって徐々に直径が小さくなっていく円錐状と成されているので、該巻線部24に巻回された導線20の巻線径も、一端(図2の右端)から他端(図2の左端)に向かって徐々に小さくなっていく。
【0017】
このように、本発明のコイルLにおいては、巻線部24に巻回された導線20の巻線径が、一端(図2の右端)から他端(図2の左端)に向かって徐々に小さくなっていくことから、図5のグラフに示す通り、広い周波数帯域に亘って連続的に多数の異なる自己共振周波数を持つこととなり、単一のコイルLでありながら、広帯域において使用することができる。
【0018】
上記コイルLの寸法は、例えば、コア22の巻線部24の最大直径が1mm、長さが2mm、導線20の直径が0.05mmと成され、この場合、上記導線20の巻回数を40回としたときのインダクタンスLは1μHであった。
【0019】
尚、コア22の巻線部24の形状は、上記した円錐状だけに限定されるものではなく、角錐状であっても良い。
さらに、複数の自己共振周波数を持ったコイルLを構成するためには、導線20の巻回されるコア22の巻線部24に、他の部分と径の異なる部分が少なくとも1箇所以上形成されていれば良い。
【0020】
図6は、本発明に係るバイアスT10を構成するコンデンサCの概略断面図であり、誘電体基板30表面に、該誘電体基板30の両端から内方に向かって、第1の導体パターン32と第2の導体パターン33とを所定の間隙を設けて対向配置すると共に、誘電体基板30内部に、上記第1の導体パターン32及び第2の導体パターン33と、部分的に重なる内部電極34を配置することにより、第1の導体パターン32と内部電極34との間に上記第1の高周波用コンデンサ12aが形成され、また、第2の導体パターン33と内部電極34との間に上記第2の高周波用コンデンサ12bが形成されている。
【0021】
また、セラミックチップコンデンサで構成された上記低周波用コンデンサ14の一方の電極14aを、第1の高周波用コンデンサ12aを構成する第1の導体パターン32に接続すると共に、他方の電極14bを、第2の高周波用コンデンサ12bを構成する第2の導体パターン33に接続することにより、該低周波用コンデンサ14と、直列接続された上記一対の高周波用コンデンサ12a,12bとが並列接続されている。
尚、上記第1の導体パターン32及び第2の導体パターン33において、上記内部電極34と重ならず高周波用コンデンサ12a,12bを構成しない部分は、高周波信号を伝送するマイクロストリップラインを構成すると共に、第1の導体パターン32及び第2の導体パターン33の外端部は、それぞれ上記第1の端子1、第2の端子2と成されている。
図6において36は、誘電体基板30の裏面全面に形成されたアース電極である。
【0022】
上記内部電極34は、該内部電極34を構成する導体パターンが表面に形成された誘電体基板30aの上に、他の誘電体基板30bを積層した後、加圧・焼成して一体化することにより形成することができる。
尚、上記誘電体基板30は、誘電率が7程度のセラミックにより構成され、上記第1の導体パターン32a、第2の導体パターン32b及び内部電極34は、Ag、Ag−Pd、Au等で構成されている。
【0023】
本発明のコンデンサCにあっては、誘電体基板30表面に形成された導体パターン32,33と、誘電体基板30内部に形成され、上記導体パターン32,33と部分的に重なる内部電極34との間に、高周波用コンデンサ12a,12bを形成しているので、従来の広帯域用のバイアスT70の如く、導体パターン92bと高周波用コンデンサ86とを接続する外部電極端子94を設ける必要がなく、従って、高周波特性の劣化防止のための外部電極端子94の煩雑な接続作業が不要となり、生産性及び特性が向上する。
また、高周波用コンデンサ12a,12bを誘電体基板30内部に形成すると共に、セラミックチップコンデンサで構成された低周波用コンデンサ14の一方の電極14aを第1の導体パターン32に、他方の電極14bを第2の導体パターン33に接続することにより、該低周波用コンデンサ14と、一対の高周波用コンデンサ12a,12bとが並列接続できるので、部品点数の減少、形状の小型化を実現できる。
【0024】
図7は、本発明に係るバイアスT10の概略平面図であり、上記コンデンサCの形成された誘電体基板30上に上記コイルLを配置し、該コイルLにおける導線20の巻線径が小さい側の端子部26を、上記第2の導体パターン33の外端部に形成された第2の端子2に接続すると共に、導線20の巻線径が小さい側の端子部26を、誘電体基板30表面に導体パターンを被着して形成した上記第3の端子3に接続することにより一体化して成る。
【0025】
本発明のバイアスT10を構成するコイルLは、コア22の巻線部24を円錐状と成し、該巻線部24に巻回された導線20の巻線径が、一端から他端に向かって徐々に小さくなっていくことから、広い周波数帯域に亘って連続的に多数の自己共振周波数を持つこととなり、単一のコイルLでありながら、広帯域において使用することができる。従って、該コイルLを用いた本発明のバイアスT10にあっては、従来の広帯域用のバイアスT70の如く複数個のコイル74の煩雑な接続作業が不要となり、生産性及び特性が向上すると共に、部品点数の減少、形状の小型化を実現できる。
【0026】
また、本発明のバイアスT10を構成するコンデンサCは、上記の通り、誘電体基板30表面に形成された導体パターン32,33と、誘電体基板30内部に形成され、上記導体パターン32,33と部分的に重なる内部電極34との間に、高周波用コンデンサ12a,12bを形成しているので、従来の広帯域用のバイアスT70の如く、導体パターン92bと高周波用コンデンサ86とを接続する外部電極端子94を設ける必要がない。また、高周波用コンデンサ12a,12bを誘電体基板30内部に形成すると共に、セラミックチップコンデンサで構成された低周波用コンデンサ14の一方の電極14aを第1の導体パターン32に、他方の電極14bを第2の導体パターン33に接続することにより、該低周波用コンデンサ14と、一対の高周波用コンデンサ12a,12bとの並列接続を行うことができる。
従って、該コンデンサCを用いた本発明のバイアスT10にあっては、従来のバイアスT70の如く高周波特性の劣化防止のための外部電極端子94の煩雑な接続作業が不要となり、生産性及び特性が向上すると共に、部品点数の減少、形状の小型化を実現できる。
【0027】
【発明の効果】
本発明のバイアスTを構成するコイルは、コアの巻線部に、他の部分と径の異なる部分を少なくとも1箇所以上形成したので、径の異なる部分に巻回された導線の巻線径と、それ以外の部分に巻回された導線の巻線径とが相違し、複数の自己共振周波数を持つこととなる。その結果、単一のコイルでありながら、広帯域において使用することが可能である。従って、該コイルを用いた本発明のバイアスにあっては、従来の広帯域用のバイアスT70の如く複数個のコイル74の煩雑な接続作業が不要となり、生産性及び特性が向上すると共に、部品点数の減少、形状の小型化を実現できる。
【0028】
また、本発明のバイアスTを構成するコンデンサは、誘電体基板表面に配置された導体パターンと、誘電体基板内部に配置され、上記導体パターンと重なる内部電極との間に、高周波用コンデンサを形成しているので、従来の広帯域用のバイアスT70の如く、導体パターン92bと高周波用コンデンサ86とを接続する外部電極端子94を設ける必要がない。従って、該コンデンサを用いた本発明のバイアスTにあっては、従来のバイアスT70の如く高周波特性の劣化防止のための外部電極端子94の煩雑な接続作業が不要となり、生産性及び特性が向上すると共に、部品点数の減少、形状の小型化を実現できる。
【図面の簡単な説明】
【図1】本発明に係るバイアスTを示す回路図である。
【図2】本発明に係るバイアスTを構成するコイルの概略正面図である。
【図3】図2のB−B断面図である。
【図4】図2のC−C断面図である。
【図5】本発明に係るバイアスTを構成するコイルのインピーダンス特性を示すグラフである。
【図6】本発明に係るバイアスTを構成するコンデンサの概略断面図である。
【図7】本発明に係るバイアスTの概略平面図である。
【図8】従来のバイアスTを示す回路図である。
【図9】従来のバイアスTに用いられるコイルを示す正面図である。
【図10】図9のA−A断面図である。
【図11】従来のバイアスTに用いられるコイルのインピーダンス特性を示すグラフである。
【図12】従来のバイアスTに用いられるコイルを複数個直列接続した場合のインピーダンス特性を示すグラフである。
【図13】広帯域用のバイアスTに用いられる従来のコンデンサを示す回路図である。
【図14】広帯域用のバイアスTに用いられる従来のコンデンサを、回路基板へ実装した状態を示す概略断面図である。
【符号の説明】
1 第1の端子
2 第2の端子
3 第3の端子
10 バイアスT
C コンデンサ
L コイル
12a 第1の高周波用コンデンサ
12b 第2の高周波用コンデンサ
14 低周波用コンデンサ
20 導線
22 コア
24 巻線部
30 誘電体基板
32 第1の導体パターン
33 第2の導体パターン
34 内部電極
[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a bias T for superimposing and supplying a DC component such as a DC current or a DC voltage without affecting a high-frequency signal.
[0002]
[Prior art]
A bias T as an electronic component for supplying a DC component such as a DC current or a DC voltage in a superimposed manner without affecting a high-frequency signal has been conventionally used as disclosed in JP-A-9-8583. I have.
As shown in FIG. 8, the bias T70 is configured by connecting a capacitor C ′ between terminals a and b and connecting a coil L ′ between terminals a and c.
The bias T70 passes a high-frequency signal between terminals a and b and removes a low-frequency component by a capacitor C ′. A DC component is input from a terminal c and a high-frequency component is removed by a coil L ′. Overlaid on the high frequency signal.
[0003]
9 and 10 show an example of a coil L 'used for the bias T70. This coil 74 has an insulating coating 78 made of a polymer insulating material such as polyester or polyurethane on the surface of the copper wire 76. The conductive wire 80 is wound around an outer peripheral surface of a cylindrical core 82 made of a magnetic material such as dielectric ceramic or ferrite. In addition, both ends of the conductive wire 80 are formed as terminal portions 84 by exfoliating the insulating coating 78 and exposing the copper wire 76.
In the coil 74, the core 82 has a cylindrical shape, and the winding diameter of the conductive wire 80 wound around the core 82 is constant at any portion, so that the coil has only one self-resonant frequency. . As a result, as shown in the graph of FIG. 11, the impedance of the coil 74 becomes maximum at its self-resonant frequency, and at a frequency equal to or higher than the self-resonant frequency, the impedance sharply decreases, and the coil does not perform its function. However, a single coil 74 could not be used in a wide band.
[0004]
Therefore, when the coil 74 is used for the bias T70 for a wide band, a plurality of coils 74a, 74b, 74c, 74d having different self-resonant frequencies are connected in series as shown in the graph of FIG. A coil usable in a wide band as shown by a solid line in the graph of FIG. 12 was configured.
[0005]
Further, as shown in FIG. 13, the capacitor C ′ used for the bias T70 for a wide band is configured by connecting a capacitor 86 for a high frequency and a capacitor 88 for a low frequency in parallel to constitute a capacitor usable in a wide band. Was.
The high frequency capacitor 86 and the low frequency capacitor 88 are composed of, for example, ceramic chip capacitors.
Then, as shown in FIG. 14, one electrode 86a of the high-frequency capacitor 86 is connected to the conductor pattern 92a on the surface of the circuit board 90, and the other electrode 86b is connected via an external electrode terminal 94 made of copper foil or the like. Connected to a conductor pattern 92b on the surface of the circuit board 90, and one electrode 88a of the low-frequency capacitor 88 is connected to the conductor pattern 92b on the surface of the circuit board 90 via the external electrode terminal 94. The other electrode 88b is connected to a conductor pattern 92a on the surface of the circuit board 90 via a conductive base 96 made of copper or the like, so that the high-frequency capacitor 86 and the low-frequency capacitor 88 are mounted on the circuit board 90. Has been done.
[Patent Document 1]
JP-A-9-8583
[Problems to be solved by the invention]
As described above, conventionally, a plurality of coils 74 having different self-resonance frequencies are connected in series to form a coil that can be used for the bias T70 for a wide band. The connection operation for obtaining a coil having stable characteristics by connecting the components is complicated, and the number of parts is increased and the size is increased.
[0007]
Conventionally, a high-frequency capacitor 86 and a low-frequency capacitor 88 composed of ceramic chip capacitors are connected in parallel to form a capacitor that can be used in a wide band, and these high-frequency capacitor 86 and low-frequency capacitor 88 are used. 14 is mounted on the circuit board 90 via the external electrode terminal 94 and the pedestal 96 (FIG. 14). In this case, since the inductance component of the external electrode terminal 94 greatly affects the high frequency characteristics of the high frequency capacitor 86, In addition, in order to prevent the characteristic deterioration as much as possible, it is necessary to perform the connection operation while finely adjusting the length and the mounting position of the external electrode terminal 94, and the connection operation is complicated. Furthermore, since the high-frequency capacitor 86 and the low-frequency capacitor 88 completed as individual components are mounted on the circuit board 90 using the external electrode terminals 94 and the pedestal 96, the number of components is increased, and the shape is large. Was brought to life.
[0008]
The present invention has been devised to solve the above-mentioned conventional problems, and an object of the present invention is to realize a bias T with good productivity, small size and stable characteristics.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, a bias T according to the present invention has first to third terminals, and a high-frequency capacitor and a low-frequency capacitor are provided between the first terminal and the second terminal. A capacitor connected in parallel with a frequency capacitor is connected, and a coil is connected between the second terminal and the third terminal or between the first terminal and the third terminal. A bias T comprising: a conductor pattern disposed on the surface of the dielectric substrate; and an internal electrode overlapping the conductor pattern disposed inside the dielectric substrate. The coil is formed by forming a high-frequency capacitor, forming at least one portion having a diameter different from that of the other portion in the winding portion of the core, and winding a conductive wire around the outer peripheral surface of the core. It is characterized by having done.
[0010]
In the coil constituting the bias T of the present invention, at least one portion having a different diameter from the other portions is formed in the winding portion of the core, so that the winding diameter of the conductor wound around the different diameter portion is different from that of the coil. The winding diameter of the conductive wire wound around the other portion is different, and has a plurality of self-resonant frequencies. As a result, a single coil can be used in a wide band. Therefore, in the bias T of the present invention using the coil, the complicated connection work of the plurality of coils 74 as in the conventional bias T70 for a wide band is not required, and the productivity and characteristics are improved. The number of points can be reduced and the size can be reduced.
[0011]
The capacitor constituting the bias T according to the present invention forms a high-frequency capacitor between a conductor pattern disposed on the surface of the dielectric substrate and an internal electrode disposed inside the dielectric substrate and overlapping the conductor pattern. Therefore, there is no need to provide the external electrode terminal 94 for connecting the conductor pattern 92b and the high-frequency capacitor 86 unlike the conventional wide band bias T70. Therefore, in the bias T of the present invention using the capacitor, complicated connection work of the external electrode terminal 94 for preventing deterioration of the high frequency characteristics as in the conventional bias T70 becomes unnecessary, and the productivity and characteristics are improved. In addition, the number of parts can be reduced and the size can be reduced.
[0012]
A first conductor pattern and a second conductor pattern are opposed to each other with a predetermined gap provided on the surface of the dielectric substrate, and the first conductor pattern and the second conductor pattern are arranged inside the dielectric substrate. By arranging the overlapping internal electrodes, a first high-frequency capacitor and a second high-frequency capacitor connected in series between the first conductor pattern and the internal electrode and between the second conductor pattern and the internal electrode. A capacitor may be formed. In this case, the low-frequency capacitor is constituted by a chip capacitor, and one electrode of the low-frequency capacitor is connected to the first conductor pattern constituting the first high-frequency capacitor, and the other electrode is connected to the first conductor pattern. By connecting to the second conductor pattern constituting the second high-frequency capacitor, the low-frequency capacitor, the first high-frequency capacitor and the second high-frequency capacitor can be connected in parallel, so that further production is possible. As a result, the number of parts can be reduced and the size can be reduced.
[0013]
It is desirable that the winding portion of the core of the coil is formed in a conical shape or a pyramid shape.
Thus, when the winding portion of the core is formed in a conical shape or a pyramid shape, the winding diameter of the conductive wire wound around the winding portion gradually decreases or increases from one end to the other end. As a result, a large number of self-resonant frequencies are continuously provided over a wide frequency band, so that a single coil can be used in a wide band.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of a bias T according to the present invention will be described with reference to the accompanying drawings. FIG. 1 is a circuit diagram of a bias T10 according to the present invention. The bias T10 has a first terminal 1, a second terminal 2, and a third terminal 3; A capacitor C formed by connecting a pair of high-frequency capacitors 12a, 12b and a low-frequency capacitor 14 connected in series is connected between the second terminal 2 and the second terminal 2. 3 is connected to a coil L. Note that the coil L can be connected between the first terminal 1 and the third terminal 3.
[0015]
As shown in FIGS. 2 to 4, the coil L is formed by connecting a conductive wire 20 having a surface of a copper wire 16 on which an insulating film 18 made of a polymer insulating material such as polyester or polyurethane is formed, to a dielectric ceramic, ferrite, or the like. It is wound around the outer peripheral surface of the winding part 24 of the conical core 22 made of a magnetic material.
In addition, both ends of the conductive wire 20 are formed as terminal portions 26 by exfoliating the insulating coating 18 to expose the copper wire 16.
[0016]
In the coil L of the present invention, as described above, the winding portion 24 of the core 22 gradually decreases in diameter from one end (the right end in FIG. 2) to the other end (the left end in FIG. 2). Because of the conical shape, the winding diameter of the conductive wire 20 wound around the winding portion 24 also gradually decreases from one end (the right end in FIG. 2) to the other end (the left end in FIG. 2). It is becoming.
[0017]
As described above, in the coil L of the present invention, the winding diameter of the conductive wire 20 wound around the winding portion 24 gradually increases from one end (the right end in FIG. 2) to the other end (the left end in FIG. 2). As it becomes smaller, as shown in the graph of FIG. 5, it has a large number of different self-resonant frequencies continuously over a wide frequency band. it can.
[0018]
The dimensions of the coil L are, for example, such that the maximum diameter of the winding portion 24 of the core 22 is 1 mm, the length is 2 mm, and the diameter of the conductor 20 is 0.05 mm. The number of turns L was 1 μH.
[0019]
The shape of the winding portion 24 of the core 22 is not limited to the above-described conical shape, but may be a pyramid shape.
Further, in order to form the coil L having a plurality of self-resonant frequencies, at least one portion having a diameter different from other portions is formed in the winding portion 24 of the core 22 around which the conductive wire 20 is wound. It would be fine.
[0020]
FIG. 6 is a schematic sectional view of the capacitor C constituting the bias T10 according to the present invention. The first conductive pattern 32 is formed on the surface of the dielectric substrate 30 from both ends of the dielectric substrate 30 to the inside. The second conductor pattern 33 and the second conductor pattern 33 are arranged facing each other with a predetermined gap therebetween, and an internal electrode 34 partially overlapping the first conductor pattern 32 and the second conductor pattern 33 is provided inside the dielectric substrate 30. By arranging, the first high-frequency capacitor 12 a is formed between the first conductor pattern 32 and the internal electrode 34, and the second high-frequency capacitor 12 a is formed between the second conductor pattern 33 and the internal electrode 34. Is formed.
[0021]
In addition, one electrode 14a of the low-frequency capacitor 14 formed of a ceramic chip capacitor is connected to the first conductor pattern 32 forming the first high-frequency capacitor 12a, and the other electrode 14b is connected to the first electrode 14b. By connecting to the second conductor pattern 33 constituting the second high-frequency capacitor 12b, the low-frequency capacitor 14 and the pair of high-frequency capacitors 12a and 12b connected in series are connected in parallel.
In the first conductor pattern 32 and the second conductor pattern 33, portions that do not overlap with the internal electrodes 34 and do not constitute the high-frequency capacitors 12a and 12b constitute a microstrip line for transmitting a high-frequency signal, and The outer ends of the first conductor pattern 32 and the second conductor pattern 33 are formed as the first terminal 1 and the second terminal 2, respectively.
In FIG. 6, reference numeral 36 denotes a ground electrode formed on the entire back surface of the dielectric substrate 30.
[0022]
The internal electrode 34 is formed by stacking another dielectric substrate 30b on a dielectric substrate 30a having a surface on which a conductor pattern constituting the internal electrode 34 is formed, and then pressing and firing to integrate them. Can be formed.
The dielectric substrate 30 is made of ceramic having a dielectric constant of about 7, and the first conductor pattern 32a, the second conductor pattern 32b, and the internal electrode 34 are made of Ag, Ag-Pd, Au, or the like. Have been.
[0023]
In the capacitor C of the present invention, the conductor patterns 32 and 33 formed on the surface of the dielectric substrate 30 and the internal electrodes 34 formed inside the dielectric substrate 30 and partially overlapping the conductor patterns 32 and 33 are provided. Since the high-frequency capacitors 12a and 12b are formed between them, there is no need to provide the external electrode terminal 94 for connecting the conductor pattern 92b and the high-frequency capacitor 86 unlike the conventional broadband bias T70. In addition, complicated connection work of the external electrode terminals 94 for preventing deterioration of high frequency characteristics is not required, and productivity and characteristics are improved.
The high-frequency capacitors 12a and 12b are formed inside the dielectric substrate 30, and one electrode 14a of the low-frequency capacitor 14 composed of a ceramic chip capacitor is connected to the first conductor pattern 32, and the other electrode 14b is connected to the other. By connecting to the second conductor pattern 33, the low-frequency capacitor 14 and the pair of high-frequency capacitors 12a and 12b can be connected in parallel, so that the number of components can be reduced and the size can be reduced.
[0024]
FIG. 7 is a schematic plan view of the bias T10 according to the present invention, in which the coil L is disposed on the dielectric substrate 30 on which the capacitor C is formed, and the coil L has a smaller winding diameter of the conductive wire 20. Is connected to the second terminal 2 formed at the outer end of the second conductor pattern 33, and the terminal 26 on the side where the winding diameter of the conductive wire 20 is smaller is connected to the dielectric substrate 30. It is integrated by connecting to the third terminal 3 formed by applying a conductor pattern on the surface.
[0025]
In the coil L constituting the bias T10 of the present invention, the winding portion 24 of the core 22 has a conical shape, and the winding diameter of the conductive wire 20 wound around the winding portion 24 increases from one end to the other end. Therefore, the coil L has a large number of self-resonant frequencies continuously over a wide frequency band, so that a single coil L can be used in a wide band. Therefore, in the bias T10 of the present invention using the coil L, complicated connection work of a plurality of coils 74 as in the conventional broadband bias T70 is not required, and productivity and characteristics are improved. The number of parts can be reduced and the size can be reduced.
[0026]
Further, as described above, the capacitor C constituting the bias T10 of the present invention includes the conductor patterns 32 and 33 formed on the surface of the dielectric substrate 30 and the conductor patterns 32 and 33 formed inside the dielectric substrate 30. Since the high-frequency capacitors 12a and 12b are formed between the partially overlapped internal electrodes 34, the external electrode terminals for connecting the conductor pattern 92b and the high-frequency capacitor 86 like the conventional broadband bias T70. There is no need to provide 94. The high-frequency capacitors 12a and 12b are formed inside the dielectric substrate 30, and one electrode 14a of the low-frequency capacitor 14 composed of a ceramic chip capacitor is connected to the first conductor pattern 32, and the other electrode 14b is connected to the other. By connecting to the second conductor pattern 33, the low-frequency capacitor 14 and the pair of high-frequency capacitors 12a and 12b can be connected in parallel.
Therefore, in the bias T10 of the present invention using the capacitor C, the complicated connection work of the external electrode terminal 94 for preventing the deterioration of the high frequency characteristics as in the conventional bias T70 becomes unnecessary, and the productivity and the characteristics are reduced. In addition to the improvement, the number of parts can be reduced and the size can be reduced.
[0027]
【The invention's effect】
In the coil constituting the bias T of the present invention, at least one portion having a different diameter from the other portions is formed in the winding portion of the core, so that the winding diameter of the conductor wound around the different diameter portion is different from that of the coil. The winding diameter of the conductive wire wound around the other portion is different, and has a plurality of self-resonant frequencies. As a result, a single coil can be used in a wide band. Therefore, in the bias of the present invention using the coil, the complicated connection work of the plurality of coils 74 as in the conventional bias T70 for a wide band is not required, and the productivity and characteristics are improved, and the number of parts is reduced. And the size can be reduced.
[0028]
The capacitor constituting the bias T according to the present invention forms a high-frequency capacitor between a conductor pattern disposed on the surface of the dielectric substrate and an internal electrode disposed inside the dielectric substrate and overlapping the conductor pattern. Therefore, there is no need to provide the external electrode terminal 94 for connecting the conductor pattern 92b and the high-frequency capacitor 86 unlike the conventional wide band bias T70. Therefore, in the bias T of the present invention using the capacitor, complicated connection work of the external electrode terminals 94 for preventing deterioration of the high frequency characteristics as in the conventional bias T70 is not required, and productivity and characteristics are improved. In addition, the number of parts can be reduced and the size can be reduced.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a bias T according to the present invention.
FIG. 2 is a schematic front view of a coil constituting a bias T according to the present invention.
FIG. 3 is a sectional view taken along line BB of FIG. 2;
FIG. 4 is a sectional view taken along the line CC of FIG. 2;
FIG. 5 is a graph showing impedance characteristics of a coil constituting a bias T according to the present invention.
FIG. 6 is a schematic sectional view of a capacitor constituting a bias T according to the present invention.
FIG. 7 is a schematic plan view of a bias T according to the present invention.
FIG. 8 is a circuit diagram showing a conventional bias T.
FIG. 9 is a front view showing a coil used for a conventional bias T.
FIG. 10 is a sectional view taken along line AA of FIG. 9;
FIG. 11 is a graph showing impedance characteristics of a coil used for a conventional bias T.
FIG. 12 is a graph showing impedance characteristics when a plurality of coils used for a conventional bias T are connected in series.
FIG. 13 is a circuit diagram showing a conventional capacitor used for a bias T for a wide band.
FIG. 14 is a schematic cross-sectional view showing a state in which a conventional capacitor used for a bias T for a wide band is mounted on a circuit board.
[Explanation of symbols]
1 first terminal 2 second terminal 3 third terminal 10 bias T
C capacitor L coil 12a first high-frequency capacitor 12b second high-frequency capacitor 14 low-frequency capacitor 20 conductor 22 core 24 winding part 30 dielectric substrate 32 first conductor pattern 33 second conductor pattern 34 internal electrode

Claims (4)

第1乃至第3の端子を有し、第1の端子と第2の端子との間に、高周波用コンデンサと低周波用コンデンサとを並列接続して構成したコンデンサを接続すると共に、第2の端子と第3の端子との間、又は、第1の端子と第3の端子との間に、コイルを接続して成るバイアスTであって、誘電体基板の表面に導体パターンを配置すると共に、誘電体基板内部に上記導体パターンと重なる内部電極を配置することにより、上記導体パターンと内部電極との間に上記高周波用コンデンサを形成し、また、コアの巻線部に他の部分と径の異なる部分を少なくとも1箇所以上形成すると共に、該コアの外周面に導線を巻回することにより、上記コイルを形成したことを特徴とするバイアスT。A capacitor having first to third terminals, a capacitor configured by connecting a high-frequency capacitor and a low-frequency capacitor in parallel between the first terminal and the second terminal, and a second capacitor. A bias T formed by connecting a coil between a terminal and a third terminal, or between a first terminal and a third terminal, wherein a conductor pattern is disposed on a surface of a dielectric substrate. By arranging an internal electrode that overlaps with the conductor pattern inside the dielectric substrate, the high-frequency capacitor is formed between the conductor pattern and the internal electrode, and the diameter of the winding portion of the core is different from that of another portion. Wherein at least one or more different portions are formed, and the coil is formed by winding a conductive wire around the outer peripheral surface of the core. 誘電体基板の表面に、第1の導体パターンと第2の導体パターンとを所定の間隙を設けて対向配置すると共に、誘電体基板内部に、上記第1の導体パターン及び第2の導体パターンと重なる内部電極を配置することにより、第1の導体パターンと内部電極との間、第2の導体パターンと内部電極との間に、直列接続された第1の高周波用コンデンサ及び第2の高周波用コンデンサを形成したことを特徴とする請求項1に記載のバイアスT。A first conductor pattern and a second conductor pattern are opposed to each other with a predetermined gap provided on the surface of the dielectric substrate, and the first conductor pattern and the second conductor pattern are arranged inside the dielectric substrate. By arranging the overlapping internal electrodes, a first high-frequency capacitor and a second high-frequency capacitor connected in series between the first conductor pattern and the internal electrode and between the second conductor pattern and the internal electrode. The bias T according to claim 1, wherein a capacitor is formed. 上記低周波用コンデンサをチップコンデンサで構成すると共に、該低周波用コンデンサの一方の電極を、第1の高周波用コンデンサを構成する第1の導体パターンに接続すると共に、他方の電極を、第2の高周波用コンデンサを構成する第2の導体パターンに接続することにより、低周波用コンデンサと、第1の高周波用コンデンサ及び第2の高周波用コンデンサとを並列接続したことを特徴とする請求項2に記載のバイアスT。The low-frequency capacitor is constituted by a chip capacitor, one electrode of the low-frequency capacitor is connected to a first conductor pattern constituting a first high-frequency capacitor, and the other electrode is connected to a second electrode. 3. A low-frequency capacitor, a first high-frequency capacitor and a second high-frequency capacitor are connected in parallel by being connected to a second conductor pattern constituting the high-frequency capacitor. Bias T described in 1. 上記コイルのコアの巻線部が、円錐状又は角錐状と成されていることを特徴とする請求項1乃至4の何れかに記載のバイアスT。The bias T according to any one of claims 1 to 4, wherein a winding portion of the core of the coil has a conical shape or a pyramid shape.
JP2002358463A 2002-12-10 2002-12-10 Bias T Expired - Fee Related JP4159346B2 (en)

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US7518463B2 (en) * 2004-12-23 2009-04-14 Agilent Technologies, Inc. Circuit assembly with conical inductor
JP2009244289A (en) * 2008-03-28 2009-10-22 Fujitsu Ltd Circuit device and circuit device apparatus
US7940454B2 (en) 2006-09-29 2011-05-10 Fujitsu Limited Optical parametric amplifier
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7518463B2 (en) * 2004-12-23 2009-04-14 Agilent Technologies, Inc. Circuit assembly with conical inductor
JP2007109839A (en) * 2005-10-13 2007-04-26 Fujitsu Ltd Coil package and bias T package
JP2008047711A (en) * 2006-08-16 2008-02-28 Fujitsu Ltd Inductor wiring board, inductor wiring method, and bias T circuit
US7940454B2 (en) 2006-09-29 2011-05-10 Fujitsu Limited Optical parametric amplifier
JP2009244289A (en) * 2008-03-28 2009-10-22 Fujitsu Ltd Circuit device and circuit device apparatus
JP2014514777A (en) * 2011-05-04 2014-06-19 アメリカン・テクニカル・セラミックス,コーポレーション Ultra-wideband assembly system and method
US10075144B2 (en) * 2015-01-15 2018-09-11 Commscope Connectivity Uk Limited Systems and methods for enhanced high frequency power bias tee designs
AU2016207976B2 (en) * 2015-01-15 2019-11-21 Commscope Connectivity Uk Limited Systems and methods for enhanced high frequency power bias tee designs

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