JP2004193601A - Semiconductor integrated circuit device and electronic card using it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device that can protect an integrated circuit from teardown even in the case that there is no ground connection or no connection to a power supply. <P>SOLUTION: Air bag equipment for a vehicle comprises a primary semiconductor region (PSUB) of a primary conduction type, a source/drain region (D) of a secondary conduction type formed in the primary semiconductor region (PSUB), a transistor (N1) with a gate electrode (G) formed through gate insulating film on a channel region between the source region and the drain region, an output terminal (PAD) electrically connected to the drain region (D) of the transistor, and a secondary semiconductor region (DN) of the secondary conduction type connected to the gate electrode of the transistor (N1). <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit device and an electronic card using the same, and more particularly, to a measure against destruction caused by charging the semiconductor integrated circuit device itself and discharging from the semiconductor integrated circuit device itself.

  The semiconductor integrated circuit device has a protection circuit and a protection function for protecting the integrated circuit from an excessive current applied to an output terminal. This test standard is established by MIL (Military Standards) and EIAJ (Electronic Industries Association of Japan).

  The semiconductor integrated circuit device is not used alone, but is usually used by being incorporated in an electronic product. Therefore, it can be considered that the semiconductor integrated circuit device is always connected to the ground point or the power supply in the market. In the test standard according to MIL or EIAJ, a needle is brought into contact with an output terminal, and an excessive current is caused to flow through the semiconductor integrated circuit device over a period of several tens of nsec to several μsec. During this test, the semiconductor integrated circuit device is connected to a ground point and a power supply. In this state, the protection circuit and the protection function allow the semiconductor integrated circuit device to release an excessive current to the ground point and the power supply, thereby protecting the integrated circuit. This makes it difficult for the semiconductor integrated circuit device to be broken even when an excessive current is accidentally applied, and improves the reliability and durability of an electronic product incorporating the semiconductor integrated circuit device.

Recently, applications of semiconductor integrated circuit devices have been spreading not only to electronic products but also to various media such as recording media and information media. Conventional recording media and information media are magnetic cards and magnetic disks, and magnetically store information. This magnetic storage part is replaced by a nonvolatile semiconductor storage device. This makes it possible to improve the information storage amount, information retention, information confidentiality, and the like, as compared with magnetic cards and magnetic disks. Examples of such a recording medium are called a memory card and an IC card, and are widely used in the market. As a document that introduces a memory card, there is, for example, Non-Patent Document 1. In this specification, any recording media and information media using these semiconductor integrated circuit devices are referred to as electronic cards.
Shigeo Araki, “The Memory Stick”, http://www.ece.umd.edu/courses/enee759m.S2002/papers/araki2000-micro20-4.pdf pp40-46.

  Electronic cards, like magnetic cards and magnetic disks, are not always incorporated into electronic products for use. It is carried or carried by humans. That is, the semiconductor integrated circuit device in the electronic card is often not electrically connected to the ground point or the power supply. When a semiconductor integrated circuit device encounters a severe environment without being connected to a ground point or a power supply, the conventional protection circuit or protection function that releases excessive current to the ground point or the power supply cannot sufficiently protect the integrated circuit. Possibilities are emerging.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor integrated circuit device capable of protecting an integrated circuit from destruction even when the integrated circuit is not connected to a ground point or a power supply, and a semiconductor integrated circuit device. It is to provide an electronic card used.

  In order to achieve the above object, a semiconductor integrated circuit device and an electronic card according to a first aspect of the present invention are formed in a semiconductor region of a first conductivity type, and formed in the semiconductor region of the first conductivity type and connected to an output terminal. A first insulated gate field effect transistor having a second conductivity type source / drain region, and an insulated gate electric field formed in the first conductivity type semiconductor region adjacent to the source / drain region. A second conductivity type semiconductor region connected to the gate of the effect transistor.

  A semiconductor integrated circuit device and an electronic card according to a second aspect of the present invention include a semiconductor region of a first conductivity type and a source of a second conductivity type formed in the semiconductor region of the first conductivity type and connected to an output terminal. And a first insulated gate field effect transistor having a drain region and a second conductivity type source formed in the first conductivity type semiconductor region and connected to the gate of the first insulated gate field effect transistor. And a second insulated gate field effect transistor having a first / second drain region and a first insulated gate field effect transistor for driving the first insulated gate field effect transistor. And a diode having the other of an anode and a cathode connected to the gate of the first insulated gate field effect transistor. To. The distance from the source / drain region of the first insulated gate field effect transistor to the other of the anode and the cathode is equal to the distance from the source / drain region of the first insulated gate field effect transistor to the second. Wherein the distance to the source / drain region of the insulated gate field effect transistor is shorter.

  A semiconductor integrated circuit device and an electronic card according to a third aspect of the present invention include a semiconductor region of a first conductivity type and a source of a second conductivity type formed in the semiconductor region of the first conductivity type and connected to an output terminal. And a first insulated gate field effect transistor having a drain region and a second conductivity type source formed in the first conductivity type semiconductor region and connected to the gate of the first insulated gate field effect transistor. And a second insulated-gate field-effect transistor having a drain / region and driving the first insulated-gate field-effect transistor; and a source formed in the first-conductivity-type semiconductor region and short-circuited to its own gate. / Drain region and a source / drain region connected to the gate of the first insulated gate field effect transistor. ; And a register. And a source / drain region connected from the source / drain region of the first insulated gate field effect transistor to a gate of the first insulated gate field effect transistor of the third insulated gate field effect transistor A distance from the source / drain region of the first insulated gate field effect transistor to the source / drain region of the second insulated gate field effect transistor.

  A semiconductor integrated circuit device and an electronic card according to a fourth aspect of the present invention include a semiconductor region of a first conductivity type and a source of a second conductivity type formed in the semiconductor region of the first conductivity type and connected to an output terminal. And a first insulated gate field effect transistor having a drain region and a second conductivity type source formed in the first conductivity type semiconductor region and connected to the gate of the first insulated gate field effect transistor. And a second insulated gate field effect transistor having a drain region and driving the first insulated gate field effect transistor; and an emitter / short-circuited to the base based on the first conductivity type semiconductor region. A bipolar transistor having a collector region and an emitter / collector region connected to the gate of the first insulated gate field effect transistor. To. The distance from the source / drain region of the first insulated gate field effect transistor to the emitter / collector region connected to the gate of the first insulated gate field effect transistor of the bipolar transistor is equal to the distance The distance from the source / drain region of the first insulated gate field effect transistor to the source / drain region of the second insulated gate field effect transistor may be shorter.

  According to the present invention, it is possible to provide a semiconductor integrated circuit device capable of protecting the integrated circuit from destruction even when the integrated circuit is not connected to a ground point or a power supply, and an electronic card using the same.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In this description, common parts are denoted by common reference symbols throughout the drawings.

  Prior to the description of the embodiment, an unexpected situation assumed when the semiconductor integrated circuit device is not connected to a ground point or a power supply will be described.

  1A and 1B are diagrams for explaining an example of an unexpected situation.

  As shown in FIG. 1A, the electronic card 1 is placed on a grounded conductor (CONDUCTOR). The semiconductor integrated circuit device chip 2 in the electronic card 1 is not connected to a ground point or a power supply. It is assumed that, for example, a positively charged body, for example, a fingertip approaches the electronic card 1 in such a state. When the distance between the fingertip and the electronic card 1 becomes a certain distance, an aerial discharge occurs between the fingertip and the electronic card 1 as shown in FIG. 1B. As a result, the electronic card 1 and / or the chip 2 are charged and charged “positively”.

  2A and 2B are diagrams for explaining another example of the unexpected situation.

  Further, as shown in FIG. 2A, it is assumed that the electronic card 1 is, for example, positively charged. It is assumed that the electronic card 1 is dropped on, for example, a grounded conductor (CONDUCTOR). The chip 2 in the electronic card 1 is not connected to a ground point or a power source as in FIGS. 1A and 1B. Also in this case, when the distance between the electronic card 1 and the grounded conductor reaches a certain distance, air discharge occurs between the electronic card 1 and the grounded conductor. As a result, the electronic card 1 is discharged, contrary to the situation shown in FIGS. 1A and 1B.

  In the above situation, as long as the chip 2 is not connected to the ground point or the power supply, there is a limit in protecting the integrated circuit by using a protection circuit or a protection function of releasing an excessive current to the ground point or the power supply. For example, in a test standard according to MIL or EIAJ, a needle is brought into contact with an output terminal, and an excessive current flows through the semiconductor integrated circuit device over a period of several tens of nsec to several μsec. In order to satisfy such a standard, the protection circuit and the protection function release an excessive current to the ground point and the power supply over a period of several tens of nanoseconds to several microseconds. FIG. 3A shows the relationship between the current I and the time t when the needle is brought into contact with the output terminal.

  However, the above situation occurs when an excessive voltage is applied to the electronic card 1 and / or the chip 2 while the chip 2 is not connected to the ground point or the power supply, and as a result, the electronic card 1 itself and / or the chip 2 Or, an air discharge occurs between the contact point and the ground point. Such aerial discharge is considered to end in a few nsec or less, generally 1 nsec or less, and is much shorter than the test time by MIL or EIAJ. Moreover, the voltage is much higher than when an excessive current flows. FIG. 3B shows the relationship between voltage V and time t when air discharge occurs. FIG. 3B shows the relationship between the voltage V and the time t when the needle is brought into contact with the output terminal by a dotted line for comparison. It is difficult to overcome such an unexpected situation only with a protection circuit or a protection function that satisfies the MIL or EIAJ test standard.

  4A and 4B are circuit diagrams showing a semiconductor integrated circuit device according to a reference example of the present invention.

  4A and 4B show an output circuit portion of the chip 2 and show a state in which the chip 2 is connected to the ground point GND and the power supply VCC. This output circuit protects the integrated circuit when an excessive current flows to the output terminal PAD as follows.

  First, as shown in FIG. 4A, the needle 17 to which a positive potential is applied is brought into contact with the output terminal PAD, and is directed toward the drain D of the N-channel MOSFET N1 and the drain D of the P-channel MOSFET P1 of the output circuit. An excessive current I flows. In this case, the PN junction between the drain of the transistor P1 and the N-type well (or N-type semiconductor substrate) where the drain is formed is forward-biased, and an excessive current I flows to the power supply VCC.

  Conversely, the needle 17 to which a negative potential is applied is brought into contact with the output terminal PAD. In this case, as shown in FIG. 4B, the PN junction between the drain D of the transistor N1 and the P-type semiconductor substrate (or P-type well) on which this drain is formed is forward-biased, and the excessive current I is applied to the ground point. It flows from VSS to the output terminal PAD.

  Thus, the semiconductor integrated circuit device according to the reference example satisfies the MIL and EIAJ test standards and protects the integrated circuit from excessive current I.

  However, as shown in FIGS. 5A and 5B, when the chip 2 is not connected to the ground point GND and the power supply VCC, the present inventor has found that the following destruction mode exists.

  Assume that the chip 2 is positively charged for some reason as shown in FIGS. 5A and 5B. The grounded needle 17 is brought close to the output terminal PAD of the positively charged chip 2. Then, air discharge occurs between the output terminal PAD and the needle 17 (1). As a result, the potential of the drain D of the transistor N1 decreases, the P-type semiconductor substrate Psub is forward-biased, and a current flows between the drain D and the P-type semiconductor substrate. As a result, the substrate potential around the drain D decreases (2). This potential drop spreads inside the substrate via a wiring (ground line GND) connected to the ground point GND (3). This is because the ground line GND has the resistance RGND. This potential drop eventually reaches the drive circuit that drives the transistor N1. The drive circuit includes an N-channel MOS transistor N2. When the potential drop reaches around the drain D of the transistor N2, the drain D and the P-type semiconductor substrate break down (4). The drain D of the transistor N2 is connected to the gate of the transistor N1. Therefore, the gate of the transistor N1 is discharged, and the potential of the gate of the transistor N1 decreases (5).

  At this time, there is a time difference between the decrease in the potential of the drain D of the transistor N1 and the decrease in the potential of its gate. This is because the resistance RGND exists in the ground line GND, and the resistance RN also exists in the wiring connecting the drain of the transistor N2 and the gate of the transistor N1. As a result, the potential drop of the gate is delayed, and a potential difference A is temporarily generated between the drain D of the transistor N1 and the gate G thereof as shown in FIG. 5B. The gate insulating film of the transistor N1 needs to be able to withstand the potential difference A, but the potential difference in the case of air discharge is expected to reach several thousand volts, and destruction is inevitable.

  In this way, if the chip 2 is not connected to the ground point GND and the power supply VCC, and an unexpected event occurs, the integrated circuit is destroyed.

  Hereinafter, semiconductor integrated circuit devices capable of overcoming the unexpected situation will be described as first to fourth embodiments of the present invention.

(1st Embodiment)
FIG. 6A is a circuit diagram showing a semiconductor integrated circuit device according to the first embodiment of the present invention.

  As shown in FIG. 6A, the semiconductor integrated circuit device according to the first embodiment is an output circuit. This output circuit includes an output buffer 21 that drives the output terminal PAD, and a drive circuit 22 that drives the output buffer 21 based on a signal from inside the integrated circuit.

  The output buffer 21 has an N-channel insulated gate field effect transistor N1 having a drain connected to the output terminal PAD, a source and a back gate connected to the ground point GND, a drain connected to the output terminal PAD, and a source and a back gate. And a P-channel insulated gate field effect transistor P1 connected to the power supply VCC. An example of an insulated gate field effect transistor is a MOSFET. The gate of the transistor P1 and the gate of the transistor N1 are connected to the drive circuit 22, respectively.

  The drive circuit 22 has an N-channel insulated gate field effect transistor N2 having a drain connected to the gate of the transistor N1, a source and a back gate connected to the ground GND, and a drain connected to the gate of the transistor N1, and a source and a back. Includes a P-channel insulated gate field effect transistor P2 whose gate is connected to power supply VCC. The transistors N2 and P2 drive the transistor N1 of the output buffer 21 based on a signal from an internal integrated circuit (not shown).

  The drive circuit 22 has an N-channel insulated gate field effect transistor N3 having a drain connected to the gate of the transistor P1, a source and a back gate connected to the ground point GND, and a drain connected to the gate of the transistor P2. And a P-channel insulated gate field effect transistor P3 having a back gate connected to the power supply VCC. Similarly to the transistors N2 and P2, the transistors N3 and P3 drive the transistor P1 of the output buffer 21 based on a signal from an internal integrated circuit (not shown).

  Further, the output circuit according to the present embodiment includes a diode DN having a cathode connected to the gate of the transistor N1, an anode connected to the ground GND, a diode connected to the anode of the transistor P1, and a cathode connected to the power supply VCC. DP. The cathode of the diode DN is formed adjacent to the drain of the transistor N1, and the anode of the diode DP is formed adjacent to the drain of the transistor P2. FIG. 6B shows an example of the pattern plane.

  As shown in FIG. 6B, in the pattern plane according to the example, the transistors N1 and P1 and the output terminal PAD are arranged in a region between the ground line GND and the power supply line VCC. The ground line GND and the power supply line VCC are formed, for example, of a second layer metal. Output terminal PAD is arranged between transistors N1 and P1. The cathode of the diode DN is formed, for example, on the P-type semiconductor substrate Psub below the ground line GND, and is connected to the gate of the transistor N1 by a first layer metal closer to the substrate than the second layer metal. Similarly, the anode of the diode DP is formed in, for example, an N-type well Nwell below the power supply line VCC, and is connected to the gate of the transistor P1 by a first layer metal. Although not shown, the transistors N2, P2, N3, and P3 are arranged in regions other than the region where the transistors N1 and P1 are arranged. As a result, the distance from the drain of the transistor N1 to the cathode of the diode DN is shorter than the distance from the drain of the transistor N1 to the drain of the transistor N2. Similarly, the distance from the drain of the transistor P1 to the anode of the diode DP is shorter than the distance from the drain of the transistor P1 to the drain of the transistor P3.

  By providing such diodes DN and DP, it is possible to overcome the unexpected situation. Hereinafter, this will be described in detail.

  7A and 7B are diagrams illustrating an example of the protection operation of the semiconductor integrated circuit device according to the first embodiment of the present invention. In this example, it is assumed that the chip 2 is positively charged.

  As shown in FIGS. 7A and 7B, the grounded needle 17 is brought close to the output terminal PAD of the positively charged chip 2 to cause air discharge between the output terminal PAD and the needle 17 (1). The potential of the drain D of the transistor N1 decreases, the drain D and the P-type semiconductor substrate Psub are forward biased, a current flows between the drain D and the P-type semiconductor substrate, and the substrate potential around the drain D decreases ( 2). With the decrease in the substrate potential, the diode DN having the substrate Psub as an anode and the N-type semiconductor region N + formed adjacent to the drain D as a cathode breaks down (3). As a result, the gate potential of the transistor N1 decreases. This breakdown occurs after a reverse voltage in the reverse direction of the diode DN, generally a potential difference of about 15 V, but as described above, the voltage due to air discharge reaches several thousand volts. Therefore, breakdown occurs instantaneously. Further, since the cathode is formed adjacent to the drain of the transistor N1, the distance from the transistor N1 to the cathode is sufficiently small. Therefore, as compared with the reference example, the time difference between the decrease in the potential of the drain of the transistor N1 and the decrease in the potential of the gate of the transistor N1 can be further reduced. As a result, it can be considered that there is practically no potential difference between the drain D of the transistor N1 and its gate G. Therefore, even when the chip 2 is discharged in the air while the chip 2 is not connected to the ground point GND and the power supply VCC, the gate insulating film of the transistor N1 is not broken and the integrated circuit can be protected. .

  8A and 8B are diagrams showing another example of the protection operation of the semiconductor integrated circuit device according to the first embodiment of the present invention. In this other example, it is assumed that a positively charged member approaches the chip 2.

  As shown in FIGS. 8A and 8B, a positively charged needle 17 is brought close to the output terminal PAD of the chip 2 to cause air discharge between the output terminal PAD and the needle 17 (1). The potential of the drain D of the transistor P1 rises, the drain D and the N-type well Nwell are forward-biased, a current flows between the drain D and the N-type well, and the well potential around the drain D rises (2). . With the rise of the well potential, the diode DP having the well Nwell as a cathode and the P-type semiconductor region P + formed adjacent to the drain D as an anode breaks down (3). As a result, the gate potential of the transistor P1 increases. 7A and 7B, even if air discharge occurs toward the chip 2 while the chip 2 is not connected to the ground point GND and the power supply VCC, the gate of the transistor P1 is protected. The insulating film is not destroyed and the integrated circuit can be protected.

  The MIL and EIAJ test standards can be satisfied by the same protection operation as the semiconductor integrated circuit device according to the reference example.

  In the present embodiment, the diode is a PN junction diode, but a diode other than a PN junction diode can be used.

(2nd Embodiment)
FIG. 9 is a circuit diagram showing a semiconductor integrated circuit device according to the second embodiment of the present invention.

  As shown in FIG. 9, in the second embodiment, the diodes DN and DP described in the first embodiment are replaced with insulated gate field effect transistors NFET and PFET, respectively. An example of the insulated gate field effect transistor is, for example, a MOSFET. The mechanism by which the chip 2 is discharged or charged by air discharge is the same as in the first embodiment. In this example, the same effect as in the first embodiment can be obtained by utilizing the surface breakdown characteristics of the channel portion of the MOSFET.

  Surface breakdown occurs at a lower voltage than PN junction breakdown. According to the second embodiment, as compared with the first embodiment, it is possible to obtain an advantage that, among the protection margins, in particular, the protection margin related to the voltage is further expanded.

(Third embodiment)
FIG. 10 is a circuit diagram showing a semiconductor integrated circuit device according to the third embodiment of the present invention.

  As shown in FIG. 10, in the third embodiment, the diodes DN and DP described in the first embodiment are replaced with bipolar transistors QNPN and QPNP, respectively. Also in this embodiment, the mechanism by which the chip 2 is discharged or charged by air discharge is the same as in the first embodiment. In this example, the same effect as in the first embodiment can be obtained by utilizing the punch-through characteristics of the bipolar transistor.

  In the third embodiment, since the bipolar transistors QNPN and QPNP are turned on, it is advantageous to flow a large current. According to the third embodiment, it is possible to obtain an advantage that, among the protection margins, in particular, the protection margin related to the current is further expanded as compared with the first embodiment.

(Fourth embodiment)
Next, some layout examples of the semiconductor integrated circuit device according to the second embodiment will be described together with their structures as a fourth embodiment.

(First layout example)
11 is a plan view showing a first layout example of a semiconductor integrated circuit device according to a fourth embodiment of the present invention, FIG. 12 is a cross-sectional view taken along line 12-12 in FIG. 11, and FIG. It is sectional drawing which follows the -13 line. FIG. 14 is a plan view showing a state where the first metal layer and the second metal layer are removed from the plane shown in FIG. 11, and FIG. 15 is a plan view showing a state where the second metal layer is removed.

  As shown in FIGS. 11 to 15, an N-type well (N-well) 102 is formed in a P-type semiconductor substrate (P-substrate), for example, a P-type silicon substrate 100. An element isolation region 104 made of, for example, a silicon oxide film is formed in a surface region of the P-type silicon substrate 100 in which the N-type well 102 is formed. In this example, the element isolation region 104 separates the active regions 106 and 108 on the P-type silicon substrate 100 and separates the active regions 110 and 112 on the N-type well 102. The active regions 106 and 108 expose the surface of the P-type silicon substrate 100, and the active regions 110 and 112 expose the surface of the N-type well 102. The N-type source / drain diffusion layer 114 of the transistor N1 described in the second embodiment is formed in the active region 106, and the source / drain diffusion layer 116 of the transistor P1 is formed in the active region 110. Similarly, the source / drain diffusion layer 118 of the transistor NFET described in the second embodiment is formed in the active region 108, and the source / drain diffusion layer 120 of the transistor PFET is formed in the active region 112.

  A gate insulating film 122 made of, for example, a silicon oxide film is formed on the active regions 106, 108, 110, and 112, and a gate layer 124 is formed on the gate insulating film 122. The gate layer 124 is made of, for example, a conductive polysilicon film, a stacked structure film of a conductive polysilicon film and a silicide film, a stacked structure film of a conductive polysilicon film and a metal film, or a metal film. In this example, the gate layer 124 includes a gate electrode 124-N1 of the transistor N1, a gate electrode 124-P1 of the transistor P1, a gate electrode 124-NFET of the transistor NFET, and a gate electrode 124-PFET of the transistor PFET. Further, the planar shape of the gate electrode 124-N1 is U-shaped, and the transistor N1 has a structure including two transistors connected in parallel between the power supply line VCC and the output terminal PAD. Since the transistor N1 includes two transistors connected in parallel, the channel width of the transistor N1 is increased as compared with the case where the transistor N1 is a single transistor. By enlarging the channel width, the driving capability required to drive the output terminal PAD can be obtained. Note that the gate electrode P1 also has the same planar shape as the gate pattern -N1, and the transistor P1 has the same contrivance as the transistor N1.

  For example, a silicon oxide film is formed on the P-type silicon substrate 100 on which the element isolation region 104, the active regions 106, 108, 110, 112, the gate electrodes 124-N1, 124-P1, 124-NFET, and 124-PFET are formed. A first-layer interlayer insulating film 126 is formed. On the first interlayer insulating film 126, a first metal layer 128 is formed. In this example, the first metal layer 128 includes a wiring 128-N and a wiring 128-P. The wiring 128-N transmits a signal output from the transistor N2 or P2 of the driving circuit 22 to the gate electrode 124-N of the transistor N1, and the wiring 128-P is output from the transistor N3 or P3 of the driving circuit 22. The signal is transmitted to the gate electrode 124-P of the transistor P1.

  The wiring 128-N is connected to a drain of the source / drain diffusion layer 118 of the transistor NFET via a contact hole formed in the first interlayer insulating film 126 or a plug 130. Further, the wiring 128-N is connected to the gate electrode 124-N1 of the transistor N1 via a contact hole or a plug 132 formed in the first interlayer insulating film 126. The contact hole or plug 130 is connected to an output node (not shown) of the drive circuit 22 of the wiring 128-N, in this example, a common output node (not shown) of the transistor N2 and the transistor P2, and a contact hole or It is formed in a portion between the plug 132. Thereby, the drain of the transistor NFET is connected between the output node of the drive circuit 22 and the gate electrode 124-N1 of the transistor N1, and the protection effect described in the above embodiment can be obtained.

  Similarly, the wiring 128-P is connected to the drain of the source / drain diffusion layer 120 of the transistor PFET via a contact hole or a plug 134 formed in the first interlayer insulating film 126. Further, the wiring 128-P is connected to the gate electrode 124-P1 of the transistor P1 via a contact hole or a plug 136 formed in the first interlayer insulating film 126. The contact hole or plug 134 is connected to an output node (not shown) of the drive circuit 22 of the wiring 128-P, in this example, a common output node (not shown) of the transistor N3 and the transistor P3, It is formed in a portion between the plug 136 and the plug 136. Thereby, the protection effect described in the above embodiment can be obtained.

  On the first interlayer insulating film 126 on which the first metal layer 128 is formed, a second interlayer insulating film 138 made of, for example, a silicon oxide film is formed. On the first interlayer insulating film 138, a second metal layer 140 is formed. In this example, the second metal layer 140 includes the wirings 140-GND, 140-VCC and the wirings 140-PAD. The wiring 140-GND supplies the ground potential GND to the circuits in the semiconductor integrated circuit device chip, and the wiring 140-VCC supplies the power supply potential VCC to the circuits in the semiconductor integrated circuit device chip. The wiring 140-PAD transmits a signal output from the transistor N1 or P1 of the output buffer 21 to the output terminal PAD.

  The wiring 140-GND is connected to a source of the source / drain diffusion layer 118 of the transistor NFET through a contact hole formed in the first interlayer insulating film 126 and the second interlayer insulating film 138 or a plug 142. At the same time, the transistor NFET is connected to the gate electrode 124-NFET of the transistor NFET via the contact hole or the plug 144. The potential of the gate electrode 124-NFET of the transistor NFET and the potential of the source become the ground potential GND when energized, and are turned off. As a result of turning off the transistor NFET during energization, the wiring 128-N is not connected to the ground potential during normal operation, and malfunction of the integrated circuit is suppressed. Further, the wiring 140-GND is connected to the source / drain diffusion layer 114 of the transistor N1 via a contact hole or a plug 146 formed in the first interlayer insulating film 126 and the second interlayer insulating film 138. Connected to.

  The wiring 140-VCC is connected to the source of the source / drain diffusion layer 120 of the transistor PFET through a contact hole or a plug 148 formed in the first interlayer insulating film 126 and the second interlayer insulating film 138. At the same time, it is connected to the gate electrode 124-PFET of the transistor PFET via the contact hole or the plug 150. The potential of the gate electrode 124-PFET and the potential of the source of the transistor PFET become the power supply potential VCC when energized and are turned off. As a result of turning off the transistor PFET during energization, the wiring 128-P is not connected to the ground potential during normal operation, and malfunction of the integrated circuit is suppressed. Further, the wiring 140-VCC is connected to the source / drain diffusion layer 116 of the transistor P1 through a contact hole or a plug 152 formed in the first interlayer insulating film 126 and the second interlayer insulating film 138. Connected to.

  The wiring 140-PAD is connected to the drain of the source / drain diffusion layer 114 of the transistor N1 via a contact hole or a plug 154 formed in the first interlayer insulating film 126 and the second interlayer insulating film 138. At the same time, it is connected to the drain of the source / drain diffusion layer 116 of the transistor P1. A pad region 156 is provided between the contact hole or the plug 154 of the wiring 140-PAD. The portion of the pad region 156 is wider than the portion of the wiring 140-PAD other than the pad region 156, and has a fringe shape.

  On the second interlayer insulating film 138 on which the second metal layer 140 is formed, a passivation film 158 made of, for example, a silicon oxide film, a silicon nitride film, or an insulating polyimide film is formed. An opening 160 is formed in a portion of the passivation film 158 located on the pad region 156, and the pad region 156 is exposed. For example, a bonding pad, a solder ball electrode, or the like is formed on the exposed portion, and functions as an output terminal PAD.

  In the first layout example, an active region 108 is formed between the gate electrode 124-N1 of the transistor N1 and an output node (not shown) of the drive circuit 22, and a transistor NFET is formed in the active region 108 (particularly, , FIG. 14). Further, the drain of the NFET of the transistor is connected to a portion of the wiring 128-N1 between the output node of the drive circuit 22 and the contact hole or the plug 132 (particularly, see FIG. 15). Thereby, the drain of the transistor NFET is connected between the output node of the drive circuit 22 and the gate electrode 124-N1 of the transistor N1. The arrangement and structure of the transistor PFET are the same as the arrangement and structure of the transistor NFET.

  Therefore, according to the first layout example, as described in the above embodiment, the chip 2 is not connected to the ground point GND and the power supply VCC, and is connected to the chip 2 or from the chip 2, for example, in the air. Even when a discharge occurs, each of the gate insulating film 122 of the transistor N1 and the gate insulating film 122 of the transistor P1 can be protected from destruction.

(Second layout example)
FIG. 16 is a plan view showing a second layout example of the semiconductor integrated circuit device according to the fourth embodiment of the present invention, and FIG. 17 is a sectional view taken along line 17-17 in FIG. FIG. 18 is a plan view showing a state where the first metal layer and the second metal layer are removed from the plane shown in FIG. 16, and FIG. 19 is a plan view showing a state where the second metal layer is removed. . In the second layout example, the same parts as those in the first layout example are denoted by the same reference numerals, and only different parts will be described.

  The second layout example differs from the first layout example particularly in that the transistor NFET is formed in the active region 106 where the transistor N1 is formed, and the transistor PFET is formed in the active region 110 where the transistor P1 is formed. It was formed in.

  Further, in the second layout example, the source of the source / drain diffusion layer 118 of the transistor NFET is shared with the source of the transistor N1, and the source of the source / drain diffusion layer 120 of the transistor PFET is set to the source of the transistor P1. Share with. The shared source / drain diffusion layers are labeled 114/118 and 116/120, respectively.

  Further, the drain of the source / drain diffusion layer 118 of the transistor NFET is connected to the contact hole or the plug 132 via the contact hole or the plug 130 and the wiring 128-N. In the first layout example, the contact hole or plug 130 is formed between the output node (not shown) of the drive circuit 22 and the contact hole or plug 132 in the wiring 128-N. As in the example, the contact hole or plug 132 reaching the gate electrode 124-N1 is connected to the output hole (not shown) of the drive circuit 22 and the contact hole reaching the drain of the transistor NFET in the wiring 128-N. It may be formed between the plug 130. The same applies to the transistor PFET. A contact hole or a plug 136 reaching the gate electrode 124-P1 is connected to an output node (not shown) of the drive circuit 22 of the wiring 128-P and a contact hole reaching the drain of the transistor PFET. Or, it may be formed between the plug 134.

  In the second layout example, transistors NFET and PFET are formed in the active regions 106 and 110, respectively (particularly, see FIG. 18). Further, the drain of the transistor NFET is connected to the contact hole or plug 132 via the contact hole or plug 130 and the wiring 128-N1 (particularly, see FIG. 19). Thereby, the drain of the transistor NFET is connected to the gate electrode 124-N1 of the transistor N1. Similarly, the drain of the transistor PFET is connected to the contact hole or plug 136 via the contact hole or plug 134 and the wiring 128-P. Thus, the drain of the transistor PFET is connected to the gate electrode 124-P1 of the transistor P1.

  Therefore, according to the second layout example, similarly to the first layout example, for example, air discharge to or from the chip 2 in a state where the chip 2 is not connected to the ground point GND and the power supply VCC. Even when the above occurs, the gate insulating film 122 of the transistor N1 and the gate insulating film 122 of the transistor P1 can be protected from destruction.

  Further, according to the second layout example, the transistors NFET and PFET are formed in the active regions 106 and 110, respectively, so that the active regions 108 and 112 can be eliminated as compared with the first layout example. That is, according to the second layout example, since the active regions 108 and 112 are eliminated, an increase in the chip area due to the provision of the new transistors NFET and PFET can be suppressed as compared with the first layout example. , Can be obtained.

  Further, according to the second layout example, since the sources of the transistors NFET and PFET are shared with the sources of the transistors N1 and P1, an increase in the area of the active regions 106 and 110 can be suppressed.

(Third layout example)
FIG. 20 is a plan view showing a third layout example of the semiconductor integrated circuit device according to the fourth embodiment of the present invention, and FIG. 21 is a plan view showing a state where the second metal layer is removed from the plane shown in FIG. It is. In the third layout example, the same parts as those in the second layout example are denoted by the same reference numerals, and only different parts will be described.

  The third layout example differs from the second layout example, in particular, in that transistors NFET and PFET each include a plurality of transistors. In this example, as an example of a plurality, the transistor NFET includes two transistors NFET1 and NFET2, and the transistor PFET includes two transistors PFET1 and PFET2.

  The transistors NFET1 and NFET2 are connected in parallel between the common output node of the transistors N2 and P2 of the drive circuit 22 (the output node of the drive circuit 22) and the ground line GND. The gate electrode 124-NFET1 of the transistor NFET1 is connected to the wiring 140-GND (ground line GND), and similarly, the gate electrode 124-NFET2 of the transistor NFET2 is connected to the wiring 140-GND (ground line GND). . The drains of the source / drain diffusion layers 118 of the transistors NFET1 and NFET2 are shared. The gate width (channel width) of the transistor NFET1 and the gate width (channel width) of the NFET2 are both "WG" (see FIG. 21).

  The transistors PFET1 and PFET2 are connected in parallel between the common output node of the transistors N3 and P3 of the drive circuit 22 (the output node of the drive circuit 22) and the power supply line VCC. The gate electrode 124-PFET1 of the transistor PFET1 is connected to the wiring 140-VCC (power supply line VCC), and similarly, the gate electrode 124-PFET2 of the transistor PFET2 is connected to the wiring 140-VCC (power supply line VCC). . The drains of the source / drain diffusion layers 120 of the transistors PFET1 and PFET2 are shared. The gate width (channel width) of the transistor PFET1 and the gate width (channel width) of the PFET2 are both WG (see FIG. 21).

  The transistors N1 and P1 also include a plurality of transistors, for example, two transistors, and the layout pattern is the same as the first and second layout examples. However, in the third layout example, for convenience, the transistor N1 will be described in more detail as including the two transistors N11 and N12, and the transistor P1 similarly including the two transistors P11 and P12. The gate width (channel width) of each of the transistors N11, N12, P11, and P12 is also WG. In this example, the transistors N11, N12, NFET1, and NFET2 are arranged in the active region 106 in an array, and the transistors P11, P12, PFET1, and PFET2 are arranged in the active region 110 in an array. I have.

  FIG. 22 is an equivalent circuit diagram showing an equivalent circuit of the third layout example.

  As shown in FIG. 22, when the third layout example is represented by an equivalent circuit, the common source diffusion layers 114/118 of the transistors N11 and NFET1 are connected to the ground line 140-GND, and the source diffusion layer 114 of the transistor N12 is , Is connected to the ground line 140-GND, and the source diffusion layer 118 of the transistor NFET2 is connected to the ground line 140-GND.

  Similarly, the common source diffusion layer 116/120 of the transistors P11 and PFET1 is connected to the power supply line 140-VCC, the source diffusion layer 116 of the transistor P12 is connected to the power supply line 140-VCC, and the source diffusion of the transistor PFET2. The layer 120 is connected to the power line 140-VCC.

  Here, the source diffusion layer 114 of the transistor N12 and the source diffusion layer 118 of the transistor NFET2 may be considered to be “always connected” to the ground line 140-GND, but the source diffusion layers 114 and 118 are connected to the ground. It can be considered "arbitrary connection" for line 140-GND. Similarly, the source diffusion layer 116 of the transistor P12 and the source diffusion layer 120 of the transistor PFET2 can be considered as “arbitrarily connected” to the power supply line 140-VCC. With “arbitrary connection”, the transistor N1 can select one transistor N11 and two transistors N11 and N12 as necessary. Similarly, for the transistor NFET, the case of one transistor N11 and the case of two transistors N11 and N12 can be selected as necessary. Similarly, for the transistor P1, the case of one transistor P11 and the case of two transistors P11 and N12 can be selected as necessary. Similarly, for the transistor PFET, the case of one transistor PFET1 and the case of two transistors PFET1 and PFET2 can be selected as necessary. As a result, it becomes possible to adjust the current driving capability of the transistors N1 and P1 of the output buffer 21, and to adjust the short-circuiting capability (hereinafter referred to as protection capability) of a short-circuit element for short-circuiting between the substrate and the gate, for example, transistors NFET and PFET.

  The reason why the protection capability and the current driving capability are adjusted is to meet the demand that the device according to the present embodiment flexibly cope with various electronic products.

  The large amount of electric power generated by the "air discharge" proposed in the present invention varies depending on, for example, the amount of charge charged / stored in the electronic card. If the amount of accumulated charge is large, the power generated in "air discharge" tends to be large. The amount of accumulated charge will vary in various ways depending on, for example, the size of the electronic card or the material of the electronic card. That is, the amount of accumulated charge differs for each electronic product. In order to cope with the variation in the accumulated charge amount, the protection capability of the transistors NFET and PFET can be adjusted.

  The adjustment of the protection capability in this example corresponds to the increase or decrease in the number of transistors NFET and PFET. Briefly, for electronic products requiring high protection capability, the number of transistors NFET and PFET is increased to a plurality. In this example, the number may be two. For electronic products that do not require high protection capability, the number of transistors included in the transistors N1 and P1 is reduced. In this example, the number may be one.

  Similarly, the current driving capability required for the output buffer 21 varies for each electronic product. For electronic products that require high current driving capability, the number of transistors N1 and P1 may be plural, for example, two. For electronic products that do not require high current driving capability, transistors N1 and P1 may be used. May be reduced, for example, the number of transistors may be reduced to one.

  An example of “arbitrary connection” is that the source diffusion layers 114 and 118 are “connectable” to the ground line 140-GND, and the source diffusion layers 116 and 120 are “connected” to the power supply line 140-VCC. "Connectable". As an example of “connectable”, in this example, as shown in FIG. 22, between the source diffusion layer 114 and the ground line 140-GND, between the source diffusion layer 118 and the ground line 140-GND, Fuses F1, F2, F3, and F4 are arranged between the layer 116 and the power supply line 140-VCC and between the layer 116 and the source diffusion layer 120, respectively.

  The term “fuse” described in the present specification means not only a fuse that mechanically breaks an electrical connection by using a laser or a large current, but also an electrical connection by not forming at least one of a wiring and a contact. Methods that can structurally break an electrical connection, restore an electrically disconnected state to an electrically connected state, and determine / change other electrically connected / disconnected states. It is defined as including all.

  FIG. 23 is a diagram illustrating a relationship between the connection / non-connection state of the fuses F1, F2, F3, and F4, and the protection capability and the current driving capability. Note that the protection capability and the current driving capability are shown as the gate width (channel width) WG.

As shown in FIG. 23, in this example, 16 combinations (4 ² = 16) can be obtained for the combination of the protection capability and the current driving capability.

  In this example, up to two transistors N1, P1, NFET, and PFET can be “arbitrarily connected”, but the number of transistors is not limited to two, and the number is arbitrary. It is. For example, when it is desired to increase the number of transistors included in the transistor N1, the patterns of the transistors N11 and N12 shown in FIGS. 20 and 21 may be repeated. Similarly, when it is desired to increase the number of transistors included in the transistor NFET, the patterns of the transistors NFET1 and NFET2 may be repeated. The number of transistors P1 and PFET can be increased similarly to the case of transistors N1 and NFET.

  Next, some examples in which a transistor is electrically disconnected / connected will be described. Note that, in this description, an example in which the transistor NFET2 is electrically disconnected / connected, that is, an example in which the fuse F3 is disconnected / connected, is shown. However, the following description also applies to the fuses F1, F2, and F4. Examples can be applied.

(First example)
FIG. 24 is a plan view showing a first example of non-connection.

  As shown in FIG. 24, in the first example, a portion of the ground line 140-VCC connected to the source diffusion layer 118 of the transistor NFET2 and a contact hole connecting the ground line 140-VCC to the source diffusion layer 118 Or the plug 146 is structurally eliminated. In the layout pattern shown in FIG. 24, the source diffusion layer 118 of the transistor NFET2 is not connected to the ground line 140-VCC, so that the transistor NFET2 can be electrically disconnected.

  In the first example, whether the transistor NFET2 is electrically connected or not electrically connected is determined, for example, only by replacing a contact hole forming photomask and a second layer metal patterning photomask. good.

(Second example)
FIG. 25 is a plan view showing a second example of non-connection.

  As shown in FIG. 25, the second example is an example in which a portion of the ground line 140-VCC connected to the source diffusion layer 118 of the transistor NFET2 is structurally eliminated. There is a contact hole or plug 146 connecting the ground line 140-VCC to the source diffusion layer 118. Also in this structure, the transistor NFET2 can be electrically disconnected.

  In the second example, whether the transistor NFET2 is to be electrically connected or not to be electrically connected can be determined, for example, only by replacing the second-layer metal patterning photomask. The advantage of the second example is that the number of photomasks to be replaced is reduced by at least one compared to the first example.

(Third example)
FIG. 26 is a plan view showing a third example of non-connection.

  As shown in FIG. 26, the third example is an example in which the contact hole or plug 146 connecting the ground line 140-VCC to the source diffusion layer 118 is structurally eliminated. The pattern of the ground line 140-VCC is the same as the case where the transistor NFET2 is connected. Also in this structure, the transistor NFET2 can be electrically disconnected.

  In the third example, whether the transistor NFET2 is electrically connected or not electrically connected is determined by, for example, a contact hole penetrating the first interlayer insulating film 126 and the second interlayer insulating film 128. Only the forming photomask needs to be replaced. The advantage of the third example is that, like the second example, at least one photomask to be replaced is reduced as compared with the first example.

(Fourth example)
FIG. 27 is a plan view showing a fourth example of non-connection.

  As shown in FIG. 27, in the fourth example, a portion of the ground line 140-VCC connected to the source diffusion layer 118 of the transistor NFET2 (hereinafter referred to as a local ground line) has the same structure as the case of connecting the transistor NFET2. 140-VCC ') was mechanically broken. The local ground line 140-VCC 'can be destroyed by using, for example, a laser or a focused ion beam used in a fuse blowing step of a semiconductor integrated circuit device. Even in this case, the transistor NFET2 can be electrically disconnected.

  In the fourth example, there is no need to replace the semiconductor manufacturing photomask. The local ground line 140-VCC may be destroyed in the fuse blowing step or at the final stage in the wafer process. This is an advantage of the fourth example.

(Fifth example)
FIG. 28 is a plan view showing a fifth example of non-connection.

  As shown in FIG. 28, in the fifth example, a ground line 140-VCC and a portion of the ground line 140-VCC connected to the source diffusion layer 118 of the transistor NFET2 (hereinafter referred to as a local ground line 140-VCC ') ) Are structurally separated from each other. The final structure is very similar to the fourth example. The difference is that in the fourth example, the local ground line 140-VCC 'is separated from the ground line 140-VCC' by mechanically breaking the local ground line 140-VCC '. On the other hand, in the fifth example, the local ground line 140-VCC 'is formed in a state separated from the ground line 140-VCC using, for example, a photomask for second layer metal patterning.

  In the fifth example, as in the second example, the transistor NFET2 can be electrically disconnected only by replacing the second-layer metal patterning photomask alone.

  Further, in the fifth example, the following usage can be performed.

  The completed state of the device is a state where the local ground line 140-VCC 'is separated from the ground line 140-VCC. Since the separated state is a completed state, when adjusting the protection capability, the local ground line 140-VCC 'may be connected to the ground line 140-VCC. That is, in the fifth example, the local ground line 140-VCC 'can be used as a state connectable to the ground line 140-VCC'.

  When connecting the local ground line 140-VCC 'to the ground line 140-VCC, for example, as shown in FIG. 29, another conductive layer 200 is formed on the separated portion, and the electrical connection is made. I just want to revive.

  An advantage of the example in which the electrical connection is restored is that even if the protection capability is found to be insufficient after completion, the device can be rescued without destroying the device. Even when the driving capability of the transistors N1 and P1 is insufficient, the same can be relieved.

  Further, the example of restoring the electrical connection can be used not only in the fifth example but also in the fourth example. The advantage of using the fourth example is that even if the local ground line 140-VCC 'is erroneously destroyed, the erroneously destroyed device can be rescued. In the case of erroneous destruction of the transistors N1 and P1, it can be similarly rescued.

  Note that the first to fifth examples can be applied in various combinations.

(Fourth layout example)
FIG. 30 is a diagram showing a basic layout of a third layout example of the semiconductor integrated circuit device according to the fourth embodiment of the present invention, and FIG. 31 is a fourth layout of the semiconductor integrated circuit device according to the fourth embodiment of the present invention. It is a figure showing the basic layout of an example.

  As shown in FIG. 30, in the third layout example, transistors N11, N12, NFET1, NFET2, P11, P12, PFET1, and PFET2 having a gate width (channel width) WG, that is, a plurality of transistors are connected in the gate length direction. Is arranged in an array along the basic layout.

  On the other hand, in the fourth layout example, as shown in FIG. 31, the transistors N11, N12, NFET1, NFET2, P11, P12, PFET1, and PFET2 are arranged in an array along the gate length direction. The basic layout is to separate a plurality of pieces along the gate width direction. In the fourth layout example, the transistor N1 includes four transistors N111, N112, N121, and N122. Hereinafter, similarly, the transistor NFET includes four transistors NFET11, NFET12, NFET21, and NFET22, the transistor P1 includes four transistors P111, P112, P121, and P122, and the transistor PFET includes four transistors PFET11, PFET12, and PFET21 and PFET22 are included. The gate width (channel width) of each of these 16 transistors is “WG / 2” in this example.

  In the fourth layout example, transistors N111, N112, N121, N122, NFET11, NFET12, NFET21, NFET22, P111, P112, P121, P122, P122, PFET11, PFET12, PFET21, and PFET22 having a gate width (channel width) WG / 2 are formed. That is, the basic layout is to arrange a plurality of transistors in a matrix along the gate length direction and the gate width direction crossing the gate length direction.

  FIG. 32 is a plan view showing a fourth layout example of the semiconductor integrated circuit device according to the fourth embodiment of the present invention, and FIG. 33 is a plan view showing a state where a second metal layer is removed from the plane shown in FIG. It is. The difference between the fourth layout example and the third layout example is as described above. 32 and 33, the same portions as those in FIGS. 20 and 21 are denoted by the same reference numerals, and description thereof will be omitted.

  FIG. 34 is an equivalent circuit diagram showing an equivalent circuit of the fourth layout example.

  As shown in FIG. 34, when the fourth layout example is represented by an equivalent circuit, the common source diffusion layers 114/118 of the transistors N111 and NFET11 are connected to the ground line 140-GND. Source diffusion layer 114 of transistor N121 is connected to ground line 140-GND via fuse F12. Source diffusion layer 118 of transistor NFET 21 is connected to ground line 140-GND via fuse F32. The common drain diffusion layer 118 of the transistors NFET11 and NFET21 is connected to a wiring 128-N to which a signal output from the transistor N2 or P2 is transmitted. The common drain diffusion layer 114 of the transistors N111 and N121 is connected to a wiring 140-PAD connected to a pad.

  The common source diffusion layers 114/118 of the transistors N112 and NFET12 are connected to the ground line 140-GND. Source diffusion layer 114 of transistor N122 is connected to ground line 140-GND via fuse F12. Source diffusion layer 118 of transistor NFET 22 is connected to ground line 140-GND via fuse F32. Source diffusion layer 118 of transistor NFET 22 is connected to ground line 140-GND via fuse F32. The common drain diffusion layer 118 of the transistors NFET12 and NFET22 is connected to the wiring 128-N via the fuse F31. The common drain diffusion layer 114 of the transistors N112 and N122 is connected to the wiring 140-PAD via the fuse F11.

  Note that regarding the connection of the transistors P111, P121, P112, P122, PFET11, PFET12, PFET21, and PFET22, the ground line 140-GND is replaced with the power supply line 140-VCC, and the wiring 128-N is replaced with the wiring 128-P. If it is almost good, the description will be omitted with reference to the drawings.

  FIG. 35 is a diagram showing the relationship between the connection / non-connection state of the fuses F11, F12, F21, F22, F31, F32, F41, and F42, and the protection capability and the current driving capability. Note that the protection capability and the current driving capability are shown as the gate width (channel width) WG.

In this example, 64 combinations (8 ² = 64) can be obtained for the combination of the protection capability and the current driving capability. However, FIG. 35 shows only the 16 main combinations.

  The advantage of this example is that the protection capability can be adjusted more finely than in the third layout example. For example, in the third layout example, the minimum adjustment unit of the protection capability is “WG”, but in the fourth layout example, the minimum adjustment unit is reduced to “WG / 2”. Reference is made to the columns of the fuses F41 and F42 and the column of the protection capability PFET in FIG. According to the combination of connection (0) / non-connection (1) of the fuses F41 and F42, the protection capability of the PFET can be adjusted in four stages of 2WG, 1.5WG and 0.5WG.

  In this example, the transistor N1, P1, NFET, or PFET is a matrix of "2" in the gate width direction and "2" in the gate length direction, that is, a matrix of 2 columns × 2 rows. And the number of rows are not limited to “2”. For example, when “4” is set in the gate width direction, the minimum adjustment unit is “WG / 4”, and the adjustment accuracy is increased. To increase the adjustment accuracy, the number of transistors arranged in the gate width direction may be increased. Further, when the value is set to "4" in the gate length direction, the maximum protection capability becomes "4WG", and the adjustable range is expanded. To increase the adjustable range, the number of transistors arranged in the gate length direction may be increased. These may be appropriately combined.

  As is common to the third and fourth layout examples, the adjustment of the protection capability and the adjustment of the current driving capability may be achieved at the same time, but the adjustment of only the protection capability and the adjustment of only the current driving capability are achieved. You may do it.

  Next, some examples in which a transistor is electrically disconnected / connected will be described. In this description, an example in which the transistor NFET 22 is electrically disconnected, that is, an example in which the fuse F31 is disconnected / connected, is shown. However, the fuses F11, F12, F21, F22, F31, F32, The following example can be applied to F41 and F42.

(First example)
FIG. 36 is a plan view showing a first example of non-connection.

  The example shown in FIG. 36 is obtained by applying the first example shown in FIG. 24 to the device according to the fourth embodiment. In FIG. 36, the same parts as those in FIG. 24 are denoted by the same reference numerals, and description thereof will be omitted.

(Second example)
FIG. 37 is a plan view showing a second example of non-connection.

  The example shown in FIG. 37 is obtained by applying the second example shown in FIG. 25 to the device according to the fourth embodiment. In FIG. 37, the same portions as those in FIG. 25 are denoted by the same reference numerals, and description thereof will be omitted.

(Third example)
FIG. 38 is a plan view showing a third example of non-connection.

  The example shown in FIG. 38 is obtained by applying the third example shown in FIG. 26 to the device according to the fourth embodiment. In FIG. 38, the same portions as those in FIG. 26 are denoted by the same reference numerals, and description thereof will be omitted.

(Fourth example)
FIG. 39 is a plan view showing a fourth example of non-connection.

  The example shown in FIG. 39 is obtained by applying the fourth example shown in FIG. 27 to the device according to the fourth embodiment. In FIG. 39, the same portions as those in FIG. 27 are denoted by the same reference numerals, and description thereof will be omitted.

(Fifth example)
FIG. 40 is a plan view showing a fifth example of non-connection. FIG. 41 is a plan view showing an example of the connection.

  The examples shown in FIGS. 40 and 41 are obtained by applying the fourth example shown in FIGS. 28 and 29 to the device according to the fourth embodiment. 40 and 41, the same parts as those in FIGS. 28 and 29 are denoted by the same reference numerals, and description thereof will be omitted.

  Although the third and fourth layout examples show the adjustment of the gate width WG, the example of the adjustment of the gate width WG is not limited to the above example. In addition to the adjustment of the gate width WG, the gate length may be adjusted. Further, the number of wiring layers is not limited to the above-described first to fourth layout examples.

(Test example)
Next, a test example of an electronic card that reproduces the unexpected situation shown in FIGS. 1A, 1B, 2A, and 2B will be described.

  FIG. 42A is a diagram illustrating a charging test for charging an electronic card and / or a chip.

  As shown in FIG. 42A, a conductive plate (conductive plate) 12 is placed on an insulator (insulator) 11, and the electronic card 1 is placed on the conductive plate 12. The conductive plate 12 is grounded. Next, the power supply 13 is connected to the battery 14 via the relay 15, and the battery 14 is charged. The power supply 13 generates a voltage of several tens of kV, for example, a voltage of 15 kV. The battery 14 has a capacity of several hundred pF, for example, a capacity of 100 pF. When charging is completed, the battery 12 is connected to one end of the resistor 16 via the relay 15. The resistor 16 has a resistance of several kΩ, for example, 1.5 kΩ, and the other end is connected to the needle 17. The needle 17 is moved closer to the electronic card 1. When the distance between the needle 17 and the electronic card 1 reaches a certain distance, air discharge occurs between the needle 17 and the electronic card 1, and the electronic card 1 and / or a chip in the card are charged. Thus, the unexpected situation shown in FIGS. 1A and 1B is reproduced.

  FIG. 42B is a diagram showing a discharge test for discharging an electronic card and / or a chip.

  As shown in FIG. 42B, for example, the electronic card 1 charged by the test of FIG. 42A is placed on the insulator 11. This time, the grounded needle 17 is brought closer to the electronic card 1. When the distance between the needle 17 and the electronic card 1 reaches a certain distance, air discharge occurs between the needle 17 and the electronic card 1, and the electronic card 1 and / or a chip in the card are discharged. Thereby, the unexpected situation shown in FIGS. 2A and 2B is reproduced.

  In addition, in the present charge test example and discharge test example, an example is shown in which the needle 17 is brought closer to the external terminal 3 of the electronic card 1. However, the test is performed not only on the external terminal 3 but also in FIGS. 42A and 42B. As shown by the dotted circle, the measurement was performed on the side surface of the electronic card 1 and the front and back surfaces of the electronic card. This is because it is impossible to predict where in the market the air discharge occurs in the electronic card 1.

  In each of the tests, the electronic card 1 including the semiconductor integrated circuit devices according to the first to third embodiments did not break down and operated normally.

  Therefore, the semiconductor integrated circuit devices according to the first to fourth embodiments and the electronic card using the same can protect the integrated circuit from destruction even when the integrated circuit is not connected to a ground point or a power supply. The advantage can be obtained.

(Application Example 1)
The semiconductor integrated circuit devices according to the first to fourth embodiments may, of course, be incorporated in an electronic product, but are particularly preferably incorporated in an electronic card. Electronic cards are carried or carried by humans. For this reason, there is a high possibility that the aforementioned unexpected situation will be encountered.

  One example of an electronic card is a memory card. The memory card has a nonvolatile semiconductor storage device as a main storage unit. Examples of the nonvolatile semiconductor memory device include a NAND flash memory and an AND flash memory. The output circuits described in the first to fourth embodiments can be used for output circuits of a NAND flash memory and an AND flash memory. 43A and 43B show an example of a NAND flash memory.

  FIG. 43A is a block diagram showing an example of a NAND EEPROM, and FIG. 43B is a circuit diagram showing an example of a memory cell array of the NAND EEPROM.

  The output circuits described in the first to fourth embodiments can be used, for example, as output circuits connected to I / O pins (I / O1 to I / O8) shown in FIG. 43A.

  Further, some memory cards incorporate not only a nonvolatile semiconductor memory device as a main memory but also a memory controller for controlling the nonvolatile semiconductor memory device. The output circuits described in the first to fourth embodiments can also be used for output circuits connected to I / O pins of the memory controller.

  Hereinafter, a specific example of the memory card will be described.

(First example of memory card)
FIG. 44 is a block diagram showing a first example of the memory card.

  As shown in FIG. 44, the memory card according to the first example includes only the nonvolatile semiconductor memory device 300. The pad PAD of the nonvolatile semiconductor memory device 300 is connected to the card terminal 302. The output circuit with protection function 304 described in the first to fourth embodiments is connected to the PAD of the nonvolatile semiconductor memory device 300 connected to the card terminal 302.

(Second example of memory card)
FIG. 45 is a block diagram showing a second example of the memory card.

  As shown in FIG. 45, the memory card according to the second example includes a nonvolatile semiconductor memory device 300 and a controller 306. The pad PAD of the nonvolatile semiconductor memory device 300 is connected to the PAD of the controller 306. For example, another pad PAD of the controller 306 is connected to the card terminal 302. The output circuit with protection function 304 is connected to the PAD of the controller 306 connected to the card terminal 302.

(Third example of memory card)
FIG. 46 is a block diagram showing a third example of the memory card.

  As shown in FIG. 46, the memory card according to the third example includes a nonvolatile semiconductor memory device 300 and a controller 306 as in the second example. The third example is different from the second example in that the output circuit with protection function 304 is also connected to the PAD of the nonvolatile semiconductor memory device 300 connected to the controller 306. The nonvolatile semiconductor memory device 300 and the controller 306 are connected to wiring on the circuit board 308 to form one system. The wiring of the circuit board 308 includes, for example, a power supply wiring VCC and a ground wiring GND. The nonvolatile semiconductor memory device 300 and the controller 306 are electrically coupled to each other through the power supply wiring VCC and the ground wiring GND. I have. When air discharge occurs in the card terminal 302, a large current flows through the output circuit 304 of the controller 306. Since this large current also flows through the semiconductor substrate or the well, there is a possibility that the large current reaches the semiconductor substrate or the well of the nonvolatile semiconductor memory device 300 via the power supply wiring VCC or the ground wiring GND. Considering an unexpected situation, even in a system in which the nonvolatile semiconductor memory device 300 is not directly connected to the card terminal 302 as in the third example, the output circuit 304 with the protection function is provided in the nonvolatile semiconductor memory device 300. It would be good to have it.

  Although the controller 306 is shown in the second and third examples, the controller 306 may be replaced with, for example, an interface circuit for electrically connecting the nonvolatile semiconductor memory device 300 to an electronic product. Is also good. Further, all the systems may be integrated on one semiconductor integrated circuit device chip.

(Fourth example of memory card)
In the first to third examples of the memory card, the memory cards are systematically classified. In the following example, memory cards are structurally classified.

  FIG. 47 is an exploded sectional view showing a fourth example of the memory card.

  As shown in FIG. 47, in the memory card according to the fourth example, the nonvolatile semiconductor memory package or the nonvolatile semiconductor memory module package 314 is directly attached to the bottom of the package mounting hole 312 provided in the card base 310. This is an example. A semiconductor integrated circuit device chip 316 is housed in the package 314. The chip 316 is the nonvolatile semiconductor memory device 300 described in the first to third examples, or the controller described in the second and third examples. That is, the chip 316 is the semiconductor integrated circuit device described in the first to fourth embodiments.

  The semiconductor integrated circuit devices according to the first to fourth embodiments can be used for a memory card having a structure in which the package 314 is directly attached to the bottom of the mounting hole 312.

(Fifth example of memory card)
FIG. 48 is an exploded sectional view showing a fifth example of the memory card.

  As shown in FIG. 48, the memory card according to the fifth example includes a package mounting hole 312 provided in the card base 310, an adhesive portion 318 formed in a step shape around the mounting hole 312, and a package 314. This is an example in which the formed fringe 320 is attached. A chip 316 in the package 314 is the semiconductor integrated circuit device described in the first to fourth embodiments.

  The semiconductor integrated circuit devices according to the first to fourth embodiments can be used for a memory card having a structure in which the fringe 320 of the package 314 is attached to an adhesive portion 318 formed around the mounting hole 312.

(Sixth example of memory card)
FIG. 49 is an exploded sectional view showing a fifth example of the memory card.

  As shown in FIG. 50, in the memory card according to the sixth example, the package 314 is connected to the circuit board 308, the circuit board 308 is adhered to the card base 310, and the circuit board 308 is provided on the card base 310. Are electrically connected to each other using a bonded wire 322. Further, a cover 324 is adhered to the card base 310 to shield the package 314 from the outside. A chip 316 in the package 314 is the semiconductor integrated circuit device described in the first to fourth embodiments.

  The semiconductor integrated circuit devices according to the first to fourth embodiments can be used for a memory card having a structure in which the package 314 is shielded from the outside.

(Application 2)
In application example 2, some examples of an application using the electronic card according to the embodiment of the present invention will be described.

  FIG. 50 is a perspective view showing an example of an electronic device using the IC card according to the embodiment of the present invention. FIG. 50 illustrates a portable electronic device, for example, a digital still camera, as an example of the electronic device. The IC card according to the embodiment is, for example, a memory card, and is used, for example, as a recording medium of a digital still camera.

  As shown in FIG. 50, a housing of the digital still camera 71 houses a card slot 72 and a circuit board connected to the card slot 72. The circuit board is not shown in FIG. The memory card 70 is detachably attached to a card slot 72 of a digital still camera 71. The memory card 70 is electrically connected to an electronic circuit on a circuit board by being inserted into the card slot 72.

  FIG. 51 is a block diagram showing a basic system of a digital still camera.

  Light from the subject is collected by the lens 73 and input to the imaging device 74. The imaging device 74 photoelectrically converts the input light into, for example, an analog signal. One example of the imaging device 74 is a CMOS image sensor. The analog signal is amplified by an analog amplifier (AMP.) And then converted into a digital signal by an A / D converter (A / D). The digitized signal is input to the camera signal processing circuit 75, and after being subjected to, for example, automatic exposure control (AE), automatic white balance control (AWB), and color separation processing, is converted into a luminance signal and a color difference signal. You.

  When monitoring an image, a signal output from the camera signal processing circuit 75 is input to a video signal processing circuit 76 and converted into a video signal. Examples of the video signal format include the NTSC (National Television System Committee). The video signal is output to a display unit 78 attached to the digital still camera 71 via a display signal processing circuit 77. One example of the display unit 78 is a liquid crystal monitor. The video signal is output to a video output terminal 80 via a video driver 79. An image captured by the digital still camera 71 can be output to an image device, for example, a display or a television of a personal computer, via the video output terminal 80, and the captured image can be enjoyed outside the display unit 78. The microcomputer 81 controls the imaging device 74, the analog amplifier (AMP.), The A / D converter (A / D), and the camera signal processing circuit 75.

  When capturing an image, an operation button, for example, a shutter button 82 is pressed. Thus, the microcomputer 81 controls the memory controller 83, and the signal output from the camera signal processing circuit 75 is written to the video memory 84 as a frame image. The frame image written in the video memory 84 is compressed by a compression / decompression processing circuit 85 based on a predetermined compression format, and is recorded on a memory card 70 mounted in a card slot 72 via a card interface 86.

  When playing back the recorded image, the image recorded on the memory card 70 is read out via the card interface 86, expanded by the compression / expansion processing circuit 85, and then written into the video memory 84. The written image is input to the video signal processing circuit 76, and is displayed on the display unit 78 and an image device as in the case of monitoring the image.

  In the basic system example, a card slot 72, an imaging device 74, an analog amplifier (AMP.), An A / D converter (A / D), a camera signal processing circuit 75, and a video signal processing circuit 76 are provided on a circuit board 89. , A display signal processing circuit 77, a video driver 79, a microcomputer 81, a memory controller 83, a video memory 84, a compression / decompression processing circuit 85, and a card interface 86. Note that the card slot 72 does not need to be mounted on the circuit board 89, and may be connected to the circuit board 89 by a connector cable or the like. In this example, a power supply circuit 87 is further mounted on the circuit board 89. The power supply circuit 87 receives power supply from an external power supply or a battery and generates an internal power supply used inside the digital still camera 71. One example of the power supply circuit 87 is a DC-DC converter. The internal power is supplied to each of the above circuits as an operating power, a power for the strobe 88, and a power for the display unit 78.

  As described above, the IC card according to the embodiment of the present invention can be used for a portable electronic device, for example, a digital still camera.

  The IC card according to the embodiment of the present invention is used not only for a digital still camera but also for a video camera (FIG. 52A) and a television (FIG. 52A) as shown in FIGS. 52A to 52F and 53A to 52F. 52B), audio / visual equipment (FIG. 52C), audio equipment (FIG. 52D), game equipment (FIG. 52E), electronic musical instrument (FIG. 52F), mobile phone (FIG. 53A), personal computer (FIG. 53B), personal digital It can also be used for an assistant (PDA, FIG. 53C), a voice recorder (FIG. 53D), a PC card (FIG. 53E), an electronic book terminal (FIG. 53F), and the like.

  The electronic card 1 can be roughly classified into, for example, a contact electronic card having the external terminal 3 and a non-contact electronic card having no external terminal 3. The semiconductor integrated circuit devices according to the above-described first to fourth embodiments can be incorporated into either a contact-type electronic card or a non-contact-type card, but air discharge is a phenomenon that tends to occur in a contact-type electronic card. It is guessed. This is because, in the contact-type electronic card, the external terminals 3 that are conductive are exposed from the card surface. As described in the test example section, it is not possible to completely predict where on the electronic card the air discharge will occur in the market, but it is generally more conductive than a card outer body that is an insulator. Is likely to occur for the external terminal 3 which is The external terminal 3 is connected to the output terminal PAD of the chip 2. Therefore, when air discharge occurs in the external terminal 3, an unexpected situation as described in the section of the embodiment occurs. Therefore, the advantages of the above embodiment can be effectively obtained in a contact-type electronic card.

  Furthermore, the possibility of air discharge occurring in the contact-type electronic card will also depend on the ratio of the area of the external terminals 3 to the card size. If the area of the external terminals 3 occupying the card size is large, the conductive material is widely exposed from the card surface, and the possibility of air discharge is increased. For example, in the electronic card 1, there is a case where the ratio of the area of the external terminal 3 to the card size exceeds 25% (for example, see the perspective views of FIGS. 38A and 38B). As described above, in the electronic card 1 in which the area ratio of the external terminals 3 to the card size exceeds 25%, the advantages of the above embodiment can be more effectively obtained.

  Of course, the semiconductor integrated circuit devices according to the first to fourth embodiments are used only for contact electronic cards and contact electronic cards in which the area of the external terminals 3 in the card size exceeds 25%. Instead, the present invention can be used for a non-contact type electronic card and a contact type electronic card in which the area ratio of the external terminal 3 to the card size is 25% or less. This is because it cannot be asserted that the unexpected situation does not occur in these cards. Therefore, the semiconductor integrated circuit device according to the first to fourth embodiments is also used for a non-contact type electronic card and a contact type electronic card in which the area of the external terminals 3 in the card size is 25% or less. However, the advantages of the above embodiment can be obtained.

  As described above, the present invention has been described with reference to the first to fourth embodiments. However, the present invention is not limited to each of the embodiments, and various modifications may be made without departing from the spirit of the present invention. It is possible.

  Each of the above embodiments can be implemented alone, but can be implemented in combination as appropriate.

  The above embodiments include various stages of the invention, and various stages of the invention can be extracted by appropriately combining a plurality of components disclosed in each embodiment.

1A and 1B are diagrams for explaining an example of an unexpected situation. 2A and 2B are diagrams for explaining another example of an unexpected situation. FIG. 3A is a diagram showing the relationship between the current I and the time t when the needle is brought into contact with the output terminal, and FIG. 3B is a diagram showing the relationship between the voltage V and the time t when air discharge occurs. 4A and 4B are circuit diagrams showing a semiconductor integrated circuit device according to a reference example of the present invention. FIG. 5A is a circuit diagram showing a semiconductor integrated circuit device according to a reference example of the present invention, and FIG. 5B is a sectional view thereof. FIG. 6A is a circuit diagram showing a semiconductor integrated circuit device according to the first embodiment of the present invention, and FIG. 6B is a plan view showing an example of a plane pattern thereof. 7A and 7B are diagrams showing an example of a protection operation of the semiconductor integrated circuit device according to the first embodiment of the present invention, respectively. 8A and 8B are diagrams showing another example of the protection operation of the semiconductor integrated circuit device according to the first embodiment of the present invention. FIG. 9 is a circuit diagram showing a semiconductor integrated circuit device according to a second embodiment of the present invention. FIG. 10 is a circuit diagram showing a semiconductor integrated circuit device according to a third embodiment of the present invention. FIG. 11 is a plan view showing a first layout example of a semiconductor integrated circuit device according to a fourth embodiment of the present invention. FIG. 12 is a sectional view taken along line 12-12 in FIG. FIG. 13 is a sectional view taken along line 13-13 in FIG. FIG. 14 is a plan view showing a state where the first metal layer and the second metal layer are removed from the plane shown in FIG. FIG. 15 is a plan view showing a state where the second metal layer is removed from the plane shown in FIG. FIG. 16 is a plan view showing a second layout example of the semiconductor integrated circuit device according to the fourth embodiment of the present invention. FIG. 17 is a sectional view taken along the line 17-17 in FIG. FIG. 18 is a plan view showing a state where the first metal layer and the second metal layer are removed from the plane shown in FIG. FIG. 19 is a plan view showing a state where the second metal layer is removed from the plane shown in FIG. FIG. 20 is a plan view showing a third layout example of the semiconductor integrated circuit device according to the fourth embodiment of the present invention. FIG. 21 is a plan view showing a state where the second metal layer is removed from the plane shown in FIG. FIG. 22 is an equivalent circuit diagram showing an equivalent circuit of the third layout example. FIG. 23 is a diagram showing the relationship between the connection / non-connection state of the fuse, the protection capability, and the current driving capability. FIG. 24 is a plan view showing a first example of non-connection. FIG. 25 is a plan view showing a second example of non-connection. FIG. 26 is a plan view showing a third example of non-connection. FIG. 27 is a plan view showing a fourth example of non-connection. FIG. 28 is a plan view showing a fifth example of non-connection. FIG. 29 is a plan view showing an example of connection FIG. 30 is a diagram showing a basic layout of a third layout example of the semiconductor integrated circuit device according to the fourth embodiment of the present invention. FIG. 31 is a diagram showing a basic layout of a fourth layout example of the semiconductor integrated circuit device according to the fourth embodiment of the present invention. FIG. 32 is a plan view showing a fourth layout example of the semiconductor integrated circuit device according to the fourth embodiment of the present invention. FIG. 33 is a plan view showing a state where the second metal layer is removed from the plane shown in FIG. FIG. 34 is an equivalent circuit diagram showing an equivalent circuit of the fourth layout example. FIG. 35 is a diagram showing a relationship between the connection / non-connection state of the fuse and the protection capability and the current driving capability. FIG. 36 is a plan view showing a first example of non-connection FIG. 37 is a plan view showing a second example of non-connection. FIG. 38 is a plan view showing a third example of non-connection. FIG. 39 is a plan view showing a fourth example of non-connection. FIG. 40 is a plan view showing a fifth example of non-connection. FIG. 41 is a plan view showing an example of connection FIG. 42A is a perspective view showing a charge test example, and FIG. 42B is a perspective view showing a discharge test example. FIG. 43A is a block diagram showing an example of a NAND EEPROM, and FIG. 43B is a circuit diagram showing an example of a memory cell array of the NAND EEPROM. FIG. 44 is a block diagram showing a first example of a memory card. FIG. 45 is a block diagram showing a second example of the memory card. FIG. 46 is a block diagram showing a third example of the memory card. FIG. 47 is an exploded sectional view showing a fourth example of the memory card. FIG. 48 is an exploded sectional view showing a fifth example of the memory card. FIG. 49 is an exploded sectional view showing a sixth example of the memory card. FIG. 50 is a perspective view showing an example of an electronic device using the IC card according to one embodiment of the present invention. FIG. 51 is a block diagram showing a basic system of a digital still camera. FIGS. 52A to 52F are diagrams showing other examples of an electronic device using an IC card according to an embodiment of the present invention. 53A to 53F are views showing other examples of the electronic device using the IC card according to one embodiment of the present invention.

Explanation of reference numerals

  DESCRIPTION OF SYMBOLS 1 ... Electronic card, 2 ... Semiconductor integrated circuit device chip, 3 ... Card external terminal, 21 ... Output buffer, 22 ... Output buffer drive circuit, P1-P3, PFET ... P-channel insulated gate field effect transistor, N1-N3, NFET: N-channel insulated gate field effect transistor, QPNP: PNP bipolar transistor, QNPN: NPN bipolar transistor

Claims (12)

A first conductivity type semiconductor region;
A first insulated gate field effect transistor formed in the first conductivity type semiconductor region and having a second conductivity type source / drain region connected to an output terminal;
A second conductivity type semiconductor region formed in the first conductivity type semiconductor region adjacent to the source / drain region and connected to a gate of the insulated gate field effect transistor. Semiconductor integrated circuit device. The first insulated gate field effect transistor having a second conductivity type source / drain region formed in the first conductivity type semiconductor region and connected to the gate of the first insulated gate field effect transistor; Further comprising a second insulated gate field effect transistor that drives
The distance from the source / drain region of the first insulated gate field effect transistor to the semiconductor region of the second conductivity type is the distance from the source / drain region of the first insulated gate field effect transistor to the second region. 2. The semiconductor integrated circuit device according to claim 1, wherein the distance is shorter than the distance to the source / drain region of the insulated gate field effect transistor. A first conductivity type semiconductor region;
A first insulated gate field effect transistor formed in the first conductivity type semiconductor region and having a second conductivity type source / drain region connected to an output terminal;
The first insulated gate field effect transistor having a second conductivity type source / drain region formed in the first conductivity type semiconductor region and connected to the gate of the first insulated gate field effect transistor; A second insulated gate field effect transistor that drives
The semiconductor region of the first conductivity type is one of an anode and a cathode, and the other of the anode and the cathode formed in the semiconductor region of the first conductivity type and connected to the gate of the first insulated gate field effect transistor is used. Having a diode with
The distance from the source / drain region of the first insulated gate field effect transistor to the other of the anode and the cathode is equal to the distance between the source / drain region of the first insulated gate field effect transistor and the second insulation. A semiconductor integrated circuit device, wherein the distance between the gate type field effect transistor and the source / drain region is shorter. A first conductivity type semiconductor region;
A first insulated gate field effect transistor formed in the first conductivity type semiconductor region and having a second conductivity type source / drain region connected to an output terminal;
The first insulated gate field effect transistor having a second conductivity type source / drain region formed in the first conductivity type semiconductor region and connected to the gate of the first insulated gate field effect transistor; A second insulated gate field effect transistor that drives
A third source / drain region formed in the first conductivity type semiconductor region and short-circuited to its own gate; and a source / drain region connected to the gate of the first insulated gate field effect transistor. And an insulated gate field effect transistor of
From the source / drain region of the first insulated gate field effect transistor to the source / drain region connected to the gate of the first insulated gate field effect transistor of the third insulated gate field effect transistor A semiconductor integrated circuit, wherein a distance is shorter than a distance from the source / drain region of the first insulated gate field effect transistor to the source / drain region of the second insulated gate field effect transistor. apparatus. A first conductivity type semiconductor region;
A first insulated gate field effect transistor formed in the first conductivity type semiconductor region and having a second conductivity type source / drain region connected to an output terminal;
The first insulated gate field effect transistor having a second conductivity type source / drain region formed in the first conductivity type semiconductor region and connected to the gate of the first insulated gate field effect transistor; A second insulated gate field effect transistor that drives
A bipolar transistor having a semiconductor region of the first conductivity type as a base and having an emitter / collector region short-circuited to the base and an emitter / collector region connected to the gate of the first insulated gate field effect transistor; With
The distance from the source / drain region of the first insulated gate field effect transistor to the emitter / collector region connected to the gate of the first insulated gate field effect transistor of the bipolar transistor is the first distance. A semiconductor integrated circuit device, wherein a distance from the source / drain region of the insulated gate field effect transistor to the source / drain region of the second insulated gate field effect transistor is shorter. The first and second insulated gate field effect transistors constitute an output circuit;
6. The semiconductor integrated circuit device according to claim 2, wherein said output circuit is an output circuit of a nonvolatile semiconductor memory device. The first and second insulated gate field effect transistors constitute an output circuit;
6. The semiconductor integrated circuit device according to claim 2, wherein the output circuit is an output circuit of a controller. 7. The semiconductor integrated circuit device according to claim 6, wherein the nonvolatile semiconductor memory device is one of a NAND type and an AND type. An electronic card using the semiconductor integrated circuit device according to claim 1. An electronic card using the semiconductor integrated circuit device according to claim 3. An electronic card using the semiconductor integrated circuit device according to claim 4. An electronic card using the semiconductor integrated circuit device according to claim 5.

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