JP2004186268A - Light emitting element - Google Patents

Abstract

An external quantum efficiency can be sufficiently increased even though a device thickness is reduced by using a transparent oxide electrode layer, and a device using a conventional oxide transparent electrode layer is provided. Provided is a light-emitting element that can significantly increase light emission luminance.
A light emitting element includes a compound semiconductor layer having a light emitting layer portion and a light emitting drive voltage applied to the light emitting layer portion formed to cover a main surface of the compound semiconductor layer. And the light from the light emitting layer portion 24 is extracted in a form that allows the light to pass through the transparent oxide electrode layer 30. A contact layer 31 for reducing the junction resistance of the oxide transparent electrode layer 30 is disposed between the compound semiconductor layer 61 and the oxide transparent electrode layer 30 so as to be in contact with the oxide transparent electrode layer 30. At the bonding interface of the transparent electrode layer 30, a region where the contact layer 31 is formed and a region where the contact layer 31 is not formed are mixed. The outermost surface of the compound semiconductor layer 61 is the concave surface 10 in which at least a part of the non-formation region of the contact layer 31 is located closer to the light emitting layer portion 24 than the remaining region.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a light emitting device.
[0002]
[Prior art]
[Patent Document 1]
JP-A-1-225178
[Patent Document 2]
U.S. Pat. No. 5,789,768
[Patent Document 3]
Japanese Patent No. 3333219
[0003]
(Al _x Ga _1-x ) _y In _1-y A light-emitting element in which a light-emitting layer portion is formed of a P mixed crystal (where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1 (hereinafter also referred to as AlGaInP mixed crystal or simply AlGaInP) has a thin AlGaInP active layer. By adopting a double hetero structure sandwiched between an n-type AlGaInP cladding layer and a p-type AlGaInP cladding layer having a larger band gap, a high-luminance element can be realized. _x Ga _y Al _1-xy A blue light-emitting element in which a similar double heterostructure is formed using N (where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, x + y ≦ 1) is also in practical use.
[0004]
For example, taking an AlGaInP light emitting device as an example, an n-type GaAs buffer layer, an n-type AlGaInP cladding layer, an AlGaInP active layer, and a p-type AlGaInP cladding layer are formed in this order by heteroepitaxial growth on an n-type GaAs substrate. The layers are stacked to form a light emitting layer portion having a double hetero structure. Electric current is applied to the light emitting layer via a metal electrode formed on the element surface. Here, since the metal electrode functions as a light shield, it is formed, for example, so as to cover only the central portion of the main surface of the light emitting layer portion, and light is extracted from the surrounding electrode non-formed region.
[0005]
In this case, reducing the area of the metal electrode as much as possible is advantageous from the viewpoint of improving the light extraction efficiency because the area of the light leakage region formed around the electrode can be increased. Conventionally, attempts have been made to increase the amount of light extraction by effectively spreading the current in the device by devising the shape of the electrodes.However, in this case, it is inevitable to increase the electrode area anyway, and the light leakage area is increased. The decrease has led to the dilemma of limiting the amount of light extraction. In addition, the carrier concentration of the dopant in the cladding layer, and consequently, the electrical conductivity, are suppressed somewhat lower in order to optimize the radiative recombination of the carriers in the active layer, and the current tends to hardly spread in the in-plane direction. . This causes the current density to concentrate in the electrode coating region, leading to a substantial decrease in light extraction in the light leakage region. Therefore, a method of forming a low-resistivity current diffusion layer having an increased carrier concentration (dopant concentration) between the cladding layer and the electrode is adopted in Patent Document 2. The current diffusion layer is formed by a metal organic vapor phase epitaxy (MOVPE method) or a liquid phase epitaxy method (Liquid Phase Epitaxy: LPE method). However, in order to obtain a sufficient current diffusion effect, the growth thickness of the current diffusion layer must be formed to be considerably thick (for example, about 50 μm), and an increase in manufacturing cost is inevitable.
[0006]
Accordingly, a proposal has been made to form an oxide transparent electrode layer (for example, ITO (Indium Tin Oxide) transparent electrode layer) so as to cover the light emitting layer portion surface instead of, or together with, the current diffusion layer made of a compound semiconductor. , Patent Document 1, Patent Document 2 or Patent Document 3. Since the conductivity of the oxide transparent electrode layer is as high as that of a metal, a sufficient current spreading effect can be obtained even if the thickness is small, and the thickness of the current spreading layer can be reduced or omitted.
[0007]
[Problems to be solved by the invention]
By the way, the light emitting element in which the current diffusion layer is formed thicker requires a cost for growing the current diffusion layer, but increases the total thickness of the element, so that the amount of light extraction from the peripheral side surface of the element can be increased. There is an advantage that external quantum efficiency is improved. However, in a light-emitting element provided with a high-conductivity oxide transparent electrode layer, the thickness of the current diffusion layer is inevitably reduced for that purpose, so that the overall thickness of the light-emitting element is also significantly reduced. As a result, there is a disadvantage that the light extraction amount from the peripheral side surface of the element is reduced, and a decrease in external quantum efficiency is unavoidable.
[0008]
Patent Document 3 proposes improving light extraction efficiency by forming irregularities by frost treatment on the outermost surface of a light emitting layer portion and covering the irregularities with a transparent oxide electrode layer. However, this proposed structure has a disadvantage that the contact layer for reducing the contact resistance of the transparent oxide electrode layer is omitted, and the forward voltage of the element is greatly increased due to the increase in the contact resistance.
[0009]
An object of the present invention is to enable the external quantum efficiency to be sufficiently increased despite the fact that the device thickness is reduced by the use of the oxide transparent electrode layer, and thus the conventional oxide transparent electrode layer. It is an object of the present invention to provide a light-emitting element whose emission luminance can be significantly increased as compared with a used element.
[0010]
[Means for Solving the Problems and Functions / Effects]
The present invention includes a compound semiconductor layer having a light emitting layer portion, and an oxide transparent electrode layer formed so as to cover a main surface of the compound semiconductor layer for applying a light emission drive voltage to the light emitting layer portion. Then, the light from the light-emitting layer portion, in the light-emitting element to extract in the form of transmitting the transparent oxide electrode layer, in order to solve the above problems, the first configuration,
A contact layer for reducing the junction resistance of the oxide transparent electrode layer is disposed between the compound semiconductor layer and the oxide transparent electrode layer so as to be in contact with the oxide transparent electrode layer. At the interface, the region where the contact layer is formed and the region where the contact layer is not formed are mixed,
The outermost surface of the compound semiconductor layer is characterized in that at least a part of the region where the contact layer is not formed is a concave surface which is recessed and located closer to the light emitting layer portion than the remaining region.
[0011]
The oxide transparent electrode layer can be composed of, for example, ITO. ITO is an indium oxide film doped with tin oxide. By setting the content of tin oxide to 1 to 9% by mass, the resistivity of the electrode layer becomes 5 × 10 ^-4 It can be a sufficiently low value of Ω · cm or less. In addition, other than the ITO electrode layer, the ZnO electrode layer has high conductivity and can be used in the present invention. Further, tin oxide (so-called Nesa) doped with antimony oxide, Cd ₂ SnO ₄ , Zn ₂ SnO ₄ , ZnSnO ₃ , MgIn ₂ O ₄ , CdSb doped with yttrium oxide (Y) ₂ O ₆ , Tin oxide doped GaInO ₃ And the like can also be used as a material for the transparent oxide electrode layer. These oxide transparent electrode materials have good transparency to visible light (that is, they are transparent), and when used as an electrode for applying a voltage to the light emitting layer, there is an advantage that light extraction is not hindered. . In addition, when a voltage for driving the device is applied through a bonding pad formed on the oxide transparent electrode layer, the device also plays a role of spreading the current in the plane to make the light emission uniform and increase the efficiency.
[0012]
Such an oxide transparent electrode layer does not necessarily form a good ohmic junction when it is directly joined to the compound semiconductor layer forming the light emitting layer portion or the current diffusion layer, and the luminous efficiency is increased due to an increase in series resistance based on contact resistance. May decrease. Therefore, a contact layer for reducing the junction resistance of the transparent oxide electrode layer needs to be disposed between the light emitting layer portion and the transparent oxide electrode layer so as to be in contact with the transparent oxide electrode layer. Such a contact layer can be formed of a compound semiconductor described later, but can also be a metal layer containing Au or Ag as a main component.
[0013]
On the other hand, a light-emitting element using a compound semiconductor is a surface-emitting element based on light-emitting recombination of carriers injected into a light-emitting layer, and light emission from the light-emitting layer is divided into in-plane directions. It is easier to understand if each is replaced with a point light source. In this case, it is considered that emitted light is emitted in all three-dimensional directions from each point light source, and the oxide transparent electrode layer formed on the outermost surface of the element is separated from the point light source in an in-plane direction. In the region, the emitted light flux enters at a lower angle. The luminous flux incident on the interface between the oxide transparent electrode layer and the compound semiconductor layer at a critical angle equal to or less than the total reflection critical angle is reflected at the interface and returned to the compound semiconductor layer side. Can not be taken out. As described above, in a light-emitting element employing an oxide transparent electrode layer, since the total thickness of the compound semiconductor layer including the light-emitting layer part is reduced and the amount of light extracted from the peripheral side of the element must be reduced, If the outermost surface region of the compound semiconductor layer covered with the transparent electrode layer is flat, the amount of light totally reflected at the interface increases, and the light extraction efficiency of the entire device is greatly impaired.
[0014]
Therefore, in the light-emitting element of the present invention, a region where a contact layer is formed and a region where a contact layer is not formed for reducing the junction resistance of the oxide transparent electrode layer are mixed on the outermost surface of the compound semiconductor layer. On the surface, at least a part of the non-formation region of the contact layer was formed as a concave surface which was recessed toward the light emitting layer portion side from the remaining region. The formation region of the contact layer forms a relatively protruding portion when viewed from the concave surface. Then, the current diffused in the oxide transparent electrode layer is supplied to the light emitting layer portion through each of the contact layers dispersedly formed in such a manner that the top surfaces of these convex portions are selected. The layer portions form so-called independent element light-emitting elements connected in parallel by an oxide transparent electrode layer, and emit light with high luminance by a current intensively supplied through a contact layer. That is, by forming the element light emitting element, the light emitting layer can be used more efficiently than the conventional light emitting element.
[0015]
The effect is that the convex portions are dispersedly formed on the outermost surface of the compound semiconductor layer, the contact layers are also dispersedly formed corresponding to the convex portions, and the contact layers are electrically formed in the in-plane direction by the oxide transparent electrode layer. It is further enhanced when a structure that is physically connected is adopted. In this case, the contact layer may be formed of a compound semiconductor or a metal. When the contact layer is made of a metal, a contact layer made of the metal is selectively formed on the top of the convex portion. In the case of a contact layer made of a compound semiconductor, it is necessary to epitaxially grow on the underlying compound semiconductor layer, and flatness of the growth surface is required. In the case of a metal contact layer, the top of the convex portion forming the contact layer is required. Has an advantage that it can be easily formed by evaporation or sputtering even if it is not necessarily flat.
[0016]
Further, according to the light emitting element of the present invention, the light incident on the interface at a position far away from the starting point of the light flux from the light emitting layer also increases the substantial incident angle due to the presence of the concave portion, and the total angle at the interface is increased. The reflected luminous flux can be greatly reduced. In other words, the strong luminous flux generated by each element light emitting element is efficiently emitted from the surface of the concave portion surrounding the convex portion to the outside via the oxide transparent electrode layer while suppressing total reflection. Therefore, a light-emitting element with extremely high brightness is realized as a whole. In addition, although the device thickness is reduced by using the transparent oxide electrode layer, the light emission luminance of the light emitting device using the transparent oxide electrode layer can be dramatically improved. Furthermore, instead of reducing the light emitted from the peripheral side surface of the element due to the decrease in the element thickness, the light emitted to the element main surface side on which the oxide transparent electrode layer is formed increases, so that the light flux concentrates on the element main surface side. There is also an advantage that bright light can be easily obtained.
[0017]
The oxide transparent electrode layer is formed by a known vapor deposition method, for example, a chemical vapor deposition (CVD) method, a physical vapor deposition method (PVD) such as sputtering or vacuum deposition, or a molecular beam epitaxial growth method (molecular). beam epitaxy (MBE). For example, the ITO layer and the ZnO electrode layer can be manufactured by high frequency sputtering or vacuum deposition, and the Nesa film can be manufactured by the CVD method. Further, instead of these vapor phase growth methods, another method such as a sol-gel method may be used.
[0018]
By pattern etching, the outermost surface of the compound semiconductor layer can be a pattern etching surface in which a concave portion corresponding to an etching region and a convex portion corresponding to a non-etching region are mixed, and the contact layer has a convex shape. It can be selectively formed on the top surface of the part. According to this structure, by performing selective etching using photolithography or the like, a concavo-convex shape favorable for light extraction can be freely obtained, and by leaving the top surface of the convex portion as a non-etching region, individual convex portions can be obtained. The contact layer can be reliably formed on the convex portion, and each of the convex portions can be effectively used without fail as the above-described element light emitting element. In the light-emitting element of Patent Document 3, irregularities are formed by frost processing on the outermost surface of the light-emitting layer portion, and the frost processing etching for forming the irregularities is performed on the entire surface of the outermost surface of the light-emitting layer portion. Therefore, even if a contact layer is formed in the light emitting layer in advance, most of the contact layer is lost by the etching. Therefore, even if there is a contact layer remaining, only an accidental one remains, so that it cannot be selectively formed on the top surface of the convex portion.
[0019]
The secondary roughness profile finer than the primary roughness profile is further superimposed on the primary roughness profile formed by the concave portion and the convex portion forming the pattern etching surface as a frost-processed surface by anisotropic etching. It can also be done. The frost-treated surface is obtained by anisotropically etching the compound semiconductor layer forming the outermost surface region using an appropriate etchant, and since minute irregularities are randomly formed, it is totally reflected at the interface. The effect of reducing the emitted luminous flux is high. As a result, the effect of preventing the total reflection of the emitted light beam peculiar to the frost processing surface and the effect of improving the light extraction efficiency by the macro concave and convex portions by the pattern etching surface are combined, and a light emitting element with higher luminance is obtained. realizable.
[0020]
Next, when the outermost surface of the transparent oxide electrode layer is flat, the luminous flux that cannot be extracted to the outside due to total reflection at the outermost surface of the transparent oxide electrode layer increases. Therefore, when forming a concave portion and a convex portion forming a pattern etching surface, it is preferable that the outermost surface of the oxide transparent electrode layer be undulated with a profile following the concave portion and the convex portion. It is desirable to further enhance.
[0021]
The contact layer for reducing the junction resistance with the oxide transparent electrode layer can be formed of a compound semiconductor as described above. In order to form a high-quality contact layer with few crystal defects, it is desirable to epitaxially grow the contact layer on the compound semiconductor layer. In this case, in order to carry out the epitaxial growth of the contact layer without generating defects such as crystal defects while forming the uneven portion on the outermost surface of the compound semiconductor layer, it is necessary to form the contact layer on the outermost surface of the compound semiconductor layer. It is preferable that a portion corresponding to the formation region is a contact formation flat surface orthogonal to the thickness direction of the light emitting layer portion, and a contact layer made of a compound semiconductor is epitaxially grown on the contact formation flat surface.
[0022]
In order to form a contact-forming flat surface and a concave portion recessed from the flat surface, for example, a flat compound semiconductor layer epitaxially grown using a mirror-polished substrate is used, and the flat layer surface is formed by a photoresist layer. By performing selective etching while partially covering (photolithography step), a region not covered with the photoresist layer becomes an etching region, and a concave portion can be formed. On the other hand, in the non-etched area covered with the photoresist layer, a flat layer surface remains as it is, and becomes a contact formation flat surface which forms the top surface of the convex portion.
[0023]
The etching for forming the concave surface can be performed by well-known mesa etching. In this case, the concave portion can be formed as having a curved cross-sectional shape so as to form the background of the contact forming flat surface. The light extraction efficiency can be further increased by forming the concave portion having the curved shape. Specifically, a contact-forming flat surface can be dispersedly formed on the outermost surface of the compound semiconductor layer in an island shape with the remaining region as a background, and the remaining region is recessed from the contact-forming flat surface. At the same time, a concave surface having at least a curved cross section can be formed around the contact layer. In this manner, each of the dispersed contact-formed flat surfaces becomes a convex portion surrounded by a curved concave surface, and the convex portions become element light emitting elements that also have a lens function. Brightness can be further increased. A part of the concave surface other than the region surrounding the contact layer may be a flat surface. On the other hand, it is also possible to disperse and form a concave surface on the outermost surface of the compound semiconductor layer in the form of an island with the remaining region forming a contact-forming flat surface as a background. In this embodiment, of the outermost surface of the compound semiconductor layer, the contact forming flat surface, which is the background, is uniformly covered with a photoresist layer, and a region to be a concave surface is exposed in an island shape and mesa etching is performed. Accordingly, the inner surface of each concave surface can be smoothly finished in a dimple shape, and conditions for obtaining a concave surface having a good shape can be easily set.
[0024]
Next, a metal bonding pad can be disposed on the oxide transparent electrode layer, and a current-carrying electrode wire can be bonded to the bonding pad. In this case, it is desirable that the region immediately below the bonding pad on the outermost surface of the compound semiconductor layer be formed flat (no concave portion or convex portion is formed). Thereby, the region where the bonding pad of the oxide transparent electrode layer is formed is also flattened, and the adhesion to the bonding pad is also improved. In addition, since the surface of the bonding pad is also smoothed, erroneous detection of an image due to surface roughness is reduced when the electrode wire is automatically bonded to the bonding pad by using image processing, and the efficiency in the wire bonding process is further reduced. It also contributes to improvement and yield improvement.
[0025]
When the contact layer is formed so as to cover the entire bonding surface of the oxide transparent electrode layer to the element side, the contact resistance of the oxide transparent electrode layer is improved even in a region immediately below the bonding pad for wire bonding. Driving current, and thus light emission, tends to concentrate on the area, and much of the generated light is blocked by the bonding pad, which may cause a decrease in light extraction efficiency. Therefore, a configuration in which a contact layer is not formed in a region directly below the bonding pad can be adopted. With this configuration, the contact resistance of the oxide transparent electrode layer increases in a region immediately below the bonding pad. As a result, the drive current of the light-emitting element in the transparent oxide electrode layer has a large component flowing outside the region immediately below the bonding pad and bypassing the region immediately below the bonding pad, so that light extraction efficiency can be greatly increased.
[0026]
Next, the second configuration of the light emitting device of the present invention is:
A light emitting layer comprising: a compound semiconductor layer having a light emitting layer portion; and an oxide transparent electrode layer formed to cover a main surface of the compound semiconductor layer and for applying a light emission drive voltage to the light emitting layer portion. In the light-emitting element, the light from the portion was taken out in a form to transmit through the transparent oxide electrode layer,
A contact layer for reducing the junction resistance of the oxide transparent electrode layer is disposed between the compound semiconductor layer and the oxide transparent electrode layer so as to be in contact with the oxide transparent electrode layer. At the interface, the region where the contact layer is formed and the region where the contact layer is not formed are mixed,
The contact layer forming region on the outermost surface of the compound semiconductor layer is a contact forming flat surface orthogonal to the thickness direction of the light emitting layer portion, and a contact layer made of a compound semiconductor is epitaxially grown on the contact forming flat surface,
At least a part of the non-formation region of the contact layer is characterized by being a surface roughened region which is rougher than the contact formation flat surface.
[0027]
According to the structure of the light-emitting element, a region where the contact layer is formed and a region where the contact layer is not formed are mixed at the bonding interface of the oxide transparent electrode layer, and the current diffused in the oxide transparent electrode layer is partially formed. Since the light-emitting layer is supplied to the light-emitting layer through the contact layer, each light-emitting layer immediately below and around the contact layer forms an independent element light-emitting element, which is connected in parallel by an oxide transparent electrode layer. In addition, light is emitted with high luminance by a current supplied intensively through the contact layer. That is, by forming the element light emitting element, the light emitting layer can be used more efficiently than the conventional light emitting element. This effect is further enhanced when a plurality of contact formation flat surfaces are dispersedly formed on the outermost surface of the compound semiconductor layer and the contact layers are formed on the respective contact formation flat surfaces.
[0028]
In addition, the luminous flux generated by each element light emitting element is efficiently emitted from the surface of the roughened area surrounding the contact layer to the outside via the transparent oxide electrode layer while suppressing total reflection. Therefore, a light-emitting element with extremely high brightness is realized as a whole. In addition, although the device thickness is reduced by using the transparent oxide electrode layer, the light emission luminance of the light emitting device using the transparent oxide electrode layer can be dramatically improved. Furthermore, instead of reducing the light emitted from the peripheral side surface of the element due to the decrease in the element thickness, the light emitted to the element main surface side on which the oxide transparent electrode layer is formed increases, so that the light flux concentrates on the element main surface side. There is also an advantage that bright light can be easily obtained.
[0029]
The third of the light emitting device of the present invention,
A light emitting layer comprising: a compound semiconductor layer having a light emitting layer portion; and an oxide transparent electrode layer formed to cover a main surface of the compound semiconductor layer and for applying a light emission drive voltage to the light emitting layer portion. In the light-emitting element, the light from the portion was taken out in a form to transmit through the transparent oxide electrode layer,
The main surface of the compound semiconductor layer is formed by pattern etching into a pattern-etched surface in which a concave portion corresponding to an etching region and a convex portion corresponding to a non-etching region are mixed.
[0030]
According to this configuration, since the main surface of the compound semiconductor layer that forms a boundary with the transparent oxide electrode layer is greatly undulated by pattern etching, compared with a conventional light-emitting element in which the main surface is flat, Light extraction efficiency is greatly improved, and light emission intensity can be increased. In the case where the concave portion and the convex portion forming the pattern etching surface are formed, the outermost surface of the oxide transparent electrode layer may be undulated with a profile following the concave portion and the convex portion, and the light extraction efficiency may be reduced. It is desirable to further enhance.
[0031]
Furthermore, a secondary roughness profile finer than the primary roughness profile is further superimposed as a frost-processed surface by anisotropic etching on the primary roughness profile formed by the concave portions and the convex portions forming the pattern etching surface. You can also. The light dispersion effect by the pattern etching surface and the light dispersion effect by the frost-treated surface act synergistically to further enhance the extraction efficiency effect.
[0032]
Next, the light emitting device of the present invention has a light emitting layer portion made of a compound semiconductor having a double hetero structure in which a first conductive type clad layer, an active layer and a second conductive type clad layer are stacked in this order. Alternatively, a light-emitting drive voltage may be applied to the light-emitting layer via an oxide transparent electrode layer covering the main surface of the second conductivity type clad layer. In this case, a metal bonding pad is arranged on the transparent oxide electrode layer, a current-carrying electrode wire is bonded to the bonding pad, and a contact layer made of a compound semiconductor for reducing the bonding resistance of the transparent oxide electrode layer. Are disposed so as to be in contact with the oxide transparent electrode layer.
[0033]
Bonding of the electrode wire to the bonding pad can be performed by ultrasonic welding or thermosonic bonding that further applies heat thereto. At this time, impact stress due to ultrasonic waves or heating (and further pressing) concentrates on the compound semiconductor layer immediately below the bonding pad, and crystal defects such as dislocations are introduced as damage. When the damaged region reaches the active layer in the light emitting layer portion, the following problem occurs.
(1) Direct decrease in light emission luminance. The cause is considered to be an increase in the non-light-emitting transition process due to crystal defects.
(2) Reduction in element life. When energization is continued to the light emitting layer in which dislocations are formed, current concentrates on the dislocations, so that the dislocations are likely to multiply, and the emission luminance deteriorates with time.
[0034]
Therefore, the light emitting layer portion is made of a compound semiconductor having a double hetero structure in which the first conductivity type cladding layer, the active layer, and the second conductivity type cladding layer are laminated in this order, and is formed on the oxide transparent electrode layer. In a configuration in which a metal bonding pad is arranged, and a current-carrying electrode wire is bonded to the bonding pad, a portion located between the active layer and the contact layer, including the outermost surface of the compound semiconductor layer, It is desirable to use a bonding side semiconductor layer having a thickness of 0.6 μm or more and less than 10 μm including the second conductivity type cladding layer. If the thickness of the bonding-side semiconductor layer is less than 0.6 μm, the influence of damage due to bonding is likely to reach the active layer, leading to a reduction in light emission intensity and device life. On the other hand, when the thickness is 10 μm or more, a long time is required for layer growth and a large amount of raw material is required, which tends to cause a decrease in manufacturing efficiency and an increase in cost.
[0035]
Further, if the dopant concentration of the bonding-side semiconductor layer is too high, the following problem may easily occur. That is, the light-emitting element gradually decreases in light emission luminance as the energization is continued. For example, when the light emission luminance measured immediately after the current supply to the element is started by a constant current is set as the initial luminance, and the light emission luminance that decreases as the integrated current supply time elapses is tracked, the light emission luminance reaches a predetermined limit luminance. When the time or the evaluation energization time is fixed to a constant value (for example, 1000 hours), the ratio of the luminance after the elapse of the evaluation energization time to the initial luminance (hereinafter referred to as element life) is used to evaluate the element life. Can be a constant measure of
[0036]
In the light-emitting element having the current diffusion layer, the dopant concentration in the cladding layer is maintained at an appropriate value in the initial stage of energization. Diffusion into the layer and the active layer is facilitated by electrical factors. When a lattice defect or the like is formed due to the excessive dopant concentration and the promotion of diffusion of the dopant atoms, an electrical non-radiative recombination center is formed in the active layer or at the interface between the P-type cladding layer and the active layer. A level is formed. As a result, the probability of radiative recombination decreases, causing a decrease in intensity. That is, the light emission luminance tends to deteriorate with time, which leads to a reduction in the element life.
[0037]
Therefore, the bonding-side semiconductor layer has a dopant concentration of 4 × 10 ¹⁶ / Cm ³ More than 1 × 10 ¹⁸ / Cm ³ It is desirable to set it to less than. The dopant concentration of the bonding side semiconductor layer is 4 × 10 ¹⁶ / Cm ³ If it is less than 1, the series resistance of the element increases, and the forward voltage of the element increases. Also, 1 × 10 ¹⁸ / Cm ³ Above, the radiative recombination of carriers in the active layer becomes difficult to progress, and the luminous efficiency is reduced.
[0038]
The bonding-side semiconductor layer is disposed in contact with the second conductive type clad layer and the oxide transparent electrode layer side of the second conductive type clad layer, and is formed of a compound semiconductor having a lower dopant concentration than the second conductive type clad layer. And a cushion layer made of such a material. By arranging such a cushion layer, even if a damaged area is generated at the time of bonding, most of the damage area remains inside the cushion layer, so that the influence on the active layer is less likely to occur, and the deterioration of light emission intensity and element life is more reduced. It can be suppressed effectively.
* Since there is a configuration (described later) in which the second cladding layer is thicker, it is described as "composed".
[0039]
Further, since the cushion layer has a lower dopant concentration than the second conductivity type cladding layer in contact with the cushion layer, the inflow of dopant atoms from the cushion layer into the second conductivity type cladding layer is suppressed, and the life of the device is reduced. Significant improvement can be achieved. In addition, the problem that the dopant diffuses into the second conductivity type cladding layer during the growth is less likely to occur.
[0040]
It is desirable that the cushion layer be made of a material that does not absorb light from the light emitting layer as much as possible in order to improve light extraction efficiency. To this end, it is effective to use a compound semiconductor having a band gap larger than that of the active layer in the light emitting layer as the compound semiconductor forming the cushion layer. When the light emitting layer portion is made of AlGaInP, specific materials of the cushion layer include AlGaAs, GaP, GaAsP, and AlGaAsP. Further, when the cushion layer is formed thin, it works advantageously from the viewpoint of suppressing light absorption. Specifically, the thickness of the cushion layer is desirably adjusted to 0.1 μm or more and 5 μm or less. If the thickness of the cushion layer is less than 0.1 μm, the total thickness of the bonding-side semiconductor layer tends to be insufficient, and the effect of bonding the electrode wires tends to reach the light emitting layer portion. On the other hand, if the thickness of the cushion layer exceeds 5 μm, the resistivity in the layer thickness direction increases because the dopant concentration is kept low, leading to a decrease in luminous efficiency due to an increase in the series resistance of the device. In addition, it takes a long time to grow a thick cushion layer, and a large amount of raw materials are required, which tends to cause a decrease in manufacturing efficiency and an increase in cost. More preferably, the thickness of the cushion layer is 0.5 μm or more and 3 μm or less.
[0041]
On the other hand, the bonding-side semiconductor layer may be configured as a second-conductivity-type cladding layer having a thickness of 0.6 μm or more and less than 10 μm. That is, by making the second conductivity type cladding layer have a necessary and sufficient thickness, it is possible to prevent the damaged region from reaching the active layer. In addition, since it is only necessary to increase the growth thickness of the clad layer of the same material, the manufacture is easy. In this case, the first conductivity type clad layer does not need to consider the influence of damage due to wire bonding, and therefore, it is desirable to form the first conductivity type clad layer thinner than the second conductivity type clad layer from the viewpoint of reducing manufacturing costs.
* This is a description of the configuration with a thicker second cladding layer. Hereafter, it is unified by "Semiconductor layer on the bonding side".
[0042]
Next, specifically, a contact layer made of a compound semiconductor that does not contain Al and has a relatively small band gap energy (for example, less than 1.42 eV) can be suitably used. By using such a contact layer, a good ohmic contact can be obtained, and an increase in resistance due to oxidation of the Al component hardly occurs.
[0043]
When the oxide transparent electrode layer is an ITO electrode layer, for example, an InGaAs layer or a GaAs layer can be used as the contact layer. The contact layer has In (at least) at the junction interface with the ITO electrode layer. _x Ga _1-x As (0 <x ≦ 1), the effect of reducing contact resistance can be particularly enhanced. (Al _x Ga _1-x ) _y In _1-y When the light emitting layer is formed by P (where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1), the GaAs layer is formed so as to be in contact with the ITO electrode layer, and then heat treatment is performed to remove the GaAs layer from the GaAs layer. By diffusing In into the layer, a contact layer made of GaAs containing In can be formed. In this case, the In concentration distribution in the thickness direction of the contact layer continuously decreases as the distance from the ITO electrode layer in the thickness direction increases. In addition, the contact layer must be In at the junction interface with the ITO electrode layer. _x Ga _1-x As.
[0044]
For the contact layer, a method of directly growing InGaAs by epitaxial growth may be adopted. However, adopting the above method has the following advantages. That is, when the contacting portion of the bonding-side semiconductor layer is made of AlGaAs, GaP, or AlGaInP, the GaAs layer is extremely easy to lattice match with these compound semiconductors, compared to the case where InGaAs is directly epitaxially grown. As a result, a uniform and highly continuous film can be formed.
[0045]
Then, after forming an ITO electrode layer on the GaAs layer, heat treatment is performed to diffuse In from the ITO electrode layer into the GaAs layer to form a contact layer. The contact layer made of GaAs containing In obtained by such a heat treatment does not have an excessive In content, and effectively suppresses quality deterioration such as a decrease in emission intensity due to lattice mismatch with the bonding-side semiconductor layer. Can be prevented.
[0046]
As shown in (1) in FIG. 11, the In concentration distribution in the thickness direction of the contact layer decreases continuously as the distance from the ITO electrode layer increases in the thickness direction (that is, the bonding side semiconductor). It is desirable that the In concentration distribution is inclined so that the In concentration becomes smaller on the layer side. Such a structure is formed by diffusing In from the ITO side to the contact layer side by heat treatment. When the light-emitting layer is formed of AlGaInP and the bonding-side semiconductor layer is made of a compound semiconductor that lattice-matches the same, if the In concentration distribution of the contact layer is small in the bonding-side semiconductor layer, the bonding-side semiconductor layer is formed. Are close to each other, and the lattice matching between the light emitting layer portion and the contact layer can be further improved. If the heat treatment temperature is excessively high or the heat treatment time is prolonged, In diffusion from the ITO electrode layer excessively proceeds, and the In concentration distribution in the contact layer is reduced as shown in (3) of FIG. 11 shows a substantially constant high value in the thickness direction, and the above effect cannot be obtained. (If the heat treatment temperature is excessively low or the heat treatment time is excessively short, (2) in FIG. As shown by ▼, the In concentration in the contact layer becomes insufficient).
[0047]
In this case, in FIG. 11, the In concentration at the boundary position of the contact layer with the ITO electrode layer is set to C _A And the In concentration near the boundary on the opposite side is C _B And C _B / C _A Is desirably adjusted so as to be 0.8 or less, and it is desirable to perform the above-described heat treatment so as to obtain the In concentration distribution of this form. C _B / C _A Exceeds 0.8, the effect of improving the lattice matching with the bonding-side semiconductor layer due to the gradient of the In concentration distribution cannot be sufficiently obtained. Note that the composition distribution (In or Ga concentration distribution) in the thickness direction of the contact layer is determined by secondary ion mass spectroscopy (SIMS) and Auger electron spectroscopy while gradually etching the layer in the thickness direction. (Auger Electron Spectroscopy), X-ray Photoelectron Spectroscopy (X-ray Photoelectron Spectroscopy: XPS) and other well-known surface analysis methods.
[0048]
The In concentration in the vicinity of the boundary between the contact layer and the ITO electrode layer is desirably 0.1 to 0.6 in terms of the atomic ratio of In to the total concentration of In and Ga. It is desirable to carry out the process so as to obtain such an In concentration. If the In concentration is less than 0.1 as defined above, the effect of reducing the contact resistance of the contact layer becomes insufficient, and if it exceeds 0.6, the quality such as a decrease in luminous intensity due to a lattice mismatch between the contact layer and the luminescent layer portion. Deterioration becomes severe. In addition, the above-mentioned desirable value (0.1 or more and 0.6 or less) can be ensured for the In concentration in the vicinity of the boundary between the contact layer and the ITO electrode layer in the atomic ratio of In to the total concentration of In and Ga. , The In concentration C in the vicinity of the boundary of the contact layer opposite to the side facing the ITO electrode layer. _B May be zero, that is, as shown in FIG. 12, an InGaAs layer may be formed on the ITO layer side of the contact layer, and the GaAs layer may be formed on the opposite side.
[0049]
ITO is an indium oxide film doped with tin oxide as described above. An ITO electrode layer is formed on a GaAs layer, and is further heat-treated in an appropriate temperature range to form a contact having the above-described desired In concentration. Layers can be easily formed. Further, by this heat treatment, the electrical resistivity of the ITO electrode layer can be further reduced. This heat treatment is desirably performed at a temperature as low as possible and in a short time so that the In concentration in the contact layer does not become excessive.
[0050]
It is preferable that the heat treatment for the In diffusion be performed at 600 ° C. or more and 750 ° C. or less. If the heat treatment temperature exceeds 750 ° C., the diffusion rate of In into the GaAs layer becomes too high, and the In concentration in the contact layer tends to become excessive. Further, the In concentration is saturated, and it becomes difficult to obtain an In concentration distribution inclined in the thickness direction of the contact layer. In any case, the lattice matching between the contact layer and the bonding-side semiconductor layer is deteriorated. Further, if the diffusion of In into the GaAs layer excessively proceeds, In of the ITO electrode layer is depleted in the vicinity of the contact portion with the contact layer, and it is difficult to avoid an increase in the electrical resistance of the electrode. Further, when the heat treatment temperature is too high, exceeding 750 ° C., oxygen in ITO diffuses into the GaAs layer to promote oxidation, and the series resistance of the device tends to increase. In any case, the light emitting element cannot be driven at an appropriate voltage. Further, when the heat treatment temperature is extremely high, the conductivity of the ITO electrode layer may be rather deteriorated. On the other hand, if the heat treatment temperature is lower than 600 ° C., the diffusion rate of In into the GaAs layer becomes too low, and it takes a very long time to obtain a contact layer with sufficiently reduced contact resistance. Efficiency drops significantly.
[0051]
The heat treatment time is desirably set to a short time of 5 seconds or more and 120 seconds or less. When the heat treatment time is longer than 120 seconds, particularly when the heat treatment temperature is close to the upper limit, the amount of In diffusion into the GaAs layer tends to be excessive (however, when the heat treatment temperature is kept low, a longer heat treatment time is required). Time (for example, up to about 300 seconds) can be employed). On the other hand, if the heat treatment time is less than 5 seconds, the diffusion amount of In into the GaAs layer becomes insufficient, and it becomes difficult to obtain a contact layer with sufficiently reduced contact resistance.
[0052]
The contact resistance between the contact layer and the bonding-side semiconductor layer is stably maintained at a low value even when the light-emitting element is kept energized for a long time, that is, the contact resistance hardly increases with time. This is very important. As one method for reducing the contact resistance, it is effective to add a dopant of the same conductivity type as the bonding-side semiconductor layer to the contact layer. In this case, the higher the amount of dopant added to the contact layer, the lower the contact resistance can be. When dopant diffusion from the contact layer to the bonding-side semiconductor layer is relatively easy to occur, if the amount of dopant added to the contact layer is excessively higher than that of the bonding-side semiconductor layer, the contact during light emission energization may occur. Diffusion of dopant from the layer to the bonding-side semiconductor layer may be easily promoted electrically, and the amount of dopant in the contact layer may be gradually depleted. Then, the contact resistance of the contact layer increases with time as the light emission energization is continued, leading to a reduction in element life.
[0053]
In order to suppress such a problem, while setting the dopant concentration in the contact layer higher than that of the bonding-side semiconductor layer, the semiconductor constituting the contact layer has a band gap energy smaller than that of the bonding-side semiconductor layer in contact with the semiconductor. It is desirable to use one. By setting the bandgap energy on the contact layer side smaller than that on the bonding side semiconductor layer, even if the dopant concentration in the contact layer is increased to some extent, diffusion of dopant atoms into the bonding side semiconductor layer is less likely to occur. Can be effectively suppressed from increasing with time.
[0054]
For example, when the oxide transparent electrode layer is an ITO electrode layer, the contact layer is formed at least at a bonding interface with the ITO electrode layer. _x Ga _1-x It is desirable to use one that satisfies As (0 <x ≦ 1). In this case, the contact layer is In on the bonding side with the bonding side semiconductor layer. _x Ga _1-x As (0 ≦ x ≦ 1), and the bonding-side semiconductor layer is a semiconductor having a bandgap energy larger than this, for example, Al _y Ga _1-y As (0 <y ≦ 1). In addition, the bonding-side semiconductor layer can be formed of a GaInP layer, an AlGaInP layer, a GaP layer, a GaAsP layer, or an AlGaAsP layer whose mixed crystal ratio is adjusted so that the band gap energy becomes higher than that of the contact layer. .
[0055]
Further, a method of suppressing diffusion into the bonding-side semiconductor layer by lowering the dopant concentration itself of the contact layer is also possible. In this case, it is desirable that the dopant concentration of the contact layer is equal to or lower than that of the bonding-side semiconductor layer. In addition, the contact layer needs to have a sufficiently low contact resistance with the oxide transparent electrode layer even with low doping, and also have a low contact resistance with the bonding-side semiconductor layer. Specifically, it is desirable to use one that does not form an extremely high heterojunction barrier with the bonding-side semiconductor layer. For example, when the contact layer is made of GaAs in which In is diffused from the side of the ITO layer, the semiconductor layer on the bonding side is made of In with a relatively small InAs mixed crystal ratio y. _y Ga _1-y As (for example, 0 ≦ y ≦ 0.2) combinations can be exemplified.
[0056]
Next, the contact layer can be connected to the bonding-side semiconductor layer via the intermediate layer. The intermediate layer is made of a compound semiconductor having an intermediate band gap energy between the bonding side semiconductor layer in contact with the intermediate layer and the contact layer. When the band edge discontinuity between the bonding-side semiconductor layer and the contact layer is large, as shown in FIG. 13, the bending ΔB of the hetero-barrier formed due to the bending of the band due to the junction increases the contact resistance. Leads to. Therefore, as shown in FIG. 14, when an intermediate layer having a band gap energy between the contact layer and the bonding-side semiconductor layer is inserted between the contact layer and the bonding-side semiconductor layer, the contact layer, the intermediate layer, In addition, since the band edge discontinuity of each of the intermediate layer and the bonding-side semiconductor layer is reduced, the barrier height ΔE formed is also reduced. As a result, the series resistance is reduced, and a sufficiently high emission intensity can be achieved at a low driving voltage.
[0057]
When the bonding-side semiconductor layer is a second conductivity type cladding layer made of AlGaInP up to a region in contact with the intermediate layer, the intermediate layer having an intermediate band gap energy with the contact layer may be formed of AlGaAs. A layer including at least one of a layer, a GaInP layer, and an AlGaInP layer (composition adjusted so that the band gap energy is smaller than that of the cladding layer) can be suitably adopted. For example, the layer is formed to include an AlGaAs layer. be able to. On the other hand, when a cushion layer having the same composition as that of the intermediate layer is provided, the role of the intermediate layer is delegated to this cushion layer, so that the intermediate layer is not particularly provided, and the contact layer is arranged so as to be in contact with the cushion layer. Can also be adopted.
[0058]
The light emitting layer can be disposed on the first main surface side of the conductive substrate. In this case, between the conductive substrate and the light emitting layer portion, a reflection layer that reflects the light emitted from the light emitting layer portion toward the oxide transparent electrode layer can be formed. The luminous flux reflected by the reflective layer can be superimposed on the luminous flux directly emitted from the light emitting layer portion via the transparent oxide electrode layer, and the light extraction efficiency can be further increased. This reflection layer may be a metal reflection layer (for example, one containing Au or Ag as a main component) or a semiconductor film having a different refractive index as disclosed in JP-A-7-66455. By stacking a plurality of layers, a DBR layer (Distributed Bragg Reflector: formed by epitaxial growth on a conductive substrate) that reflects light using Bragg reflection may be used.
[0059]
Further, in the case where the conductive substrate in the light emitting device of the present invention is formed of a transparent conductive substrate, the light emitting layer may be disposed on the first main surface side of the transparent conductive substrate. In this case, the second main surface of the transparent conductive substrate can be covered by the reflective metal layer also serving as the back electrode. Thereby, the luminous flux reflected by the metal reflective layer on the back surface can be superimposed on the luminous flux directly radiated from the light emitting layer portion via the oxide transparent electrode layer, and the light extraction efficiency can be further increased. In this case, a plurality of convex portions may be dispersedly formed on the second main surface of the transparent conductive substrate, and the second main surface may be covered with a reflective metal layer also serving as a back electrode in a form following the convex portions. it can. Since the reflective metal layer formed in a shape following the convex portion functions as a concave mirror-shaped light-collecting surface for the luminous flux from the light-emitting layer portion, a light-emitting element with higher luminance can be realized.
[0060]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a conceptual diagram showing a light emitting device 100 according to one embodiment of the present invention. The light emitting element 100 includes a compound semiconductor layer 61 having a light emitting layer portion 24 and an oxide transparent layer formed to cover a main surface of the compound semiconductor layer 61 for applying a light emission driving voltage to the light emitting layer portion 24. An electrode layer 30 is provided, and light from the light emitting layer section 24 is extracted in a form that allows the light to pass through the transparent oxide electrode layer 30. Specifically, a light-emitting layer portion 24 made of AlGaInP is arranged on a first main surface 7a of an n-type GaP single crystal substrate (hereinafter, also simply referred to as “substrate”) 7 which is a transparent conductive substrate, and A p-type cushion layer 20 and an ITO electrode layer 30 as an oxide transparent electrode layer are formed in this order so as to cover the layer portion 24. A bonding pad 9 made of Au or the like is arranged at a substantially central portion of the ITO electrode layer 30, and an electrode wire 47 made of Au or the like is joined to the bonding pad 9 here. On the other hand, on the other main surface side of the substrate 7, a back electrode layer 15 made of a metal such as an Au-Ge-Ni alloy is formed on the entire surface.
[0061]
The outermost surface region of the compound semiconductor layer 61 which is covered with the ITO electrode layer 30 suppresses the total reflection of light from the light emitting layer portion 24 at the interface with the ITO electrode layer 30 while suppressing the total reflection. It has an uneven surface leading to the inside. The uneven surface is formed by pattern etching using photolithography as a pattern etching surface in which a concave portion 10 corresponding to an etching region and a convex portion 11 corresponding to a non-etching region are mixed. In the present embodiment, the inner surface of the concave portion 10 (or the outer surface of the convex portion 11) has a downwardly curved surface by a mesa etching method described later. In addition, as shown in FIG. 25, of the inner surface of the concave portion 10, only a region around the convex portion 11 may have a curved surface shape, and the other portions may be formed flat. The outermost surface of the ITO electrode layer 30 is undulated with a profile following the concave portions 10 and the convex portions 11.
[0062]
A contact layer 31 for reducing the junction resistance of the ITO electrode layer 30 is formed between the compound semiconductor layer 61 and the ITO electrode layer 30. The contact layer 31 is in contact with the ITO electrode layer 30 and is selectively formed on the top surface of the convex portion 11. As shown in FIG. 3, the current diffused in the ITO electrode layer 30 is supplied to the light emitting layer section 24 via the contact layers 31 dispersed and formed so as to select the top surface of the convex section 11. The respective light emitting layer portions 24 immediately below the convex portions 11 form so-called independent element light emitting elements connected in parallel by the ITO electrode layer 30. In the present embodiment, the convex portions 11 are dispersedly formed in the outermost surface region of the compound semiconductor layer 61 as shown in FIG. 2, and the contact layers 31 are also dispersedly formed corresponding to the convex portions 11. The contact light emitting elements corresponding to the contact layers 31 and the convex portions 11 are electrically connected in the in-plane direction by the ITO electrode layer 30.
[0063]
The portion corresponding to the formation region of the contact layer 31 is a contact formation flat surface 11a orthogonal to the thickness direction J of the light emitting layer portion, and the contact layer 31 is epitaxially grown on the contact formation flat surface 11a. Further, the concave portion 10 is formed to have a curved cross-sectional shape so as to form a background of the contact forming flat surface 11a.
[0064]
Each of the light emitting layer portions 24 includes (Al _x Ga _1-x ) _y In _1-y In addition to the P mixed crystal, the first conductive type clad layer 4, the second conductive type clad layer 6, and the active layer 5 located between the first conductive type clad layer 4 and the second conductive type clad layer 6 It has a double heterostructure. Specifically, non-doped (Al _x Ga _1-x ) _y In _1-y The active layer 5 made of a P (0 ≦ x ≦ 0.55, 0.45 ≦ y ≦ 0.55) mixed crystal is p-type (Al _x Ga _1-x ) _y In _1-y P cladding layer 6 and n-type (Al _x Ga _1-x ) _y In _1-y The structure is sandwiched between the P cladding layers 4. In the light emitting device 100 of FIG. 1, the p-type AlGaInP cladding layer 6 (the p-type dopant is Zn: C from an organic metal molecule can also contribute as a p-type dopant) is disposed on the cushion layer 20 side, and the back electrode layer The n-type AlGaInP cladding layer 4 (the n-type dopant is Si) is disposed on the 15th side. It is obvious to those skilled in the art that the term "non-doped" as used herein means "do not actively add a dopant", and a dopant component unavoidably mixed in a normal manufacturing process. (For example, 10 ^Thirteen -10 ¹⁶ / Cm ³ Is not excluded).
[0065]
The p-type AlGaInP cladding layer 6 has a p-type carrier concentration (majority carrier concentration) of 5 × 10 ¹⁶ / Cm ³ More than 1 × 10 ¹⁸ / Cm ³ Less than 1 × 10 ¹⁷ / Cm ³ More than 7 × 10 ¹⁷ / Cm ³ It is as follows. In the present embodiment, the cushion layer 20 is formed of an AlGaAs layer (for example, Al) to which Zn is added as a p-type dopant. _x Ga _1-x In As, x = about 0.7), and the p-type dopant concentration is 4 × 10 ¹⁶ / Cm ³ More than 9 × 10 ¹⁷ / Cm ³ Below, preferably 9 × 10 ¹⁶ / Cm ³ 6 × 10 or more ¹⁷ / Cm ³ It is set smaller than the p-type AlGaInP cladding layer 6 within the following range. The thickness t2 of the cushion layer 20 is 0.1 μm or more and 5 μm or less, preferably 0.5 μm or more and 3 μm or less.
[0066]
The p-type AlGaInP clad layer 6 and the cushion layer 20 constitute the bonding-side semiconductor layer 60, and the current spreading effect is sufficiently ensured by the ITO electrode layer 30, so that the thickness t1 of the bonding-side semiconductor layer 60 (that is, , The total thickness of the p-type AlGaInP cladding layer 6 and the cushion layer 20) is kept as small as 0.6 μm or more and less than 10 μm. The total thickness of the light emitting element 100 (substrate 7 + light emitting layer part 24 + bonding side semiconductor layer 60 + ITO electrode layer 30) is 80 μm or more and less than 400 μm. On the other hand, the dimension L of one side in square conversion of the main surface of the light emitting layer portion 24 is, for example, 200 μm or more, and 400 μm or more (upper limit is, for example, 40 mm) when a high-luminance surface light emitting element for illumination is formed. In the case of a large chip, by setting the thickness of the ITO electrode layer 20 to 400 nm or more (the upper limit is, for example, 3 μm), the sheet resistance is sufficiently reduced, the current spreading effect is enhanced, and the forward voltage of the element is reduced. Can be significantly reduced. The coverage area ratio of the ITO electrode layer 30 by the bonding pad 9 is 0.1% or more and 10% or less.
[0067]
Considering that the light emitting layer portion 24 of the light emitting element 100 is subdivided in the in-plane direction and each is replaced by a point light source, as shown in FIGS. 4 and 5, each point light source emits a three-dimensionally emitted light beam in all directions. Is released. The luminous flux is incident on the ITO electrode layer 30 formed on the outermost surface of the device at a lower angle in a region farther from the point light source in the in-plane direction. As shown in FIG. 5, a luminous flux incident on the interface between the ITO electrode layer 30 and the compound semiconductor layer 61 at a critical angle equal to or less than the total reflection critical angle is reflected at the interface and returned to the compound semiconductor layer 61 side. It cannot be extracted outside through the layer 30. As described above, since the light-emitting element 100 employs the ITO electrode layer 30 having a high current diffusion capability, the total thickness of the compound semiconductor layer 61 is reduced, and the amount of light extracted from the peripheral side of the element is small. Therefore, when the outermost surface region of the compound semiconductor layer 61 covered with the ITO electrode layer 30 is flat as shown in FIG. 5, the amount of luminous flux totally reflected at the interface increases, and the light extraction efficiency of the entire device is greatly impaired. You.
[0068]
However, in the light emitting device 100 of the present embodiment, as shown in FIG. 4, since the outermost surface region of the compound semiconductor layer 61 is undulated by the convex portions 11 and the concave portions 10, the luminous flux from the light emitting layer portion 24 is The light incident on the interface at a position far away from the starting point of the light beam also has a substantial incident angle because the surface of the concave portion 10 is inclined or bent, and the luminous flux totally reflected at the interface greatly increases. To decrease. As a result, the luminous flux extracted through the ITO electrode layer 30 is significantly increased, and the light extraction efficiency of the light emitting element can be significantly improved despite the reduced element thickness.
[0069]
Hereinafter, a method for manufacturing the light emitting device 100 of FIG. 1 will be described.
First, as shown in step A of FIG. 6, an n-type GaAs buffer layer 2 is formed on a first main surface of a GaAs single crystal substrate 23, a GaAs layer 31 ″ which will be a contact layer later, a cushion layer 20 made of AlGaAs, Then, a p-type AlGaInP cladding layer 6, an active layer 5 made of non-doped AlGaInP, and an n-type AlGaInP cladding layer 4 are epitaxially grown in this order as the light-emitting layer portion 24. The epitaxial growth of each of these layers is performed by a known metal organic vapor phase epitaxy (MetalOrganic). The method can be performed by a vapor phase epitaxy (MOVPE) method, and the following source gases can be used as the source of each component of Al, Ga, In, P and As;
-Al source gas; trimethyl aluminum (TMAl), triethyl aluminum (TEAl), etc .;
Ga source gas; trimethylgallium (TMGa), triethylgallium (TEGa), etc.
In source gas: trimethyl indium (TMIn), triethyl indium (TEIn), or the like.
P source gas: tert-butylphosphine (TBP), phosphine (PH ₃ )Such.
As source gas; tert-butyl arsine (TBA), arsine (AsH) ₃ )Such.
[0070]
The following can be used as the dopant gas;
(P-type dopant)
-Mg source: biscyclopentadienyl magnesium (Cp ₂ Mg).
-Zn source: dimethyl zinc (DMZn), diethyl zinc (DEZn) and the like.
(N-type dopant)
-Si source: silicon hydride such as monosilane.
[0071]
The growth of each layer can be performed continuously in the same vapor phase growth apparatus by switching the source gas. Further, the dopant concentration of each layer can be adjusted to a desired value by the supply ratio of the dopant gas to the source gas.
[0072]
Next, as shown in Step B of FIG. 6, a transparent conductive oxide layer (for example, an ITO layer) 7c is formed on the uppermost n-type AlGaInP clad layer 4, and a transparent conductive substrate as a transparent conductive substrate is formed thereon. The n-type GaP single crystal substrate 7 is bonded by heat treatment, and then, as shown in Step 1 of FIG. 7, the GaAs single crystal substrate 23 used for growth and the GaAs buffer layer 2 are separated.
[0073]
Next, as shown in Step 2, the entire surface of the GaAs layer 31 ″ exposed by the peeling is covered with a photoresist layer 40, and is exposed and developed via a mask for forming the convex portion 11 (see FIG. 1). Thus, the photoresist layer 40 'is patterned so that it remains only in a portion to be a non-etched region, and as shown in Step 3, the region not covered by the photoresist layer 40' is etched. Then, the GaAs layer 31 ″ is removed with an etching solution composed of an ammonia / hydrogen peroxide aqueous solution (the remaining GaAs layer is denoted by reference numeral “31 ′”). Next, as shown in Step 4, the cushion layer 20 made of AlGaAs is mesa-etched with an etching solution containing an aqueous solution of sulfuric acid / hydrogen peroxide, bromomethanol, or an aqueous solution of phosphoric acid / hydrogen peroxide to form the concave portion 10. . The non-etched area covered with the photoresist layer 40 'becomes the convex portion 11 on which the contact formation flat surface is formed. After that, the photoresist layer 40 'is removed.
[0074]
Then, as shown in Step 5, the ITO electrode layer 30 is formed by the well-known high frequency sputtering method so as to cover the cushion layer 20 in which the concave portions 10 and the convex portions 11 are dispersedly formed by etching. It is formed in an undulating form following the convex portion 11. At this time, the above-mentioned GaAs layer 31 ′ is also covered with the ITO electrode layer 30.
[0075]
In this state, the substrate is placed in a furnace, for example, in a nitrogen atmosphere or an inert gas atmosphere such as Ar at a low temperature of 600 ° C. to 750 ° C. (eg, 700 ° C.) for 5 seconds to 120 seconds. A short-time heat treatment (for example, 30 seconds) is performed. Thereby, In diffuses from the ITO electrode layer 20 into the GaAs layer 31 ′, and the contact layer 31 (FIG. 1) is obtained. As a result of the heat treatment, the contact layer 31 was changed to the In concentration C near the boundary with the ITO electrode layer in FIG. _A Becomes 0.1 or more and 0.6 or less in atomic ratio of In to the total concentration of In and Ga. Further, the In concentration continuously decreases as the distance from the ITO electrode layer 20 in the thickness direction increases. _A And the In concentration at the opposite boundary position is C _B And C _B / C _A Is adjusted to be 0.8 or less. The contact layer 31 has a high p-type dopant concentration (for example, 1 ×) in order to reduce the contact resistance in consideration of the fact that the bonding-side semiconductor layer portion in contact with the contact layer 31, that is, the cushion layer 20 is made of AlGaAs. 10 ¹⁹ / Cm ³ Degree) is set.
[0076]
Next, the back electrode layer 15 is formed on the second main surface 7b of the substrate 7 by a vacuum evaporation method. Then, bonding pads 9 are arranged on the ITO electrode layer 30 in regions corresponding to the respective light emitting element chips, and baking for electrode fixing is performed at an appropriate temperature, so that the light emitting element wafer shown in step 7 of FIG. 50 are obtained. The light emitting device wafer 50 is half-diced as shown in step 8 to separate each light emitting device chip region, and after removing processing strain on the dicing surface by mesa etching, scribing is performed as shown in step 9. It is separated into light emitting element chips 51. Then, as shown in step 10, the back electrode layer 15 (see FIG. 3) is fixed to the terminal electrode 9a also serving as a support using a conductive paste such as Ag paste, and an electrode wire 47 is attached to the bonding pad 9. By bonding (bonding) and forming a resin mold 52 as shown in step 11, the light emitting element 100 is obtained.
[0077]
When bonding the electrode wires 47 to the bonding pads 9 made of Au, for example, ultrasonic welding (or thermosonic bonding) is used. The impact stress of this ultrasonic welding reaches the bonding-side semiconductor layer 60 immediately below the bonding pad 9 via the ITO electrode layer 30, and forms a damaged region DM such as a crystal defect. For example, as shown in FIG. 10, when the light emitting layer portion 24 is formed immediately below the ITO electrode layer 30, the damaged region DM extends deep into the light emitting layer portion 24, for example, to the active layer 5, and the light emission luminance and This leads to poor characteristics such as a reduction in element life. However, in the light emitting device of the present embodiment, as shown in FIG. 9, since the cushion layer 20 is interposed, the damaged region DM remains in the cushion layer 20, and the influence extends deep into the light emitting layer portion 24. It is difficult to reduce the emission luminance.
[0078]
The cushion layer 20 has a p-type dopant concentration of 4 × 10 ¹⁶ / Cm ³ More than 9 × 10 ¹⁷ / Cm ³ It is set smaller than the p-type AlGaInP cladding layer 6 within the following range. This makes it difficult for the diffusion of the p-type dopant from the cushion layer 20 to the p-type AlGaInP cladding layer 6 to be electrically promoted when the light emission energization is continued, thereby improving the element life. The p-type dopant concentration of the p-type AlGaInP cladding layer 6 is 5 × 10 ¹⁶ / Cm ³ More than 1 × 10 ¹⁸ / Cm ³ Less than 4 × 10 4 when viewed as a whole bonding-side semiconductor layer 60. ¹⁶ / Cm ³ More than 1 × 10 ¹⁸ / Cm ³ Within the range of less than.
[0079]
Further, the cushion layer 20 shown in FIG. 3 has a slightly high sheet resistance due to a low dopant concentration, but the ITO electrode layer 30 having a very high conductivity is formed thereon. The current can be sufficiently spread. By adjusting the p-type dopant concentration in the above-described range, the cushion layer 20 has sufficient conductivity in the layer thickness direction. As a result, it is possible to uniformly supply the light to the light emitting layer portion 24. The luminous efficiency can be increased.
[0080]
Hereinafter, various modifications of the light emitting device of the present invention will be described. The light emitting element 300 of FIG. 16 is an example in which the concave portion 10 and the convex portion 11 are formed by the above-described mesa etching, and the concave portion 11 is further subjected to frost processing. The frosted surface 25 has a uniform and random roughness profile. In step 5 of FIG. 7, a frosted surface such as hydrofluoric acid (in the case where the outermost surface region of the compound semiconductor layer 61 is AlGaAs: in the case of GaP, hydrochloric acid) is used. It can be formed by anisotropically etching the surface of the convex portion 10 using a treatment liquid. In this configuration, the pattern etching surface formed by the concave portion 10 and the convex portion 11 (the top surface is a contact forming flat surface 11a) forms a primary roughness profile, and the surface of the concave portion 10 is formed by frost processing. A secondary roughness profile 25 finer than the primary roughness profile is superimposed. The primary roughness profile composed of the concave portion 10 and the convex portion 11 is such that the average interval between the convex portions 11 is 3 μm or more and 50 μm or less, and the distance between the bottom of the concave portion 10 and the top of the convex portion 11 is different. The height of the convex portion represented by the average value is 3 μm or more and 50 μm or less. In a convex portion having an average interval of less than 3 μm and a height of less than 3 μm, patterning by selective etching may be difficult. On the other hand, a convex portion having an average interval of more than 50 μm or a height of more than 50 μm saturates the effect of improving the light extraction efficiency, and leads to wasteful loss of the compound semiconductor by etching, which is uneconomical.
[0081]
Since the frost-treated surface is formed with minute irregularities at random, as shown in FIG. 15, when viewed locally, the inclined surfaces having various angles with respect to the in-plane direction of the light emitting layer portion 24 are fine. Since it is formed in a complicated manner, the probability that the emitted light flux is totally reflected at the interface is extremely low. The roughness of the minute irregularities is, for example, in the range of 0.01 μm or more and 1 μm or less in arithmetic average roughness measured by a method based on JIS: B0601.
[0082]
When the unevenness formed on the outermost surface of the compound semiconductor layer has an arithmetic mean roughness Ra of about 0.01 μm or more and 1 μm or less by frost treatment, the ITO electrode layer (transparent oxide electrode layer: (For example, 300 nm or more), the concave portion may be buried, and an uneven profile following the shape of the outermost surface of the compound semiconductor layer may not be formed on the surface of the ITO electrode layer. In this case, the luminous flux returning to the light emitting layer due to total reflection at the outermost surface of the ITO electrode layer increases, and the light extraction efficiency may be impaired. However, a convex portion having an average interval of the convex portions of 3 μm or more and a height of 3 μm or more represented by an average value of the distance between the bottom of the concave portion 10 and the top of the convex portion 11 is formed by pattern etching. In this case, even if a considerably thick ITO electrode layer is formed, the surface shape of the ITO electrode layer follows the profile of the convex portion, and the light extraction efficiency can be improved.
[0083]
Next, in the light emitting element 100 of FIG. 1, the bonding pad 9 shields most of the light from the light emitting layer section 24. Therefore, in the light emitting layer portion 24, the energizing current does not concentrate on the region directly below the bonding pad 9, that is, the first region where the amount of light extraction is small. Is preferably distributed as much as possible in order to increase the light extraction efficiency. Therefore, in the light emitting element 400 of FIG. 17, the contact layer 31 is not formed in the first region, which is a region directly below the bonding pad 9 and has a small light extraction amount, but is located in the second region around the bonding pad 9 where the light extraction amount is large. Only selectively formed. Since the contact layer 31 is not formed in the region directly below the bonding pad 9, the contact resistance of the ITO electrode layer 30 is increased in this region, so that current does not easily flow. As a result, the current supplied to the light emitting layer section 24 via the ITO electrode layer 30 is preferentially distributed to the second region where the light extraction amount is large, bypassing the first region where the light extraction amount is small, and Efficiency can be increased. Note that, in a region directly below the bonding pad 9, the outermost surface of the cushion layer 20 has a flat shape in which no concave portion or convex portion is formed. Thereby, the adhesion between the ITO electrode layer 30 and the bonding pad 9 is improved, and the surface of the bonding pad 9 is also smoothed, so that when the electrode wire 47 is automatically bonded by using image processing, surface roughness may occur. The advantage is obtained that false detection of images is reduced.
[0084]
FIG. 18 shows a step of manufacturing the light emitting device 400 of FIG. Until the step 2 in FIG. 7, the same steps as those of the light emitting device 100 in FIG. 1 are employed. Then, as shown in Step 11 of FIG. 18, an etching window 40w to be a region immediately below the bonding pad 9 is formed on the photoresist layer 40 by exposure and development. Then, in a step 12, the GaAs layer 31 "in the etching window 40w is removed by etching. Next, in a step 13, a photoresist layer 42 for blocking the inside of the etching window 40w and a convex portion 11 are formed. And a photoresist layer 41 for forming a non-etched region is formed by patterning by exposure and development, and as shown in step 14, the GaAs layer 31 ″ around the photoresist layer 41 is etched, Further, as shown in step 15, the cushion layer 20 is mesa-etched to form the concave portion 10. Further, if the ITO electrode layer 30 is formed as shown in Step 16, the following steps are the same as those of the light emitting device 100 in FIG.
[0085]
In the light emitting device 500 of FIG. 19, a plurality of convex portions 16 are dispersedly formed on the second main surface 7b of the GaP single crystal substrate 7 which is a transparent conductive substrate, This is an example in which the second main surface 7b is covered with a reflective metal layer 15 also serving as a back electrode. When viewed from the substrate side, the reflective metal layer 15 formed so as to follow the convex portion 16 forms a concave mirror-shaped light receiving surface 17 for the luminous flux from the light emitting layer portion 24, so that reflected light is extracted. It can be concentrated in the plane.
[0086]
In the light emitting device 600 shown in FIGS. 20 and 21, the concave surface 10 c having a curved cross section is formed on the outermost surface of the cushion layer (compound semiconductor layer) 20 with the remaining region forming the contact forming flat surface 11 r as a background. It is dispersed and formed in an island shape. In this embodiment, of the outermost surface of the cushion layer 20, the contact-forming flat surface 11r, which is the background, is uniformly covered with a photoresist layer, and a region to be the concave surface 10c is exposed in an island shape and is mesa-etched. Can be formed. Note that the bottom surface of the concave surface 10c may be partially flat. In FIG. 21, the contact layer 31 is selectively formed at a part of the contact forming flat surface 11r which is the background of the concave surface 10c, specifically, at a position surrounded by the plurality of concave surfaces 10c. However, it is a matter of course that the contact layer 31 may be formed on the entire surface of the contact formation flat surface 11r, as a matter of course.
[0087]
Further, in the above embodiment, the contact layer is made of a compound semiconductor. However, as shown in FIG. 24, a metal contact layer 131 can be formed. In FIG. 24, a metal contact layer 131 is selectively formed on the top of the convex portion 20b formed on the surface of the cushion layer 20. Since the metal contact layer 131 can be formed by vapor deposition or sputtering and does not need to be epitaxially grown on the cushion layer 20, the top surface of the convex portion 20b does not need to be particularly flat. As the material of the metal contact layer 131, Au alone and / or an alloy mainly composed of Au can be adopted, and for example, an AuGe alloy can be used.
[0088]
In the light emitting device 700 of FIG. 22, an n-type Si single crystal substrate 107, which is an opaque conductive substrate, is used instead of the GaP single crystal substrate 7, and the metal reflection layer 107m mainly composed of Ag or Au is used. Is formed on the first main surface 107a of the Si single crystal substrate 107, and the light emitting layer portion 24 is further formed thereon. The back electrode layer 15 is formed on the entire surface of the second main surface 107b of the Si single crystal substrate 107. According to this structure, the light emitted from the light emitting layer 24 is reflected by the metal reflective layer 107m and is superimposed on the light emitted directly from the light emitting layer 24 toward the ITO electrode layer 30, so that the light extraction efficiency is improved. .
[0089]
In the light emitting device 800 of FIG. 23, an n-type GaAs single crystal substrate 207 which is an opaque conductive substrate is used, and the DBR reflection layer 207d made of an AlGaAs / GaAs multilayer film is the same as the GaAs single crystal substrate 207. The light-emitting layer 24 is formed on one main surface 207a. The back electrode layer 15 is formed on the entire surface of the second main surface 207b of the GaAs single crystal substrate 207. According to this structure, the light emitted from the light emitting layer 24 is reflected by the DBR reflection layer 207m, and is superimposed on the light emitted directly from the light emitting layer 24 toward the ITO electrode layer 30. 23 is advantageous because the metal reflection layer of FIG. 23 has smaller dependency on the incident angle of the reflected light. However, the DBR reflection layer 207d is required to be epitaxially grown on the GaAs single crystal substrate 207 together with the light emitting layer section 24. Therefore, there is an advantage that the manufacturing process is simplified.
[0090]
In the above embodiment, each layer of the light emitting layer section 24 is formed of AlGaInP mixed crystal, but each layer (the p-type cladding layer 6, the active layer 5, and the n-type cladding layer 4) is formed of AlGaInN mixed crystal. You can also. Also, the p-type cladding layer 6 is located on the light extraction surface side where the ITO electrode layer 30 is formed, but the stacking order of the light emitting layer section 24 is reversed, and the n-type cladding layer 4 is located on the light extraction surface side. You may.
[Brief description of the drawings]
FIG. 1 is a schematic sectional view showing a first embodiment of a light emitting device of the present invention.
FIG. 2 is a schematic plan view of the same.
FIG. 3 is an enlarged schematic view showing a main part of the light emitting device of FIG. 1;
FIG. 4 is an explanatory diagram of an operation of the light emitting device of FIG. 1;
FIG. 5 is an explanatory diagram showing a defect of a light emitting element of a comparative example.
FIG. 6 is an explanatory view showing an example of a manufacturing process of the light-emitting element of FIG.
FIG. 7 is an explanatory view following FIG. 6;
FIG. 8 is an explanatory view following FIG. 7;
FIG. 9 is a view for explaining the operation of the cushion layer.
FIG. 10 is a view for explaining a problem when there is no cushion layer.
FIG. 11 is a diagram schematically showing an example of an In concentration distribution in a contact layer.
FIG. 12 is a diagram schematically showing another example of the In concentration distribution in the contact layer.
FIG. 13 is a schematic diagram showing an example of a band structure of a contact layer when an intermediate layer is not formed.
FIG. 14 is a schematic view showing an example of a band structure of a contact layer when an intermediate layer is formed.
FIG. 15 is an explanatory diagram of an operation of the light emitting element when a frosted surface is formed.
FIG. 16 is a schematic sectional view showing a third embodiment of the light emitting device of the present invention.
FIG. 17 is a schematic sectional view showing a fourth embodiment of the light emitting device of the present invention.
FIG. 18 is a view illustrating a manufacturing process of the light-emitting element of FIG.
FIG. 19 is a schematic sectional view showing a fifth embodiment of the light emitting device of the present invention.
FIG. 20 is a schematic sectional view showing a sixth embodiment of the light emitting device of the present invention.
FIG. 21 is a schematic plan view of the same.
FIG. 22 is a schematic sectional view showing a seventh embodiment of the light emitting device of the present invention.
FIG. 23 is a schematic sectional view showing an eighth embodiment of the light emitting device of the present invention.
FIG. 24 is a schematic sectional view showing an example in which a contact layer is made of metal.
FIG. 25 is a schematic sectional view showing an example in which the bottom surface of the concave portion is formed flat.
[Explanation of symbols]
4 n-type cladding layer (first conductivity type cladding layer)
5 Active layer
6 p-type cladding layer (second conductivity type cladding layer)
9 Bonding pad
10 Concave part
11 convex part
11a, 11r Contact forming flat surface 11r
24 Light emitting layer
25 Roughened area
20 cushion layer
30 ITO electrode layer
31 Contact layer
60 Bonding side semiconductor layer
61 Compound semiconductor layer
100, 200, 300, 400, 500, 600, 700, 800 light emitting device

Claims (20)

A compound semiconductor layer having a light emitting layer portion, and an oxide transparent electrode layer formed so as to cover a main surface of the compound semiconductor layer, for applying a light emission drive voltage to the light emitting layer portion, The light from the light-emitting layer portion, in a light-emitting element to take out in the form of transmitting the oxide transparent electrode layer,
A contact layer for reducing the junction resistance of the oxide transparent electrode layer is disposed between the compound semiconductor layer and the oxide transparent electrode layer so as to be in contact with the oxide transparent electrode layer. At the junction interface of the electrode layer, the formation region and the non-formation region of the contact layer are mixed, and
The light emitting device according to claim 1, wherein an outermost surface of the compound semiconductor layer has a concave surface in which at least a part of a region where the contact layer is not formed is recessed toward the light emitting layer portion side from a remaining region. The convex portions are dispersedly formed on the outermost surface of the compound semiconductor layer, and the contact layers are also dispersedly formed corresponding to the convex portions, and the contact layers are formed by the oxide transparent electrode layer. The light emitting device according to claim 1, wherein the light emitting device is electrically connected in an in-plane direction. 3. The light emitting device according to claim 2, wherein the contact layer is made of a metal, and a contact layer made of the metal is selectively formed on the top of the projection. The outermost surface of the compound semiconductor layer is a pattern etching surface in which a concave portion corresponding to an etching region and a convex portion corresponding to a non-etching region are mixed by pattern etching, and the contact layer is The light emitting device according to claim 1, wherein the light emitting device is selectively formed on a top surface of the portion. The secondary roughness profile finer than the primary roughness profile was further superimposed as a frost-processed surface by anisotropic etching on the primary roughness profile formed by the concave and convex portions forming the pattern etching surface. The light-emitting device according to claim 4, wherein: The light emitting device according to claim 4, wherein an outermost surface of the transparent oxide electrode layer is undulated with a profile following the concave portion and the convex portion forming the pattern etching surface. . The contact layer formation region on the outermost surface of the compound semiconductor layer is a contact formation flat surface orthogonal to a thickness direction of the light emitting layer portion, and a contact layer made of a compound semiconductor is provided on the contact layer formation flat surface. The light emitting device according to claim 2, wherein the light emitting device is formed by epitaxial growth. The flat surface on which the contact is formed is formed on the outermost surface of the compound semiconductor layer in an island shape with the remaining region as a background, and the remaining region is recessed from the flat surface on which the contact is formed. 8. The light emitting device according to claim 7, wherein said light emitting element has a concave surface having at least a curved cross section around said contact layer. 8. The light emitting device according to claim 7, wherein the concave surface on the outermost surface of the compound semiconductor layer is dispersedly formed in an island shape with the remaining region forming the contact forming flat surface as a background. A metal bonding pad is disposed on the oxide transparent electrode layer, and a current-carrying electrode wire is bonded to the bonding pad,
10. The semiconductor device according to claim 1, wherein a region immediately below the bonding pad on the outermost surface of the compound semiconductor layer is formed flat, and the contact layer is not formed in the region directly below the bonding pad. Item 2. The light-emitting element according to item 1. A compound semiconductor layer having a light emitting layer portion, and an oxide transparent electrode layer formed so as to cover a main surface of the compound semiconductor layer, for applying a light emission drive voltage to the light emitting layer portion, The light from the light-emitting layer portion, in a light-emitting element to take out in the form of transmitting the oxide transparent electrode layer,
A contact layer for reducing the junction resistance of the oxide transparent electrode layer is disposed between the compound semiconductor layer and the oxide transparent electrode layer so as to be in contact with the oxide transparent electrode layer. At the junction interface of the electrode layer, the formation region and the non-formation region of the contact layer are mixed, and
The contact layer formation region on the outermost surface of the compound semiconductor layer is a contact formation flat surface orthogonal to a thickness direction of the light emitting layer portion, and a contact layer made of a compound semiconductor is epitaxially grown on the contact formation flat surface. Have been
A light emitting device, wherein at least a part of a non-formation region of the contact layer is a surface roughened region which is rougher than the contact formation flat surface. 12. The light emitting device according to claim 11, wherein a plurality of the contact forming flat surfaces are dispersedly formed on the outermost surface of the compound semiconductor layer, and the contact layer is formed on each contact forming flat surface. The light-emitting layer portion, the first conductivity type clad layer, the active layer and the second conductivity type clad layer is made of a compound semiconductor having a double hetero structure laminated in this order,
A metal bonding pad is disposed on the oxide transparent electrode layer, and a current-carrying electrode wire is bonded to the bonding pad,
Including the outermost surface of the compound semiconductor layer, a portion located between the active layer and the contact layer is a bonding-side semiconductor layer having a thickness of 0.6 μm or more and less than 10 μm including the second conductivity type cladding layer. The light-emitting device according to any one of claims 1 to 12, which is formed. The bonding-side semiconductor layer is disposed in contact with the second conductive type clad layer and the oxide transparent electrode layer side of the second conductive type clad layer, and has a lower dopant concentration than the second conductive type clad layer. The light emitting device according to claim 13, further comprising a cushion layer made of a compound semiconductor. The light emitting layer portion is disposed on the first main surface side of the conductive substrate, and between the first main surface of the conductive substrate and the light emitting layer portion, the luminous flux from the light emitting layer portion, The light emitting device according to any one of claims 1 to 14, wherein a reflection layer that reflects light is formed on the oxide transparent electrode layer side. The light emitting layer portion is disposed on the first main surface side of the transparent conductive substrate, while the second main surface of the transparent conductive substrate is covered by a reflective metal layer also serving as a back electrode. The light emitting device according to claim 1. A plurality of convex portions are dispersedly formed on a second main surface of the transparent conductive substrate, and the second main surface is covered with the reflective metal layer in a manner following the convex portions. Item 17. A light emitting device according to Item 16. A compound semiconductor layer having a light emitting layer portion, and an oxide transparent electrode layer formed so as to cover a main surface of the compound semiconductor layer, for applying a light emission drive voltage to the light emitting layer portion, The light from the light-emitting layer portion, in a light-emitting element to take out in the form of transmitting the oxide transparent electrode layer,
The main surface of the compound semiconductor layer is formed by pattern etching to have a pattern etching surface in which a concave portion corresponding to an etching region and a convex portion corresponding to a non-etching region are mixed. element. 19. The light emitting device according to claim 18, wherein the outermost surface of the oxide transparent electrode layer is undulated with a profile following the concave portion and the convex portion forming the pattern etching surface. The secondary roughness profile finer than the primary roughness profile was further superimposed as a frost-processed surface by anisotropic etching on the primary roughness profile formed by the concave and convex portions forming the pattern etching surface. The light-emitting device according to claim 18, wherein:

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