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JP2004172247A - Semiconductor device - Google Patents

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Publication number
JP2004172247A
JP2004172247A JP2002334564A JP2002334564A JP2004172247A JP 2004172247 A JP2004172247 A JP 2004172247A JP 2002334564 A JP2002334564 A JP 2002334564A JP 2002334564 A JP2002334564 A JP 2002334564A JP 2004172247 A JP2004172247 A JP 2004172247A
Authority
JP
Japan
Prior art keywords
wiring layer
main surface
multilayer substrate
semiconductor element
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002334564A
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Japanese (ja)
Inventor
Shigehiro Hosoi
重広 細井
Toshihiro Okamoto
敏宏 岡本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
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Toshiba Corp
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Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2002334564A priority Critical patent/JP2004172247A/en
Publication of JP2004172247A publication Critical patent/JP2004172247A/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor device having an electromagnetic shielding performance and an excellent airtightness. <P>SOLUTION: On a surface (a first main surface) of a multilayer substrate 1 laminated by insulation substrates comprising alumina which includes ferrite, a plurality of passive element comprising a semiconductor element 21, a chip resistor 22, a chip capacitor 23, an inductor 24, or the like are electrically and mechanically fixed by alloy material 25. Both the ends of the surface (the first main surface) of the multilayer substrate 1 and an insulation cap 32 comprising alumina which includes ferrite are firmly fixed by an adhesive agent 31, and these mounted components 21, 22, 23, 24, the alloy material 5, and a bonding wire 27 are hermetically sealed by the multilayer substrate 1 and the insulation cap 32. <P>COPYRIGHT: (C)2004,JPO

Description

【0001】
【発明の属する技術分野】
本発明は、携帯無線電話機や自動車電話機等の電子機器に使用される高周波モジュールに代表される半導体装置に係わり、特に、高周波領域における電磁波の障害を抑制し、信頼性に優れた半導体装置に関する。
【0002】
【従来の技術】
近年、高周波モジュールにおいては、小型・薄型化、および高機能化とともに、高周波モジュール内で発生する電磁波をモジュール外に放出しないこと、また外部からの電磁波の進入を防止する等の電磁波の障害を防止することを要求されている。この種の高周波モジュールとしては、図3で示すものが知られている(例えば、特許文献1参照。)。図3は高周波モジュールを示す断面図である。
【0003】
この特許文献に開示された高周波モジュール140は、図3に示すように、金属基板101の表面に絶縁層102を介して配線層105が選択形成され、この金属基板101の所定の配線層105上に、半導体素子121と、チップ抵抗体122やチップコンデンサ123等からなる複数の受動素子と、外部端子128とが合金材125により電気的および機械的に固着されている。
【0004】
また、半導体素子121の電極126と配線層105とは、ボンデイングワイヤ127で電気的に接続されている。これらの搭載部品121、122、123、外部端子128、合金材125、ボンデイングワイヤ127および金属基板101は、フェライトを含むモールド樹脂130で気密封止されている。
【0005】
【特許文献1】
特開平11―40708号公報(第11頁、図1)
【0006】
【発明が解決しようとする課題】
上述した従来の高周波モジュールでは、電磁波の障害を防止するためにフェライトを含むモールド樹脂130で搭載部品等を覆うことより、高周波モジュール内で発生する電磁波の外部への放出および高周波モジュール外からの電磁波の進入を防ぎ、さらに、このモールド樹脂130の熱膨張係数を金属基板101の熱膨張係数に近づけることにより、金属基板101とモールド樹脂130間の接合界面の剥離を防止している。
【0007】
ところが、最近の携帯無線電話機や自動車電話機に用いられる高周波モジュールにおいては、更なる高機能化および多機能化が要求され、そのために高周波モジュールに採用する基板には、表面に配線層を有するセラミック基板を積層形成してなる多層セラミック基板が採用されるようになってきた。
【0008】
しかし、このような多層セラミック基板の熱膨張係数は、モールド樹脂の熱膨張係数よりも1/2から1/6と小さく、多層セラミック基板上の搭載部品等をモールド樹脂で封止してなる高周波モジュールにおいては、多層セラミック基板とモールド樹脂の接合界面の剥離が起こり、水分等の進入により信頼性が低下するという問題を有していた。
【0009】
本発明は、上記問題を解決するためになされたもので、その目的とするところは、電磁遮断機能を有し、機密性に優れた高信頼性の半導体装置を提供することにある。
【0010】
【課題を解決するための手段】
上記目的を達成するために、本発明の半導体装置は、主面に配線層を有する絶縁性基板が積層されてなり、この積層構造の絶縁性基板の第1主面上に第1の配線層が設けられ、前記積層構造の絶縁性基板間に第2の配線層が設けられ、前記第1主面と相対向する第2主面上に第3の配線層が設けられ、第1乃至第3の配線層間がビアを介して電気的に接続され、且つ前記絶縁性基板にフェライトが含有されている多層基板と、この多層基板の第1主面上に設けられ、前記第1の配線層と電気的に接続された半導体素子および受動素子と、この半導体素子および受動素子を覆って、前記多層基板の第1主面に封着され、且つフェライトを含む絶縁性キャップとを具備することを特徴とする。
【0011】
本発明によれば、多層基板と絶縁性キャップとにフェライトが含有されているので、電磁波の外部への放出および外部からの進入が防止されるとともに、多層基板と絶縁性キャップとの熱膨張係数が近似した値を有するため、両者の封着部分は気密性を保持することになる。
【0012】
従って、電磁遮蔽機能を有し、気密性に優れた高信頼性の高周波モジュールからなる半導体装置を提供できる。
【0013】
【発明の実施の形態】
以下本発明の実施形態について図面を参照しながら説明する。
【0014】
(第1の実施の形態)
まず、本発明の第1の実施の形態に係わる半導体装置としての高周波モジュールについて図1を参照して説明する。図1は高周波モジュールを示す断面図である。
【0015】
図1に示すように、本実施の形態の高周波モジュール40は、表面(第1主面)にキャビティ(凹部)2が形成されたアルミナ製の多層基板1と、このキャビティ2内に半導体素子21およびチップ抵抗体22、コンデンサ23、インダクタ24等の複数の受動素子と、この半導体素子21および受動素子を気密封止する絶縁性キャップ32とを備えている。
【0016】
この多層基板1は、表面に配線層4が所定パターンに形成され、且つフェライトを含むアルミナ製の絶縁性基板3a、3b、3c、3dと、表面にキャビティ2が設けられ、このキャビティ2の底面に配線層6が所定パターンに形成され、且つフェライトを含むアルミナ製の絶縁性基板3eとをこの順序で積層し、燒結して形成している。また、多層基板1の裏面(第2主面)には、全面にグランドとしての配線層5が形成されている。
【0017】
これらの配線層4,5,6は、例えばCuからなり、キャビテイ内の配線層(第1の配線層)6は、実装される半導体素子21およびチップ抵抗体22、コンデンサ23、インダクタ24等の電極の配置に対応して形成され、この第1の配線層6、絶縁性基板3間の配線層(第2の配線層)4a、4b、4c、4dおよび第3の配線層5は、所定の絶縁性基板3a、3b、3c、3d、3eを貫通して設けられたビア7で電気的に接続されている。さらに、キャビティ2の底面における実装面から絶縁性基板3aの裏面に至るまでの絶縁性基板を貫通してビアホールが設けられ、金属が埋め込まれた熱伝導性に優れたサーマルビア8が形成されている。
【0018】
そして、多層基板1表面のキャビティ2内の所定の第1の配線層6に、例えば、パワーアンプ機能のGaAsHBTからなる半導体素子21がSn−Sbからなる合金材25により固着され、サーマルビア8を介してグランドとしての第3の配線層5に接続されると共に電極26と第1の配線層6とが、ボンデイングワイヤ27で電気的に接続されている。また、チップ抵抗体22、チップコンデンサ23およびインダクタ24等からなる複数の受動素子とが合金材25により他の所定の第1の配線層6にそれぞれ電気的及び機械的に固着されている。
【0019】
さらに、多層基板1表面のキャビティ2上にフェライトを含むアルミナ製の絶縁性キャップ32が配設され、キャビティ2の周縁部に接着剤31で封着され、これら搭載部品21、22、23、24、合金材5やボンデイングワイヤ27は、多層基板1と絶縁性キャップ32で気密封止されている。
【0020】
ここで使用されるフェライトは、金属と鉄酸化物とからなり、具体的にはNiFe2O4、ZnFe2O4、CdFe2O4、CoFe2O4、CuFe2O4、MgFe2O4、MnFe2O4、BaFe2O4、SrFe2O4、PbFe2O4およびそれらの混合物である。
【0021】
なお、フェライトを含有するアルミナからなる多層基板1とフェライトを含有するアルミナからなる絶縁性キャップ32の熱膨張係数は、GaAsの熱膨張係数5.7ppm/Kに近い値を有する。
【0022】
上述したような本実施の形態の高周波モジュールにおいては、多層基板1と絶縁性キャップ32とにフェライトが含まれていることから、高周波モジュール40内で発生する電磁波の外部への放出および外部からの電磁波の進入が防止でき、また、多層基板1と絶縁性キャップ32の熱膨張係数がほぼ同じであることから、接着剤31の剥離がほとんどなく、高周波モジュール40内への水分等の進入により高周波モジュール40の信頼性が低下するという問題も発生しない。
【0023】
さらに、多層基板1の熱膨張係数と半導体素子21の熱膨張係数が近い値であることから、熱サイクルによって発生する半導体素子21の多層基板1からの剥離という問題も発生しない。
【0024】
(第2の実施の形態)
次に、本発明の第2の実施の形態に係わる半導体装置としての高周波モジュールについて図2を参照して説明する。図2は高周波モジュールを示す断面図である。なお、図において、第1の実施の形態と同一構成部分には、同一符号を付している。
【0025】
図2示すように、本実施の形態の高周波モジュール40aは、表面にキャビティ2が形成された窒化アルミ(AlN)製の多層基板1と、このキャビティ2内に第1の半導体素子21および第2の半導体素子21a並びにチップ抵抗体22、コンデンサ23、インダクタ24等の複数の受動素子を気密封止する絶縁性キャップ32を備えている。
【0026】
この多層基板1は、表面に配線層4が所定パターンに形成されたフェライトを含む窒化アルミ(AlN)からなる絶縁性基板3a、3b、3c、3dと、表面にキャビティ2が設けられ、このキャビティ2の底面に配線層6が所定パターンに形成され、且つフェライトを含む窒化アルミ(AlN)からなる絶縁性基板3eとをこの順序で積層し、燒結して形成している。また、多層基板1の裏面(第2主面)には、全面にグランドとしての配線層5が形成されている。
【0027】
これらの配線層4,5,6は、例えばCuからなり、キャビティ2内の配線層(第1の配線層)6は、実装される第1および第2半導体素子21、21a並びにチップ抵抗体22、コンデンサ23、インダクタ24等受動素子の電極の配置に対応して形成され、第1の配線層6、絶縁性基板3間の配線層(第2の配線層)4a、4b、4c、4d、および裏面の第3の配線層5は、所定の絶縁性基板3a、3b、3c、3c、3eを貫通して設けられたビア7で電気的に接続されている。さらに、キャビティ2の底面における実装面から絶縁性基板3aの裏面に至るまでの絶縁性基板を貫通してビアホールが設けられ、金属が埋め込まれた熱伝導性に優れたサーマルビア8が形成されている。
【0028】
そして、多層基板1表面のキャビティ2内に、例えば、パワーアンプからなる第1のシリコン半導体素子21が、フェースダウンして設けられ、バンプ33によって所定の第1の配線層6に固着されている。また、例えば、入力制御機能を有する第2のシリコン半導体素子21aが、他の第1の配線層6にSn−Pbからなる合金材25によって固着されてサーマルビア8を介して第3の配線層8と電気的に接続されると共に電極26と第1の配線層6とが、ボンデイングワイヤ27で電気的に接続されている。さらに、チップ抵抗体22、チップコンデンサ23およびインダクタ24等からなる複数の受動素子が合金材25により他の第1の配線層6にそれぞれ電気的及び機械的に固着されている。
【0029】
上記絶縁性キャップ32は、フェライトを含む窒化アルミ(AlN)からなり、内側面に合金材25が設けられ、外側面に例えば、Cuからなる放熱板34が設けられ、合金材25と放熱板34とがビア9を介して互いに接続された構造に形成されている。
【0030】
そして、この絶縁性キャップ32は、多層基板1表面のキャビティ2上に配設され、第1のシリコン半導体素子21の裏面と合金材25を介して固着されると共に、キャビティ2の周縁部に接着剤31により封着され、これら搭載部品21、21a、22、23、24、合金材5、バンプ33やボンデイングワイヤ27を気密封止している。
【0031】
なお、フェライトを含有する窒化アルミ(AlN)からなる多層基板1とフェライトを含有する窒化アルミ(AlN)からなる絶縁性キャップ32の熱膨張係数は、シリコンの熱膨張係数3.5ppm/Kに近い値を有する。
【0032】
上述したような本実施の形態の高周波モジュールにおいては、第1の実施の形態と同様に、高周波モジュール40a内で発生する電磁波の外部への放出および外部からの電磁波の進入が防止でき、また、高周波モジュール40a内への水分等の進入により高周波モジュール40aの信頼性が低下するという問題も発生しない。さらに、熱サイクルによって発生する半導体素子21aの多層基板1からの剥離および半導体素子21の絶縁性キャップ32からの剥離という問題も発生しない。
【0033】
また、本実施の形態では、絶縁性キャップ32に放熱板34を設け、この放熱板34にシリコン半導体素子21の裏面をビア9を介して接続しているので、シリコン半導体素子21の動作時の温度上昇が抑制されパワーアンプの効率が向上する。
【0034】
本発明は、上記実施の形態に限定されるものではなく、発明の要旨を逸脱しない範囲で、種々、変更しても良い。例えば、上記第1及び第2の実施の形態では、多層基板の絶縁基板としてアルミナ及び窒化アルミを用いているが、ガラス・セラミックス系絶縁体、アラミド・エポキシ系絶縁体およびガラス・エポキシ系絶縁体を用いてもよい。
【0035】
また、多層基板の第1主面にキャビティを設けたが、必ずしもキャビティは必要ではない。
【0036】
【発明の効果】
本発明によれば、電磁遮断性能を有し、機密性に優れた高信頼性の半導体装置が提供できる。
【図面の簡単な説明】
【図1】本発明の第1の実施の形態に係わる高周波モジュールを示す断面図。
【図2】本発明の第2の実施の形態に係わる高周波モジュールを示す断面図。
【図3】従来の高周波モジュールを示す断面図。
【符号の説明】
1 多層基板
2 キャビティ
3a、3b、3c、3d、3e 絶縁性基板
4a、4b、4c、4d 第2の配線層
5 第3の配線層
6 第1の配線層
7、9 ビア
8 サーマルビア
21、21a、121 半導体素子
22、122 チップ抵抗体
23、123 チップコンデンサ
24 インダクタ
25、125 合金材
26、126 電極
27、127 ボンデイングワイヤ
128 外部端子
31 接着剤
32 絶縁性キャップ
33 バンプ
34 放熱版
101 金属基板
102 絶縁層
105 配線層
130 モールド樹脂
40、40a、140 高周波モジュール
[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device typified by a high-frequency module used for an electronic device such as a portable radio telephone or a car telephone, and more particularly to a semiconductor device which suppresses electromagnetic wave disturbance in a high-frequency region and has excellent reliability.
[0002]
[Prior art]
In recent years, high-frequency modules have become smaller, thinner, and more sophisticated, while preventing electromagnetic waves generated in the high-frequency module from being emitted to the outside of the module and preventing electromagnetic wave disturbances such as preventing electromagnetic waves from entering from outside. Is required to do so. As this type of high-frequency module, the one shown in FIG. 3 is known (for example, see Patent Document 1). FIG. 3 is a sectional view showing the high-frequency module.
[0003]
In the high-frequency module 140 disclosed in this patent document, as shown in FIG. 3, a wiring layer 105 is selectively formed on a surface of a metal substrate 101 with an insulating layer 102 interposed therebetween. In addition, a semiconductor element 121, a plurality of passive elements including a chip resistor 122 and a chip capacitor 123, and an external terminal 128 are electrically and mechanically fixed by an alloy material 125.
[0004]
The electrode 126 of the semiconductor element 121 and the wiring layer 105 are electrically connected by a bonding wire 127. These mounted components 121, 122, 123, external terminals 128, alloy material 125, bonding wires 127, and metal substrate 101 are hermetically sealed with mold resin 130 containing ferrite.
[0005]
[Patent Document 1]
JP-A-11-40708 (page 11, FIG. 1)
[0006]
[Problems to be solved by the invention]
In the above-described conventional high-frequency module, the mounted components and the like are covered with the mold resin 130 containing ferrite in order to prevent interference of electromagnetic waves, so that electromagnetic waves generated inside the high-frequency module are emitted to the outside and electromagnetic waves from outside the high-frequency module are And the thermal expansion coefficient of the mold resin 130 is made closer to the thermal expansion coefficient of the metal substrate 101, thereby preventing separation of the bonding interface between the metal substrate 101 and the mold resin 130.
[0007]
However, high-frequency modules used in recent mobile radiotelephones and automobile telephones are required to have even higher functions and more functions. For this reason, substrates used in high-frequency modules are ceramic substrates having a wiring layer on the surface. Have been adopted.
[0008]
However, the coefficient of thermal expansion of such a multilayer ceramic substrate is smaller than the coefficient of thermal expansion of the mold resin by half to one-sixth. The module has a problem that the bonding interface between the multilayer ceramic substrate and the mold resin is peeled off, and the reliability is reduced due to the entry of moisture and the like.
[0009]
The present invention has been made to solve the above problems, and an object of the present invention is to provide a highly reliable semiconductor device having an electromagnetic shielding function and excellent in confidentiality.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor device according to the present invention includes an insulating substrate having a wiring layer on a main surface thereof laminated, and a first wiring layer on a first main surface of the insulating substrate having the laminated structure. Is provided, a second wiring layer is provided between the insulating substrates of the laminated structure, and a third wiring layer is provided on a second main surface opposite to the first main surface, and 3 is electrically connected through vias, and the insulating substrate contains ferrite, and the first wiring layer is provided on a first main surface of the multilayer substrate. A semiconductor element and a passive element that are electrically connected to the semiconductor element and a passive element, and an insulating cap that covers the semiconductor element and the passive element, is sealed on the first main surface of the multilayer substrate, and includes ferrite. Features.
[0011]
According to the present invention, since the ferrite is contained in the multilayer substrate and the insulating cap, emission of electromagnetic waves to the outside and entry from the outside are prevented, and the coefficient of thermal expansion between the multilayer substrate and the insulating cap is reduced. Has an approximate value, so that the sealed portions of the two maintain airtightness.
[0012]
Therefore, it is possible to provide a semiconductor device including a high-reliability high-frequency module having an electromagnetic shielding function and excellent airtightness.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0014]
(First Embodiment)
First, a high-frequency module as a semiconductor device according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a sectional view showing the high-frequency module.
[0015]
As shown in FIG. 1, a high-frequency module 40 according to the present embodiment has a multilayer substrate 1 made of alumina having a cavity (recess) 2 formed on the surface (first main surface), and a semiconductor element 21 in the cavity 2. And a plurality of passive elements such as a chip resistor 22, a capacitor 23, and an inductor 24, and an insulating cap 32 for hermetically sealing the semiconductor element 21 and the passive elements.
[0016]
The multilayer substrate 1 has an insulating substrate 3a, 3b, 3c, 3d made of alumina containing a ferrite, a wiring layer 4 formed on a surface thereof, a ferrite, and a cavity 2 on the surface. A wiring layer 6 is formed in a predetermined pattern, and an insulating substrate 3e made of alumina containing ferrite is laminated in this order and sintered. A wiring layer 5 as a ground is formed on the entire back surface (second main surface) of the multilayer substrate 1.
[0017]
The wiring layers 4, 5, and 6 are made of, for example, Cu, and the wiring layer (first wiring layer) 6 in the cavity is used for mounting the semiconductor element 21 and the chip resistor 22, the capacitor 23, the inductor 24, and the like. The first wiring layer 6, the wiring layers (second wiring layers) 4a, 4b, 4c, 4d between the insulating substrate 3 and the third wiring layer 5 are formed corresponding to the arrangement of the electrodes. Are electrically connected by vias 7 provided through the insulating substrates 3a, 3b, 3c, 3d, and 3e. Further, via holes are provided through the insulating substrate from the mounting surface on the bottom surface of the cavity 2 to the back surface of the insulating substrate 3a, and a thermal via 8 having excellent thermal conductivity in which a metal is embedded is formed. I have.
[0018]
Then, for example, a semiconductor element 21 made of GaAsHBT having a power amplifier function is fixed to a predetermined first wiring layer 6 in the cavity 2 on the surface of the multilayer substrate 1 by an alloy material 25 made of Sn-Sb, and the thermal via 8 is formed. The electrode 26 and the first wiring layer 6 are electrically connected to the third wiring layer 5 serving as ground via a bonding wire 27. In addition, a plurality of passive elements including the chip resistor 22, the chip capacitor 23, the inductor 24, and the like are electrically and mechanically fixed to the other predetermined first wiring layer 6 by the alloy material 25.
[0019]
Further, an insulating cap 32 made of alumina containing ferrite is provided on the cavity 2 on the surface of the multilayer substrate 1 and sealed around the periphery of the cavity 2 with an adhesive 31, and these mounted components 21, 22, 23, 24 The alloy material 5 and the bonding wire 27 are hermetically sealed with the multilayer substrate 1 and the insulating cap 32.
[0020]
The ferrite used here is composed of a metal and an iron oxide, specifically, NiFe2O4, ZnFe2O4, CdFe2O4, CoFe2O4, CuFe2O4, MgFe2O4, MnFe2O4, BaFe2O4, SrFe2O4, PbFe2O4, and a mixture thereof.
[0021]
The thermal expansion coefficients of the multilayer substrate 1 made of alumina containing ferrite and the insulating cap 32 made of alumina containing ferrite have values close to the thermal expansion coefficient of GaAs of 5.7 ppm / K.
[0022]
In the high-frequency module of the present embodiment as described above, since the multilayer substrate 1 and the insulating cap 32 contain ferrite, the electromagnetic waves generated in the high-frequency module 40 are emitted to the outside and emitted from the outside. Electromagnetic waves can be prevented from entering, and since the multilayer substrate 1 and the insulating cap 32 have substantially the same coefficient of thermal expansion, there is almost no peeling of the adhesive 31, and the entry of moisture and the like into the high-frequency module 40 causes high-frequency waves. There is no problem that the reliability of the module 40 is reduced.
[0023]
Further, since the coefficient of thermal expansion of the multilayer substrate 1 and the coefficient of thermal expansion of the semiconductor element 21 are close to each other, there is no problem that the semiconductor element 21 is separated from the multilayer substrate 1 due to a thermal cycle.
[0024]
(Second embodiment)
Next, a high-frequency module as a semiconductor device according to a second embodiment of the present invention will be described with reference to FIG. FIG. 2 is a sectional view showing the high-frequency module. In the drawings, the same components as those in the first embodiment are denoted by the same reference numerals.
[0025]
As shown in FIG. 2, a high-frequency module 40a according to the present embodiment includes a multilayer substrate 1 made of aluminum nitride (AlN) having a cavity 2 formed on a surface thereof, a first semiconductor element 21 and a second An insulating cap 32 for hermetically sealing a plurality of passive elements such as the semiconductor element 21a and the chip resistor 22, the capacitor 23, and the inductor 24 is provided.
[0026]
This multilayer substrate 1 is provided with insulating substrates 3a, 3b, 3c, 3d made of aluminum nitride (AlN) containing ferrite having a wiring layer 4 formed in a predetermined pattern on the surface and a cavity 2 on the surface. A wiring layer 6 is formed in a predetermined pattern on the bottom surface of the substrate 2, and an insulating substrate 3e made of aluminum nitride (AlN) containing ferrite is laminated in this order and sintered. A wiring layer 5 as a ground is formed on the entire back surface (second main surface) of the multilayer substrate 1.
[0027]
The wiring layers 4, 5, and 6 are made of, for example, Cu, and the wiring layer (first wiring layer) 6 in the cavity 2 includes first and second semiconductor elements 21, 21a and a chip resistor 22 to be mounted. , The capacitor 23, the inductor 24, and the like, and are formed corresponding to the arrangement of the electrodes of the passive elements, and the wiring layers (second wiring layers) 4a, 4b, 4c, 4d between the first wiring layer 6 and the insulating substrate 3 are formed. The third wiring layer 5 on the back surface is electrically connected to via holes 7 provided through predetermined insulating substrates 3a, 3b, 3c, 3c and 3e. Further, via holes are provided through the insulating substrate from the mounting surface on the bottom surface of the cavity 2 to the back surface of the insulating substrate 3a, and a thermal via 8 having excellent thermal conductivity in which a metal is embedded is formed. I have.
[0028]
A first silicon semiconductor element 21 composed of, for example, a power amplifier is provided face-down in the cavity 2 on the surface of the multilayer substrate 1, and is fixed to a predetermined first wiring layer 6 by a bump 33. . Further, for example, a second silicon semiconductor element 21 a having an input control function is fixed to another first wiring layer 6 by an alloy material 25 made of Sn—Pb, and the third wiring layer The electrode 26 and the first wiring layer 6 are electrically connected to each other by a bonding wire 27. Further, a plurality of passive elements including a chip resistor 22, a chip capacitor 23, an inductor 24, and the like are electrically and mechanically fixed to the other first wiring layer 6 by an alloy material 25.
[0029]
The insulating cap 32 is made of aluminum nitride (AlN) containing ferrite. The alloy material 25 is provided on the inner surface, and a heat radiating plate 34 made of, for example, Cu is provided on the outer surface. Are formed in a structure connected to each other via a via 9.
[0030]
The insulating cap 32 is disposed on the cavity 2 on the surface of the multilayer substrate 1 and is fixed to the back surface of the first silicon semiconductor element 21 via the alloy material 25 and adheres to the peripheral edge of the cavity 2. The components 31, 21a, 22, 23, and 24, the alloy material 5, the bumps 33, and the bonding wires 27 are hermetically sealed with an agent 31.
[0031]
The thermal expansion coefficients of the multilayer substrate 1 made of aluminum nitride (AlN) containing ferrite and the insulating cap 32 made of aluminum nitride (AlN) containing ferrite are close to the thermal expansion coefficient of silicon, 3.5 ppm / K. Has a value.
[0032]
In the high-frequency module of the present embodiment as described above, similarly to the first embodiment, it is possible to prevent the electromagnetic waves generated in the high-frequency module 40a from being released to the outside and from entering the electromagnetic waves from the outside. There is no problem that the reliability of the high-frequency module 40a is reduced due to the entry of moisture or the like into the high-frequency module 40a. Further, there is no problem of peeling of the semiconductor element 21a from the multilayer substrate 1 and peeling of the semiconductor element 21 from the insulating cap 32 caused by the thermal cycle.
[0033]
Further, in the present embodiment, since the heat radiating plate 34 is provided on the insulating cap 32 and the back surface of the silicon semiconductor element 21 is connected to the heat radiating plate 34 via the via 9, the operation of the silicon semiconductor element 21 during operation is Temperature rise is suppressed, and the efficiency of the power amplifier is improved.
[0034]
The present invention is not limited to the above embodiment, and may be variously changed without departing from the gist of the invention. For example, in the first and second embodiments, alumina and aluminum nitride are used as the insulating substrate of the multilayer substrate. However, glass-ceramic-based insulators, aramid-epoxy-based insulators, and glass-epoxy-based insulators May be used.
[0035]
Although the cavity is provided on the first main surface of the multilayer substrate, the cavity is not necessarily required.
[0036]
【The invention's effect】
According to the present invention, it is possible to provide a highly reliable semiconductor device having electromagnetic shielding performance and excellent confidentiality.
[Brief description of the drawings]
FIG. 1 is a sectional view showing a high-frequency module according to a first embodiment of the present invention.
FIG. 2 is a sectional view showing a high-frequency module according to a second embodiment of the present invention.
FIG. 3 is a sectional view showing a conventional high-frequency module.
[Explanation of symbols]
Reference Signs List 1 multilayer substrate 2 cavity 3a, 3b, 3c, 3d, 3e insulating substrate 4a, 4b, 4c, 4d second wiring layer 5 third wiring layer 6 first wiring layer 7, 9 via 8 thermal via 21, 21a, 121 Semiconductor element 22, 122 Chip resistor 23, 123 Chip capacitor 24 Inductor 25, 125 Alloy material 26, 126 Electrode 27, 127 Bonding wire 128 External terminal 31 Adhesive 32 Insulating cap 33 Bump 34 Heat sink 101 Metal substrate 102 Insulating layer 105 Wiring layer 130 Mold resin 40, 40a, 140 High frequency module

Claims (3)

主面に配線層を有する絶縁性基板が積層されてなり、この積層構造の絶縁性基板の第1主面上に第1の配線層が設けられ、前記積層構造の絶縁性基板間に第2の配線層が設けられ、前記第1主面と相対向する第2主面上に第3の配線層が設けられ、第1乃至第3の配線層間がビアを介して電気的に接続され、且つ前記絶縁性基板にフェライトが含有されている多層基板と、
この多層基板の第1主面上に設けられ、前記第1の配線層と電気的に接続された半導体素子および受動素子と、
この半導体素子および受動素子を覆って、前記多層基板の第1主面に封着され、且つフェライトを含む絶縁性キャップと、
を具備することを特徴とする半導体装置。
An insulating substrate having a wiring layer on the main surface is laminated, a first wiring layer is provided on a first main surface of the insulating substrate having the laminated structure, and a second wiring layer is provided between the insulating substrates having the laminated structure. Is provided, a third wiring layer is provided on a second main surface opposite to the first main surface, and the first to third wiring layers are electrically connected via vias. And a multilayer substrate containing ferrite in the insulating substrate,
A semiconductor element and a passive element provided on a first main surface of the multilayer substrate and electrically connected to the first wiring layer;
An insulating cap that covers the semiconductor element and the passive element, is sealed to the first main surface of the multilayer substrate, and includes ferrite;
A semiconductor device comprising:
主面に配線層を有する絶縁性基板が積層されてなり、この積層構造の絶縁性基板の第1主面上に第1の配線層が設けられ、前記積層構造の絶縁性基板間に第2の配線層が設けられ、前記第1主面と相対向する第2主面上に第3の配線層が設けられ、第1乃至第3の配線層間がビアを介して電気的に接続され、且つ前記絶縁性基板にフェライトが含有されている多層基板と、
前記多層基板上にその主面をフェースダウンして設けられ、前記第1の配線層と電気的に接続された第1半導体素子と、
前記多層基板の第1主面上に設けられ、前記第1の配線層と電気的に接続された第2の半導体素子および受動素子と、
第1の半導体素子、第2の半導体素子および受動素子を覆って、前記多層基板の第1主面に封着され、且つフェライトを含む絶縁性キャップと、
を具備し、
前記絶縁性キャップは、内側面が前記第1の半導体素子の主面と反対面に接触し、外側面に放熱板を有し、この放熱板がビアを介して前記第1の半導体素子の反対面と接触していることを特徴とする半導体装置。
An insulating substrate having a wiring layer on the main surface is laminated, a first wiring layer is provided on a first main surface of the insulating substrate having the laminated structure, and a second wiring layer is provided between the insulating substrates having the laminated structure. Is provided, a third wiring layer is provided on a second main surface opposite to the first main surface, and the first to third wiring layers are electrically connected via vias. And a multilayer substrate containing ferrite in the insulating substrate,
A first semiconductor element provided on the multilayer substrate with its main surface face-down, and electrically connected to the first wiring layer;
A second semiconductor element and a passive element provided on a first main surface of the multilayer substrate and electrically connected to the first wiring layer;
An insulating cap that covers the first semiconductor element, the second semiconductor element, and the passive element, is sealed to the first main surface of the multilayer substrate, and includes ferrite;
With
The insulating cap has an inner surface in contact with a surface opposite to the main surface of the first semiconductor element, and has a heatsink on an outer surface, and the heatsink is opposite to the first semiconductor element via a via. A semiconductor device which is in contact with a surface.
前記絶縁性基板と前記絶縁性キャップを構成する材料は同一であることを特徴とする請求項1または2記載の半導体装置。3. The semiconductor device according to claim 1, wherein a material forming the insulating substrate and the material forming the insulating cap are the same.
JP2002334564A 2002-11-19 2002-11-19 Semiconductor device Pending JP2004172247A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006275601A (en) * 2005-03-28 2006-10-12 Kyocera Corp Magnetic sensor package and magnetic sensor device
JP2007324303A (en) * 2006-05-31 2007-12-13 Hitachi Cable Ltd Optical module and mounting method thereof
JP2013207132A (en) * 2012-03-29 2013-10-07 Toshiba Corp Semiconductor package and manufacturing method of the same
CN113161318A (en) * 2015-08-21 2021-07-23 意法半导体(R&D)有限公司 Sensor package

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006275601A (en) * 2005-03-28 2006-10-12 Kyocera Corp Magnetic sensor package and magnetic sensor device
JP2007324303A (en) * 2006-05-31 2007-12-13 Hitachi Cable Ltd Optical module and mounting method thereof
JP2013207132A (en) * 2012-03-29 2013-10-07 Toshiba Corp Semiconductor package and manufacturing method of the same
CN113161318A (en) * 2015-08-21 2021-07-23 意法半导体(R&D)有限公司 Sensor package

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