JP2004159217A - TDD switching signal generation method and generation circuit - Google Patents

Abstract

Provided is a TDD switching signal generation circuit that can output a TDD switching signal having a precise time width even if the characteristics of components are poor and the characteristics change under installation conditions.
A TDD switching signal sent from an IDU (first unit) is demodulated by an ASK detection circuit of an ODU (second unit). The logic circuits of the shift registers 32 and 33, the NOT circuit 34, and the NAND circuit 35 detect the completion of the rise of the demodulation TDD switching signal. The counter 36 counts the clock of the reference oscillator 38 from the time when the completion of the rise is detected. The count value comparator 37 sets the point in time when the completion of the rise is detected as a switching point to one operation mode, and sets the point in time when the count of the counter reaches a predetermined count number as a switching point to the other operation mode. .
[Selection] Fig. 2

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a TDD switching signal generation method and a generation circuit used in a TDD (Time Division Duplex) transmission / reception apparatus, and more particularly to a transmission / reception apparatus in which a transmission / reception apparatus is separated from a first unit and a first unit. And a second unit connected to the first unit. The first unit sets the operation mode to the transmission mode or the reception mode in order to perform transmission / reception of a TDD system with a communication partner via the second unit. When appropriately switching to the mode, the first unit sends the modulated TDD switching signal to the second unit, and the second unit demodulates the received modulated TDD switching signal, and demodulates the demodulated TDD switching signal. The present invention relates to a TDD switching signal generation method and a generation circuit for switching an operation mode by using a method.
[0002]
[Prior art]
FIG. 6 is a block diagram illustrating a conventional example of a transmission / reception apparatus that performs wireless communication using a TDD (Time Division Duplex) scheme as a duplex scheme. The transmitting / receiving apparatus shown in FIG. 6 includes an indoor unit (IDU = In Door Unit) 110, an outdoor unit (ODU = Out Door Unit) 120, and a cable 130 connecting these. The IDU 110 includes a transmission unit 111, a reception unit 112, and a TDD switch 113, and the ODU 120 includes TDD switches 121 and 124, a transmission unit 122, and a reception unit 123. In this case, it is necessary to transmit a TDD switching signal from the IDU 110 to the TDD switches 121 and 124 of the ODU 120 when switching between transmission and reception.
[0003]
When switching is performed using the above-described TDD switching signal, at the time of transmission, the TDD is transmitted such that the transmission signal transmitted from the IDU 110 via the cable 130 passes through the TDD switches 121 and 124 and the transmission unit 122 and is transmitted from the antenna 125. The switches 121 and 124 are switched, and at the time of reception, the TDD switches 121 and 124 are switched so that the reception signal from the antenna 125 passes through the TDD switches 121 and 124 and the receiving unit 123 and is transmitted to the IDU 110 via the cable 130. Therefore, a transmission / reception signal, a TDD switching signal, a control signal from the IDU 110 to the ODU 120, a control signal from the ODU 120 to the IDU 110, a DC current for the ODU power supply, and the like are superimposed and flow through the cable 130. Among these, the TDD switching signal and the control signal are rectangular waves having wideband frequency components, and if they are transmitted as they are, they become a noise source for transmission / reception signals, so that it is necessary to limit the band. As a method of band limitation, ASK modulation, which can be configured with a simple circuit, is often used.
[0004]
As described above, the circuit configuration of the TDD switching signal generation circuit when ASK modulation is used will be described with reference to FIG. The ASK modulation signal generation circuit 115 of the IDU 110 includes an AND circuit 115a, a capacitor 115b, and a band pass filter (BPF) 115c. The AND circuit 115a calculates the logical product of the TDD switching signal and the carrier signal of a predetermined frequency, the capacitor 115b removes the DC component from the output of the AND circuit 115a, and the BPF 115c determines the carrier frequency from the signal from the capacitor 115b. The components other than the components are removed and transmitted to the ODU 120 via the cable 130.
[0005]
The ASK detection circuit 126 of the ODU 120 that receives a signal from the ASK modulation signal generation circuit 115 of the IDU 110 includes a BPF 126a, a Log AMP 126b, and a comparator 126c. The BPF 126a filters the received signal to remove components other than the carrier frequency component, the Log AMP 126b performs envelope detection of the output of the BPF 126a, and the comparator 126c outputs a low level signal when the output level of the Log AMP 126b is lower than the threshold value. When the output level of the Log AMP 126b is higher than the threshold, the output is high. As a result, a pulse-like TDD switching signal as shown in FIG. 8 is output from the comparator 126c.
[0006]
[Problems to be solved by the invention]
As can be seen from FIG. 8, since the output waveform of the LogAMP 126b obtained by amplifying the TDD switching signal from the IDU 110 is not steep at the rising and falling, the rising and falling of the output by comparison with the threshold in the comparator 126c are as follows. Deviations DA and DB occur with respect to the original waveform. As a result, the time width of the TDD switching signal output from the comparator 126c is not the same as the time width of the original TDD switching signal. If this difference is within one symbol, no problem occurs, but depending on the value of the threshold value, the difference may be several symbols, which may cause a problem. Therefore, it is necessary to adjust the threshold value given to the comparator 126c after the Log AMP 126b so that the time width of the TDD switching signal transmitted from the IDU 110 is equal to the time width of the TDD switching signal demodulated by the comparator 126c. However, even if the threshold is adjusted, if the length of the cable 130 between them changes due to a change in the installation location of the IDU 110 or the ODU 120, the output of the Log AMP 126b changes, and the threshold must be adjusted again. Such a problem occurs.
[0007]
The present invention has been made in order to solve the above-described problem. Even when the rising and falling of the output waveform to the Log AMP 126b is not steep, even if the output of the Log AMP 126b changes depending on the installation condition, An object of the present invention is to provide a transmission / reception device that can output a TDD switching signal having an appropriate time width.
[0008]
[Means for Solving the Problems]
In order to solve the above-described problem, the present invention includes a first unit and a second unit connected to the first unit, and the first unit is connected via the second unit. In switching the operation mode to the transmission mode or the reception mode in order to perform transmission / reception of the TDD system with a communication partner, the first unit sends a modulated TDD switching signal to the second unit, and the second unit In a TDD switching signal generation circuit for demodulating a transmitted modulated TDD switching signal and switching an operation mode using the demodulated TDD switching signal, a second unit detects a completion of rising of the demodulated TDD switching signal. And a counter that counts the clock of the reference oscillator from the time when the completion of the rise is detected, and the detection circuit detects the completion of the rise. With the switching point to the one operating mode of the point, and a count value comparator for a time when the counter counts reaches a count previously given the switching point to the next operating mode.
[0009]
In the TDD switching signal generation circuit according to the present invention, the detection circuit of the second unit includes a first shift register that latches a rising edge of the demodulation TDD switching signal in synchronization with a clock, A second shift register that latches an output in synchronization with a clock; and a logic circuit that detects completion of rising of the clock based on an output of the second shift register and an output of the first shift register.
[0010]
In addition, the present invention comprises a first unit and a second unit, and the first unit operates in an operation mode for transmitting and receiving a TDD system to and from a communication partner via the second unit. When switching to the transmission mode or the reception mode, the first unit sends the modulated TDD switching signal to the second unit, and the second unit demodulates the transmitted modulated TDD switching signal, and demodulates the demodulated TDD switching signal. In the TDD switching signal generation method for switching an operation mode using a switching signal, the second unit detects completion of the rise of the demodulated TDD switching signal, and determines a point in time when the completion of the rise is detected as a switching point to one operation mode. At the same time, the clock of the reference oscillator is counted, and when the count reaches the preset count number, the other It is an switching point to the work mode.
[0011]
According to such a configuration, the time width of the TDD switching signal is from the switching point to one operation mode to the switching point to the other operation mode, and the width is determined by the count number of the clock. Since the clock is supplied from a reference oscillator or the like and has extremely high accuracy and is stable, the time width of the TDD switching signal is not affected even if a fluctuation or the like occurs in a used circuit element. Also, when the time width of the TDD switching signal is changed, it can be executed only by changing the predetermined count number, and the flexibility is high.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram showing a transmission / reception device using the TDD switching signal generation circuit of the present invention. FIG. 2 is a block diagram showing an embodiment of the TDD switching signal generation circuit of the present invention arranged in the transmission / reception device of FIG. FIG. 3 and FIG. 3 are time charts for explaining the operation of the TDD switching signal generation circuit of FIG. 2, and FIG. 4 is a diagram for explaining a possible variation of the time width of the TDD switching signal in the TDD switching signal generation circuit of FIG. FIG. 5 is a block diagram showing a modification of the TDD switching signal generation circuit of FIG.
[0013]
The transmitting and receiving apparatus shown in FIG. 1 includes an indoor unit (IDU = In Door Unit) 10, an outdoor unit (ODU = Out Door Unit) 20, and a cable 30 for connecting these units. TDD (Time) is used as a duplex system. (Division Duplex) method. The IDU 10 includes a transmission unit 11, a reception unit 12, and a TDD switch 13. The ODU 20 includes TDD switches 21, 24, a transmission unit 22, a reception unit 23, and an antenna 25. In this case, it is necessary to transmit a TDD switching signal from the IDU 10 to the TDD switches 21 and 24 of the ODU 20 at the time of switching between transmission and reception, and a TDD switching signal generation circuit for transmitting the TDD switching signal is shown in FIG. 1 is the circuit shown in FIG.
[0014]
When switching is performed by the above-described TDD switching signal, at the time of transmission, the TDD is transmitted such that the transmission signal transmitted from the IDU 10 via the cable 30 passes through the TDD switches 21 and 24 and the transmission unit 22 and is transmitted from the antenna 25. The switches 21 and 24 are switched, and at the time of reception, the TDD switches 21 and 24 are switched so that the reception signal from the antenna 25 passes through the TDD switches 21 and 24 and the receiving unit 23 and is transmitted to the IDU 10 via the cable 30. Therefore, a transmission / reception signal, a TDD switching signal, a control signal from the IDU 10 to the ODU 20, a control signal from the ODU 20 to the IDU 10, a DC current for the ODU power supply, and the like are superimposed and flow through the cable 30. Among these, the TDD switching signal and the control signal are rectangular waves having wideband frequency components, and if they are transmitted as they are, they become a noise source for transmission / reception signals, so that it is necessary to limit the band. As a method of band limitation, ASK modulation, which can be configured with a simple circuit, is often used.
[0015]
An example of a circuit configuration of the TDD switching signal generation circuit in the case of using ASK modulation among the above-described TDD switching signal generation circuits will be described with reference to FIG. The ASK modulation signal generation circuit 15 arranged in the IDU 10 includes an AND circuit 15a, a capacitor 15b, and a band pass filter (BPF) 15c. The AND circuit 15a calculates the logical product of the TDD switching signal and the carrier signal of a predetermined frequency, the capacitor 15b removes the DC component from the output of the AND circuit 15a, and the BPF 15c calculates the carrier frequency from the signal from the capacitor 15b. Components other than the components are removed and transmitted to the ODU 20 via the cable 30. Therefore, IDU 10 has substantially the same configuration as conventional IDU 110.
[0016]
The TDD switching signal generation circuit arranged in the ODU 20 includes an ASK detection circuit 31, shift registers 32 and 33, a NOT circuit 34, a NAND circuit 35, a counter 36, a count value comparator 37, and a reference oscillator 38. Having. The ASK detection circuit 31 includes a BPF 31a, a Log AMP 31b, and a comparator 31c. The BPF 31a filters the received signal to remove components other than the carrier frequency component, the Log AMP 31b performs envelope detection of the output of the BPF 31a, and the comparator 31c outputs a low level signal when the output level of the Log AMP 31b is lower than the threshold value. When the output level of the Log AMP 31b is higher than the threshold, the output is high. As a result, a pulsed TDD switching signal SA demodulated in the same manner as in the conventional example is output from the comparator 31c.
[0017]
The shift register 32 latches the TDD switching signal SA demodulated by the ASK detection circuit 31 in synchronization with the clock CLK from the reference oscillator 38, and outputs the same as the TDD switching signal SB. The shift register 33 latches the TDD switching signal SB in synchronization with the next clock CLK and outputs the same as the TDD switching signal SC. The NOT circuit inverts the logic of the TDD switching signal SC and outputs it as an inverted TDD switching signal SD. The NAND circuit 35 NANDs the TDD switching signal SB and the inverted TDD switching signal SD, and outputs a count start signal SE. When the counter 36 receives the count start signal SF, it clears the count value and then counts the clock CLK. The count value comparison unit 37 clears the count value (counts “0”) by the counter 36, sets the output to a high level, and compares the count value at which the counter 36 counts the clock CLK with the count determination value. When the two match, the output is switched to the low level again to output the final TDD switching signal SZ.
[0018]
In the above-described example, the time width during which the TDD switching signal SZ output from the count value comparator 37 is at a high level is appropriately set by appropriately selecting the count determination value because the frequency of the clock CLK is known. it can. For example, consider the count determination value when the number of symbols in a transmission frame is 500 symbols, the symbol rate is 7 M symbols / second, and the frequency of the reference oscillator 38 of the ODU 20 is 10 MHz. The time of the transmission section is 500 symbols ÷ 7 M symbols / second, which results in 71.43 μs. If this time is counted with a 10 MHz clock, 714.3 counts are required. Therefore, when rounded, 715 counts are obtained. However, in the count value comparator 37 in this example, since the output is at a high level from the time when the count value of the counter 36 is “0”, it is necessary to set the count determination value to a value obtained by subtracting 1 from 715. Of course, the output may be set to the high level after the count value of the counter 36 becomes “1”, and the count determination value may be set to 715.
[0019]
As is clear from the setting example of the count determination value, the time width of the desired TDD switching signal SZ may not be divisible by the time width of the clock CLK of the reference oscillator 38. In order that the latch by the clock CLKB causes the delay DL, the time width is shorter or longer by one clock at maximum than the desired time width. Therefore, even in such a case, it is preferable that the clock CLK supplied to the counter 36 be as fast as possible in order to keep the time width of the TDD switching signal SZ close to the desired time width. As described above, even if the rising and falling of the output waveform of the Log AMP 31b or the like of the ASK detection circuit 31 is not steep or the output of the Log AMP 31b changes depending on installation conditions, the time width of the TDD switching signal SZ may vary. Is determined by the accuracy of the time width of one clock CLK, and can output the TDD switching signal SZ having a time width of higher precision than that of the conventional one, so that accurate switching of the TDD switches 13, 21, and 24 can be performed. It becomes possible.
[0020]
A second operation example of the above-described TDD switching signal generation circuit will be described with reference to FIG. In this example, it is assumed that the symbol rate is 6 M symbols / second, the frequency of the reference oscillator is 20 MHz, the frame symbol length is 1300 symbols, and the TDD ratio is 1: 1, that is, the time between transmission and reception is equal. The time of the transmission (reception) section of the TDD switching signal is 650 symbols because the TDD ratio is 1: 1, and the time is 650 ÷ 6M symbols = 108.33 μsec. The TDD switching signal having this section of 108.33 μs is ASK-modulated and transmitted to the ODU 20. In the ODU 20 that receives the ASK-modulated TDD switching signal, the ASK detection circuit performs collapse detection and demodulates the TDD switching signal.
[0021]
As in the previous example, a count start signal SE is generated from the demodulated TDD switching signal, the counter is cleared by the generated count start signal SE, and then the clock CLK is counted. In this case, in order to count 108.33 μs of the transmission (reception) time with the clock CLK of 20 MHz, the count determination value needs to be set to 2166. In such a case, the output is kept at a low level until the count value comparator starts counting the clock CLK, and when the count is started, the output is kept at a high level until the count reaches the count determination value 2166, Becomes the count determination value 2166, the output is set to the low level until the next count value is cleared. The TDD switch switches between transmission and reception in accordance with the TDD switching signal by switching to the high level or the low level.
[0022]
Instead of the TDD switching signal generation circuit in the ODU 20 shown in FIG. 2, a circuit configuration as shown in FIG. 5 can be used. In this case, the connection method of the logic circuit is changed, and an OR circuit 39 is employed instead of the NAND circuit 35. Further, in the above example, the case where the TDD ratio is 1: 1 has been described. However, when the TDD ratio is 1: 2 or 1: 3, the count determination value satisfying the transmission time is counted as the count value. This can be handled by setting in a comparator. As described above, the TDD switching signal generation circuit according to the present invention generates the TDD switching signal by counting the clock CLK from the reference oscillator 38 arranged in the ODU 20 by a preset count number, so that the comparator 31c It is possible to supply a stable TDD switching signal which is not affected by a change in electrical characteristics due to a change in the positional relationship between the IDU 10 and the ODU 20 or the like.
[0023]
【The invention's effect】
Since the TDD switching signal generation method and the generation circuit according to the present invention are configured as described above, the time width of the TDD switching signal is changed from the switching point to one operation mode to the switching point to the other operation mode. And its width is determined by the count number of the clock. Since the clock is supplied from a reference oscillator or the like and has extremely high accuracy and is stable, the time width of the TDD switching signal is not affected even if a fluctuation or the like occurs in a used circuit element. Also, when the time width of the TDD switching signal is changed, it can be executed only by changing the predetermined count number, and the flexibility is high.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a transmission / reception device using a TDD switching signal generation circuit according to the present invention.
FIG. 2 is a block diagram showing an embodiment of a TDD switching signal generation circuit of the present invention arranged in the transmission / reception apparatus of FIG. 1;
FIG. 3 is a time chart for explaining an operation of the TDD switching signal generation circuit of FIG. 2;
FIG. 4 is a time chart for explaining a change in a time width of a TDD switching signal which may occur in the TDD switching signal generation circuit of FIG. 2;
FIG. 5 is a block diagram showing a modification of the TDD switching signal generation circuit of FIG. 2;
FIG. 6 is a block diagram showing a conventional example of a TDD transmission / reception apparatus.
FIG. 7 is a block diagram illustrating a TDD switching signal generation circuit arranged in the transmission / reception device of FIG. 6;
FIG. 8 is a time chart for explaining an operation of the TDD switching signal generation circuit of FIG. 7;
[Explanation of symbols]
10 IDU (indoor unit), 11, 22 transmitter, 12, 23 receiver, 13, 21, 24 TDD switch, 15 ASK modulation signal generation circuit, 15a AND circuit, 15b capacitor, 15c, 31a BPF, 20 ODU (outdoor) Device), 25 antennas, 30 cables, 31 ASK detection circuit, 31b Log AMP, 31c comparator, 32, 33 shift register, 34 NOT circuit, 35 NAND circuit, 36 counter, 37 count value comparator, 38 reference oscillator, 39 OR circuit.

Claims (3)

It comprises a first unit and a second unit connected to the first unit. The first unit transmits and receives a TDD system to and from a communication partner via the second unit. When switching the operation mode to the transmission mode or the reception mode, the first unit sends the modulated TDD switching signal to the second unit, and the second unit demodulates the transmitted modulated TDD switching signal and demodulates the modulated TDD switching signal. In the TDD switching signal generation circuit for switching the operation mode using the TDD switching signal thus obtained,
The second unit is
A detection circuit for detecting the completion of rising of the demodulation TDD switching signal;
A counter that counts the clock of the reference oscillator from the time when the completion of the rise is detected,
A time point when the detection circuit detects the completion of the rising is set as a switching point to one operation mode, and a time point when the count of the counter reaches a predetermined count number is set as a switching point to the next operation mode. A TDD switching signal generation circuit, comprising: a value comparator. The TDD switching signal generation circuit according to claim 1,
The detection circuit of the second unit includes a first shift register that latches a rising edge of the demodulation TDD switching signal in synchronization with a clock, and a second shift register that latches an output of the first shift register in synchronization with a clock. A TDD switching signal generation circuit, comprising: a shift register; a logic circuit for detecting completion of rising of a clock based on an output of the second shift register and an output of the first shift register. The first unit includes a first unit and a second unit, and the first unit sets an operation mode to a transmission mode or a reception mode in order to perform transmission and reception of a TDD system with a communication partner via the second unit. In switching to the first unit, the first unit sends the modulated TDD switching signal to the second unit, and the second unit demodulates the transmitted modulated TDD switching signal, and operates using the demodulated TDD switching signal. In a TDD switching signal generation method for switching modes,
The second unit detects the completion of the rising edge of the demodulation TDD switching signal, sets the time point at which the completion of the rising edge is detected as a switching point to one operation mode, and counts the clock of the reference oscillator from that time point. A method for generating a TDD switching signal, in which the point at which a preset count number is reached is set as a switching point to the other operation mode.

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