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JP2004158678A - Bonding pad - Google Patents

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Publication number
JP2004158678A
JP2004158678A JP2002323786A JP2002323786A JP2004158678A JP 2004158678 A JP2004158678 A JP 2004158678A JP 2002323786 A JP2002323786 A JP 2002323786A JP 2002323786 A JP2002323786 A JP 2002323786A JP 2004158678 A JP2004158678 A JP 2004158678A
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Japan
Prior art keywords
metal layer
layer
uppermost
piece
bonding pad
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Pending
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JP2002323786A
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Japanese (ja)
Inventor
Shinya Mori
真也 森
Junji Yamada
順治 山田
Yutaka Yamada
裕 山田
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Priority to JP2002323786A priority Critical patent/JP2004158678A/en
Publication of JP2004158678A publication Critical patent/JP2004158678A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To improve the adhesive property of a bonding wire to a multilayered metallic bonding pad. <P>SOLUTION: The bonding pad is formed by alternately laminating insulating layers 6 and 8 and metallic layers upon another on a semiconductor substrate 1 and forming the uppermost insulating layer 10 having an opening 11 through which the uppermost metallic layer 9 is exposed on the metallic layer 9. Each metallic layer excluding the uppermost one 9 is composed of a plurality of metallic layer pieces 5 and 7 disposed separately from each other. On the surface of the uppermost metallic layer 9, recessed and projecting sections are formed by reflecting the steps produced by the pieces 5 and 7. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、ボンディングパッドに関し、特に多層メタルから成るボンディングパッドに関する。
【０００２】
【従来の技術】
近年、半導体集積回路の高集積化のために多層メタル配線が広く用いられている。図４は、２層メタル配線の半導体集積回路のボンディングパッド構造を示す断面図である。半導体基板１００の表面には、内部回路（不図示）に接続された第１のＡｌ層１０１が形成されている。また、第１のＡｌ層１０１上にはシリコン窒化膜やＳｉＯ２膜等の絶縁膜１０２が形成され、この絶縁層１０２にビア１０３が形成され、この開口部１０３を介して上層の第２のＡｌ層１０４と下層の第１のＡｌ層１０１とが電気的に接続されている。そして、ビア１０３で露出された第２のＡｌ層１０４の表面に、ボンディングマシンにより、Ａｕ等から成るボンディングワイヤー（不図示）が圧着される。
【０００３】
図４では、絶縁層１０２に１つのビア１０３が形成されているが、以下の特許文献１には、絶縁層に複数のビアを形成して、これらの複数のビアを介して上層と下層の金属層を電気的に接続する技術が記載されている。
【０００４】
【特許文献１】
特開昭６１−５９８５５号公報
【０００５】
【発明が解決しようとする課題】
しかしながら、図４に示した構造では、第２のＡｌ層１０４の表面がほぼ平坦（ビア１０３のエッジ部を除く）であるために、ボンディングワイヤーとの密着性が悪く、接触不良が生じる場合があった。また、絶縁層に形成される大きなビアを１つ形成した構造では、ビア１０３のエッジ部で第２のＡｌ層１０４の段差が大きくなり、第２のＡｌ層１０４のパターニングが難しくなる。これは段差があるために、レジスト露光時に焦点深度の差が生じるためである。図４には２層メタルのボンディングパッド構造を示したが３層メタル以上のボンディングパッド構造では更に上層のメタルの段差が大きくなり、メタルのパターニングが益々難しくなる。
【０００６】
【課題を解決するための手段】
本発明は、基板上に絶縁層と金属層とが交互に積層され、最上層の金属層上に、該最上層の金属層を露出する開口部を有した最上層の絶縁層を有し、前記最上層の金属層を除く各層の金属層は、互いに離間して配置された複数の金属層片から成り、該金属層片による段差を反映して、前記最上層の金属層の表面が凹凸を有することを特徴とする。
【０００７】
これにより、最上層の金属層の表面には凹凸が形成されるので、この最上層の金属層にボンディングを行えば、ボンディングワイヤーの密着性が向上する。また、最上層の金属層に大きな段差が生じることが防止されるので、この最上層の金属層のパターニングも容易になる。
【０００８】
【発明の実施の形態】
次に、本発明の実施形態について図面を参照しながら詳細に説明する。図１は実施形態に係るボンディングパッドを説明する図であり、図１は、このボンディングパッドの平面図であり、図２は図１のＸ−Ｘ線に沿った断面図である。また、図３は図１のＹ−Ｙ線に沿った断面図である。
【０００９】
このボンディングパッドは、図１に示すように、ボンディングワイヤーが圧着される部分であるボンディング部Ａと、このボンディング部Ａと配線部Ｃとを接続するための接続部Ｂから成る。配線部Ｃは半導体チップの入出力回路等（不図示）に接続されている。
【００１０】
まず、上記のボンディング部Ａについて図１，図２を参照して説明する。
【００１１】
例えばＳｉ基板等の半導体基板１上に、互いに離間された複数のＬＯＣＯＳ膜２が形成されている。このＬＯＣＯＳ膜２は、いわゆる素子分離のためのフィールド酸化膜として形成されるものであるが、この部分ではＬＯＣＯＳ膜段差を作り出すために形成されている。
【００１２】
そして、ＬＯＣＯＳ膜２上には、互いに離間された複数のポリシリコン膜片３が形成されている。ポリシリコン膜は、ＭＯＳトランジスタのゲートとして形成されるが、この部分ではポリシリコン膜段差を作り出すために形成されている。これらのポリシリコン膜片３上には、第１の絶縁層４を介して、互いに離間された第１の金属層片５が形成されている。
【００１３】
また、これらの第１の金属層片５上には、第２の絶縁層６を介して、互いに離間された第２の金属層片７が形成されている。
【００１４】
更に、これらの第２の金属層片７上には、第３の絶縁層８を介して、最上層の第３の金属層９が形成されている。ここで、第１の絶縁層４，第２の絶縁層６及び第３の絶縁層８はＳｉＯ２等から成り、膜厚は例えば８００ｎｍ程度である。また、第１の金属層片５、第２の金属層片７及び、第３の金属層９は例えばＡｌ、Ａｌ−Ｓｉ、Ａｌ−Ｃｕ、Ａｌ−Ｓｉ−Ｃｕ等から成り、その膜厚は１μｍ程度である。
【００１５】
そして、第３の金属層９上には、１つの開口部１１を有する第４の絶縁層１０が設けられ、この開口部１１において、第３の金属層片９が露出されている。上記ボンディング部の構造によれば、下層に配置されたＬＯＣＯＳ膜２、ポリシリコン膜片３、第１の金属層片５、第２の金属層片７による段差が、最上層の第３の金属層片９の表面に反映されるため、最上層の第３の金属層９の表面には凹凸が形成される。
【００１６】
また、図１に示すように、平面的に見ると、ＬＯＣＯＳ膜２、ポリシリコン膜片３、第１の金属層片５、第２の金属層片７は互いに重なったパターンとして行列状に多数配置されており、第３の金属層の表面の全体に渡り、多くの凹凸が形成されるように構成されている。なお、このパターン配置の形態は、行列配置のような規則的な配置には限られず、ランダムな配置であってもよい。
【００１７】
次に、接続部Ｂ、配線部Ｃついて図１，図３を参照して説明する。半導体基板１上に第１の絶縁層４、第１の金属層２０が積層されている。第１の金属層２０は前記第１の金属層片５と同層である。第１の金属層２０は、接続部Ｂから引き出され、第１の絶縁層４上を延在して不図示の入出力回路等に接続されている。
【００１８】
この第１の金属層２０上には複数の第１のビア１２を有する第２の絶縁層６が形成され、この複数の第１のビア１２に高融点金属、例えばタングステン（Ｗ）１３が埋め込まれている。そして、第２の絶縁層６上には第２の金属層２１が形成されている。第２の金属層２１は前記第２の金属層片７と同層である。
【００１９】
更に、この第２の金属層２１上には複数の第２のビア１４を有する第３の絶縁層８が形成され、複数の第２のビア１４に高融点金属、例えばタングステン（Ｗ）１５が埋め込まれている。そして、第３の絶縁層８上には第３の金属層９が形成されている。この第３の金属層９の上には、前記第４の絶縁層１０が形成されている。そして、この第３の金属層９は、上述したボンディング部Ａに延在している。
【００２０】
このように、本実施形態によれば、ＬＯＣＯＳ膜２、ポリシリコン膜片３、第１の金属層片５、第２の金属層片７による段差が、最上層の第３の金属層片９の表面に反映されるため、最上層の第３の金属層９の表面には凹凸が形成される。これにより、ボンディングワイヤーが密着される最上層の第３の金属層の表面積が増加するので、ワイヤボンディング時に、ボンディングワイヤーと最上層の第３の金属層９との密着性が向上し、両者の接触不良が防止される。
【００２１】
なお、本実施形態では、第１の金属層片５、第２の金属層片７の下層にＬＯＣＯＳ膜２、ポリシリコン膜片３を配置することで、段差を増大させ、最上層の第３の金属層９の表面には、大きな凹凸を形成しているが、他の実施形態として、ＬＯＣＯＳ膜２、ポリシリコン膜片３を設けないものがある。この場合は、第１の金属層片５、第２の金属層片７の段差により、最上層の第３の金属層９に凹凸を生じさせる。さらに他の実施形態として、ＬＯＣＯＳ膜２を設け、ポリシリコン膜片３を設けないものがある。この場合は、ＬＯＣＯＳ膜２、第１の金属層片５、第２の金属層片７の段差により、最上層の第３の金属層９に凹凸を生じさせる。
【００２２】
【発明の効果】
本発明によれば、最上層の金属層の表面には凹凸が形成されるので、この最上層の金属層にボンディングを行えば、ボンディングワイヤーの密着性が向上し、接触不良を防止することができる。また、最上層の金属層に大きな段差が生じることが防止されるので、この最上層の金属層のパターニングも容易になる。
【図面の簡単な説明】
【図１】本発明の実施形態に係るボンディングパッドを説明する平面図である。
【図２】図１のＸ−Ｘ線に沿った断面図である。
【図３】図１のＹ−Ｙ線に沿った断面図である。
【図４】従来例のボンディングパッドを説明する断面図である。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a bonding pad, and more particularly to a bonding pad made of a multilayer metal.
[0002]
[Prior art]
2. Description of the Related Art In recent years, multilayer metal wiring has been widely used for high integration of semiconductor integrated circuits. FIG. 4 is a sectional view showing a bonding pad structure of a semiconductor integrated circuit having two-layer metal wiring. On the surface of the semiconductor substrate 100, a first Al layer 101 connected to an internal circuit (not shown) is formed. An insulating film 102 such as a silicon nitride film or a SiO 2 film is formed on the first Al layer 101, a via 103 is formed in the insulating layer 102, and an upper second Al layer is formed through the opening 103. The layer 104 and the lower first Al layer 101 are electrically connected. Then, a bonding wire (not shown) made of Au or the like is pressure-bonded to the surface of the second Al layer 104 exposed by the via 103 by a bonding machine.
[0003]
In FIG. 4, one via 103 is formed in the insulating layer 102. However, in the following Patent Document 1, a plurality of vias are formed in the insulating layer, and upper and lower layers are formed through the plurality of vias. A technique for electrically connecting metal layers is described.
[0004]
[Patent Document 1]
JP-A-61-59855 [0005]
[Problems to be solved by the invention]
However, in the structure shown in FIG. 4, since the surface of the second Al layer 104 is almost flat (excluding the edge of the via 103), the adhesion to the bonding wire is poor, and a contact failure may occur. there were. Further, in the structure in which one large via formed in the insulating layer is formed, the step of the second Al layer 104 is large at the edge of the via 103, and it is difficult to pattern the second Al layer 104. This is because there is a step, which causes a difference in the depth of focus during resist exposure. FIG. 4 shows a bonding pad structure of a two-layer metal. However, in a bonding pad structure of a three-layer metal or more, the step of the metal in the upper layer is further increased, and the patterning of the metal becomes more and more difficult.
[0006]
[Means for Solving the Problems]
The present invention includes an insulating layer and a metal layer alternately stacked on a substrate, and having an uppermost insulating layer having an opening exposing the uppermost metal layer on the uppermost metal layer, The metal layer of each layer except the uppermost metal layer is composed of a plurality of metal layer pieces arranged apart from each other, and the surface of the uppermost metal layer is uneven due to the step due to the metal layer pieces. It is characterized by having.
[0007]
As a result, irregularities are formed on the surface of the uppermost metal layer, so that bonding to the uppermost metal layer improves the adhesion of the bonding wires. Further, since a large step is prevented from being generated in the uppermost metal layer, patterning of the uppermost metal layer is also facilitated.
[0008]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram illustrating a bonding pad according to an embodiment. FIG. 1 is a plan view of the bonding pad, and FIG. 2 is a cross-sectional view taken along line XX of FIG. FIG. 3 is a sectional view taken along the line YY in FIG.
[0009]
As shown in FIG. 1, the bonding pad includes a bonding portion A to which a bonding wire is crimped, and a connection portion B for connecting the bonding portion A and the wiring portion C. The wiring section C is connected to an input / output circuit or the like (not shown) of the semiconductor chip.
[0010]
First, the bonding portion A will be described with reference to FIGS.
[0011]
For example, a plurality of LOCOS films 2 separated from each other are formed on a semiconductor substrate 1 such as a Si substrate. The LOCOS film 2 is formed as a field oxide film for so-called element isolation. In this portion, the LOCOS film 2 is formed to create a LOCOS film step.
[0012]
On the LOCOS film 2, a plurality of polysilicon film pieces 3 separated from each other are formed. The polysilicon film is formed as a gate of the MOS transistor. In this portion, the polysilicon film is formed to create a polysilicon film step. On these polysilicon film pieces 3, first metal layer pieces 5 separated from each other are formed via a first insulating layer 4.
[0013]
Further, on these first metal layer pieces 5, second metal layer pieces 7 separated from each other are formed via a second insulating layer 6.
[0014]
Further, on these second metal layer pieces 7, an uppermost third metal layer 9 is formed via a third insulating layer 8. Here, the first insulating layer 4, the second insulating layer 6, and the third insulating layer 8 are made of SiO 2 or the like, and have a thickness of, for example, about 800 nm. The first metal layer piece 5, the second metal layer piece 7, and the third metal layer 9 are made of, for example, Al, Al-Si, Al-Cu, Al-Si-Cu, and the like. It is about 1 μm.
[0015]
The fourth insulating layer 10 having one opening 11 is provided on the third metal layer 9, and the third metal layer piece 9 is exposed in the opening 11. According to the structure of the bonding portion, a step formed by the LOCOS film 2, the polysilicon film piece 3, the first metal layer piece 5, and the second metal layer piece 7 arranged in the lower layer causes the uppermost third metal layer Since the light is reflected on the surface of the layer piece 9, irregularities are formed on the surface of the third metal layer 9 as the uppermost layer.
[0016]
As shown in FIG. 1, when viewed in a plan view, the LOCOS film 2, the polysilicon film piece 3, the first metal layer piece 5, and the second metal layer piece 7 are arranged in a large number in a matrix as an overlapping pattern. The third metal layer is arranged so that many irregularities are formed over the entire surface of the third metal layer. The form of the pattern arrangement is not limited to a regular arrangement such as a matrix arrangement, but may be a random arrangement.
[0017]
Next, the connection portion B and the wiring portion C will be described with reference to FIGS. A first insulating layer 4 and a first metal layer 20 are stacked on a semiconductor substrate 1. The first metal layer 20 is the same layer as the first metal layer piece 5. The first metal layer 20 is drawn out from the connection portion B, extends on the first insulating layer 4, and is connected to an input / output circuit (not shown) or the like.
[0018]
A second insulating layer 6 having a plurality of first vias 12 is formed on the first metal layer 20, and a high melting point metal, for example, tungsten (W) 13 is embedded in the plurality of first vias 12. Have been. Then, a second metal layer 21 is formed on the second insulating layer 6. The second metal layer 21 is the same layer as the second metal layer piece 7.
[0019]
Further, a third insulating layer 8 having a plurality of second vias 14 is formed on the second metal layer 21, and a refractory metal, for example, tungsten (W) 15, is formed in the plurality of second vias 14. Embedded. Then, a third metal layer 9 is formed on the third insulating layer 8. On the third metal layer 9, the fourth insulating layer 10 is formed. The third metal layer 9 extends to the above-described bonding portion A.
[0020]
As described above, according to the present embodiment, the step caused by the LOCOS film 2, the polysilicon film piece 3, the first metal layer piece 5, and the second metal layer piece 7 is the uppermost third metal layer piece 9. Is formed on the surface of the third metal layer 9 as the uppermost layer. This increases the surface area of the uppermost third metal layer to which the bonding wire is adhered, so that the adhesion between the bonding wire and the uppermost third metal layer 9 is improved at the time of wire bonding. Poor contact is prevented.
[0021]
In this embodiment, the step is increased by disposing the LOCOS film 2 and the polysilicon film piece 3 under the first metal layer piece 5 and the second metal layer piece 7, so that the third layer of the uppermost layer is formed. Although large irregularities are formed on the surface of the metal layer 9, there is another embodiment in which the LOCOS film 2 and the polysilicon film piece 3 are not provided. In this case, the steps of the first metal layer piece 5 and the second metal layer piece 7 cause irregularities in the uppermost third metal layer 9. As still another embodiment, there is an embodiment in which the LOCOS film 2 is provided and the polysilicon film piece 3 is not provided. In this case, unevenness is generated in the uppermost third metal layer 9 due to a step between the LOCOS film 2, the first metal layer piece 5, and the second metal layer piece 7.
[0022]
【The invention's effect】
According to the present invention, since irregularities are formed on the surface of the uppermost metal layer, if bonding is performed on this uppermost metal layer, the adhesion of the bonding wire is improved, and poor contact can be prevented. it can. Further, since a large step is prevented from being generated in the uppermost metal layer, patterning of the uppermost metal layer is also facilitated.
[Brief description of the drawings]
FIG. 1 is a plan view illustrating a bonding pad according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view taken along line XX of FIG.
FIG. 3 is a sectional view taken along the line YY of FIG. 1;
FIG. 4 is a cross-sectional view illustrating a conventional bonding pad.

Claims (5)

基板上に絶縁層と金属層とが交互に積層され、最上層の金属層上に、該最上層の金属層を露出する開口部を有した最上層の絶縁層を有し、前記最上層の金属層を除く各層の金属層は、互いに離間して配置された複数の金属層片から成り、該金属層片による段差を反映して、前記最上層の金属層の表面が凹凸を有することを特徴とするボンディングパッド。An insulating layer and a metal layer are alternately stacked on a substrate, and an uppermost insulating layer having an opening exposing the uppermost metal layer is provided on the uppermost metal layer. The metal layer of each layer excluding the metal layer is composed of a plurality of metal layer pieces arranged apart from each other, and reflecting the step due to the metal layer pieces, the surface of the uppermost metal layer has irregularities. Characteristic bonding pad. 基板上に、複数のＬＯＣＯＳ膜が互いに離間して配置され、これらの複数のＬＯＣＯＳ膜上に、絶縁層と金属層とが交互に積層され、最上層の金属層上に、該最上層の金属層を露出する開口部を有した最上層の絶縁層を有し、前記最上層の金属層を除く各層の金属層は、互いに離間して配置された複数の金属層片から成り、前記ＬＯＣＯＳ膜及び前記金属層片による段差を反映して、前記最上層の金属層の表面が凹凸を有することを特徴とするボンディングパッド。On the substrate, a plurality of LOCOS films are arranged apart from each other, and an insulating layer and a metal layer are alternately stacked on the plurality of LOCOS films, and the uppermost metal layer is formed on the uppermost metal layer. An uppermost insulating layer having an opening for exposing the layer, the metal layer of each layer excluding the uppermost metal layer includes a plurality of metal layer pieces spaced apart from each other, and the LOCOS film And a bonding pad, wherein a surface of the uppermost metal layer has irregularities reflecting a step caused by the metal layer piece. 前記金属層片が前記ＬＯＣＯＳ膜上に配置されていることを特徴とする請求項２記載のボンディングパッド。The bonding pad according to claim 2, wherein the metal layer piece is disposed on the LOCOS film. 基板上に、複数のＬＯＣＯＳ膜が互いに離間して配置され、各ＬＯＣＯＳ膜上にそれぞれシリコン層片が配置され、更にこれらのシリコン層片の上に、絶縁層と金属層とが交互に積層され、最上層の金属層上に、該最上層の金属層を露出する開口部を有した最上層の絶縁層を有し、
前記最上層の金属層を除く各層の金属層は、互いに離間して配置された複数の金属層片から成り、前記ＬＯＣＯＳ膜、前記シリコン層片、及び前記金属層片による段差を反映して、前記最上層の金属層の表面が凹凸を有することを特徴とするボンディングパッド。On the substrate, a plurality of LOCOS films are arranged apart from each other, a silicon layer piece is arranged on each LOCOS film, and an insulating layer and a metal layer are alternately laminated on these silicon layer pieces. Having an uppermost insulating layer having an opening exposing the uppermost metal layer on the uppermost metal layer,
The metal layer of each layer except for the uppermost metal layer is composed of a plurality of metal layer pieces arranged apart from each other, reflecting the step by the LOCOS film, the silicon layer piece, and the metal layer piece, A bonding pad, wherein the surface of the uppermost metal layer has irregularities. 前記金属層片が前記シリコン層片の上に配置されていることを特徴とする請求項４記載のボンディングパッド。5. The bonding pad according to claim 4, wherein the metal layer piece is disposed on the silicon layer piece.
JP2002323786A 2002-11-07 2002-11-07 Bonding pad Pending JP2004158678A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008294159A (en) * 2007-05-23 2008-12-04 Denso Corp Manufacturing method of semiconductor device and semiconductor device
US7880256B2 (en) 2005-03-25 2011-02-01 Sanyo Electric Co., Ltd. Semiconductor device with passivation layer covering wiring layer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7880256B2 (en) 2005-03-25 2011-02-01 Sanyo Electric Co., Ltd. Semiconductor device with passivation layer covering wiring layer
JP2008294159A (en) * 2007-05-23 2008-12-04 Denso Corp Manufacturing method of semiconductor device and semiconductor device

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