JP2004153160A - Chip resistor and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a chip resistor capable of preventing or suppressing any failure being the generation of large fluctuation in a resistance value due to how solder is brought into contact with an electrode. <P>SOLUTION: This chip resistor A is provided with a chip-shaped resistor 1 and at least a pair of electrodes 3 arranged on one face of the resistor 1 so as to be isolated from each other. The pair of electrodes 3 are isolated from a terminal edge 1a of the resistor 1 in a direction where those electrodes 3 are lined up. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a chip resistor and a method for manufacturing the same.
[0002]
[Prior art]
FIG. 9 shows an example of a conventional chip resistor (see Patent Document 1). The illustrated chip resistor B has a configuration in which a pair of electrodes 91 are provided on the lower surface of a metal chip-shaped resistor 90. The pair of electrodes 91 are separated from each other via the gap 93, and have a relatively large area over the entire lower surface of the resistor 90 except for the gap 93. On the lower surface of each electrode 91, a solder layer 92 is formed as means for improving solderability during mounting.
[0003]
This chip resistor B is manufactured by a method as shown in FIG. First, as shown in FIG. 3A, two metal plates 90 'and 91' are prepared as respective materials of the resistor 90 and the electrode 91, and as shown in FIG. A metal plate 91 'is overlapped and joined to the lower surface of 90'. Next, as shown in FIG. 9C, a part of the metal plate 91 ′ is cut by machining to form a gap 93. Thereafter, as shown in FIG. 5D, a solder layer 92 'is formed on the lower surface of the metal plate 91', and then the metal plates 90 'and 91' are cut as shown in FIG. . Thereby, the chip resistor B is manufactured.
[0004]
[Patent Document 1]
JP-A-2002-57009 (FIG. 1)
[0005]
[Problems to be solved by the invention]
In the above-described chip resistor B, the width Sa of each electrode 91 is large in the direction in which the pair of electrodes 91 are arranged. Therefore, when the resistance value is measured by bringing the measurement probe into contact with the pair of electrodes 91, the resistance value Ra when the measurement probe is brought into contact with the respective inner edge portions 91a of the pair of electrodes 91, and the outer edge portion 91b , The difference from the resistance value Rb when contact was made large. Since the resistance value greatly differs depending on which part of each electrode 91 the measurement probe contacts, when the chip resistor B is used, a large variation occurs in the resistance value depending on how the chip resistor B is used. Which is not preferable.
[0006]
More specifically, for example, when the chip resistor B is surface-mounted at a desired location by using solder, the solder does not adhere to the entire lower surface of each electrode 91 but, for example, the inside of each electrode 91. There is a case where only the portion near the edge portion 91a comes into contact in a biased manner. Conversely, the solder may come into contact with only a portion of the lower surface of each electrode 91 near the outer edge 91b. Conventionally, if the mounting is performed in such a state, a large variation occurs in the resistance value, and there is a possibility that the specification of an electric circuit configured using the chip resistor B may be out of order. When the chip resistor B has a low resistance of, for example, 10 mΩ or less, even if the difference between the above-described resistance value Ra and the resistance value Rb is small, when compared with the overall resistance value of the chip resistor B, The percentage of difference is very large. Therefore, the lower the resistance of the chip resistor B is, the more serious the above-mentioned problem is.
[0007]
As means for suppressing the above problem, for example, means for increasing the thickness of each electrode 91 and reducing the electric resistance of each electrode 91 itself can be considered. However, according to such means, in addition to increasing the overall thickness of the chip resistor B, the amount of cutting of the metal plate 91 ′ when forming the gap 93 increases, and the production of the chip resistor B is increased. This causes a problem that the cost is high.
[0008]
Further, in the above-mentioned prior art, there is a problem that the manufacturing operation of the chip resistor B is complicated and its productivity is poor. More specifically, conventionally, the formation of the gap 93 is performed by machining. In the processing, it is necessary to finish the dimension between the pair of electrodes 91 with high accuracy, and it is necessary to take care that the surface of the metal plate 90 'is not cut into a concave shape. For this reason, the above processing must be performed very carefully, and the productivity of the chip resistor B has deteriorated. Further, in the above-described conventional technique, since the chip resistor B is manufactured through the cutting process, an error in the inter-electrode resistance value due to the cutting accuracy has also occurred.
[0009]
The present invention has been conceived in view of the above circumstances, and has a chip resistor capable of eliminating or suppressing a problem that a large variation occurs in a resistance value depending on how a solder contacts an electrode. The task is to provide equipment. Another object of the present invention is to provide a method for manufacturing a chip resistor capable of efficiently and appropriately manufacturing such a chip resistor.
[0010]
DISCLOSURE OF THE INVENTION
In order to solve the above problems, the present invention employs the following technical means.
[0011]
That is, the chip resistor provided by the first aspect of the present invention includes a chip-shaped resistor, and at least one pair of electrodes provided on one surface of the resistor and spaced apart from each other. Wherein the pair of electrodes are separated from an edge of the resistor in a direction in which the electrodes are arranged.
[0012]
According to such a configuration, since the pair of electrodes are separated from the edge of the resistor in the direction in which they are arranged, the width in the direction is reduced by that much. Therefore, the difference between the resistance between the inner edges of the pair of electrodes and the resistance between the outer edges is also reduced. As a result, when mounting the chip resistor, even if the solder is biased toward the inner edge of each electrode or contacts the bias toward the outer edge of each electrode, Unlike the prior art, it is possible to prevent a large variation in the resistance value from occurring, and to prevent a large deviation from occurring in the specification of the electric circuit formed by using the chip resistor.
[0013]
In a preferred embodiment of the present invention, the resistor includes an insulating layer provided on one surface of the resistor, and the pair of electrodes are separated from each other across all or part of the insulating layer. According to such a configuration, the interval between the pair of electrodes can be defined by the insulating layer. More specifically, when the width of the portion of the insulating layer sandwiched between the pair of electrodes is set to a predetermined dimension, the distance between the pair of electrodes can be accurately defined to the predetermined dimension. On the other hand, if the insulating layer is formed by using a method such as thick film printing described later, the width can be finished to a desired width with high dimensional accuracy. Therefore, the distance between the pair of electrodes can be set to a desired size with high dimensional accuracy. In order to set the rated resistance value of the chip resistor to a desired target resistance value, it is one condition that the interval between the pair of electrodes is specified to a predetermined accurate dimension. This is suitable for satisfying the conditions.
[0014]
In a preferred embodiment of the present invention, of the one surface of the resistor, a region between each of the electrodes and the edge of the resistor is covered with the insulating layer. According to such a configuration, the width of each of the electrodes can be regulated to an accurate dimension by the insulating layer. In addition, by covering a portion of the one surface of the resistor other than a portion where each of the electrodes is formed with the insulating layer, it is possible to prevent solder or the like from directly touching the one surface of the resistor.
[0015]
In a preferred embodiment of the present invention, the insulating layer is formed by thick-film printing. According to such a configuration, even when the insulating layer has a complicated shape, the insulating layer can be easily formed with high dimensional accuracy.
[0016]
In a preferred embodiment of the present invention, an overcoat layer having electrical insulation is provided on a surface of the resistor opposite to the one surface. According to such a configuration, the resistor is protected by the overcoat layer, and, for example, the resistor does not directly contact other electrical components or the like, and an unreasonable current flows between them. You can do so.
[0017]
In a preferred embodiment of the present invention, the overcoat layer and the insulating layer are made of the same material. According to such a configuration, the use of the same material for the overcoat layer and the insulating layer is suitable for reducing the production cost.
[0018]
In a preferred embodiment of the present invention, the thickness of each of the electrodes is greater than the thickness of the insulating layer. According to such a configuration, when the chip resistor is mounted at a desired position by using solder, the solder can be easily attached to the entire distal end surface of the electrode.
[0019]
A method for manufacturing a chip resistor provided by a second aspect of the present invention includes a step of patterning an insulating layer on one surface of a plate serving as a material of a resistor, and the step of forming the insulating layer on the one surface of the plate. Forming a conductive layer in a region where no is formed, and a step of dividing the plate into a plurality of chip-shaped resistors. A part of the layer is formed as a pair of electrodes separated from each other across a part of the insulating layer, and the pair of electrodes is formed so as to be separated from an edge of the resistor in a direction in which the electrodes are arranged. And
[0020]
According to such a configuration, the chip resistor provided by the first aspect of the present invention can be efficiently and appropriately manufactured.
[0021]
In a preferred embodiment of the present invention, the division of the plate is performed by punching. According to blanking, a dimensional difference between a punched product and a die for punching is small, and a dimensional error of the product can be reduced. Therefore, the above configuration is suitable for finishing the resistor to a desired size with high dimensional accuracy. In addition, punching can be performed with good workability, and is more preferable for increasing the productivity of the chip resistor.
[0022]
Other features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention.
[0023]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of the present invention will be specifically described with reference to the drawings.
[0024]
1 to 3 show an example of a chip resistor according to the present invention. 1 and 2, the chip resistor A of the present embodiment includes a resistor 1, an overcoat layer 2, a pair of electrodes 3, and an insulating layer 4.
[0025]
The resistor 1 has a rectangular chip shape with a constant thickness at each part, and is made of metal. Specific examples of the material include a Cu—Mn-based alloy, a Ni—Cu-based alloy, and a Ni—Cr-based alloy, but are not limited thereto. What is necessary is just to select suitably what has a resistivity suitable for. Although not very realistic, the resistor 1 can be made of non-metal.
[0026]
The overcoat layer 2 is provided so as to cover the entire surface 10a of the resistor 1, and has electrical insulation. The overcoat layer 2 is formed by thick-film printing, and is, for example, an epoxy resin-based resin film.
[0027]
The insulating layer 4 is formed at a total of three places on the back surface 10 b of the resistor 1, and includes a first region 4 a formed in a middle portion of the resistor 1 in the width direction (left and right width directions in FIGS. 1 and 2). And a pair of second regions 4b formed at both ends in the width direction of the resistor 1. The insulating layer 4 is made of the same material as the overcoat layer 2, and is a resin film formed by thick film printing similarly to the overcoat layer 2.
[0028]
The pair of electrodes 3 are provided on the back surface 10 b of the resistor 1, and are formed, for example, by plating the resistor 1 with copper, as described later. The pair of electrodes 3 are separated from each other in the width direction of the resistor 1 with the first region 4a of the insulating layer 4 interposed therebetween, and are also sandwiched between the first and second regions 4a and 4b. . Therefore, each electrode 3 is separated from the edge 1a of the resistor 1 by the width s1 of the second region 4b in the width direction of the resistor 1, and the width s2 of each electrode 3 can be reduced accordingly. The structure is as planned.
[0029]
Each electrode 3 is in contact with the end face 40a so that no gap is formed between the electrode 3 and the end face 40a in the width direction of the first region 4a of the insulating layer 4. Thus, the dimension s3 between the pair of electrodes 3 is accurately defined by the insulating layer 4. That is, the dimension s3 between the pair of electrodes 3 is the same as the width of the first region 4a. On the lower surface of each electrode 3, a solder layer 39 for improving the solderability is formed.
[0030]
1 and 2, the ends of the electrode 3 and the solder layer 39 are schematically shown. However, since the electrode 3 and the solder layer 39 are formed by plating, the electrodes 3 and the solder layer 39 are actually shown in FIG. As shown, some of them overlap on the insulating layer 4. However, since the overlapping portion itself does not directly contact the back surface 10b of the resistor 1, it does not cause an error in the resistance value between the electrodes of the resistor 1. Therefore, the width of the overlap may be relatively large. Further, the electrode 3 is in contact with the end surface 40b of the second region 4b of the insulating layer 4 so that no gap is generated. Therefore, the width s2 of the electrode 3 is also precisely defined by the insulating layer 4.
[0031]
The total thickness t1 of each electrode 3 and each solder layer 39 is greater than the thickness t2 of the insulating layer 4, and each solder layer 39 has a structure projecting below the lower surface of the insulating layer 4. I have. In the present embodiment, the single thickness t3 of each electrode 3 is also larger than the thickness t2 of the insulating layer 4.
[0032]
As an example of the thickness of each part, the overcoat layer 2 and the insulating layer 4 are each about 20 μm, each electrode 3 is about 30 μm, and each solder layer 39 is about 5 μm. The resistor 1 has a thickness of about 0.1 mm to 1 mm, and the vertical and horizontal dimensions are about 2 mm to 7 mm, respectively. However, it goes without saying that the size of the resistor 1 is variously changed according to the magnitude of the target resistance value. The chip resistor A is configured as a low resistor having a resistance of about 0.5 mΩ to 50 mΩ.
[0033]
Next, an example of a method of manufacturing the above-described chip resistor A will be described with reference to FIGS.
[0034]
First, as shown in FIG. 4A, a metal plate 1A serving as a material of the resistor 1 is prepared. The plate 1A has a vertical and horizontal size in which a plurality of resistors 1 can be formed, and has a uniform thickness throughout. As shown in FIG. 1B, an overcoat layer 2A is formed on the entire or substantially entire upper surface 10a of the plate 1A. The overcoat layer 2A is formed by printing a resin, which is a material of the overcoat layer 2A, in a solid-like thick film. After the formation of the overcoat layer 2A, a step of marking the overcoat layer 2A may be performed.
[0035]
Next, as shown in FIG. 3C, the plate 1A is turned upside down, and then a plurality of insulating layers 4A are formed in a stripe pattern on the upwardly facing surface 10b of the plate 1A. The formation of the plurality of insulating layers 4A is performed by thick film printing using the same resin and apparatus as used for forming the overcoat layer 2. This is preferable for reducing the manufacturing cost of the chip resistor A as compared with the case where a plurality of types of materials and devices are used. According to the method of thick film printing, the width and the like of each insulating layer 4A can be accurately finished to predetermined dimensions.
[0036]
In a region between the plurality of insulating layers 4A on the surface 10b of the plate 1A, as shown in FIG. 5D, a conductive layer 3A and a solder layer 39A are sequentially formed. The conductive layer 3A is formed by plating copper, for example. According to this plating process, it is possible to uniformly form the conductive layer 3A in a region between the adjacent insulating layers 4A without causing a gap between the conductive layer 3A and the insulating layer 4A. The formation of the solder layer 39A is also performed by plating.
[0037]
After that, as shown in FIG. 5E, the plate 1A is repeatedly subjected to punching (blanking) to divide the plate 1A into a plurality of chip-shaped resistors 1 (in FIG. 5C, cross-hatching). Are the portions corresponding to the insulating layers 4 and 4A. The same applies to the following drawings). When such a punching operation is repeatedly performed, preferably, one punching die (not shown) is repeatedly used.
[0038]
In the punching operation, a part of each of the two conductive layers 3A and the part of the solder layer 39A adjacent to each other, a part of one insulating layer 4A interposed therebetween, and two parts located on both sides thereof The plate 1A is punched so that a part of each of the two insulating layers 4A remains on one surface of the resistor 1. Due to this punching, a part of each of the two conductive layers 3A becomes a pair of electrodes 3 in the chip resistor A shown in FIGS. 1 and 2, and a part of the insulating layer 4A becomes the first and third electrodes of the insulating layer 4. 2 areas 4a and 4b. In this way, a plurality of chip resistors A can be appropriately taken from the plate 1A. In FIG. 5E, the punched regions are indicated by imaginary lines, but as shown in FIG. 5A, in the punching of the plate 1A, a plurality of punched regions are arranged in a matrix at an appropriate interval s4. You can proceed to
[0039]
As described above, if the punching means is adopted as a means for dividing the plate 1A into the plurality of resistors 1, the vertical and horizontal dimensions of the resistor 1 can be finished to an accurate size with almost no error. Further, if the punching operation is performed by repeatedly using one punching die, unlike a case where a plurality of punching dies are used alternately, a plurality of chip resistors caused by a variation in the dimensions of the plurality of punching dies are obtained. There is no dimensional variation between them.
[0040]
The chip resistor A of the present embodiment is surface-mounted on a desired mounting object by using, for example, a solder reflow technique. Since the solder layer 39 protrudes below the lower surface of the insulating layer 4, it is possible to appropriately perform soldering during surface mounting. In particular, since the thickness t3 of each electrode 3 is greater than the thickness t2 of the insulating layer 4 and each electrode 3 itself protrudes below the insulating layer 4, soldering to each electrode 3 is more appropriate. Can be performed. Since the entire upper surface of the resistor 1 is covered with the overcoat layer 2, the occurrence of improper electrical conduction between the resistor 1 and other members or devices is also prevented.
[0041]
As described above, each electrode 3 is separated from the edge 1a of the resistor 1 by an appropriate dimension s1 in the width direction of the resistor 1, and the width s2 of each electrode 3 is, for example, a It becomes narrower than when it is formed to extend to the edge 1a of the body 1. As described above, when the width s2 of each electrode 3 is reduced, the difference between the resistance value R1 between the inner edges of the pair of electrodes 3 and the resistance value R2 between the outer edges is reduced (see FIG. 2). As a result, when the chip resistor A is surface-mounted at a desired location, for example, the solder may come into contact with a portion near the inner edge of the pair of electrodes 3 or, on the contrary, the outside of the pair of electrodes 3 Even if a situation occurs in which a portion near the edge is unevenly contacted, a large difference in resistance value can be prevented. According to the present embodiment, it is not necessary to increase the thickness of each electrode 3 and reduce its electrical resistance as means for reducing the difference between the resistance values R1 and R2. Therefore, from such a viewpoint, the thickness of each electrode 3 does not need to be increased, so that it is preferable to reduce the thickness of the entire chip resistor A.
[0042]
If the error of the resistance value caused by the width of the electrode 3 is not considered, the resistance between the electrodes of the chip resistor A is determined by the resistivity of the resistor 1, the dimension s3 between the pair of electrodes 3, and the size of the resistor 1. It is determined. On the other hand, in the chip resistor A, as described above, the vertical and horizontal dimensions of the resistor 1 can be finished to a desired size with high accuracy by punching, and the thickness of the resistor 1 can be reduced. , From the stage of the plate 1A. The dimension s3 between the pair of electrodes 3 is equal to the width of the first region 4a of the insulating layer 4. However, the width of the first region 4a can be formed with considerably high dimensional accuracy by thick film printing. Since it is possible, the dimension s3 can be finished to a desired value with high accuracy. As described above, when the size of the resistor 1 and the dimension s1 between the pair of electrodes 3 are finished to a desired value with high accuracy, the error of the actual interelectrode resistance of the chip resistor A with respect to the target resistance value is very small. Become. As a result, in the chip resistor A, it is possible to eliminate the necessity of performing trimming for adjusting the resistance value after the manufacture.
[0043]
6 to 8 show other embodiments of the chip resistor according to the present invention. In these drawings, the same or similar elements as those in the above embodiment are denoted by the same reference numerals.
[0044]
In the chip resistor Aa shown in FIGS. 6A and 6B, four electrodes 3 (3 a, 3 b) are formed on the back surface of the resistor 1. Of these, the two electrodes 3a form a pair, and are separated from the edge 1a of the resistor 1 by an appropriate distance s5 in the direction in which they are arranged (the horizontal direction in the figure). Similarly, the two electrodes 3b are also paired and are separated from the edge 1a by an appropriate distance. In order to manufacture the chip resistor Aa, the insulating layer 4A formed on one surface of the plate 1A is shaped as shown in FIG. 3C, and the plate 1A is cut at a location indicated by a virtual line in FIG. Good. As a means for dividing the plate 1A into a plurality of chip-shaped resistors 1, a cutting means such as using a shear (shearing machine) or a rotary cutter may be used instead of punching.
[0045]
Since such a chip resistor Aa has four electrodes 3, it can be used, for example, as follows. That is, of the four electrodes 3 (3a, 3b), one pair of electrodes 3a is used as a current electrode, and the other pair of electrodes 3b is used as a voltage electrode. When the current of the electric circuit is detected, the pair of current electrodes 3a is electrically connected to the electric circuit so that the electric current of the electric circuit flows. A voltmeter is connected to the pair of voltage electrodes 3b. Since the resistance value of the chip resistor Aa is known, the voltage drop in the resistor 1 of the chip resistor Aa is measured using the voltmeter, and the measured value is applied to the Ohm formula to obtain the resistance. The value of the current flowing through the body 1 can be accurately known. Since the arrangement of the four electrodes 3 (3a, 3b) is symmetric, even if the chip resistor Aa is rotated by 180 ° and mounted, there is no problem and it is convenient. Of course, since each electrode 3 is separated from the edge 1a of the resistor 1 and has a small width s6, it is possible to prevent a large variation in resistance value depending on the mounting method. .
[0046]
The chip resistors Ab and Ac shown in FIGS. 7 and 8 are another example in which four electrodes are provided. Each of these chip resistors Ab and Ac has a pair of two electrodes 3c and a pair of two electrodes 3d, and the electrodes 3c and 3d have different shapes and sizes from each other. Has become. The electrode 3c is separated from the edge 1a of the resistor 1 by an appropriate dimension s7, while the electrode 3d is not separated from the edge 1a. In order to manufacture these chip resistors Ab and Ac, the insulating layer 4A formed on the plate 1A is shaped as shown in FIGS. 7 (c) and 8 (c), for example. The plate 1A may be cut at the location indicated by the line.
[0047]
In these chip resistors Ab and Ac, a pair of narrow electrodes 3c is used as a voltage electrode, and a pair of electrodes 3d wider than them are used as current electrodes. Since the voltage electrode is used for accurately measuring the voltage drop amount, an accurate voltage drop amount can be obtained by using a pair of narrow electrodes 3c as the voltage electrode. It becomes. Thus, in the present invention, when four electrodes are provided, only a pair of the electrodes may be configured to be separated from the edge of the resistor.
[0048]
The present invention is not limited to the contents of the above-described embodiment. The specific configuration of each part of the chip resistor according to the present invention can be variously changed in design. Similarly, the specific configuration of each step of the method for manufacturing a chip resistor according to the present invention can be variously changed.
[0049]
The chip resistor according to the present invention is not limited to one provided with one or two pairs of electrodes, but may be provided with three or more electrodes. As long as at least one pair of these electrodes is separated from the edge of the resistor in the direction in which they are arranged, the technical scope of the present invention is included. The specific dimensions from the edge to the electrode are not limited. When the number of electrodes is increased, for example, a method of using some of them as dummy electrodes is also possible.
[0050]
It is easy to form the electrodes by plating, but the present invention is not limited to this, and another method may be used. As a means for forming the insulating layer on one side of the resistor, a means such as transfer can be adopted. Needless to say, the chip resistor according to the present invention may be manufactured by a manufacturing method different from the manufacturing method of the chip resistor according to the present invention, for example, the same method as the prior art described with reference to FIG. No. The present invention is suitable for a case where the chip resistor has a low resistance, but the specific resistance value is not limited.
[Brief description of the drawings]
FIG. 1 is a perspective view showing an example of a chip resistor according to the present invention.
FIG. 2 is a sectional view taken along line II-II of FIG.
FIG. 3 is an enlarged view of a main part of FIG. 2;
FIGS. 4A to 4C are perspective views showing a part of a manufacturing process of the chip resistor shown in FIG. 1;
5D is a perspective view showing a part of the manufacturing process of the chip resistor shown in FIG. 1, and FIG. 5E is a plan view showing a part of the manufacturing process of the chip resistor shown in FIG. FIG.
6 (a) is a front view showing another example of the chip resistor according to the present invention, FIG. 6 (b) is a bottom view of FIG. 6 (a), and FIG. It is a principal part top view which shows the example of a process of manufacturing the shown chip resistor.
7 (a) is a front view showing another example of the chip resistor according to the present invention, FIG. 7 (b) is a bottom view of FIG. 7 (a), and FIG. It is a principal part top view which shows the example of a process of manufacturing the shown chip resistor.
8A is a front view showing another example of the chip resistor according to the present invention, FIG. 8B is a bottom view of FIG. 8A, and FIG. It is a principal part top view which shows the example of a process of manufacturing the shown chip resistor.
FIG. 9 is a perspective view showing an example of a conventional chip resistor.
FIGS. 10A to 10E are explanatory views showing an example of a conventional method for manufacturing a chip resistor.
[Explanation of symbols]
A Chip resistor 1 Resistor 1a Edge (of resistor)
1A plate 2 overcoat layer 3 electrode 4 insulating layer 39 solder layer

Claims (8)

A chip resistor comprising a chip-shaped resistor and at least one pair of electrodes provided on one surface of the resistor and arranged apart from each other,
A chip resistor, wherein the pair of electrodes are separated from an edge of the resistor in a direction in which the electrodes are arranged. 2. The chip resistor according to claim 1, further comprising an insulating layer provided on one surface of the resistor, and wherein the pair of electrodes are separated from each other with the whole or a part of the insulating layer interposed therebetween. 3. 3. The chip resistor according to claim 2, wherein a region between each of the electrodes and the edge of the resistor on the one surface of the resistor is covered with the insulating layer. 4. The chip resistor according to claim 2, wherein the insulating layer is formed by thick-film printing. 5. The chip resistor according to claim 1, wherein an overcoat layer having electrical insulation is provided on a surface of said resistor opposite to said one surface. The chip resistor according to claim 5, wherein the overcoat layer and the insulating layer are made of the same material. 7. The chip resistor according to claim 2, wherein the thickness of each of the electrodes is greater than the thickness of the insulating layer. A step of patterning an insulating layer on one side of a plate serving as a material of the resistor,
A step of forming a conductive layer in a region of the one surface of the plate where the insulating layer is not formed,
Dividing the plate into a plurality of chip-shaped resistors,
In the division of the plate, a part of the conductive layer is formed as a pair of electrodes separated from each other across a part of the insulating layer on one surface of each of the resistors, and the pair of electrodes are arranged in a direction in which these are arranged. A method of manufacturing a chip resistor, wherein the method is performed so as to be separated from an edge of the resistor.

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