JP2004146520A - Capacitor - Google Patents

Abstract

A capacitor structure capable of easily coping with miniaturization of a semiconductor device and a method for forming the structure are provided.
According to the present invention, a first electrode made of carbon nanotubes (CNT) extending in a cylindrical shape along a predetermined direction, and a first electrode provided around a cylindrical wall surface of the carbon nanotube via an insulator. Provided is a capacitor having a second electrode. As a result, even if the dimensions of the semiconductor device are miniaturized, it is possible to secure a capacitance of a certain value or more.
[Selection diagram] Fig. 4

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to a capacitor structure used in a semiconductor device and a method of making the structure.
[0002]
[Prior art]
2. Description of the Related Art In recent years, the size of semiconductor devices has been increasingly reduced, and in particular, the degree of integration of semiconductor storage elements such as dynamic random access memories (DRAMs) has been extremely improved.
[0003]
FIG. 1 and FIG. 2 are schematic sectional views showing main steps for manufacturing a conventional DRAM. FIG. 1A illustrates a gate transistor 12, 14 for a memory cell and a bit line 16 coupled to a common source / drain region of the gate transistor 12, 14. The gates of the gate transistors 12, 14 are coupled to a word line extending in a direction perpendicular to the plane of the paper. Source / drain regions different from the common source / drain regions are coupled to conductive plugs 18 and 20, respectively. On the right side of FIG. 1A, a sense amplifier for a memory cell and other peripheral devices are schematically shown. An insulator 26 such as a shallow trench isolation (STI) is provided between the region 22 for the memory cell and the region 24 for the peripheral device, and between the transistors.
[0004]
On such a base structure 28, a nitride film 30 functioning as an etch stopper is formed, and, for example, silicon dioxide (SiO 2) is formed thereon. ₂ ) Is formed. Then, openings 34 and 36 are formed using a lithography method and an etching method. The opening is formed to have a size of about 0.2 μm × 0.5 μm in a 0.15 μm node (１ ／ pitch) generation, for example, depending on the generation. The conductive plugs 18, 20 are exposed at the bottoms of the openings 34, 36. These openings 34, 36 will act as molds for forming the capacitor electrodes forming the memory cells.
[0005]
In the step shown in FIG. 1B, a conductive film 38 having excellent coverage characteristics is formed in the openings 34 and 36 and on the entire surface of the insulating film 32. As the conductive film 38, doped silicon, ruthenium (Ru), titanium nitride (TiN), tungsten (W), or the like can be used, but is not limited thereto. Thereafter, the conductive film 38 other than the openings 34 and 36 is removed by a chemical mechanical polishing (CMP) method.
[0006]
In the step shown in FIG. 1C, the insulating film 32 around the conductive film 38 is removed by etching with a chemical solution of, for example, hydrofluoric acid (HF). As a result, cylindrical electrodes 40 and 42 projecting from the substrate are formed, and these become one electrode of the capacitor. The thickness of the electrodes 40 and 42 is very thin, for example, about 20 nm.
[0007]
In the step shown in FIG. 2D, a dielectric film 44 is formed on the wall surfaces of the electrodes 40 and 42, and a conductive film 46 is formed thereon. The conductive film 46 becomes the other electrode of the capacitor. Unnecessary conductive films 44 and 46 other than the memory cell region are removed by etching.
[0008]
In the step shown in FIG. 2E, for example, SiO 2 is formed on the conductive film 46. ₂ An insulating film 48 is formed. Then, a contact hole reaching the conductive film 46 is formed, and the conductive plug 50 connected to the conductive film 46 is filled. Similarly, conductive plugs 52 for peripheral devices are filled.
[0009]
In the step shown in FIG. 2F, a wiring layer 54 for connecting the plug electrodes 50 and 52 to a reference potential such as ground (GND) is formed, and the capacitor structure is completed.
[0010]
FIG. 3 shows an equivalent circuit of the portion 22 of the memory cell in the structure created according to FIGS. As shown, two capacitors (40, 44, 46), (42, 44, 46), one end of which is connected to the reference potential GND, are coupled to the bit line (B) 16 through the gate transistors 12, 14. Is done. The gates of the gate transistors 12, 14 are coupled to a word line (W). That is, one memory cell is provided at the intersection of the word line and the bit line. By activating the desired word and bit lines, the required memory cells can be accessed, and data is read and written through the charge stored on the capacitors.
[0011]
By the way, it is considered that a finer semiconductor device can be realized by uniformly reducing all dimensions of the semiconductor device. Since the gate length, line width, and all other dimensions are reduced, the dimensions of the capacitor are also reduced, and the amount of charge stored is also reduced. However, if the charge amount is too small, it is determined whether or not the charge stored in the capacitor exists due to the effects of cosmic rays (such as alpha rays), the effects of electrical noise, and the effects of thermal fluctuations (ie, information Is difficult to read. For this reason, it is necessary to consider a predetermined lower limit as the capacitance of the capacitor required for the memory cell, and this lower limit is, for example, 30 femto farads (fF / cell) per cell.
[0012]
Therefore, when miniaturizing a semiconductor device, it is necessary to reduce the size of the element while maintaining a certain capacitor capacitance. In general, the capacitance of a capacitor tends to increase as the dielectric constant and the electrode area increase, and decrease as the distance between the electrode plates increases. If the same dielectric film is used before and after miniaturization, it is necessary to increase the electrode area. Therefore, when miniaturizing the semiconductor device as shown in FIGS. 1 and 2, the gate length and the line width are reduced and the aspect ratio of the capacitor electrodes 40 and 42 formed in FIG. It is necessary to increase the size (the height of the electrode is increased) to increase the electrode area.
[0013]
However, in order to form the electrodes 40 and 42 having a large aspect ratio, it is necessary to form the openings 34 and 36 (FIG. 1A) serving as molds for the electrodes also in a large aspect ratio, and it is difficult to form the openings by etching. Problem arises. There is also a problem that it is difficult to appropriately form the conductive film 38 (FIG. 1B) in the opening having a large aspect ratio. Further, when the aspect ratio of the electrodes 40 and 42 is large, the mechanical strength of the electrodes 40 and 42 is weakened, and there is a problem that the electrodes 40 and 42 are easily tilted. For example, when the insulating film 32 serving as a mold is removed, a problem arises in that the electrode film falls down due to stirring of the chemical solution, or the electrodes come into contact with each other when pulled up from the chemical solution, and the electrode structure is destroyed. Can also occur. Thus, miniaturization of a conventional semiconductor device has not always been easy.
[0014]
[Non-patent document 1]
Nikkei Science, August 2002, p. 18-45.
[0015]
[Problems to be solved by the invention]
A general object of the present application is to provide a capacitor structure which can easily cope with miniaturization of a semiconductor device and a method for manufacturing the structure.
[0016]
A specific object of the present application is to provide a capacitor structure capable of securing a capacitor capacitance of a certain value or more even when the size of a semiconductor device is miniaturized, and a method of forming the structure.
[0017]
[Means for Solving the Problems]
According to the present invention,
A first electrode made of carbon nanotubes extending in a cylindrical shape along a predetermined direction;
A second electrode provided around the cylindrical wall surface of the carbon nanotube via an insulator
Capacitor characterized by having
Is provided.
[0018]
[Action]
At least one electrode of the capacitor according to the present invention is made of carbon nanotube (CNT) extending in a cylindrical shape along a predetermined direction. CNT is a cylindrical substance composed of carbon atoms (C), and has a cylindrical structure that can be formed by rolling graphite having a large number of hexagonal network structures. The electrical characteristics of the CNT also differ depending on the rounding method. In general, CNT has semiconductor or conductor properties. In the rounding method, the "armchair type" in which hexagonal structures are aligned without twisting in the direction in which the CNTs extend, the "zigzag type" in which hexagonal structures are alternately aligned, hexagonal There is a "spiral type" in which the structure is spirally twisted. Since CNTs are strongly bonded to each other, CNTs have not only a high mechanical strength, but also a property that problems such as electromigration hardly occur even when a large current flows. In addition, since conductivity is caused by delocalized π electrons, the material exhibits excellent conductivity with low resistance. (For carbon nanotubes, see Non-Patent Document 1, for example.)
According to the present invention, an electrode of a capacitor is formed using CNT having such properties. For this reason, a mold structure for forming a conventional electrode is unnecessary, and an electrode having a high aspect ratio, which has conventionally been difficult to form, can be appropriately formed. Thereby, a capacitor structure that can easily cope with miniaturization of a semiconductor device is obtained. Further, even if the dimensions of the semiconductor device are miniaturized, it is possible to secure a capacitor capacity of a certain value or more.
[0019]
CNTs are produced by an arc discharge method in which CNTs are produced by causing an arc discharge to evaporate carbon, a laser ablation (laser furnace) method in which graphite is heated in an electric furnace and irradiated with a laser beam to evaporate the carbon, Alternatively, it can be formed by a chemical vapor deposition (CVD) method in which CNTs are grown by blowing metal fine particles serving as a catalyst into a high-temperature reactor. In particular, if a seed layer containing catalyst fine particles of a transition metal element such as iron (Fe), cobalt (Co), nickel (Ni), or titanium (Ti) is prepared, CNTs are grown from the seed layer. It becomes possible. Therefore, a desired CNT can be formed by forming a seed layer at an appropriate place.
[0020]
CNTs include not only single-walled nanotubes having a single-walled tubular structure but also multi-walled nanotubes in which a plurality of tubes are nested. These can be separately formed by changing various conditions (especially reaction temperature) for growing the CNT and changing the material of the seed layer.
[0021]
By appropriately changing the conditions of the seed layer and the conditions (temperature, pressure, time, and the like) during the growth of the CNT, it is possible to adjust the thickness, length, number, and electrical characteristics of the CNT. Note that CNT of a semiconductor usually has P-type properties, but ion implantation of an element such as potassium (K) is effective for forming N-type CNTs. Further, by heating the CNT in a vacuum, it is possible to convert the P-type to the N-type.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
FIGS. 4 and 5 are schematic sectional views showing the main steps for manufacturing the DRAM according to the first embodiment of the present invention. 4A, a base structure 28 similar to that described with reference to FIG. 1A is formed. Gate transistors 12 and 14 are formed in a region 22 of the memory cell, and the common source / drain regions of the gate transistors 12 and 14 are coupled to the bit line 16. The gates of the gate transistors 12 and 14 constitute a word line extending in a direction perpendicular to the plane of the drawing. Source / drain regions different from the common source / drain regions are coupled to conductive plugs 18 and 20, respectively. The conductive plugs 18, 20 are made of, for example, doped silicon. On the right side of FIG. 4A, a sense amplifier for a memory cell and other peripheral devices are schematically shown. An insulator 26 such as a shallow trench isolation (STI) is provided between the region 22 for the memory cell and the region 24 for the peripheral device, and between the transistors.
[0023]
On such a base structure 28, an insulating film 402 made of, for example, SiN is formed. Openings 404, 406 leading to the conductive plugs 18, 20 are formed using lithography and etching. It should be noted that, unlike the conventional process (FIG. 1A), the insulating film 32 serving as a mold for the capacitor electrode and the deep openings 34 and 36 are not formed.
[0024]
In the step shown in FIG. 4B, a transition metal element such as cobalt (Co) is formed on the entire surface of the structure formed in FIG. 1A by using a film forming technique such as CVD or sputtering. Is formed. Next, a heat treatment at, for example, 500 ° C. to 700 ° C. is performed. By this heat treatment, silicide is formed in the openings 404 and 406. Then, an unnecessary metal film on the insulating film 402 is removed. In this manner, seed layers 408 and 410 that serve as starting points for carbon nanotube growth are formed in the openings 404 and 406. As the transition metal element for forming the seed layer, for example, iron (Fe), nickel (Ni), titanium (Ti), or the like can be used other than cobalt. In this embodiment, the conductive plugs 18 and 20 are made of doped silicon, but other conductive materials can be used. However, from the viewpoint of forming the seed layer while reducing the resistance by silicidation, it is preferable to use doped silicon.
[0025]
In this embodiment, the openings 404 and 406 are formed larger than the sizes of the conductive plugs 18 and 20, but the present invention is not limited to this. However, such a size is advantageous in that, for example, the capacity of the capacitor can be increased.
[0026]
Note that since silicidation is a reaction between silicon and a metal element, the insulating film 402 is not necessarily required from the viewpoint of forming silicide. Silicide is also formed on the conductive plugs 18 and 20 by forming a layer of cobalt directly on the lower structure 28 and performing a heat treatment. However, from the viewpoint of appropriately forming a seed layer larger than the diameter of the conductive plug, it is preferable that the insulating layer 402 for providing the openings 404 and 406 be prepared.
[0027]
In the step shown in FIG. 4C, starting from the seed layers 408 and 410, carbon nanotubes (CNT) 412 and 414 having properties as a conductor are grown. In this embodiment, a plurality of bundles of thin CNTs are formed. In the drawing, reference numerals 413 and 415 schematically show cross sections of the bundle of the CNTs 412 and 414. In this embodiment, the CNT 412 (or 414) can function as a columnar conductor, and the electrode area can be increased by increasing the height of the column. Since CNTs have excellent mechanical strength, it is possible to easily form a capacitor electrode (having a large aspect ratio) protruding from a substrate without using a conventional mold structure.
[0028]
In the step shown in FIG. 5D, a dielectric film 416 is formed around the CNTs 412 and 414 and over the insulating film 402. As the dielectric film 416, SiO 2 ₂ , Nitride film, alumina film, TaO ₅ , BST, STO, and other materials having excellent coverage characteristics can be used. Next, a conductive film 418 is formed over the dielectric film 416. The conductive film 418 serves as a counter electrode facing the electrodes 412 and 414 made of CNT. As the conductive film 418, ruthenium (Ru), ruthenium oxide (Ru) _x O _y ) It is possible to use doped silicon, titanium nitride (TiN), tungsten (W), tungsten nitride (WN), carbon (C) and other conductive materials having excellent coverage characteristics. The thickness of the dielectric film 416 can be appropriately adjusted as needed. In this embodiment, since the CNTs 412 and 414 form different memory cells, the thickness of the dielectric film 416 is small enough to secure a gap for forming an electrode (conductive film 418) between the two. Is limited.
[0029]
In the step shown in FIG. 5E, unnecessary portions of the dielectric film 416 and the conductive film 418 are removed, and SiO ₂ An insulating film 420 is formed.
[0030]
In the step shown in FIG. 5F, a contact hole reaching the conductive film 418 is formed, and a conductive plug 422 for the conductive film 418 which is an electrode of the capacitor is formed. Similarly, conductive plugs 424 for peripheral devices are formed. The plug electrodes 422 and 424 are connected to a reference potential such as, for example, ground (GND) to complete the capacitor structure.
[0031]
In the first embodiment, one of the capacitor electrodes is formed by bundling a plurality of thin CNTs to form one columnar conductor as a whole. This form is advantageous, for example, in that it is very excellent in mechanical strength. However, the electrode made of CNT is not limited to this form, and various shapes can be used.
[0032]
FIG. 6 shows a process of forming an electrode used for a capacitor according to the second embodiment of the present invention. This step is performed in place of the step shown in FIG. 4C in the manufacturing steps of the first embodiment. According to this embodiment, a group (603 or 605) of thin CNTs separated from each other forms one capacitor electrode. A schematic cross-sectional view for these CNTs is indicated by 606. This embodiment utilizes the property of CNTs in that the shapes of the CNTs are aligned one by one. According to this embodiment, since the outer surface of each CNT 602 (or 604) contributes to the electrode area, it is possible to increase the capacitance of the capacitor by increasing not only the height (length) but also the number of CNTs. Become. Instead of reducing the height, it is also possible to increase the number. However, since it is necessary to form a dielectric film and a counter electrode between CNTs separated from each other, for example, SiN or Ta is used. ₂ O ₅ It is necessary to select a material for the dielectric film and the counter electrode having excellent coverage characteristics, such as a dielectric film made of and a counter electrode made of TiN, Ru or doped silicon.
[0033]
From the viewpoint of increasing the capacitance of the capacitor, it is preferable that the periphery of the CNTs 602 and 604 is covered with the dielectric film and the counter electrode without any gap. The portion functions as a capacitor. However, if a conductive film is formed on a portion of the CNT not covered with the dielectric film, a short circuit occurs. Therefore, it is preferable that the dielectric film has better coverage characteristics than the conductive film. This applies not only to this embodiment but also to other embodiments.
[0034]
Although the CNTs formed in this embodiment have a very thin and long shape, it is difficult to form an electrode having such a shape by a conventional mold structure and a technique using lithography.
[0035]
FIG. 7 shows a step of forming an electrode used in a capacitor according to the third embodiment of the present invention. This step is performed in place of the step shown in FIG. 4C in the manufacturing steps of the first embodiment. According to this embodiment, one electrode is formed by one cylindrical CNT 702 (or 704). A schematic cross-sectional view for these CNTs is shown at 706. It is possible to use not only one CNT but also a plurality of thick CNTs, provided that the CNTs have a thickness capable of filling the inside of the CNT with the dielectric film and the conductive film. According to this embodiment, the counter electrode is provided so as to face the inner and outer wall surfaces of the CNT. For this reason, since the inner and outer wall surfaces of the CNT contribute to the electrode area, it is possible to improve the capacitance of the capacitor. The shape is the same as that of the electrode formed by using the conventional mold structure (FIG. 1C), but unlike the conventional electrode, the electrode according to the present embodiment has extremely low mechanical strength and conductivity. Are better.
[0036]
As described above, according to the embodiment of the present application, the capacitor is provided with the first electrode made of carbon nanotubes (CNT) extending in a cylindrical shape in a predetermined direction and the first electrode provided around the cylindrical wall surface of the CNT via the insulator. It has two electrodes. It is possible to form a high aspect ratio electrode having excellent mechanical strength without forming a mold for forming the electrode. It becomes possible to form an electrode structure having a high aspect ratio, which was difficult to form conventionally, and it is possible to easily cope with miniaturization of a semiconductor device. In order to form the mold structure, it is not necessary to perform steps such as forming an opening with a high aspect ratio, forming a high-coverage conductive film, and removing the mold, thereby simplifying the manufacturing process. The electrode area can be adjusted by changing the thickness, the length, the number, and the like of the CNTs, so that the degree of freedom to increase the capacitance is increased.
[0037]
According to the embodiment of the present application, a seed layer containing a predetermined transition metal element is provided at a position where the growth of carbon nanotubes starts. By providing a seed layer at a desired location, a desired CNT can be grown. Since CNT electrodes can be formed by self-alignment without the need for alignment using a mask, it is advantageous for miniaturization of a semiconductor device. In addition, when a seed layer is formed using silicide obtained by reacting silicon with a transition metal element such as iron, cobalt, nickel and titanium, desired CNTs can be formed while lowering the resistance of the electrode. Becomes possible.
[0038]
According to the embodiment of the present application, only one electrode (first electrode) of the capacitor has a structure made of CNT. However, not only one but also the other electrode (second electrode) can be formed of carbon nanotubes extending in a cylindrical shape along a predetermined direction. When a multi-walled nanotube in which a plurality of nanotubes are nested is formed, the first and second electrodes can be formed simultaneously.
[0039]
According to the embodiment of the present invention, the capacitor is used in the memory cell of the semiconductor memory device. However, the present invention is not limited to this, and the present invention can be applied to any capacitor. In a semiconductor memory device, it is necessary to secure a capacitance of a certain value or more before and after miniaturization. By adjusting the shape of the CNT (especially, by increasing the length of the CNT), the capacity of the memory cell can be easily ensured. Therefore, the capacitor structure according to the present invention is advantageous for a semiconductor memory device. Particularly, in the case of a DRAM, an improvement in the degree of integration is strongly demanded, and the structure of a capacitor greatly affects the possibility of miniaturization.
[0040]
For example, the present invention can be applied to a semiconductor memory device in which a memory cell is formed by a capacitor, such as an FeRAM, other than a DRAM. The memory cell of the FeRAM is structurally the same as the DRAM, and the memory cell can be composed of, for example, one transistor and one capacitor. However, FeRAM is significantly different from DRAM in that the dielectric film of the capacitor is made of a ferroelectric material. For this reason, FeRAM has a non-volatile function that the memory is not erased even after the power is turned off. As described above, the present invention can be widely applied to applications using structurally identical capacitors.
[0041]
It is also possible to use a transition element other than a transition metal for the seed layer. Furthermore, it is also possible to use elements other than transition elements, such as C and SiC. In short, what is necessary is just to form the seed layer which becomes the starting point of CNT. The transition metal elements include Sc, Ti, Fe, Co, Ni, Cu, Y, Zr, Nb, Pd, Ag, Cd, Hf, Ta, Ir, Pt, Au, and Hg. Includes elements having atomic numbers of 21 to 30, 39 to 48, 57 to 80, and 89 to 112 in addition to the transition metal elements.
[0042]
In the embodiment of the present invention, a carbon nanotube extending along a predetermined direction was used. Carbon nanotubes can be formed to have the flexibility (flexibility) of bending like a rubber hose. Therefore, it is not essential that the carbon nanotubes used in the present invention be completely linear, but it is not limited to a gentle curve, a spiral, or a whole or a part of the nanotube. Various shapes are possible.
[0043]
Hereinafter, means taught by the present invention will be listed.
[0044]
(Supplementary Note 1) A first electrode made of carbon nanotubes extending in a cylindrical shape along a predetermined direction;
A second electrode provided around the cylindrical wall surface of the carbon nanotube via an insulator
A capacitor comprising:
[0045]
(Supplementary Note 2) The capacitor according to Supplementary Note 1, wherein a seed layer containing a predetermined element is provided at a position that is a starting point of the growth of the carbon nanotube.
[0046]
(Supplementary note 3) The capacitor according to supplementary note 2, wherein the predetermined element is a metal element selected from at least a group consisting of iron, cobalt, nickel, and titanium.
[0047]
(Supplementary note 4) The capacitor according to supplementary note 1, wherein the first electrode is formed by a bundle of a plurality of carbon nanotubes extending along a predetermined direction.
[0048]
(Supplementary Note 5) The capacitor according to Supplementary Note 1, wherein the first electrode is made of a plurality of carbon nanotubes having a positional relationship separated from each other.
[0049]
(Supplementary Note 6) The capacitor according to supplementary note 1, wherein the second electrode is provided so as to face an inner wall surface of the tubular carbon nanotube that forms the first electrode.
[0050]
(Supplementary note 7) The capacitor according to supplementary note 1, wherein the second electrode is provided to provide a reference potential common to a plurality of capacitors.
[0051]
(Supplementary Note 8) The capacitor according to supplementary note 1, wherein the second electrode is also made of carbon nanotubes extending in a cylindrical shape along a predetermined direction.
[0052]
(Supplementary Note 9) The capacitor according to Supplementary Note 1, wherein the insulator is made of a material having coverage characteristics better than the coverage characteristics of the second electrode.
[0053]
(Supplementary Note 10) A semiconductor memory device including a memory cell formed by the capacitor according to Supplementary Note 1.
[0054]
(Supplementary Note 11) A method for creating a capacitor structure, comprising:
Forming a structure in which at least a part of the conductive layer is exposed on the semiconductor substrate,
Forming a seed layer serving as a starting point of carbon nanotube growth by introducing a predetermined transition metal element to the exposed portion of the conductive layer;
Forming a first capacitor electrode by growing a carbon nanotube having a cylindrical shape with a predetermined length from the seed layer as a starting point;
Providing an insulating layer around the cylindrical wall surface of the carbon nanotube,
Forming a second capacitor electrode by providing a conductive layer on the insulating layer;
A method of making a capacitor structure comprising:
[0055]
(Supplementary Note 12) In the method according to Supplementary Note 11, the step of forming the seed layer includes a step of introducing the predetermined transition metal element into the conductive layer containing silicon and silicidizing a surface of the conductive layer. The method characterized by the above.
[0056]
【The invention's effect】
As described above, according to the present invention, it is possible to easily cope with miniaturization of a semiconductor device. Further, even if the dimensions of the semiconductor device are miniaturized, it is possible to secure a capacitor capacity of a certain value or more.
[0057]
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view (part 1) of a main manufacturing process of a conventional DRAM.
FIG. 2 is a schematic cross-sectional view (No. 2) of main manufacturing steps of a conventional DRAM.
FIG. 3 shows an equivalent circuit for a portion 22 of a memory cell in the structure created according to FIGS. 1 and 2;
FIG. 4 is a schematic sectional view (part 1) of a main manufacturing process of the DRAM according to the first embodiment;
FIG. 5 is a schematic sectional view (part 2) of a main manufacturing step of the DRAM according to the first embodiment;
FIG. 6 is a schematic sectional view of a step of forming an electrode of a capacitor according to a second embodiment.
FIG. 7 is a schematic sectional view of a step of forming an electrode of a capacitor according to a third embodiment.
[Explanation of symbols]
12,14 gate transistor
16 bit line
18,20 conductive plug
22 Memory cell area
24 Peripheral device area
26 Field insulation film
28 Substructure
30, 32 insulating film
34,36 opening
38 Conductive Film
40, 42 capacitor electrode
44 Dielectric film
46 conductive film
48 Insulating film
50, 52 conductive plug
54 Wiring layer
402 insulating film
404,406 opening
408,410 Seed layer
412,414 CNT
416 Dielectric film
418 conductive film
420 insulating film
422,424 conductive plug
602,604 CNT
603,605 CNT group
702,704 CNT

Claims (5)

A first electrode made of carbon nanotubes extending in a cylindrical shape along a predetermined direction;
A capacitor comprising a second electrode provided around a cylindrical wall surface of the carbon nanotube via an insulator. 2. The capacitor according to claim 1, wherein a seed layer containing a predetermined element is provided at a position where the growth of the carbon nanotubes starts. 2. The capacitor according to claim 1, wherein the first electrode is formed by a bundle of a plurality of carbon nanotubes extending along a predetermined direction. 2. The capacitor according to claim 1, wherein the second electrode is provided so as to face an inner wall surface of the tubular carbon nanotube forming the first electrode. 3. A semiconductor memory device comprising a memory cell formed by the capacitor according to claim 1.

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