JP2004140790A - Automatic frequency control signal generating circuit, receiving apparatus, base station apparatus, wireless transmitting / receiving system, and frequency error detecting method in wireless communication apparatus - Google Patents

Abstract

Kind Code: A1 The present invention provides quick frequency correction control for a wide range of frequency errors in a wireless communication device.
A frequency error is detected by using a known symbol different from a data signal included in an input signal. At least two known symbols located at some distance from the input signal are extracted from the input signal. The phase shift of the two known symbols in the input signal is representative of the frequency shift of the input signal. From this phase shift, the frequency shift of the input signal is detected. A first symbol set including at least two different known symbols from the input signal and a second symbol set including at least two known symbols having a symbol interval different from the symbol interval of the first symbol set are extracted. Then, based on the extracted first and second symbol sets, a first frequency error and a second frequency error are detected, and one of the outputs of the first and second frequency error detectors is subjected to frequency error control. Select as signal.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to automatic frequency control in a wireless communication device, and more particularly to automatic frequency control applicable to a digital receiver of a received signal whose modulation scheme is phase shift keying (PSK) or quadrature amplitude modulation (QAM).
[0002]
[Prior art]
In a receiver, a frequency error occurs in a detected signal between a carrier frequency of a received signal and a frequency to be demodulated due to a frequency error of an oscillator included therein. In particular, in a digital receiver for a reception signal of a PSK or QAM modulation method, an error occurs in demodulated data due to a frequency deviation, and thus automatic frequency control for correcting the frequency deviation is required.
[0003]
For example, Patent Literature 1, Patent Literature 2, Patent Literature 3, and Patent Literature 4 disclose a frequency error control technique in a wireless communication device.
[0004]
[Patent Document 1]
JP 2000-324080 A
[Patent Document 2]
JP-A-9-246916
[Patent Document 3]
JP-A-11-308157
[Patent Document 4]
JP-A-7-297779
[0005]
[Problems to be solved by the invention]
However, in the frequency error control technique of the conventional wireless communication device, the receiving device or the transmitting device must perform a frequency error correcting operation to quickly and accurately converge to a correct frequency even if a wide range of frequency error occurs. There was nothing I could do.
[0006]
It is an object of the present invention to provide a circuit, an apparatus, a system, and a method therefor, which enable rapid frequency correction control for a wide range of frequency errors in a wireless communication apparatus.
[0007]
[Means for Solving the Problems]
In the frequency error detection and frequency control according to the present invention, a frequency error is detected using a known symbol different from the data signal included in the input signal. At least two known symbols located at some distance from the input signal are extracted from the input signal. If no frequency shift occurs in the input signal, the two known separated symbols have a constant phase relationship and no phase shift (phase rotation). If there is a phase shift between two separated known symbols, a frequency shift has occurred. Thus, the phase shift of the two known symbols in the input signal is representative of the frequency shift of the input signal. If this phase shift can be detected, the frequency shift of the input signal can be known. The frequency error can be corrected by controlling the frequency of the reference frequency source of the receiving device or the transmitting device so that the detected frequency shift becomes zero.
[0008]
If the interval between two known symbols is small, the frequency range in which an error can be detected is large and the frequency can converge to the target value at high speed, but the error correction accuracy is low. If the interval between two known symbols is wide, the frequency range in which an error can be detected is small, and the speed at which the frequency converges to the target value is low, but the error correction accuracy is high. Therefore, by combining high-speed and low-precision error detection with low-speed and high-precision error detection, high-speed and high-precision frequency correction control can be performed for a wide range of frequency errors.
[0009]
According to the present invention, a first symbol set including at least two different known symbols from the input signal and a second symbol set including at least two known symbols having a symbol interval different from the symbol interval of the first symbol set are included. Extract. Then, a frequency error of the input signal is detected based on the extracted first symbol set and second symbol set, and a first frequency error and a second frequency error are detected. Can be selected as the frequency error control signal.
[0010]
According to one embodiment of the present invention, if the frame format of the input signal includes a known pilot signal, a data portion having a predetermined symbol length, and a known synchronization word symbol portion having a predetermined symbol length, One frequency error is detected based on at least two synchronization word symbols in the synchronization word symbol portion, and a second frequency error is detected based on the pilot signal and one synchronization word symbol in the synchronization word symbol portion. Detected.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Since the method of correcting the frequency deviation is different between the base station receiver and the terminal station receiver, each will be described below.
[0012]
First, the automatic frequency control in the base station receiver will be described with reference to FIG. FIG. 3 is a block diagram showing an example of the configuration of the base station receiver.
[0013]
A signal received from the antenna is input to the reception signal input terminal 301 and input to the reception high-frequency circuit 302. The reception high-frequency unit circuit 302 converts the frequency of a received high-frequency signal in a wireless band into an intermediate frequency that can be sampled by the A / D converter 303 and supplies the converted signal to the A / D converter 303. A signal of a reference frequency is input from the oscillator 310 to the reception high-frequency section circuit 302 and used as a reference signal for frequency conversion. The A / D converter 303 samples and quantizes the frequency-converted received signal into a digital signal, and inputs the digital signal to the quadrature detector 304.
[0014]
The quadrature detector 304 converts the intermediate frequency signal input from the A / D converter 303 into a baseband signal, and inputs the signal to the low-pass filter 305. The low-pass filter 305 is a low-pass filter having a root roll-off characteristic, removes unnecessary frequency components, and inputs the result to the frequency correction unit 306. The frequency correction unit 306 corrects the frequency deviation due to the error of the oscillator 310 using the frequency correction amount input from the frequency control unit 307 and inputs the frequency deviation to the demodulation circuit 308 and the buffer 311. The demodulation circuit 308 performs demodulation using the timing information input from the timing synchronization unit 312, and outputs the demodulated data to the demodulated data output terminal 309.
[0015]
The buffer 311 uses the timing information input from the timing synchronization unit 312 to accumulate the output signals of the frequency correction unit 306 in order from the top of the frame. The timing synchronization section 312 detects the position of the synchronization word from the signal stored in the buffer 311, calculates the delay time of the received signal based on the detected position, and inputs the delay time to the demodulation section 308 and the buffer 311 as timing information. In the demodulation unit 308 and the buffer 311, the timing information input from the timing synchronization unit 312 is reflected from the processing of the next frame.
[0016]
The frequency control unit 307 detects a frequency error from the signal stored in the buffer 311 and controls the frequency correction amount of the frequency correction unit 306 using the detected error.
[0017]
Next, an automatic frequency control method in the terminal station receiver will be described with reference to FIG. FIG. 4 is a block diagram showing an example of the configuration of the terminal station receiver.
[0018]
In the block diagram of FIG. 4, the configurations of the received signal input terminal 301, the reception high-frequency circuit 302, the A / D converter 303, the quadrature detector 304, and the low-pass filter 305 are the same as those in FIG. The output of the low-pass filter 305 is input to the demodulation circuit 308 and the buffer 311. The demodulation circuit 308 performs demodulation using the timing information input from the timing synchronization unit 312, and outputs the demodulated data to the demodulated data output terminal 309.
[0019]
The buffer 311 uses the timing information input from the timing synchronization section 312 to accumulate the output signals of the low-pass filter 305 in order from the top of the frame. The timing synchronization section 312 detects the timing from the signal accumulated in the buffer 311 and inputs timing information to the demodulation circuit 308 and the buffer 311.
[0020]
The frequency control unit 307 detects a frequency error from the signal accumulated in the buffer 311 and controls the control voltage of the voltage control oscillator 403 via the adder 401 and the D / A converter 402 using the detected error. The adder 401 adds a reference value to the correction value calculated by the frequency control unit 307, and inputs the result to the D / A converter 402. The D / A converter 402 converts the digital value input from the adder 401 into an analog voltage, and inputs the analog voltage to the voltage controlled oscillator 403.
[0021]
As a result, the oscillation frequency of the voltage controlled oscillator 403 is controlled, the frequency-controlled reference signal is input to the receiving high-frequency unit circuit 302, and the receiving high-frequency unit circuit 302 corrects the frequency deviation.
[0022]
Before describing the frequency control unit 307, a frame format of a received signal will be described with reference to FIG.
[0023]
In a digital wireless communication system, a transmission signal is divided by frames at a fixed time interval and is composed of a series of many frames. FIG. 5 is a diagram showing an example of the frame format of the received signal. The ramp section (R) is a section that gradually rises from a no-signal state (ramp-up), and is usually provided with about 3 to 4 symbols. The pilot symbol (P) is a known reference symbol for demodulating the data part signal, and is provided one symbol before, after, or in the middle of the data part signal. In the example of FIG. 5, one symbol is provided at each end of the data part signal. The synchronization word (SW) is a known symbol for performing frame synchronization, and is usually provided with about 10 to 20 symbols. The guard time (G) is a section for preventing interference between frames, and this section does not include information. It is also a section for gradually lowering to a no-signal state (ramp down), and about 5 to 10 symbols are provided in a guard section including 3 to 4 symbols of ramp down.
[0024]
Next, details of the frequency control unit 307 will be described with reference to FIG.
[0025]
The signal accumulated in the buffer 311 in FIG. 3 or 4 is input to the frequency error detection unit 201 via the input terminal 101. FIG. 6 is a block diagram illustrating an example of the frequency error detection unit 201 in detail. FIG. 11 is a diagram in which a signal calculated by each block of the frequency error detection unit 201 is represented by a vector. The horizontal axis indicates the I component. The operation of the frequency error detection unit 201 will be described with reference to FIGS.
[0026]
The complex multiplier 6011 outputs the first symbol (x) of the synchronization word portion of the signal stored in the buffer 311.₁) And the symbol pattern s of the first symbol of the synchronization word₁Complex conjugate s of₁ ^*Complex product of y₁= X₁s₁ ^*And the result of the operation is input to the complex conjugate operation circuit 602. Here, complex conjugate means inverting the sign of the imaginary part. For example, a = a_r+ Ja_i(A_r, A_iIs a real number, j is an imaginary unit, and the complex conjugate of j = √ (−1) is a^*= A_r-Ja_iIt is.
[0027]
y₁Is calculated using the symbol pattern s₁For x in buffer 311₁Is performed to detect how much the phase is rotated. This operation will be described with reference to FIGS. 11A and 11C.₁The phase of θ_x1, S₁The phase of θ_s1(See FIG. 11A), y₁= X₁s₁ ^*Is s₁ ^*Is -θ_s1And y₁Phase is θ₁= Θ_x1+ (-Θ_s1) And y₁Phase θ₁Is x₁And s₁Represents the phase difference.
[0028]
The complex multiplier 6012 outputs the ninth symbol (x₂) And the symbol pattern s of the ninth symbol of the synchronization word₉Complex conjugate s of₉ ^*Complex product of y₂= X₂s₉ ^*Is calculated and input to the complex multiplier 6013.
[0029]
y₂7 (b) and 7 (d) are vector diagrams for the operation of₂Phase θ₂Is x₂And s₉Represents the phase difference.
[0030]
Complex operation circuit 602 receives y from complex multiplier 6011₁And the result of the operation is input to the complex multiplier 6013.
[0031]
The complex multiplier 6013 outputs y which is the output of the complex multiplier 6012.₂And the output y of the complex conjugate operation circuit 602₁ ^*Product of complex with d = y₂y₁ ^*Is calculated, and the calculation result is input to the phase detection circuit 603.
[0032]
The operation of d will be described with reference to the vector diagram of FIG.₂Phase θ₂, Y₁Is -θ₁And the phase of d is φ = θ₂+ (-Θ₁) And the phase φ of d is y₁And y₂Represents the phase difference of
[0033]
Above θ₁And θ₂Is θ if there is no frequency error in the received signal₁= Θ₂When there is a frequency error in the received signal, the phase of the received signal rotates by a fixed angle per unit time, and θ₁And θ₂Generates a phase difference, and the phase difference is proportional to the frequency error.
[0034]
The phase detection circuit 603 detects the phase φ of d input from the complex multiplier 6013, and inputs the phase φ to the positive / negative determination circuit 107 in FIG.
[0035]
The positive / negative determining unit 107 determines whether the phase shift amount φ detected by the frequency error detecting unit 201 is positive or negative. If φ> φ0, “+1”, if φ <−φ0, “−1”, | φ | ≦ If it is φ0, “0” is input to the integrator 108. Here, φ0 is 0 or a positive constant.
[0036]
The integrator 108 is internally provided with a memory for holding an output value, and is reset to “0” when the power is turned on. When “+1” is input from the positive / negative determining unit 107, the value ΔP is added to the value in the internal memory, and when “−1” is input, ΔP is subtracted from the value in the internal memory, and “0” is input. If this is done, the value in the internal memory is retained. Subsequently, the value of the internal memory is input to the frequency correction unit 306 of FIG. 3 or the adder 401 of FIG. 4 via the output terminal 109. Here, the value ΔP is a constant for adding to or subtracting from the internal memory, and is set according to the speed at which convergence is desired.
[0037]
The method of detecting the frequency deviation and generating the frequency control signal will be described in more detail with reference to FIG. FIGS. 12A and 12B are timing charts showing output signals of the frequency error detection unit 201, the positive / negative determination unit 107, and the integrator 108. FIG. 12A is a reception signal, and FIG. The output value of the shift amount φ, (c) is the positive / negative determination value input from the positive / negative determining unit 107 to the integrator 108, (d) is the integrated value inside the integrator 108, and (e) is the frequency correcting unit in FIG. 306 or the frequency correction amount input to the adder 401 in FIG.
[0038]
Since the calculation of the phase shift amount φ in FIG. 12B, the sign determination output of (c), and the integrated value of (d) are performed immediately after the synchronization word at the center of the frame is input, (b) to (d) ) Are output at 801-1, 801-2,... 801-N-1, 801-N, 801-N + 1.
[0039]
FIG. 12 illustrates a case where the frequency deviation is positive. Since the phase shift amount φ of (b) detected at the timing of 801-1 of frame 1 is φ> φ0, the positive / negative judgment output of (c) is +1 and + ΔP is added to the integrated value of (d). The integrated value of (d) is reflected as the frequency correction amount of (e) at the timing of 802-2 which is the head of the next frame, and the frequency of the received signal is corrected. In this frequency correction, the detected error is not corrected at one time, so that the frequency error still remains at the timing of 802-1, and the detection of the phase shift amount φ in the frame 2, the frame 3,... Repeat the correction.
[0040]
The detected value of the phase shift amount φ at the timing 801-N of the frame N is φ = φ0, the positive / negative determination output of (c) is 0, the integrated value of (d) converges, and the frequency correction of (e) is performed. The amount also converges after frame N.
[0041]
Since the frequency error detection unit 201 detects the frequency error based on the phase shift between two known symbols, the detectable range is that the absolute value | φ | of the phase shift φ between the two symbols used is 180 degrees. Less than the range.
[0042]
For example, in a radio system having a radio frequency of 60 MHz and a symbol rate of 11.25 kHz, if the allowable frequency range is ± 3 ppm, the maximum frequency deviation is ± 360 Hz (the maximum deviation is ± 3 ppm on the transmission side and ± 3 ppm on the reception side). 6 ppm = ± 360 Hz), the frame format of FIG. 5 uses two symbols of the synchronization word (SW), for example, the first symbol and the ninth symbol (interval of eight symbols), and has a maximum phase shift of 180 °, It can be detected up to 11.25 kHz × (180 degrees / 360 degrees) / 8 symbols = 703 Hz.
[0043]
The input signal contains distortion due to the distortion due to the group delay of the filter inside the reception high frequency section circuit and the influence of multipath on the propagation path. For example, assuming that the detected phase shift φ includes an error of 5 degrees due to this distortion (when the phase shift is detected by the phase shift between eight symbols), the frequency deviation is corrected to 11.25 kHz × (5 degrees / An error of (360 degrees) / 8 symbols = 19.5 Hz occurs.
[0044]
When the modulation scheme is a received signal of π / 4 shift QPSK, demodulation is performed with a phase difference from the previous symbol. In the case of the above error, the influence is almost 5 degrees / 8 symbols per symbol = 0.625 degrees. Absent.
[0045]
However, if an attempt is made to perform automatic frequency control by a method described above on a digital receiver for a received signal having a modulation scheme of PSK or QAM, an absolute phase (absolute phase and absolute amplitude in the case of QAM) is required. If the above error is present, for example, while demodulating a data portion signal of 64 symbols, the phase is rotated by 0.625 degrees × 64 symbols = 40 degrees, so that an error may occur in code determination and demodulation may not be performed.
[0046]
An embodiment of the frequency control of the present invention that solves such a problem will be described in detail below.
[0047]
FIG. 1 is a block diagram of an embodiment of a circuit for generating a frequency control signal of a main part of a digital receiver that performs automatic frequency control according to the present invention.
[0048]
In FIG. 1, the first frequency error detector 103 calculates a phase shift amount φ between two symbols (for example, the first symbol and the ninth symbol) of the synchronization word from the buffer 311 in FIG.₁Is detected and input to the terminal a of the switch 106 and the selection determination unit 105.
[0049]
Further, the second frequency error detecting section 104 determines whether the pilot symbol from the buffer 311 in FIG. 3 or 4 is equal to one symbol of the synchronization word (for example, the pilot symbol immediately after the ramp section and the first symbol of the synchronization word). The phase shift amount φ2 is detected and input to the terminal b of the switch 106.
[0050]
As the first frequency error detection unit 103, for example, the circuit shown in FIG. 6 described above can be used. The circuit shown in FIG. 7 can be used for the second frequency error detection unit 104. The circuit of FIG. 7 differs from that of FIG. 6 in that the input signal is the pilot signal and the first symbol of the synchronization word symbol part, and its operation is basically the same as that of the circuit of FIG. .
[0051]
Note that two input symbols x of the frequency error detection unit in FIGS.₁, X₂If the symbol interval is set to n symbols, it is preferable to select the value of n to be a power of 2 for easy circuit design.
[0052]
The selection determination unit 105 determines the output value φ of the first frequency error detection unit 103₁Absolute value of | φ₁| Is a preset positive integer φ_thAnd | φ₁| ≦ φ_thThen, connect the terminal b and the terminal c of the switch 106, and | φ₁|> Φ_thIf so, the switch 106 is controlled so that the terminal a and the terminal c of the switch 106 are connected.
[0053]
The switch 106 controls the output value φ of the first frequency error detector 103 according to the control of the selection controller 105.₁Or the output value φ of the second frequency error detection unit 104₂Is input to the positive / negative determination unit 107.
[0054]
The operation of the integrator 108 is the same as that of FIG.
[0055]
The preset positive constant φ_thIs the output value φ of the first frequency error detection unit 103₁And the output value φ of the second frequency error detection unit 104₂Is the threshold value for switching, and the output value φ detected by the first frequency error detection unit 103 at the limit frequency error detectable by the second frequency error detection unit 104₁Specify a value smaller than the absolute value of. That is, the frequency error is detected by the second frequency error detection unit 104 as much as possible, and if not possible, the first frequency error detection unit 103 detects the frequency error.
[0056]
For example, the data part signal in the first half of FIG. 5 is 63 symbols, and the first and ninth symbols of the synchronization word are used for the phase shift detection by the first frequency error detection unit 103 (the phase shift between 8 symbols). If the second frequency error detection unit 104 detects the phase shift amount using the pilot symbol immediately after the ramp section and the first symbol of the synchronization word (phase shift amount detection between 64 symbols), the second The limit of the frequency error that can be detected by the frequency error detection unit 104 is 11.25 kHz × (180 degrees / 360 degrees) / 64 symbols = 87.9 Hz.₁Is 180 degrees × (8 symbols / 64 symbols) = 22.5 degrees. To prevent malfunction, φ_thSpecifies a smaller value, for example, 11.25 degrees, which is a half of the value. That is, when the frequency error is 49.9 Hz or less, the second frequency error detection unit 104 performs automatic frequency control, and otherwise, the first frequency error detection unit 103 performs automatic frequency control.
[0057]
Since the frequency error is large immediately after the start of the operation, the control is performed using the first frequency error detection unit 103._thIf it converges within the range, the operation is switched to the second frequency error detection unit 104, so that high-accuracy and fast frequency control can be performed.
[0058]
Thereby, even if the input signal is distorted, φ₁Error of φ_thIf the frequency is not exceeded, frequency control is finally performed using the second frequency error detection unit 104, so that errors in frequency control due to distortion can be reduced. For example, if there is an error of 5 degrees in the phase of the input signal, the detection error in the second frequency error detection unit 104 is 11.25 kHz × (5 degrees / 360 degrees) / 64 symbols = 2.44 Hz. The amount of phase shift during demodulation of the first half data portion is 5 degrees.
[0059]
Therefore, according to the present embodiment, demodulation can be performed by applying the present invention to a digital receiver of a reception signal of the PSK or QAM modulation method that demodulates using an absolute phase (or an absolute phase and an absolute amplitude).
[0060]
As described above, when the frequency error detection value is small, the automatic frequency control is performed using the second frequency error detection unit 104 with high detection accuracy, and otherwise, the first frequency error detection with a wide detection range is performed. By performing automatic frequency control using the unit 103, frequency control can be performed for a wide range of frequency deviations, and at the same time, errors in frequency correction can be reduced.
[0061]
Next, another embodiment of the frequency error detection unit described above with reference to FIGS. 6 and 7 will be described with reference to FIGS. 8, 9, 10, and 13. FIG.
[0062]
FIG. 8 is an example of an internal configuration of the first frequency error detection unit 103 in FIG. Since the internal configuration and operation of the block 103 in FIG. 8 are the same as those in FIG. 6, the description thereof is omitted. 8 is different from FIG. 6 in that a switch unit 604 for selecting a synchronization word symbol is provided between the buffer 311 and the input of the frequency error detection unit 103. The switch section 604 can select any two synchronization words in the synchronization word symbol section. Therefore, two input synchronization word symbols x₁, X₂By selecting the symbol interval arbitrarily by the switch unit 604, the detection accuracy and frequency correction speed of the first frequency error detection unit 103 can be set to appropriate values desired by the user.
[0063]
FIG. 9 is an example of an internal configuration of the second frequency error detection unit 104 in FIG. The internal configuration and operation of block 103 in FIG. 9 are the same as those in FIG. 9 differs from FIG. 7 in that a switch unit 605 for selecting a synchronization word symbol is provided between the buffer 311 and the input of the frequency error detection unit 104. The switch section 605 can select any two synchronization words in the synchronization word symbol section. Therefore, two input synchronization word symbols x₁, X₂By selecting the symbol interval arbitrarily by the switch unit 605, the detection accuracy and the frequency correction speed of the second frequency error detection unit 104 can be set to appropriate values desired by the user.
[0064]
Next, FIGS. 10 and 13 show an example in which both the first frequency error detection unit 103 and the second frequency error detection unit 104 in FIG. 1 are realized by one frequency error detection unit 203. FIG. 10 shows an example of the internal configuration of the frequency error detection section 203. Since the internal configuration and operation of the block 203 in FIG. 10 are the same as those in FIG. 6, the description thereof will be omitted. 10 differs from FIG. 6 in that a switch unit 606 for selecting a pilot signal and a first symbol of a synchronous word symbol portion is provided between the buffer 311 and the input of the frequency error detection unit 203. . When the switch section 606 selects the first sync word symbol of the sync word symbol section, two input sync word symbols x₁, X₂Are the same as in FIG. 6, and the same output as that of the first frequency error detection unit 103 is obtained. When a pilot signal is selected by the switch unit 606, two input synchronization word symbols x₁, X₂Are the same as those in FIG. 7, and the same output as that of the second frequency error detection unit 104 is obtained. Therefore, the two frequency error signals φ₁And φ₂Will be obtained.
[0065]
FIG. 13 shows an embodiment of a frequency control signal generator using the frequency error detecting section 203. In FIG. 13, parts other than the switch unit 606 and the frequency error detection unit 203 are the same as those in the configuration of FIG.
[0066]
Next, an embodiment of a base station radio and a terminal station radio according to the present invention will be described with reference to FIGS.
[0067]
FIG. 14 is a block diagram showing an example of the configuration of the base station radio. The antenna 901 is shared by the transmission / reception duplexer 902 for transmission and reception operations. A received signal received by the antenna 901 is input to the reception high-frequency unit circuit 302 via the duplexer 902. The reception high-frequency unit circuit 302 frequency-converts the received radio-frequency high-frequency signal into an intermediate frequency that can be sampled by the A / D converter 303, and converts the frequency-converted signal into an A / D converter. At 303, it is converted into a digital signal. A signal of a reference frequency is input from the oscillator 310 to the reception high-frequency circuit 302 and used as a reference signal for frequency conversion. The A / D converter 303 samples and quantizes the frequency-converted reception signal and inputs the digital signal to the reception demodulation unit 904. Reception demodulation section 904 demodulates a signal input from A / D converter 303 and outputs demodulated data to demodulated data output terminal 309.
[0068]
The transmission modulation section 905 generates a baseband signal based on the data input from the modulation data input terminal 909, converts the baseband signal into an analog signal with the D / A converter 906, inputs the analog signal to the transmission high-frequency section circuit 907, and Converts the frequency of the baseband signal supplied from the D / A converter 906 into a signal of a radio frequency band, and supplies the signal to the power amplifier 908. The power amplifier 908 amplifies the power of the signal input from the transmission high-frequency circuit 907 and outputs the amplified signal to the antenna 901 via the duplexer 902.
[0069]
The signal output from the oscillator 310 is input to the high-frequency receiving circuit 302 and also to the high-frequency transmitting circuit 907.
[0070]
Note that the reception demodulation unit 904 and the transmission modulation unit 905 are processed by a DSP (Digital Signal Processor) 903 and software that controls the DSP.
[0071]
FIG. 15 is a block diagram showing an example of the configuration of the terminal station radio, which is the same as the configuration of the base station in FIG. 14 except for the voltage controlled oscillator 403 and the D / A converter 402. The terminal station radio of FIG. 15 detects the frequency error of the received signal inside the reception demodulation section 1001 and controls the voltage controlled oscillator 403 via the D / A converter 402 so as to reduce the error. Since the output signal of the voltage controlled oscillator 403 is supplied to the reception high-frequency unit circuit 302 and the transmission high-frequency unit circuit 907, in the terminal station radio, the frequency of the transmission signal follows the frequency detected from the reception signal from the base station. Controlled.
[0072]
【The invention's effect】
According to the present invention, it is possible to obtain a circuit, a device, a system, and a method therefor that can control frequency correction quickly for a wide range of frequency errors in a wireless communication device.
[Brief description of the drawings]
FIG. 1 is a block diagram of an embodiment of a circuit for generating a frequency control signal in a main part of a digital receiver for performing automatic frequency control according to the present invention.
FIG. 2 is a block diagram of an example of a circuit that generates a frequency control signal.
FIG. 3 is a block diagram illustrating an example of a configuration of a receiver of a base station in a wireless communication system to which the present invention is applied.
FIG. 4 is a block diagram illustrating an example of a configuration of a receiver of a terminal station in a wireless communication system to which the present invention is applied.
FIG. 5 is a diagram illustrating an example of a frame format of a signal to be transmitted.
FIG. 6 is a block diagram of an embodiment of a frequency error detection circuit according to the present invention.
FIG. 7 is a block diagram of an embodiment of a frequency error detection circuit according to the present invention.
FIG. 8 is a block diagram of an embodiment of a frequency error detection circuit according to the present invention.
FIG. 9 is a block diagram of an embodiment of a frequency error detection circuit according to the present invention.
FIG. 10 is a block diagram of an embodiment of a frequency error detection circuit according to the present invention.
FIG. 11 is an IQ coordinate diagram for explaining a frequency error detection method according to the present invention.
FIG. 12 is a diagram showing a signal timing chart for explaining a frequency error detection method according to the present invention.
FIG. 13 is a block diagram of another embodiment of a circuit for generating a frequency control signal provided with a frequency error detection circuit according to the present invention.
FIG. 14 is a block diagram of an embodiment of a base station radio apparatus to which the present invention is applied.
FIG. 15 is a block diagram of an embodiment of a terminal station radio apparatus to which the present invention is applied.
[Explanation of symbols]
101: input terminal, 103: first frequency error detecting unit, 104: second frequency error detecting unit, 105: selection determining unit, 106: switch, 107: positive / negative determining unit, 108: integrator, 109: output terminal , 201: frequency error detection unit, 301: reception signal input terminal, 302: reception high-frequency unit circuit, 303: A / D converter, 304: quadrature detector, 305: low-pass filter, 306: frequency correction unit, 307: frequency Control unit, 308: demodulation circuit, 309: demodulated data output terminal, 310: oscillator, 311: buffer, 312: timing synchronization unit, 401: adder, 402: D / A converter, 403: voltage controlled oscillator, 602: Complex conjugate operation circuit, 603: phase detection circuit, 604, 605, 606: switch unit, 901: antenna, 902: duplexer, 903: DPS, 04: reception demodulation unit, 905: transmission modulation unit, 906: D / A converter, 907: transmission high-frequency unit circuit, 908: power amplifier, 909: modulation data input terminal, 1001: reception demodulation unit, 6011, 6012, 6013 : Complex multiplier.

Claims (6)

An automatic frequency control signal generation circuit,
A first frequency error detecting unit that extracts at least two different known symbols from the input signal as a first symbol set, and detects and outputs a frequency error of the input signal based on the extracted first symbol set; When,
At least two known symbols having a symbol interval different from the symbol interval of the first symbol set are extracted as a second symbol set from the input signals, and the input signal of the input signal is extracted based on the extracted second symbol set. A second frequency error detector that detects and outputs a frequency error;
A determination unit that determines which output of the first and second frequency error detection units is to be selected;
A control signal unit for generating a control signal for controlling a frequency of the input signal based on an output of the frequency error detection unit selected by the determination unit. A receiving device,
An RF receiving unit comprising the automatic frequency control signal generating circuit according to claim 1, further comprising: converting a received signal into a frequency; converting a frequency-converted received signal into a digital signal;
An oscillating unit that outputs a reference frequency signal for frequency conversion to the RF receiving unit;
A quadrature detection unit that converts the digitally converted received signal into a baseband signal and outputs the converted signal;
A filter that removes and outputs unnecessary frequency components of the output baseband signal,
A frequency correction unit that corrects and outputs an error between the frequency of the baseband signal output from the filter and the frequency of the reference frequency signal based on the control signal from the automatic frequency control signal generation circuit,
A demodulation unit that demodulates and outputs the baseband signal output from the frequency correction unit,
A buffer for holding the output of the frequency correction unit,
The automatic frequency control signal generating circuit extracts the first and second symbol sets using the signal held in the buffer as the input signal, generates the control signal based on the symbol set, and A receiving device for providing a signal to the frequency correction unit. A wireless base station device,
A receiving device according to claim 2,
A radio transmission unit for converting a signal for transmission in a baseband converted into an analog signal into a radio frequency band based on a reference frequency signal of the oscillation unit. A wireless transmitting and receiving system,
A wireless base station device according to claim 3,
At least one mobile radio transmitting / receiving device, wherein the at least one mobile radio transmitting / receiving device receives a transmission signal from the radio base station and performs the mobile radio transmission / reception based on a reference frequency signal extracted from the received signal. A wireless transmission / reception system for controlling a reference frequency signal in a device. A frequency error detection method,
(A) extracting at least two different known symbols from the input signal as a first symbol set;
(B) calculating and outputting a product of one symbol of the first symbol set and a complex conjugate of the symbol;
(C) outputting the output of step (b) after inverting the phase;
(D) calculating and outputting a product of another symbol of the first symbol set and a complex conjugate of the symbol;
(E) complexly multiplying the output of step (c) and the output of step d) and outputting the result;
(E) detecting the phase of the output of step (f) and outputting the detected phase as a first frequency error of the input signal. An automatic frequency control signal generation circuit,
At least two different known symbols from the input signal are extracted as a first symbol set, and at least two known symbols having a symbol interval different from the symbol interval of the first symbol set are extracted from the input signal. A frequency error detection unit that extracts as a second symbol set, detects and outputs first and second frequency errors of the input signal based on the extracted first and second symbol sets,
A determining unit that determines which one of the first and second frequency errors is to be selected according to the error value;
A control signal section for generating a control signal for controlling the frequency of the input signal based on the first or second frequency error selected by the determination section. .

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