JP2004134573A - Semiconductor device and its manufacturing process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a process for manufacturing a leadless surface mount resin package IC. <P>SOLUTION: After an adhesive tape 13 is bonded to the lower surface of a conductive substrate 11, the conductive substrate 11 is patterned to prepare a multi-terminal group frame 14 where a plurality of terminal groups 16, each having a chip mount part 17 and a plurality of terminals 18, are arranged in a frame 15. A chip 1 is bonded to the chip mount part 17 of each terminal group 16 and a wire 5 is bonded between the electrode pad 3 of the chip 1 and the terminal 18. The internal space of the frame 15 on the adhesive tape 13 is filled with sealing resin to mold a resin sealed body 21. The adhesive tape 13 is then stripped off from the resin sealed body 21 to expose the chip mount part 17 and the terminal 18. Subsequently, the resin sealed body 21 is cut into individual pieces. Since etching can be eliminated, the required man-hours can be reduced. Since the force to strip the adhesive tape is small, the terminal can be prevented from being stripped from the resin sealed body by the adhesive tape. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a technology for manufacturing a semiconductor device, and more particularly to a technology that is effective when used for manufacturing a semiconductor integrated circuit device (hereinafter, referred to as an IC) having a leadless surface-mount type resin-sealed package.
[0002]
[Prior art]
As an IC having a leadless surface-mount type resin-sealed package, resin protrusions are integrally provided on a mounting surface, which is one main surface of the resin-sealed body, and terminals formed of a metal film are provided on the resin protrusions. There is a method of manufacturing an IC having this leadless surface-mount type resin-sealed package, in which a concave portion is previously immersed in a lead frame, and a metal film is formed in the concave portion. And a step of selectively attaching (see, for example, Patent Document 1).
[0003]
[Patent Document 1]
JP-A-11-150143
[Problems to be solved by the invention]
In the above-described method for manufacturing an IC having a leadless surface mount type resin-sealed package, in order to separate the resin-sealed body in which the resin protrusion having the metal film is projected from the lead frame, the lead frame is etched. A method of dissolving and removing or a method of mechanically peeling the resin sealing body from the lead frame is adopted. However, in the separation method of removing the lead frame by etching, there is a problem that the time required for the step of separating the resin sealing body from the lead frame increases because an etching process is required. Further, in the method of mechanically peeling the resin sealing body from the lead frame, there is a problem that the external terminal is dropped because the metal film remains on the lead frame.
[0005]
SUMMARY OF THE INVENTION An object of the present invention is to provide a technique for manufacturing a semiconductor device having a leadless surface-mount type resin-sealed package capable of eliminating the need for an etching process and preventing the loss of external terminals.
[0006]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0007]
[Means for Solving the Problems]
The outline of a typical invention disclosed in the present application will be described as follows.
[0008]
That is, the semiconductor device includes a semiconductor chip, a resin sealing body obtained by resin-sealing the semiconductor chip, and external terminals that are exposed flush on one main surface of the resin sealing body. And the external terminals are electrically connected inside the resin sealing body.
[0009]
This semiconductor device can be manufactured by the following manufacturing method.
That is, a semiconductor chip preparation step in which a semiconductor chip having a plurality of electrode pads on one main surface is prepared,
By selectively patterning the conductive substrate after adhering a tape to one main surface of the conductive substrate, a chip mounting portion and a plurality of terminal groups having a plurality of terminals are arranged in an internal space of the frame. A terminal group frame preparing step in which a terminal group frame is prepared;
A chip bonding step in which the semiconductor chip is bonded to each of the chip mount portions in the plurality of terminal groups of the multi-terminal group frame;
A wire bonding step in which each wire is bridged between each electrode pad and each terminal of the semiconductor chip,
A resin sealing body molding step in which a sealing resin is filled into the internal space of the frame above the tape to form a resin sealing body,
A tape removing step in which the tape is removed from the resin sealing body,
A method for manufacturing a semiconductor device, comprising:
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
[0011]
As shown in FIG. 1, a method of manufacturing an IC including a leadless surface-mount type resin-sealed package according to the present embodiment (hereinafter, referred to as a leadless surface-mount type IC) includes a chip preparing step K1. A multi-terminal group frame preparation step K2, a chip bonding step K3, a wire bonding step K4, a resin sealing body forming step K5, a tape removing step K6, a solder dipping step K7, and a resin sealing body cutting step K8. Hereinafter, a method of manufacturing the leadless surface mount IC according to the present embodiment will be described in the order of each process. By this description, the structure of the leadless surface mount IC according to the present embodiment will be clarified.
[0012]
The chip preparation step K1 shown in FIG. 1 is constituted by a so-called preceding step of the IC manufacturing method. That is, in a so-called pre-process in an IC manufacturing method, an integrated circuit including a semiconductor element such as a system LSI is manufactured for each chip portion defined in a matrix shape in a state of a semiconductor wafer. The semiconductor wafer in which the integrated circuit is formed is divided into chips shown in FIG. 2 in a dicing process. The chip 1 according to the present embodiment is formed in a square flat plate shape, and a protection film 2 is applied to the main surface of the chip 1 on the active area side, and the protection film 2 is electrically connected to the active area. The electrode pads (hereinafter referred to as “pads”) 3 connected to are exposed on two sides of each of the four sides.
[0013]
As shown in FIG. 1, the multi-terminal group frame preparing step K2 includes a tape bonding step K2a and a patterning step K2b. In the tape bonding step K2a, the conductive substrate 11 and the adhesive tape 13 are prepared. As shown in FIG. 3, the conductive substrate 11 is made of a material having good conductivity such as a copper-based material (copper or copper alloy) and is formed in a rectangular flat plate shape. A plurality of feed holes 12 are opened at predetermined intervals at the side end. The adhesive tape 13 is formed by applying an epoxy-based adhesive to a polyamide-based substrate, and the entirety of the adhesive tape 13 with the feed holes 12 left on one main surface (hereinafter, referred to as a lower surface) of the conductive substrate 11. Adhesively bonded.
[0014]
In the patterning step K2b, the multi-terminal group frame 14 shown in FIG. 4 is manufactured by selectively forming the pattern shown in FIG. 5 on the conductive substrate 11 by lithography and etching. The multi-terminal group frame 14 includes a frame 15 formed in a rectangular frame shape, and a plurality of terminal groups 16 arranged in a matrix inside the frame 15. In the present embodiment, the terminal group 16 Are arranged on the multi-terminal group frame 14 in seven columns in the horizontal direction and three rows in the vertical direction. The thickness of the frame 15 is set to be larger than the thickness of the terminal group 16. As shown in FIG. 5, the terminal group 16 includes a chip mount portion 17 disposed at the center and a plurality of terminals 18 disposed outside the chip mount portion 17. The portion 17 and the plurality of terminals 18 are positioned and held by being adhered to the adhesive tape 13. The chip mount portion 17 is formed in a square plate shape slightly larger than the chip 1, and is arranged concentrically with the terminal group 16. The plurality of terminals 18 are each formed in a square plate shape having an area that allows wire bonding to be described later, and are equally spaced circumferentially on two large and small rows of square frame lines outside the chip mount portion 17. Are arranged.
[0015]
In the chip bonding step K3 shown in FIG. 1, the chip 1 shown in FIG. 2 is mounted on the chip mount 17 in the terminal group 16 of the multi-terminal group frame 14 shown in FIG. Chip bonding. That is, the chip 1 is concentrically arranged on the chip mount portion 17 of the terminal group 16 and bonded by the bonding portion 19 made of silver paste, and thereafter, is mechanically and electrically connected by being subjected to a cure bake process. .
[0016]
In the wire bonding step K4 shown in FIG. 1, a bonding wire (not shown) such as an ultrasonic thermocompression bonding wire bonding device is used between the bonding wire 5 and each pad 3 of the chip 1 and each terminal 18. By being used, both ends are respectively bonded and bridged as shown in FIG. As a result, the integrated circuit formed in the chip 1 is brought out to the outside via the pad 3, the bonding wire 5 and the terminal 18. In addition, in the chip bonding step K3 and the wire bonding step K4, the multi-terminal group frame 14 is fed in the lateral direction by pitch using the feed holes 12.
[0017]
In the resin sealing body forming step K5 shown in FIG. 1, a resin sealing body 21 for entirely resin-sealing the multi-terminal group frame 14 is attached to the assembly 20 referred to in FIG. 7 after wire bonding. Formed by potting as shown in FIG. That is, after a sealing resin such as an epoxy resin is filled into the internal space of the frame 15 of the multi-terminal group frame 14 by a screen printing method, a coating method, or the like, the resin sealing body 21 is formed by a curing and baking process. . At the time of molding the resin sealing body 21, the adhesive tape 13 is adhered to the lower surface of the multi-terminal group frame 14, so that the potted sealing resin fills the internal space of the frame 15. Further, since the thickness of the frame 15 is set to be larger than the entire height of the wire 5, the frame 15 serves as a dam for closing the potted sealing resin. The chip 1 and the group of terminals 18 including the group can be securely sealed with resin (non-hermetic sealing). In the molded product 22 shown in FIG. 8, the resin sealing body 21 is molded so as to collectively seal all the terminal groups 16 in the multi-terminal group frame 14 with the resin. That is, the chip 1, the terminal 18 group, and the wire 5 group in all the terminal groups 16 are collectively resin-sealed inside the resin sealing body 21.
[0018]
In the tape removing step K6 shown in FIG. 1, the adhesive tape 13 is peeled off from the lower surface of the multi-terminal group frame 14 on which the resin sealing body 21 is formed, and is removed as shown in FIG. . At this time, when the adhesive force of the adhesive of the adhesive tape 13 is weakened by irradiating the adhesive tape 13 with ultraviolet light, the adhesive tape 13 peels off the chip mount portion 17 and the terminal 18 from the lower surface of the resin sealing body 21. Therefore, it can be easily peeled off from the lower surface of the resin sealing body 21. Since the chip mount portion 17 and the terminal 18 group are adhered to the adhesive tape 13, the adhesive surface of the chip mount portion 17 and the terminal 18 is in a state of being exposed flush with one main surface of the resin sealing body 21. .
[0019]
In the solder dip step K7 shown in FIG. 1, as shown in FIG. 10, the solder dip coating 23 flows on the exposed surface of the chip mount portion 17 and the terminal 18 group on the mounting surface of the resin sealing body 21. It is applied by a solder dipping process using a soldering device (not shown) or the like.
[0020]
In the multi-terminal group frame and resin sealing body cutting step K8 shown in FIG. 1, as shown in FIG. 11, the molded product 24 on which the solder dip coating 23 referred to in FIG. It is cut into a leadless surface mount IC 25 shown in FIG. 12 by a diamond cutter of a dicing device.
[0021]
As described above, the leadless surface mount IC 25 shown in FIG. 12 is manufactured. That is, as shown in FIG. 12, the chip 1 is bonded on the chip mount section 17 by the bonding section 19, and the wire 5 is provided between each pad 3 of the chip 1 and each terminal 18. Each is bridged. The chip 1, the group of terminals 18, and the group of wires 5 are resin-sealed by the resin sealing body 21, and the lower surface of the chip mount portion 17 and the lower surface of the terminal 18 are the main surfaces of the resin sealing body 21 on the side opposite to the chip 1. At the same time.
[0022]
According to the embodiment described above, the following effects can be obtained.
[0023]
1) A multi-terminal in which a tape is adhered to one main surface of the conductive substrate and then the conductive substrate is selectively patterned to arrange a chip mount portion and a plurality of terminal groups having a plurality of terminals in the internal space of the frame. Prepare the group frame, bond the chip to each of the chip mounts in the plurality of terminal groups of the multi-terminal group frame, wire bond each wire between each electrode pad and each terminal of the chip, and The interior space of the frame is filled with a sealing resin to form a resin sealing body, and then the tape is removed from the resin sealing body to manufacture a leadless surface mount IC, so that etching can be performed. Since a leadless surface-mount IC can be manufactured without using the same, the manufacturing cost and manufacturing period of the leadless surface-mount IC can be significantly reduced.
[0024]
2) Also, by suppressing the peeling force when removing the tape that has positioned and held the terminal group from the resin sealing body, it is possible to prevent the terminal from falling off from the resin sealing body, so that the leads can be prevented. It is possible to reduce the production yield and the like of a surface-less IC without wires.
[0025]
3) The resin-sealed body is molded into a multi-terminal group frame so that a plurality of terminal groups are collectively resin-sealed, and the multi-terminal group frame and the resin-sealed body are cut for each terminal group and individually leadless. By manufacturing a surface mount IC, productivity can be increased as compared with a case where a resin-sealed body is molded for each individual leadless surface mount IC. It can be greatly reduced.
[0026]
4) By exposing the chip mount portion to the main surface on the opposite side to the chip on one main surface of the resin sealing body, heat generated by the semiconductor chip can be directly emitted to the outside of the resin sealing body, so that heat dissipation performance Can be greatly increased.
[0027]
5) By molding a resin encapsulant for encapsulating the chip and the terminal group in a lump by potting the encapsulation resin into the internal space of the frame of the multi-terminal group frame, without using a transfer molding apparatus. As a result, productivity can be increased and manufacturing costs can be reduced.
[0028]
Although the invention made by the present inventor has been specifically described based on the embodiment, the present invention is not limited to the above embodiment, and various changes can be made without departing from the gist of the invention. Needless to say.
[0029]
For example, the resin sealing body is not limited to being formed by potting, but may be formed by using a transfer molding apparatus.
[0030]
Not only the solder dip film is applied to the exposed surface of the terminal but also a solder bump may be protruded.
[0031]
In the above description, mainly the case where the invention made by the inventor is applied to a system LSI which is a field of application as a background has been mainly described, but the present invention is not limited to this, and DRAM, SRAM and other ICs And semiconductor devices such as transistors and arrays.
[0032]
【The invention's effect】
The effect obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows.
[0033]
A multi-terminal group frame in which a tape is adhered to one main surface of the conductive substrate and then the conductive substrate is selectively patterned to arrange a plurality of terminal groups having a chip mount portion and a plurality of terminals in an internal space of the frame. The chip is bonded to each of the chip mounting portions of the plurality of terminal groups of the multi-terminal group frame, each wire is wire-bonded between each electrode pad of the chip and each terminal, and the frame on the tape is mounted. Filling the inner space with a sealing resin to form a resin sealing body, and then removing the tape from the resin sealing body to manufacture a leadless surface mount semiconductor device without using etching. Since it is possible to manufacture leadless surface-mount semiconductor devices in a short time, it is possible to reduce the manufacturing cost and production period of leadless surface-mount semiconductor devices. Kill.
[0034]
Also, by suppressing the peeling force when removing the tape that has positioned and held the terminal group from the resin sealing body, it is possible to prevent the terminal from falling off from the resin sealing body. The manufacturing yield of the mounted semiconductor device can be reduced.
[Brief description of the drawings]
FIG. 1 is a process chart showing a method for manufacturing a leadless surface-mounted IC according to an embodiment of the present invention.
FIGS. 2A and 2B show a chip used therein, wherein FIG. 2A is a plan view, and FIG. 2B is a cross-sectional view taken along line bb of FIG.
3A and 3B show a state after a tape bonding step in a multi-terminal group frame preparing step, wherein FIG. 3A is a plan view and FIG. 3B is a cross-sectional view taken along line bb of FIG.
4A and 4B also show a state after a patterning step in a multi-terminal group frame preparation step, wherein FIG. 4A is a partially omitted plan view, and FIG. 4B is a cross-sectional view taken along line bb of FIG.
5A and 5B show a terminal group, wherein FIG. 5A is a plan view, and FIG. 5B is a cross-sectional view taken along line bb of FIG.
6A and 6B show a state after the chip bonding step, in which FIG. 6A is a partially omitted plan view, and FIG. 6B is a cross-sectional view taken along line bb of FIG.
7A and 7B show a terminal group after a wire bonding step, wherein FIG. 7A is a plan view, and FIG. 7B is a cross-sectional view taken along line bb of FIG.
8A and 8B show a state after a resin sealing body forming step, in which FIG. 8A is a partially omitted plan view, and FIG. 8B is a cross-sectional view taken along line bb of FIG.
9A and 9B show a state after the tape removing step, in which FIG. 9A is a partially omitted bottom view, and FIG. 9B is a front sectional view taken along the line bb of FIG. 9A.
FIGS. 10A and 10B show a terminal group after a solder dip process, wherein FIG. 10A is a plan view and FIG. 10B is a front sectional view taken along line bb of FIG.
11A and 11B show a state after the resin sealing body cutting step, in which FIG. 11A is a plan view, and FIG. 11B is a front sectional view taken along line bb of FIG.
12A and 12B show a leadless surface mount IC according to an embodiment of the present invention, wherein FIG. 12A is a plan sectional view, FIG. 12B is a front sectional view, and FIG. 12C is a bottom view.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... chip, 2 ... protective film, 3 ... pad (electrode pad), 4 ... insulating tape (insulating layer), 5 ... bonding wire, 11 ... conductive substrate, 12 ... feed hole, 13 ... adhesive tape, 14 ... multi Terminal group frame, 15: Frame, 16: Terminal group, 17: Chip mount part, 18: Terminal, 19: Bonding part, 20: Assembly, 21: Resin sealing body, 22: Molded product, 23: Solder dip coating Reference numeral 24 denotes a molded product to which a solder dip coating is applied, and 25 denotes a leadless surface mount IC (semiconductor device).

Claims (5)

A semiconductor chip, a resin-sealed body obtained by sealing the semiconductor chip with a resin, and a terminal that is flush with one main surface of the resin-sealed body, wherein the semiconductor chip and the terminal are formed of the resin A semiconductor device electrically connected inside a sealing body. 2. The semiconductor device according to claim 1, wherein a solder dip coating is applied to an exposed surface of the terminal from the resin sealing body. A semiconductor chip preparation step in which a semiconductor chip having a plurality of electrode pads on one main surface is prepared,
By selectively patterning the conductive substrate after adhering a tape to one main surface of the conductive substrate, a chip mounting portion and a plurality of terminal groups having a plurality of terminals are arranged in an internal space of the frame. A terminal group frame preparing step in which a terminal group frame is prepared;
A chip bonding step in which the semiconductor chip is bonded to each of the chip mount portions in the plurality of terminal groups of the multi-terminal group frame;
A wire bonding step in which each wire is bridged between each electrode pad and each terminal of the semiconductor chip,
A resin sealing body molding step in which a sealing resin is filled into the internal space of the frame above the tape to form a resin sealing body,
A tape removing step in which the tape is removed from the resin sealing body,
A method for manufacturing a semiconductor device, comprising: 4. The method according to claim 3, further comprising a cutting step of cutting the multi-terminal group frame and the resin sealing body for each of the terminal groups to manufacture individual semiconductor devices. The method for manufacturing a semiconductor device according to claim 3, wherein the resin sealing body is molded by a potting molding method.

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