JP2004118235A - Data processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the responsiveness, by specifying the interrupt factor of a functional block used with higher priority, without performing tree-structure tracking processing for the interrupt factor and by speeding up to shorten the turnaround time of interrupt processing. <P>SOLUTION: A data processor 100, having a plurality of function blocks for executing a data processing function and an interrupt control block 140 for outputting an interrupt request signal, by inputting and collecting a plurality of interrupt signals output from the function blocks is provided with a priority setting register for setting whether priority interrupts are needed for each functional block; and each functional block outputs priority interrupt signals, including block codes specified the function blocks other than the interrupt signals and inputs the priority interrupt signals to the control block 140, when the priority setting register is set as the priority interrupts are needed. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a data processing device in which the time required for interrupt processing is shortened to improve responsiveness.
[0002]
[Prior art]
2. Description of the Related Art Data processing devices are used to control peripheral devices such as personal computers. In a multi-function data processing device having a plurality of functions, when an interrupt request signal is notified to a connected processor, an interrupt request of each function block that controls execution of a plurality of mounted functions is provided. In many cases, the signals are aggregated by an interrupt control block, and then a single interrupt request signal is output. In the system including the multi-function data processing device and the processor, in order to identify the interrupt factor, the data stored in the factor register in the interrupt control block is read to identify the functional block, and further, the identified functional block The data stored in the interrupt factor register is read out to perform a tree structure tracking process of the interrupt factor to further specify the sub-block, and the tree structure tracking process finally specifies the interrupt factor.
Conventionally, with regard to the acceleration of the interrupt processing of a multifunction device, a technology that speeds up a cycle in which software determines a cause by transmitting interrupt factor data of a functional block in which a device generates an interrupt request to a processor side. (For example, see Patent Document 1).
[0003]
[Patent Document 1]
JP 2001-209548 A (page 1)
[0004]
[Problems to be solved by the invention]
However, the depth of the tree structure of the interrupt factor (the number of layers of the interrupt factor) differs depending on the function block. The deeper the depth (the greater the number of layers), the longer the access time required to specify the interrupt factor, The time required to specify the interrupt factor is increased.
[0005]
SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and an interrupt factor of a functional block to be used with priority among a plurality of functional blocks is determined by a tree structure tracking process of the interrupt factor. It is an object of the present invention to specify the data without interrupt, shorten the time required for the interrupt processing, increase the speed, and improve the responsiveness.
[0006]
[Means for Solving the Problems]
The present invention achieves the above object by inputting and aggregating a plurality of functional blocks for executing a data processing function and a plurality of interrupt signals output from the respective functional blocks to output an interrupt request signal. A data processing device having an interrupt control block to perform, wherein each of the functional blocks is provided with a priority setting unit for setting whether or not the priority is required, and each of the functional blocks is configured such that the priority setting unit is set to the priority required. A data processing device which outputs a priority interrupt signal including a block code specifying the functional block separately from the interrupt signal and inputs the signal to the interrupt control block.
This data processing device includes means for storing the priority of each functional block, and means for storing a block code included in the priority interrupt signal in accordance with the priority stored in the means. It may be provided in the control block.
The interrupt control block may be provided with a storage unit to which an area unique to each function block according to each priority is assigned for each function block.
[0007]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
First, a data processing device 200 related to a data processing device according to the present invention will be described with reference to FIGS.
The data processing device 200 is a data processing device for which priority setting is not required, has a plurality of input / output interfaces, and has a plurality of input / output control blocks and direct memory access control (DMAC) blocks for which priority is not set. Built-in function blocks. That is, the data processing device 200 includes a USB (Universal serial bus) function block 210, a plurality of input / output function blocks (in FIG. 8, a first input / output function block 220, an n-th input It has an output function block 230) and an interrupt control block 240, and is connected to the processor 150 via the processor bus 151.
[0008]
As shown in FIG. 9, the USB function block 210 includes a plurality of sub-blocks, and each sub-block has an individual function. Each sub-block has a USB transmission DMAC block 211, a USB reception DMAC block 212, a USB input / output control block 213, and a factor register 210a, and the USB input / output control block 213 includes a first endpoint block 215, A second endpoint block 216. The USB transmission DMAC block 211, the USB reception DMAC block 212, the USB input / output control block 213, and the first and second endpoint blocks 215 and 216 have factor registers 211a, 212a, 213a, 215a and 216a, respectively. I have. Since the USB has a plurality of functional divisions called endpoints, the USB input / output control block 213 includes first and second endpoint blocks 215 and 216.
The first and n-th input / output function blocks 220 and 230 and the interrupt control block 240 have factor registers 220a, 230a and 240a, respectively.
[0009]
In the data processing device 200, each functional block generates an interrupt signal according to an internal state. Then, the interrupt signal of each functional block (for example, USB functional block 210) is input to the upper functional block and finally input to the interrupt control block 240 to be aggregated. The request signal a is output to the processor 150. In the data processing device 200, no priority is set for each of the built-in functional blocks, and therefore, any of the output interrupt signals has no priority. Therefore, the data processing device 200 performs a tree-structured interrupt factor tracking process to determine the interrupt factor. This is performed as in the flowchart shown in FIG.
Here, in the case of each function block, for example, the USB function block 210, the connection path of the output interrupt signal is as shown in FIG. In FIG. 9, the data path and blocks and signals for controlling the data path are omitted. In the following description, it is assumed that a reception completion interrupt occurs in the first endpoint block 215 of the USB function block 210. In FIG. 10, steps are abbreviated as S.
[0010]
First, when a reception completion interrupt occurs, the data processing device 200 outputs an interruption request signal a to notify the processor 150 of the occurrence of the reception completion interrupt. Then, in the processor 150, a predetermined judgment program (interrupt handler) is operated, and the process proceeds to step 20 to access the interrupt control block 240 in the data processing device 200 via the processor bus 151, and The information stored in 240a is read. Then, by reading this information, it is found that the interrupt is the USB function block 210.
Next, the process proceeds to a step S21, where the factor register 210a of the USB function block 210 is accessed to read the information stored therein. Then, by reading out this information, it is found that the interrupt is output from the first endpoint block 215 (this is an interrupt of the sub-block). In the following step 22, it is determined whether or not the interrupt is a sub-block interrupt. If the interrupt is a sub-block interrupt, the process proceeds to step 23; otherwise, the process proceeds to step 24. Since the interrupt of the first endpoint block 215 is a sub-block interrupt, the process proceeds from step 22 to step 23, and the determination program continues to access the factor register 215a of the first endpoint block 215 which is a sub-block. To read the stored information. By reading this information, it is understood that the reception completion interrupt has occurred. When step 22 is executed following step 23, there is no further sub-block, that is, no functional block included in the first endpoint block 215. A process corresponding to the reception completion interrupt of the endpoint block 215 is executed, and the interrupt factor determination process is terminated.
[0011]
Next, the data processing device 100 according to the present invention will be described. The data processing device 100 has a plurality of input / output interfaces and incorporates a plurality of functional blocks such as an input / output control block and a direct memory access control (DMAC) block, similarly to the data processing device 200 described above. Are different from the data processing device 200 in that they have a priority setting register which is a priority setting unit for setting the necessity of priority.
That is, as shown in FIG. 1, the data processing device 100 includes a USB function block 110 and a plurality of input / output function blocks (in FIG. 1, a first input / output function block 120, an n-th input / output function block 130 ) And an interrupt control block 140, and are connected to the processor 150 via the processor bus 151.
[0012]
As shown in FIG. 2, the USB function block 110 includes a USB transmission DMAC block 111, a USB reception DMAC block 112, a USB input / output control block 113, a factor register 110a and a priority setting register 110b. The input / output control block 113 has a first endpoint block 115 and a second endpoint block 116. Then, the USB transmission DMAC block 111, the USB reception DMAC block 112, the USB input / output control block 113, and the first and second endpoint blocks 115 and 116, together with the factor registers 111a, 112a, 113a, 115a and 116a, respectively. , Priority setting registers 111b, 112b, 113b, 115b and 116b.
The first and n-th input / output function blocks 120 and 130 have priority setting registers 120b and 130b, respectively, in addition to the factor registers 120a and 130a, respectively.
Further, as shown in FIG. 3, the interrupt control block 140 includes a factor number 140a, a block number decoder 140c, and a priority block number register 140d.
[0013]
As described above, in the data processing device 100, each functional block including the higher order and its sub-blocks has a priority setting register, and the priority setting register is given priority to each functional block with respect to each function setting register (priority setting register). Necessity), that is, whether to output an interrupt signal to be prioritized (priority interrupt signal) can be set in one-to-one correspondence with each interrupt factor. Also, when an interrupt occurs due to an interrupt factor (priority interrupt factor) corresponding to the setting of the priority setting register, each functional block outputs a priority interrupt signal and directly inputs the signal to the higher-order interrupt control block 140. Notify. In the data processing device 100, unlike the data processing device 200, each functional block outputs a priority interrupt signal in addition to the interrupt signal.
Then, similarly to the data processing device 200, the interrupt control block 140 inputs and aggregates the interrupt signals from the lower functional blocks and outputs the interrupt request signal a, while the lower functional blocks (for example, USB) When the priority interrupt signal is input from the functional block 110), the block code included in the priority interrupt signal is decoded by the block number decoder 140c from the active state of the signal (for example, the priority interrupt signal of the first endpoint block 115 is activated). If so, the block code of the first endpoint block 115 is decoded), and the obtained block code is stored in the priority block number register 140d. This block code includes information for specifying each functional block, for example, a number unique to each functional block.
[0014]
The above data processing apparatus 100 inputs and aggregates the interrupt signals output from each functional block to the interrupt control block 140 and outputs the interrupt request signal a to the processor 150. Unlike the above, since a priority interrupt signal is output from each of the built-in function blocks, the flow of the interrupt factor determination is performed as shown in the flowchart of FIG. Here, in the case of each functional block, for example, the USB functional block 110, the connection path of the output interrupt request signal is as shown in FIG. In FIG. 2, the data path and blocks and signals for controlling the data path are omitted.
In the following description, of the built-in function blocks, priority is set in the priority setting register 110b of the USB function block 110 and the priority setting register 115b of the first endpoint block 115, and the priority is set. The interrupt factor (priority interrupt factor) is used as the reception completion interrupt. The determination of the interrupt factor in that case is performed as in the flowchart shown in FIG. In FIG. 11, steps are abbreviated as S.
[0015]
First, the data processing device 100 receives a program instruction from the processor 150, accesses the priority setting register 115b of the first endpoint block 115, sets "1" in a corresponding area, sets a bit, The priority setting for giving priority to the reception completion interrupt is performed.
Then, the data processing apparatus 100 executes normal control such as execution of reception (it is assumed that a reception completion interrupt in the first endpoint block 115 is generated by this operation).
In the data processing apparatus 100, a reception completion interrupt has occurred in the first endpoint block 115. Since this reception completion interrupt is a priority interrupt factor, the reception completion interrupt is generated from the first endpoint block 115. The priority interrupt signal b is directly input to the control block 140 for notification. Then, the interrupt control block 140 activates the block number decoder 140c, specifies the block code included in the input priority interrupt signal b, and stores it in the priority block number register 140d. If the correspondence between each functional block and the block code set in the block number decoder 140c is clear in the data processing device 100, and the correspondence is clear even in the program of the processor 150, the block number From the block code stored in the register 140d, it can be recognized from which functional block the input priority interrupt signal b is output. When the functional block that has output the priority interrupt signal b is determined, the processor 150 outputs an interrupt request signal a to notify the processor 150 of the occurrence of the interrupt.
[0016]
Next, in the processor 150, a predetermined judgment program (interrupt handler) is activated, and proceeds to step 1 to access the priority block number register 140d of the interrupt control block 140 via the processor bus 151 and store the same. Read the current information (block code). In the following step 2, it is determined whether or not the information stored in the priority block number register 140d is a valid function block number (that is, a function block provided in the data processing device 100). If the number is a valid function block number, the process proceeds to step 3; otherwise, the process proceeds to step 4 to execute the above-described tree structure interrupt factor tracking process.
When the process proceeds to step 3, since the information indicating the first endpoint block 115 has been obtained by reading the information in step 1, it is determined that the interrupt is from the first endpoint block 115. The determination is made and the interrupt factor is determined. In this case, when the processor 150 executes a process corresponding to the generated interrupt, the process of determining the cause of the interrupt is terminated.
[0017]
If the generated interrupt does not depend on the priority interrupt factor of the functional block for which the priority is not set, the priority control signal 140 is not notified (not activated) to the interrupt control block 140, so that the interrupt is not performed. No information is set in the priority block number register 140d of the write control block 140, and the priority block number register 140d becomes empty. At this time, when the information set in the priority block number register 140d is read in accordance with the instruction of the program of the processor 150, it is determined that the interrupt is an interrupt that is not a cause of a priority interrupt due to a functional block for which priority is not set. Therefore, an interrupt factor determination process is executed according to the above-described tree structure tracking process.
In the above description, the function block for which the priority is set is set to one, but there is a case where the setting of the priority is performed for a plurality of function blocks, and they simultaneously output an interrupt signal. . In that case, the priority interrupt signal b may be stored in the order of arrival, or the block codes may be stored in the priority block number register 140d in the order of the block codes.
[0018]
As described above, the data processing apparatus 100 described above stores the priority block number register 140d of the interrupt control block 140 when the priority interrupt signal according to the priority interrupt factor is output from the function block in which the priority is set in advance. As a target, it is possible to identify a preset interrupt factor only by reading out information (block code) set therein, and it is not necessary to perform a tree structure tracking process. Therefore, the processing for the interrupt can be speeded up.
Next, another data processing device will be described. This data processing device has the same configuration as the data processing device 100 except that the interrupt control block 140 is replaced by an interrupt control block 143. The description of the block 143 will be mainly given, and the description of the common parts will be omitted or simplified.
The interrupt control block 143 is different in that it has a priority setting register 144, a priority table 145, and a table control register 146 as shown in FIG. 4, and the other configuration is the same.
[0019]
The priority setting register 144 is configured to output a plurality of priority interrupt signals according to a priority interrupt factor from a plurality of function blocks for which priority is set, and to set a priority between function blocks set in advance. This is a means for storing degrees. The priority table 145 has a plurality of table entries 145a, 145b,..., And is a means for storing a block code of each functional block according to the priority stored in the priority setting register 144. The table control register 146 stores data necessary for resetting the priority table 145. For example, as shown in FIG. 5, in the priority setting register 144, a setting is made such that “1” is set only in the item of “reception completed”, and “0” is set in the other items so that “reception completed” has priority. You are.
This priority table 145 stores block codes as follows. This procedure will be described with reference to the flowchart of FIG.
[0020]
When the data setting process of the priority table 145 is started, the initialization program is operated to initialize and reset the priority table 145 using the data stored in the table control register 146.
In step 5, for each priority interrupt signal, in accordance with the priority stored in the priority setting register 144, the block codes of the functional blocks are sorted in the order of higher priority in each table entry 145a in the priority table 145. , 145a... Subsequently, in step 6, it is determined whether or not all the function blocks for which priority is set have been set (registered). If all of the function blocks have been set, the process is terminated; otherwise, the process returns to step 5. By the above processing, the block codes of the functional blocks are sequentially stacked in each of the table entries 145a, 145a,. The entry number of the table entry is automatically updated (added) every time a block code is written.
When a plurality of function blocks for which priority is set output a priority interrupt signal at the same time, the interrupt control block 140 refers to the priority table 145 and has the highest priority among the table entries. That is, the block code having the smallest entry number is read, and the block code is stored in the priority block number register 140d. For example, in addition to the first endpoint block 115 of the USB function block 110, when the USB transmission DMAC block 111 also outputs a priority interrupt signal in accordance with the reception completion interrupt, the USB transmission DMAC block 111 outputs In order to give priority to the first endpoint block 115, the first endpoint block 115 is given priority over the block code of the USB transmission DMAC block 111 according to the above procedure (priority of the first endpoint block 115). The priority is written into the priority setting register 144 (increasing the degree).
[0021]
By providing the priority table 145, even if two or more functional blocks output a priority interrupt request at the same time, the data processing apparatus can use any of the priority blocks stored in the priority setting register 144 according to the priority. Is given priority. Therefore, for example, even if a priority interrupt signal according to the completion interrupt of the USB transmission DMAC block 111 occurs first, if a priority interrupt signal with a higher priority occurs later, the priority interrupt signal generated thereafter has priority. Is done.
This data processing device can determine the cause of an interrupt only by reading one register when a priority interrupt signal is output from a function block set in advance as a priority required, and furthermore, there are a plurality of the function blocks, Even if each of them outputs the priority interrupt signal at the same time, the priority between the functional blocks is set in advance in the priority setting register 144, so that the priority of the interrupt processing can be given to each functional block. . Therefore, not only can the processing for the interrupt be speeded up, but also the priority processing can be flexibly performed.
[0022]
Next, another data processing apparatus will be described. This data processing device has the same configuration as the data processing device 100 except that the interrupt control block 140 is replaced by an interrupt control block 147. The description of the block 147 will be mainly given, and the description of the common parts will be omitted or simplified.
As shown in FIG. 6, the interrupt control block 147 differs from the interrupt control block 140 in that the priority block number register 140d is a priority block bitmap register (hereinafter, referred to as a “BM register”) 148. And the other configurations are the same.
In the BM register 148, an area unique to each functional block is assigned to each functional block in accordance with its priority, and a priority interrupt signal from each functional block is bit-mapped and corresponds to the functional block. Set a bit in a storage area. In the BM register 148, for example, as shown in FIG. 7, a predetermined bit position is assigned to each functional block, and a bit is set in the bit position and stored.
[0023]
Similarly to the above-described data processing device, when a priority interrupt signal is output from a plurality of function blocks set as priority required, for example, the first endpoint block 115 of the USB function block 110 and the USB transmission DMAC block Assuming that a reception completion interrupt has occurred from step 111, the interrupt factor determination using the BM register 148 is as shown in the flowchart of FIG.
Assuming that a reception completion interrupt has occurred in the first endpoint block 115 and the USB transmission DMAC block 111, both priority interrupt signals are input to the interrupt control block 147. In response to this, the interrupt control block 147 expands the input priority interrupt signal into a bit map, and sets a bit in an area of the BM register 148 corresponding to both functional blocks. Next, an interrupt request signal a is output to the processor 150.
[0024]
Then, after the start of the interrupt factor determination process, the process proceeds to step 7, in which the BM register 148 of the interrupt control block 143 is accessed to read the set information in accordance with a program (interrupt handler) instruction from the processor 150. .
Then, the process proceeds to a step 8, wherein it is determined whether or not all the read information is "0". If all are "0", it means that the priority interrupt factor is not included in the generated interrupt, and the BM register 148 of the interrupt control block 147 is empty without any information set. . In this case, the process branches from step 8 to step 4, and executes the above-described interrupt factor determination processing (tree structure tracking processing). If not, the process proceeds to step 9 where a process corresponding to the generated interrupt is executed and the process ends.
When proceeding to step 9, it is determined which of the functional blocks has been set as the priority required, and the interrupt factor is determined. In the BM register 148, the bits are set in the area allocated to the first endpoint block 115 and the USB transmission DMAC block 111 in the processing up to that point, so that the function blocks for which both of them are set as prioritized are required. Therefore, the processing branches off to the one with the higher priority (the function block with the higher priority is delegated to the program of the processor 150. Here, the program is transferred to the USB transmission DMAC block 111). If the processing branches to the processing corresponding to the completion interrupt of the above, the USB transmission DMAC block 111 has priority.)
As described above, this data processing device can detect the interrupt factor only by reading one register when the priority interrupt factor of the function block set as the priority required in advance occurs. Even when there are a plurality of such function blocks and an interrupt occurs at the same time, the priority between the function blocks can be arbitrarily defined and processed. Therefore, the processing for the interrupt can be speeded up and flexible priority processing can be performed.
[0025]
【The invention's effect】
As described above, according to the present invention, the interrupt factor can be specified by reading the information set in one register when the priority interrupt signal is output. Since it is not necessary to perform the processing, the processing for the interrupt can be speeded up.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an internal configuration of a data processing device and a processor according to the present invention.
FIG. 2 is a block diagram showing an internal configuration of a USB function block of the data processing device shown in FIG.
FIG. 3 is a block diagram showing an internal configuration of an interrupt control block of the data processing device shown in FIG.
FIG. 4 is a block diagram showing an internal configuration of an interrupt control block of another data processing device.
FIG. 5 is a block diagram showing an example of an internal configuration of a priority setting register and a factor register inside the interrupt control block shown in FIG. 4;
FIG. 6 is a block diagram showing an internal configuration of an interrupt control block of another data processing device.
FIG. 7 is a block diagram showing a configuration of a priority block bit map register in the interrupt control block shown in FIG. 6;
FIG. 8 is a block diagram showing an internal configuration of a data processing device and a processor related to the present invention.
FIG. 9 is a block diagram showing an internal configuration of a USB function block of the data processing device shown in FIG. 8;
FIG. 10 is a flowchart illustrating a procedure of an interrupt factor determination process performed by the data processing device illustrated in FIG. 1;
FIG. 11 is a flowchart illustrating a procedure of an interrupt factor determination process performed by another data processing device.
FIG. 12 is a flowchart illustrating a procedure of a process of setting a block code in a priority table.
FIG. 13 is a flowchart illustrating a procedure of an interrupt factor determination process performed by another data processing device.
[Explanation of symbols]
100: data processing device 150: processor
110: USB function block
111: USB transmission DMAC block
112: USB reception DMAC block
113: USB input / output control block
115: first endpoint block
116: Second endpoint block
111a, 112a: Cause register
113a, 115a: Cause register
116a: Cause register
111b, 112b: priority setting register
113b, 115b: priority setting register
116b: priority setting register
120: first input / output function block
130: n-th input / output function block
140, 143, 147: Interrupt control block
140a: Cause register
140c: block number decoder
140d: priority block number register

Claims (3)

A data processing device having a plurality of functional blocks for performing data processing functions and an interrupt control block for inputting and aggregating a plurality of interrupt signals output from the respective functional blocks and outputting an interrupt request signal. So,
Each of the functional blocks is provided with a priority setting unit for setting the priority necessity,
Each of the functional blocks outputs a priority interrupt signal including a block code for specifying the functional block separately from the interrupt signal when the priority setting unit is set to priority priority, thereby controlling the interrupt control. A data processing device for inputting to a block. The data processing device according to claim 1,
Means for storing the priority of each of the functional blocks;
Means for storing a block code included in the priority interrupt signal in accordance with the priority stored in the means, provided in the interrupt control block. The data processing device according to claim 1,
A data processing device, characterized in that a storage unit to which an area unique to each functional block according to each priority is assigned to each functional block is provided in the interrupt control block.

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