JP2004112453A - Signal transmission apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an LVDS transmission type signal transmission apparatus capable of reducing a chip area, current consumption, and increasing an operating range at a low voltage. <P>SOLUTION: A timing adjusting logic circuit 11 generates and outputs four signals D1-D4, which are logical signals, in response to one logical signal. A first and a second differential amplifier circuits 21, 22 control the switching of PMOS transistors 23, 24 and NMOS transistors 25, 26, respectively, in accordance with the input logical signals D1 to D4. The PMOS transistors 23, 24 and the NMOS transistors 25, 26 output currents when they are turned on, and enter a shutdown state to stop current outputs when they are turned off. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a signal transmission device for transmitting a differential signal, and more particularly to a signal transmission device of an LVDS transmission system.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, there has been a transmission / reception circuit including a single transmission line, which employs a circuit for adjusting the output impedance of a transmission circuit (for example, see Patent Document 1).
On the other hand, a differential signal interface such as the LVDS transmission system is a current output system, and a pair of currents output from a transmission unit are generated with a differential output voltage having a small amplitude by a termination resistor and input to a reception unit. .
As shown in FIG. 10, the circuit of such a transmission unit has one input and two outputs, and the timing adjustment logic circuit 202 composed of a logic circuit outputs a plurality of logic signals from the logic signal input to the input terminal IN. The logic signals D1 to D4 are generated and output. The signals D1 to D4 are input to the current input / output circuit 203. Alternatively, two types of logic signals D1 and D2 are generated and output from the logic signal input to the input terminal IN, and the signals D1 and D2 are input to the current input / output circuit 203.
[0003]
As shown in FIG. 11, the current input / output circuit 203 includes a constant current source 211, a PMOS transistor 212, an NMOS transistor 213, and a constant current source 214 connected in series between a positive power supply voltage V1 and a negative power supply voltage V2. It is connected. Further, a series circuit of a PMOS transistor 215 and an NMOS transistor 216 is connected in parallel with the series circuit of the PMOS transistor 212 and the NMOS transistor 213. Further, as shown in FIG. 12, the constant current source 214 in FIG.
[0004]
11 and 12, the PMOS transistors 212 and 215 and the NMOS transistors 213 and 216 are switched by the logic signal from the timing adjustment logic circuit 202, and the currents input and output from the connection between the PMOS transistor 212 and the NMOS transistor 213, Also, the current input and output from the connection between the PMOS transistor 215 and the NMOS transistor 216 changes. The constant current sources 211 and 214 can be easily realized by transistors forming a current mirror circuit.
[0005]
Further, since the timing adjustment logic circuit 202 generates and outputs a normal rotation and an inversion for one logic signal, the logic signals D1 and D4 and the logic signals D2 and D3 have the same timing. 11 and 12, in order to make the description easy to understand, the input signals at the same timing are common, and two of the logic signals D1 to D4 are input to the corresponding input terminals INa and INb. I have.
[0006]
[Patent Document 1]
Japanese Patent No. 3189546
[0007]
[Problems to be solved by the invention]
However, noise caused by switching of the PMOS transistors 212 and 215 and the NMOS transistors 213 and 216 or noise caused by switching timing errors in the PMOS transistors 212 and 215 and the NMOS transistors 213 and 216 forms the constant current sources 211 and 214. This affects the transistor, causing an error in the current value output from the constant current sources 211 and 214. As a result, the voltage amplitude generated by the terminating resistor changes, and the change is erroneously received by the receiving unit. There was a problem.
[0008]
This is because the switching of the PMOS transistors 212 and 215 and the NMOS transistors 213 and 216 affects the drain portions of the transistors forming the constant current sources 211 and 214, and the gates of the transistors are connected to each other via the gate-drain capacitance. Even affect. For this reason, the current values output from the constant current sources 211 and 214 have caused an error.
[0009]
Normally, a current of several mA is output from the constant current sources 211 and 214, so that the size of the transistors forming the constant current sources 211 and 214 increases, and the switching of the PMOS transistors 212 and 215 and the NMOS transistors 213 and 216 is performed. The effect is greater. Note that the size of the PMOS transistors 212 and 215 and the NMOS transistors 213 and 216 in the miniaturization process may be increased due to the use of an I / O transistor in consideration of withstand voltage such as surge.
[0010]
In order to suppress the influence on the currents output from the constant current sources 211 and 214, there is a method of adding a stabilizing capacitance to the gates of the current mirror transistors forming the constant current sources 211 and 214. However, there is a problem in that the chip area occupied by the capacitor increases in performing integration, and an extra charge / discharge current for the capacitor occurs. In addition, when integrated, transistors have a vertically stacked structure, so that the operation range of the transistors is narrowed, and there is a problem in that when the voltage is reduced, the operation is easily restricted.
[0011]
The present invention has been made to solve the above-described problems, and can reduce an error in an output current value due to switching of a transistor without using a stabilizing capacitor. It is an object of the present invention to provide an LVDS transmission signal transmission device that can be reduced in size and current consumption can be reduced, and can operate in a low voltage.
[0012]
[Means for Solving the Problems]
A signal transmission device according to the present invention generates a plurality of logic signals from an input signal, adjusts and outputs the timing of each of the logic signals, and a timing adjustment circuit unit that outputs each of the logic signals. A pair of first and second currents are generated from a signal, and a current input / output circuit unit for inputting and outputting a pair of currents is output. Signal transmission device,
The current input / output circuit unit includes:
First and second transistors connected in series between a predetermined first power supply voltage and a predetermined second power supply voltage;
Third and fourth transistors connected in series between the first power supply voltage and the second power supply voltage;
A first differential amplifier circuit that controls operation of the first and second transistors in accordance with a corresponding logic signal output from the timing adjustment circuit unit;
A second differential amplifier circuit that controls the operation of each of the third and fourth transistors according to a corresponding logic signal output from the timing adjustment circuit;
With
The first current is input / output from a connection between the first transistor and the second transistor, and the second current is input / output from a connection between the third transistor and the fourth transistor. is there.
[0013]
Further, a signal transmission device according to the present invention generates a plurality of logic signals from an input signal, adjusts and outputs the timing of each of the logic signals, and outputs the timing adjustment circuit unit. And a current input / output circuit unit for generating and inputting and outputting a pair of first and second currents from the respective signals. In the signal transmission device that outputs to
The current input / output circuit unit includes:
First and third transistors for inputting and outputting the first and second currents, respectively, and the first and third transistors are provided in accordance with corresponding logic signals output from the timing adjustment circuit unit. A first differential amplifier circuit for controlling the operation of each transistor of
Second and fourth transistors for inputting and outputting the first and second currents, respectively, according to the corresponding logic signals output from the timing adjustment circuit unit; A second differential amplifier circuit section that controls the operation of each transistor of
With
The first and second transistors are connected in series between a predetermined first power supply voltage and a predetermined second power supply voltage, and the third and fourth transistors are connected to the first and second transistors, respectively. The power supply voltage and the second power supply voltage are connected in series.
[0014]
Specifically, the first differential amplifier circuit section includes:
A first differential pair to which a corresponding logic signal output from the timing adjustment circuit unit is input;
A first constant current source that supplies a predetermined current to the first differential pair;
A first current mirror circuit forming a load on one of the transistors in the first differential pair, wherein the first transistor is a transistor on the output side;
A second current mirror circuit forming a load on the other transistor in the first differential pair, wherein the third transistor forms an output-side transistor;
A first current control circuit that controls current output of each of the first and second current mirror circuits according to a logic signal input to the first differential pair;
With
The second differential amplifier circuit section includes:
A second differential pair to which a corresponding logic signal output from the timing adjustment circuit unit is input;
A second constant current source for supplying a predetermined current to the second differential pair;
A third current mirror circuit forming a load on one of the transistors in the second differential pair, wherein the second transistor forms an output-side transistor;
A fourth current mirror circuit forming a load on the other transistor in the second differential pair, wherein the fourth transistor forms an output-side transistor;
A second current control circuit that controls current output of each of the third and fourth current mirror circuits according to a logic signal input to the second differential pair;
Was provided.
[0015]
In this case, the first current control circuit controls the current output of each of the first and second current mirror circuits according to a control signal input from the outside, and the second current control circuit The current output of each of the third and fourth current mirror circuits is controlled in accordance with a control signal input from the outside.
[0016]
Further, an I / O transistor may be used as each of the first to fourth transistors.
[0017]
Further, an I / O transistor may be used as each of the first to fourth transistors, and each of the transistors forming the current mirror circuit with the corresponding first to fourth transistors.
[0018]
On the other hand, a plurality of resistors connected in series between a first output terminal for inputting / outputting the first current and a second output terminal for inputting / outputting the second current, and A reference voltage generating circuit for applying a predetermined reference voltage to a connection between the resistors.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, the present invention will be described in detail based on an embodiment shown in the drawings.
First embodiment.
FIG. 1 is a diagram illustrating an example of a signal transmission device according to the first embodiment of the present invention, and illustrates a signal transmission device of the LVDS transmission system.
In FIG. 1, the signal transmission device 1 includes a transmission unit 2, a reception unit 3, and a terminating resistor 4, and a pair of currents output from the transmitting unit 2 are converted into a small-amplitude differential output voltage by the terminating resistor 4. Input to the receiving unit 3.
[0020]
FIG. 2 is a diagram illustrating a configuration example of the transmission unit 2 of FIG.
In FIG. 2, a transmission unit 2 has one input and two outputs, and a timing adjustment logic circuit 11 formed of a logic circuit generates a plurality of logic signals D1 to D4 from a logic signal input to an input terminal IN. The signals D1 to D4 are input to the current input / output circuit 12. The signals D1 to D4 may be configured such that only the two types D1 and D2 are used to input the signal D1 to the third input terminal IN3 and the signal D2 to the fourth input terminal IN4.
[0021]
The current input / output circuit 12 has four inputs and two outputs, and includes a first differential amplifier circuit 21, a second differential amplifier circuit 22, PMOS transistors 23 and 24, and NMOS transistors 25 and 26. Note that the timing adjustment logic circuit 11 forms a timing adjustment circuit section, the PMOS transistor 23 is a first transistor, the PMOS transistor 24 is a third transistor, the NMOS transistor 25 is a second transistor, and the NMOS transistor 26 is a second transistor. 4 transistors.
[0022]
For example, the first power supply voltage V1 is a predetermined power supply voltage VCC, and the second power supply voltage V2 is a ground voltage GND.
A series circuit of a PMOS transistor 23 and an NMOS transistor 25 and a series circuit of a PMOS transistor 24 and an NMOS transistor 26 are connected in parallel between the first power supply voltage V1 and the second power supply voltage V2. Two input terminals of the first differential amplifier circuit 21 correspond to a first input terminal IN1 and a second input terminal IN2 of the current input / output circuit 12, and two input terminals of the second differential amplifier circuit 22. The two input terminals correspond to the third input terminal IN3 and the fourth input terminal IN4 of the current input / output circuit 12. Logic signals D1 to D4 from the timing adjustment logic circuit 11 are correspondingly input to the first to fourth input terminals IN1 to IN4.
[0023]
In the first differential amplifier 21, signals of opposite signal levels are output from the respective output terminals o 1 and o 1 B, and the output terminal o 1 is connected to the gate of the PMOS transistor 23, and the output terminal o 1 B is connected to the gate of the PMOS transistor 24. Each is connected. Similarly, in the second differential amplifier circuit 22, signals of opposite signal levels are output from the respective output terminals o2 and o2B, the output terminal o2 is connected to the gate of the NMOS transistor 25, and the output terminal o2B is connected to the NMOS transistor 26. Are connected to the respective gates. The connection between the PMOS transistor 23 and the NMOS transistor 25 is connected to the output terminal OUT of the current input / output circuit 12, and the connection between the PMOS transistor 24 and the NMOS transistor 26 is connected to the output terminal OUTB of the current input / output circuit 12. Have been.
[0024]
In such a configuration, the PMOS transistors 23 and 24 and the NMOS transistors 25 and 26 are switching-controlled by signals output from the first and second differential amplifier circuits 21 and 22, respectively, and output a current when turned on. When it is turned off, it enters a cutoff state and stops outputting current. When the PMOS transistor 23 and the NMOS transistor 26 turn on, respectively, the PMOS transistor 24 and the NMOS transistor 25 turn off. When the PMOS transistor 24 and the NMOS transistor 25 are turned on, the PMOS transistor 23 and the NMOS transistor 26 are turned off.
[0025]
On the other hand, the current input / output circuit 12 is configured to generate and output two logic signals from the four input signals D1 to D4, which are logic signals. Since the inverted and inverted signals are generated and output, the logic signals D1 and D4 and the logic signals D2 and D3 have the same timing. Therefore, in order to make the description easy to understand, a case where the logic signals D1 and D2 are input to the current input / output circuit 12 will be described below as an example.
[0026]
FIG. 3 is a diagram showing a circuit example of each of the first and second differential amplifier circuits in the current input / output circuit 12 shown in FIG. In FIG. 3, the first input terminal IN1 and the fourth input terminal IN4 of FIG. 2 are combined into one to form an input terminal INa, and the second input terminal IN2 and the third input terminal IN3 of FIG. And an input terminal INb.
[0027]
3, the first differential amplifier circuit 21 includes NMOS transistors 31 and 32, a constant current source 33, and resistors 34 and 35. A resistor 34, an NMOS transistor 31, and a constant current source 33 are connected in series between the first power supply voltage V1 and the second power supply voltage V2, and a resistor 35 is connected in parallel with a series circuit of the resistor 34 and the NMOS transistor 31. And an NMOS transistor 32 in series. The gate of the NMOS transistor 31 is connected to the input terminal INa, and the gate of the NMOS transistor 32 is connected to the input terminal INb. The connection between the resistor 34 and the NMOS transistor 31 forms the output terminal o1 of the first differential amplifier circuit 21 and is connected to the gate of the PMOS transistor 23. The connection between the resistor 35 and the NMOS transistor 32 forms an output terminal o1B of the first differential amplifier circuit 21 and is connected to the gate of the PMOS transistor 24.
[0028]
On the other hand, the second differential amplifier circuit 22 includes PMOS transistors 41 and 42, a constant current source 43, and resistors 44 and 45. A constant current source 43, a PMOS transistor 41 and a resistor 44 are connected in series between the first power supply voltage V1 and the second power supply voltage V2, and a PMOS transistor is connected in parallel with a series circuit of the PMOS transistor 41 and the resistor 44. A series circuit of 42 and a resistor 45 is connected. The gate of the PMOS transistor 41 is connected to the input terminal INa, and the gate of the PMOS transistor 42 is connected to the input terminal INb. The connection between the PMOS transistor 41 and the resistor 44 forms the output terminal o2 of the second differential amplifier circuit 22, and is connected to the gate of the NMOS transistor 25. The connection between the PMOS transistor 42 and the resistor 45 forms the output terminal o2B of the second differential amplifier circuit 22, and is connected to the gate of the NMOS transistor 26.
[0029]
The current output from the output terminal OUT is the current output from the PMOS transistor 23 according to the signal output from the output terminal o1 of the first differential amplifier circuit 21 and the output of the second differential amplifier circuit 22. The current output from the NMOS transistor 25 is synthesized according to the signal output from the terminal o2. Similarly, the current output from the output terminal OUTB is different from the current output from the PMOS transistor 24 in response to the signal output from the output terminal o1B of the first differential amplifier circuit 21 and the second differential amplifier circuit. The current output from the NMOS transistor 26 is synthesized according to the signal output from the output terminal o2B of the output terminal 22.
[0030]
Here, for example, a case where the same voltage as the first power supply voltage V1 is input to the input terminal INa and the same voltage as the second power supply voltage V2 is input to the input terminal INb will be described.
In this case, in the first differential amplifier circuit 21, the NMOS transistor 31 is turned on and the NMOS transistor 32 is turned off, the constant current of the constant current source 33 flows to the resistor 34, and the gate of the PMOS transistor 23 A voltage shifted by the resistor 34 and the current is input from the power supply voltage V1 of 1 and a current corresponding to the voltage between the gate and the source of the PMOS transistor 23 tends to flow from the drain of the PMOS transistor 23. On the other hand, when the NMOS transistor 32 is turned off, no current flows through the resistor 35, and the output terminal o1B almost reaches the first power supply voltage V1, so that the PMOS transistor 24 is turned off and current flows from the PMOS transistor 24. Absent.
[0031]
On the other hand, in the second differential amplifier circuit 22, the PMOS transistor 41 is turned off and the PMOS transistor 42 is turned on, the constant current from the constant current source 43 flows to the resistor 45, and the gate of the NMOS transistor 26 A voltage shifted from the second power supply voltage V2 by the resistor 45 and the current is input, and a current corresponding to the gate-source voltage of the NMOS transistor 26 tends to flow through the NMOS transistor 26. On the other hand, when the PMOS transistor 41 is turned off, no current flows through the resistor 44, and the output terminal o2 becomes almost the second power supply voltage V2. Therefore, the NMOS transistor 25 is turned off and current flows through the NMOS transistor 25. Absent.
[0032]
The output terminals OUT and OUTB are connected by the terminating resistor 4, and the current flowing from the PMOS transistor 23 flows to the NMOS transistor 26 via the terminating resistor 4, and the currents flowing to the PMOS transistor 23 and the NMOS transistor 26 are equal. In this case, the same current flows through each of the PMOS transistor 23, the NMOS transistor 26, and the terminating resistor 4, and a voltage difference occurs between the current and the resistance of the terminating resistor 4 at the output terminals OUT and OUTB.
[0033]
Next, a case where the same voltage as the second power supply voltage V2 is input to the input terminal INa and the same voltage as the first power supply voltage V1 is input to the input terminal INb will be described.
In this case, in the first differential amplifier circuit 21, the NMOS transistor 31 is turned off and the NMOS transistor 32 is turned on, the constant current of the constant current source 33 flows to the resistor 35, and the gate of the PMOS transistor 24 1, a voltage shifted by the resistor 35 and the current from the power supply voltage V1 is input, and a current corresponding to the gate-source voltage of the PMOS transistor 24 tends to flow from the drain of the PMOS transistor 24. On the other hand, when the NMOS transistor 31 is turned off, no current flows through the resistor 34, and the output terminal o1 becomes almost the first power supply voltage V1, so that the PMOS transistor 23 is turned off and current flows from the PMOS transistor 23. Absent.
[0034]
On the other hand, in the second differential amplifier circuit 22, the PMOS transistor 41 is turned on and the PMOS transistor is turned off, the constant current from the constant current source 43 flows through the resistor 44, and the gate of the NMOS transistor 25 is Is inputted with a voltage shifted from the second power supply voltage V2 by the resistor 44 and the current, and the current according to the gate-source voltage of the NMOS transistor 25 tends to flow through the NMOS transistor 25. On the other hand, when the PMOS transistor 42 is turned off, no current flows through the resistor 45, and the output terminal o2B almost reaches the second power supply voltage V2. Therefore, the NMOS transistor 26 is turned off and current flows through the NMOS transistor 26. Absent.
[0035]
The output terminals OUT and OUTB are connected by the terminating resistor 4, and the current flowing from the PMOS transistor 24 flows to the NMOS transistor 25 via the terminating resistor 4, and the currents flowing to the PMOS transistor 24 and the NMOS transistor 25 are equal. The same current flows through the PMOS transistor 24, the NMOS transistor 25, and the terminating resistor 4, respectively, and a voltage difference occurs between the output terminals OUT and OUTB due to the current and the resistance value of the terminating resistor 4.
[0036]
By doing so, in the signal transmission device according to the first embodiment, the error in the output current value due to the switching of the transistor can be reduced without using a stabilizing capacitor, so that the chip area Can be reduced, current consumption can be reduced, and the operating range at low voltage can be widened.
[0037]
Second embodiment.
The PMOS transistors 23 and 24 and the NMOS transistors 25 and 26 in the first embodiment may be formed as a current mirror circuit, and such a configuration is referred to as a second embodiment of the present invention.
FIG. 4 is a diagram illustrating an example of a signal transmission device according to the second embodiment of the present invention. FIG. 4 illustrates only the current input / output circuit of the transmission unit illustrated in FIG. Since the configuration is the same as that of FIG. 2, the description is omitted. In FIG. 4, the same or similar components as those in FIG. 2 are denoted by the same reference numerals.
In FIG. 4, the current input / output circuit 51 has four inputs and two outputs, and includes a first differential amplifier circuit 52 and a second differential amplifier circuit 53.
[0038]
One input terminal of a first differential amplifier circuit 52 forming a first input terminal IN1 of the current input / output circuit 51, and a first differential amplifier circuit forming a second input terminal IN2 of the current input / output circuit 51 Logic signals D1 and D2 are correspondingly input to the other input terminal of 52. Further, one output terminal of the first differential amplifier circuit 52 is connected to the output terminal OUT, and the other output terminal of the first differential amplifier circuit 52 is connected to the output terminal OUTB. One input terminal of a second differential amplifier circuit 53 forming a third input terminal IN3 of the current input / output circuit 51, and a second differential amplifier circuit forming a fourth input terminal IN4 of the current input / output circuit 51 Logic signals D3 and D4 are correspondingly input to the other input terminal of 53. Further, one output terminal of the second differential amplifier circuit 53 is connected to the output terminal OUT, and the other output terminal of the second differential amplifier circuit 53 is connected to the output terminal OUTB.
[0039]
The first differential amplifier circuit 52 includes a first differential pair 61, a first current control circuit 62, first and second current mirror circuits 63 and 64, and a first constant current source 65. ing. The second differential amplifier circuit 53 includes a second differential pair 71, a second current control circuit 72, third and fourth current mirror circuits 73 and 74, and a second constant current source 75. It is configured.
[0040]
In the first differential amplifier circuit 52, one input terminal of the first differential pair 61 is connected to the first input terminal IN1, and the other input terminal of the first differential pair 61 is connected to the second input terminal IN2. Connected to each other. The first current control circuit 62 and the first and second current mirror circuits 63 and 64 are connected to the first power supply voltage V1 to supply power. One output terminal and the input terminal of the first current mirror circuit 63 are connected to one output terminal of the first differential pair 61, respectively.
[0041]
Further, the other output terminal of the first current control circuit 62 and the input terminal of the second current mirror circuit 64 are connected to the other output terminal of the first differential pair 61, respectively. Further, a first constant current source 65 is connected between the first differential pair 61 and the second power supply voltage V2, and the first differential pair 61 Is supplied. The output terminal of the first current mirror circuit 63 is connected to the output terminal OUT, and the output terminal of the second current mirror circuit 64 is connected to the output terminal OUTB.
[0042]
In the second differential amplifier circuit 53, one input terminal of the second differential pair 71 is connected to the third input terminal IN3, and the other input terminal of the second differential pair 71 is connected to the fourth input terminal IN4. Connected to each other. The second current control circuit 72 and the third and fourth current mirror circuits 73 and 74 are connected to the second power supply voltage V2 to supply power. One output terminal and the input terminal of the third current mirror circuit 73 are connected to one output terminal of the second differential pair 71, respectively.
[0043]
Further, the other output terminal of the second current control circuit 72 and the input terminal of the fourth current mirror circuit 74 are connected to the other output terminal of the second differential pair 71, respectively. In addition, a second constant current source 75 is connected between the second differential pair 71 and the first power supply voltage V1, and the second differential pair 71 Is supplied. The output terminal of the third current mirror circuit 73 is connected to the output terminal OUT, and the output terminal of the fourth current mirror circuit 74 is connected to the output terminal OUTB.
[0044]
FIG. 5 is a diagram showing a circuit example of the current input / output circuit 51 of FIG. Note that FIG. 5 shows an example in which input signals at the same timing are common, that is, a case where the logic signals D1 and D2 are input to the current input / output circuit 51, for simplicity of explanation. Accordingly, the first input terminal IN1 and the third input terminal IN3 in FIG. 4 are combined into one input terminal INa, and the second input terminal IN2 and the fourth input terminal IN4 in FIG. Input terminal INb.
[0045]
In the first differential amplifier circuit 52, the first differential pair 61 includes NMOS transistors 81 and 82, and the first current control circuit 62 includes PMOS transistors 83 and 84. Further, the first current mirror circuit 63 is constituted by PMOS transistors 85 and 86, and the second current mirror circuit 64 is constituted by PMOS transistors 87 and 88. Note that the PMOS transistor 86 forms a first transistor, and the PMOS transistor 88 forms a third transistor.
[0046]
In the first differential pair 61, each gate of the NMOS transistors 81 and 82 forms an input terminal, and the gate of the NMOS transistor 81 is connected to the input terminal INa, and the gate of the NMOS transistor 82 is connected to the input terminal INb. I have. The sources of the NMOS transistors 81 and 82 are connected, and a first constant current source 65 is connected between the connection and the second power supply voltage V2. The drains of the NMOS transistors 81 and 82 form output terminals of the first differential pair 61, respectively.
[0047]
In the first current control circuit 62, the PMOS transistor 83 is connected between the first power supply voltage V1 and the drain of the NMOS transistor 81, and the PMOS transistor 84 is connected between the first power supply voltage V1 and the drain of the NMOS transistor 82. Connected between. The gate of the PMOS transistor 83 is connected to the input terminal INa, and the gate of the PMOS transistor 84 is connected to the input terminal INb.
[0048]
In the first current mirror circuit 63, the sources of the PMOS transistors 85 and 86 are connected to the first power supply voltage V1, respectively, and the gates of the PMOS transistors 85 and 86 are connected and connected to the drain of the PMOS transistor 85. I have. The drain of the PMOS transistor 85 is connected to the drain of the NMOS transistor 81, and the drain of the PMOS transistor 86 is connected to the output terminal OUT.
[0049]
In the second current mirror circuit 64, the sources of the PMOS transistors 87 and 88 are connected to the first power supply voltage V1, respectively, and the gates of the PMOS transistors 87 and 88 are connected and connected to the drain of the PMOS transistor 87. I have. The drain of the PMOS transistor 87 is connected to the drain of the NMOS transistor 82, and the drain of the PMOS transistor 88 is connected to the output terminal OUTB.
[0050]
On the other hand, in the second differential amplifier circuit 53, the second differential pair 71 includes PMOS transistors 91 and 92, and the second current control circuit 72 includes NMOS transistors 93 and 94. The third current mirror circuit 73 includes NMOS transistors 95 and 96, and the fourth current mirror circuit 74 includes PMOS transistors 97 and 98. Note that the NMOS transistor 96 forms a second transistor, and the NMOS transistor 98 forms a fourth transistor.
[0051]
In the second differential pair 71, the gates of the PMOS transistors 91 and 92 each form an input terminal, the gate of the PMOS transistor 91 is connected to the input terminal INa, and the gate of the PMOS transistor 92 is connected to the input terminal INb. I have. The sources of the PMOS transistors 91 and 92 are connected, and a second constant current source 75 is connected between the connection and the first power supply voltage V1. Each drain of the PMOS transistors 91 and 92 forms an output terminal of the second differential pair 71, respectively.
[0052]
In the second current control circuit 72, the NMOS transistor 93 is connected between the second power supply voltage V2 and the drain of the PMOS transistor 91, and the NMOS transistor 94 is connected between the second power supply voltage V2 and the drain of the PMOS transistor 92. Connected between. The gate of the NMOS transistor 93 is connected to the input terminal INa, and the gate of the NMOS transistor 94 is connected to the input terminal INb.
[0053]
In the third current mirror circuit 73, the sources of the NMOS transistors 95 and 96 are connected to the second power supply voltage V2, respectively, and the gates of the NMOS transistors 95 and 96 are connected and connected to the drain of the NMOS transistor 95. I have. The drain of the NMOS transistor 95 is connected to the drain of the PMOS transistor 91, and the drain of the NMOS transistor 96 is connected to the output terminal OUT.
[0054]
In the fourth current mirror circuit 74, the sources of the NMOS transistors 97 and 98 are connected to the second power supply voltage V2, and the gates of the NMOS transistors 97 and 98 are connected and connected to the drain of the NMOS transistor 97. I have. The drain of the NMOS transistor 97 is connected to the drain of the PMOS transistor 92, and the drain of the NMOS transistor 98 is connected to the output terminal OUTB.
[0055]
In such a configuration, a current corresponding to the current flowing from the first power supply voltage V1 to the PMOS transistor 85 and the NMOS transistor 81 is about to be output from the PMOS transistor 86 by the first current mirror circuit 63. Further, a current corresponding to the current flowing from the first power supply voltage V1 to the PMOS transistor 87 and the NMOS transistor 82 is about to be output from the PMOS transistor 88 by the second current mirror circuit 64.
[0056]
Similarly, a current corresponding to the current flowing from the PMOS transistor 91 to the second power supply voltage V2 via the NMOS transistor 95 tends to flow to the NMOS transistor 96 by the third current mirror circuit 73. Further, a current corresponding to the current flowing from the PMOS transistor 92 to the second power supply voltage V2 via the NMOS transistor 97 tends to flow to the NMOS transistor 98 by the fourth current mirror circuit 74.
[0057]
In other words, the current output from one output terminal of the first differential amplifier circuit 52 composed of the first differential pair 61 from the output terminal OUT and the current composed of the second differential pair 71 As a current output from one output terminal of the second differential amplifier circuit 53, a current obtained by combining currents output from the corresponding first current mirror circuit 63 and the corresponding current current output from the third current mirror circuit 73 is output. You. Similarly, from the output terminal OUTB, a current outputted from the other output terminal of the first differential amplifier circuit 52 composed of the first differential pair 61 and a current composed of the second differential pair 71 The current output from the other output terminal of the second differential amplifier circuit 53 is a current obtained by combining the currents output from the corresponding second current mirror circuit 64 and fourth current mirror circuit 74, respectively. Is done.
[0058]
The PMOS transistors 83 and 84 constituting the first current control circuit 62 are adapted so that the first power supply voltage V1 is applied to o3 and o3B in accordance with signals input to the input terminals INa and INb, respectively. The operation of the PMOS transistors 86 and 88 is controlled. Similarly, the NMOS transistors 93 and 94 constituting the second current control circuit 72 are applied with the second power supply voltage V2 to o4 and o4B, respectively, according to the signals input to the input terminals INa and INb. Then, the operation of the corresponding NMOS transistors 96 and 98 is controlled.
[0059]
For example, assume that the same voltage as the first power supply voltage V1 is input to the input terminal INa, and the same voltage as the second power supply voltage V2 is input to the input terminal INb.
In this case, the NMOS transistor 81 turns on and the NMOS transistor 82 turns off, and the current supplied from the first constant current source 65 flows through the PMOS transistor 85 of the first current mirror circuit 63. Since the PMOS transistor 83 is turned off, a current corresponding to the size ratio of the PMOS transistors 85 and 86 to the current tends to flow from the PMOS transistor 86. Further, when the NMOS transistor 82 is turned off, no current flows through the PMOS transistor 87, and the PMOS transistor 84 is turned on, so that the gate voltage of the PMOS transistor 88 becomes close to the first power supply voltage V1. Stops flowing.
[0060]
On the other hand, the PMOS transistor 91 is turned off and the PMOS transistor 92 is turned on, and the current supplied from the second constant current source 75 flows through the NMOS transistor 97 of the fourth current mirror circuit 74. Since the NMOS transistor 94 is turned off, a current corresponding to the size ratio of the NMOS transistors 97 and 98 to the current tends to flow from the NMOS transistor 98. Further, when the PMOS transistor 91 is turned off, no current flows through the NMOS transistor 95, and the NMOS transistor 93 is turned on, so that the gate voltage of the NMOS transistor 96 becomes close to the second power supply voltage V2. The current stops flowing.
[0061]
Normally, since the terminating resistor 4 is connected between the output terminal OUT and OUB, the current output from the PMOS transistor 86 flows to the NMOS transistor 98 via the terminating resistor 4. If the currents supplied from the first constant current source 65 and the second constant current source 75 are the same and the size ratio between the PMOS transistors 85 and 86 is equal to the size ratio between the NMOS transistors 97 and 98, the PMOS transistor A current having the same current value flows through 86 and the NMOS transistor 98, and a voltage difference occurs between the output terminals OUT and OUTB based on the current value and the resistance value of the terminating resistor 4.
[0062]
Next, a case where the same voltage as the second power supply voltage V2 is input to the input terminal INa and the same voltage as the first power supply voltage V1 is input to the input terminal INb will be described.
In this case, the NMOS transistor 81 is turned off and the NMOS transistor 82 is turned on, and the current supplied from the first constant current source 65 flows through the PMOS transistor 87 of the second current mirror circuit 64. Since the PMOS transistor 84 is off, a current corresponding to the size ratio of the PMOS transistors 87 and 88 with respect to the current tends to flow from the PMOS transistor 88. When the NMOS transistor 81 is turned off, no current flows through the PMOS transistor 85, and the PMOS transistor 83 is turned on, so that the gate voltage of the PMOS transistor 86 becomes close to the first power supply voltage V1. Stops flowing.
[0063]
On the other hand, the PMOS transistor 91 turns on and the PMOS transistor 92 turns off, and the current supplied from the second constant current source 75 flows through the NMOS transistor 95 of the third current mirror circuit 73. Since the NMOS transistor 93 is turned off, a current corresponding to the size ratio of the NMOS transistors 95 and 96 to the current tends to flow from the NMOS transistor 96. Further, when the PMOS transistor 92 is turned off, no current flows through the NMOS transistor 97, and the NMOS transistor 94 is turned on, so that the gate voltage of the NMOS transistor 98 becomes close to the second power supply voltage V2. The current stops flowing.
[0064]
Normally, since the terminating resistor 4 is connected between the output terminal OUT and OUB, the current output from the PMOS transistor 88 flows to the NMOS transistor 96 via the terminating resistor 4. If the currents supplied from the first constant current source 65 and the second constant current source 75 are the same and the size ratio between the PMOS transistors 87 and 88 is equal to the size ratio between the NMOS transistors 95 and 96, the PMOS transistor A current having the same current value flows through the NMOS transistor 88 and the NMOS transistor 96, and a voltage difference is generated between the output terminals OUT and OUTB from the current value and the resistance value of the terminating resistor 4.
[0065]
As described above, in the signal transmission device according to the second embodiment, the same effect as that of the first embodiment can be obtained, and the current output transistor forms a current mirror circuit to provide a differential signal. Since a part of the amplifier circuit is configured, the current mirror circuit can discharge and sink a constant current, and can easily realize the same current value of the source and the sink.
[0066]
Third embodiment.
In the second embodiment, the first current control circuit 62 and the second current control circuit 72 are connected to the first to fourth current mirror circuits 63, 64, 73, in response to an external control signal. The output control of the current from 74 may be performed, and such a control is referred to as a third embodiment of the present invention.
FIG. 6 is a diagram illustrating an example of a signal transmission device according to the third embodiment of the present invention. FIG. 6 illustrates only the current input / output circuit of the transmission unit illustrated in FIG. Since the configuration is the same as that of FIG. 2, the description is omitted. 6, the same or similar components as those in FIG. 4 are denoted by the same reference numerals, and the description thereof will be omitted, and only different points from FIG. 4 will be described.
[0067]
6 is different from FIG. 4 in that the first and second current control circuits 62 and 72 in FIG. 4 are controlled in operation by an external current control signal Sc. 4 to the first current control circuit 62a, and the second current control circuit 72 in FIG. 4 to the second current control circuit 72a. The first differential amplifier circuit 52 is a first differential amplifier circuit 52a, the second differential amplifier circuit 53 of FIG. 4 is a second differential amplifier circuit 53a, and the current input / output circuit 51 of FIG. The input / output circuit 51a was used.
[0068]
In FIG. 6, the current input / output circuit 51a has four inputs and two outputs, and includes a first differential amplifier circuit 52a and a second differential amplifier circuit 53a.
The first differential amplifier circuit 52a includes a first differential pair 61, a first current control circuit 62a, first and second current mirror circuits 63 and 64, and a first constant current source 65. ing.
[0069]
Further, the second differential amplifier circuit 53a includes a second differential pair 71, a second current control circuit 72a, third and fourth current mirror circuits 73 and 74, and a second constant current source 75. It is configured. An external current control signal Sc is input to each of the first and second current control circuits 62a and 72a, and the first current control circuit 62a outputs the first and second current control signals in response to the current control signal Sc. The second current control circuit 72a controls the current output of the third and fourth current mirror circuits 73 and 74 according to the current control signal Sc. Do each. Other operations of the first and second current control circuits 62a and 72a are the same as those of the first and second current control circuits 62 and 72 in FIG.
[0070]
The current control signal Sc is a signal that is independent of the logic signals D1 to D4 and prevents a current from flowing to the output terminals OUT and OUTB regardless of the logic signals D1 to D4. During normal operation, the first and second current control circuits 62a and 72a perform the same operation as the first and second current control circuits 62 and 72 shown in FIGS. The control signal Sc is fixed near the second power supply voltage V2. Note that, depending on the circuit configuration, the current control signal Sc is usually fixed near the first power supply voltage V1.
[0071]
As shown in FIG. 2, the logic signals D1 to D4 are generated by the timing adjustment logic circuit 11 from one input logic signal, and the timing control logic circuit 11 is used to generate the current control signal Sc to perform the logic operation. It is possible to make it output. However, by directly inputting the current control signal Sc from the outside to the first and second current control circuits 62a and 72a, the speed at which the current output from the output terminals OUT and OUTB is stopped is increased, and the timing adjustment logic is adjusted. The circuit 11 also has a simple configuration.
[0072]
FIG. 7 is a diagram showing a circuit example of the current input / output circuit 51a of FIG. Note that FIG. 7 shows an example in which the input signals at the same timing are common, that is, the case where the logic signals D1 and D2 are input to the current input / output circuit 51a, in order to make the description easy to understand. Accordingly, the first input terminal IN1 and the third input terminal IN3 in FIG. 6 are combined into one input terminal INa, and the second input terminal IN2 and the fourth input terminal IN4 in FIG. 6 are combined into one. Input terminal INb. In FIG. 7, the same components as those in FIG. 5 are denoted by the same reference numerals, and the description thereof will be omitted and only the differences from FIG. 5 will be described.
The difference between FIG. 7 and FIG. 5 is that logic circuits 101 and 102 are added to the first current control circuit 62 of FIG. 5 and logic circuits 103 and 104 are added to the second current control circuit 72 of FIG. That is, the MOS transistors 85, 87, 95, and 97 constituting the current mirror circuit have MOS transistors inserted between the respective gates and drains.
[0073]
In FIG. 7, the first current control circuit 62a includes PMOS transistors 83, 84, 121, 122 and logic circuits 101, 102, and the second current control circuit 72a includes NMOS transistors 93, 94, 123, 124. , Logic circuits 103 and 104 and inverters 125 and 126. In the first current control circuit 62a, the current control signal Sc is input to one input terminal of the logic circuit 101, and the other input terminal of the logic circuit 101 is connected to the input terminal INa. The end is connected to the gate of the PMOS transistor 83. Similarly, the current control signal Sc is input to one input terminal of the logic circuit 102, the other input terminal of the logic circuit 102 is connected to the input terminal INb, and the output terminal of the logic circuit 102 is connected to the PMOS transistor 84. Connected to the gate. Further, a PMOS transistor 121 is connected between the gate and the drain of the PMOS transistor 85, and a PMOS transistor 122 is connected between the gate and the drain of the PMOS transistor 87.
[0074]
On the other hand, in the second current control circuit 72a, the current control signal Sc is input to one input terminal of the logic circuit 103, and the other input terminal of the logic circuit 103 is connected to the input terminal INa. Is connected to the gate of the NMOS transistor 93. Similarly, the current control signal Sc is input to one input terminal of the logic circuit 104, the other input terminal of the logic circuit 104 is connected to the input terminal INb, and the output terminal of the logic circuit 104 is connected to the NMOS transistor 94. Connected to the gate. Further, an NMOS transistor 123 is connected between the gate and drain of the NMOS transistor 95, and an NMOS transistor 124 is connected between the gate and drain of the NMOS transistor 97. A current control signal Sc is input to each gate of the NMOS transistors 123 and 124 via corresponding inverters 125 and 126, respectively.
[0075]
In such a configuration, when the current control signal Sc becomes a voltage near the first power supply voltage V1, the output terminals of the logic circuits 101 and 102 become respectively near the second power supply voltage V2, and the PMOS transistors 83 and 84 become When the PMOS transistors 121 and 122 are turned off and the PMOS transistors 121 and 122 are turned off, the gates of the PMOS transistors 86 and 88 become voltages near the first power supply voltage V1 and are turned off and cut off. Therefore, the current output from the first differential amplifier circuit 52a stops. Further, when the current control signal Sc becomes a voltage near the first power supply voltage V1, the output terminals of the logic circuits 103 and 104 become near the first power supply voltage V1, respectively, and the NMOS transistors 93 and 94 turn on, respectively. When the NMOS transistors 123 and 124 are turned off, respectively, the gates of the NMOS transistors 96 and 98 become voltages near the second power supply voltage V2, and are turned off and cut off. Thus, the current input to the second differential amplifier circuit 53a stops.
[0076]
On the other hand, when the current control signal Sc becomes a voltage near the second power supply voltage V2, a signal similar to the logic signal input to the input terminal INa is output from the output terminal of the logic circuit 101, and the output of the logic circuit 102 From the end, a signal similar to the logic signal input to the input terminal INb is output. When the current control signal Sc becomes a voltage near the second power supply voltage V2, a signal similar to the logic signal input to the input terminal INa is output from the output terminal of the logic circuit 103, and the output of the logic circuit 104 is output. From the end, a signal similar to the logic signal input to the input terminal INb is output. The PMOS transistors 121 and 122 and the NMOS transistors 123 and 124 are turned on. For this reason, when the current control signal Sc becomes a voltage near the second power supply voltage V2, the current input / output circuit 51a performs the same operation as the current input / output circuit 51 of the second embodiment.
[0077]
As described above, in the signal transmission device according to the third embodiment, the same effect as that of the second embodiment can be obtained, and the current input / output from the current input / output circuit can be stopped. In addition, the current consumption can be reduced. In addition, since the current control signal is provided on a separate path from the timing adjustment logic circuit that creates logical forward and reverse signals from the input signal, current input / output from the current input / output circuit can be stopped at high speed. Also, the timing adjustment logic circuit can have a simple configuration.
[0078]
Fourth embodiment
In each of the first to third embodiments, the terminating resistor 4 is connected between the output terminals OUT and OUTB of the current input / output circuit as shown in FIG. In such a case, there is a problem that the center of the voltage amplitude changes due to a variation in process, power supply voltage, temperature and the like. Therefore, the voltage amplitude may be stabilized at a predetermined reference voltage, and such a configuration is referred to as a fourth embodiment of the present invention.
FIG. 8 is a diagram illustrating an example of a signal transmission device according to the fourth embodiment of the present invention. In FIG. 8, the transmission unit 2 shown in FIGS. 1 and 2 is shown as an example, and the same or similar components as those in FIG. 1 are denoted by the same reference numerals. Only the differences from 1 will be described.
[0079]
8 is different from FIG. 1 in that resistors 111 and 112 and a reference voltage generating circuit 113 for generating and outputting a predetermined reference voltage Vr are provided instead of the terminating resistor 4. The signal transmission device 1 of FIG.
8, the signal transmission device 110 includes a transmission unit 2, a reception unit 3, resistors 111 and 112, and a reference voltage generation circuit 113. Resistances 111 and 112 are connected in series between the output terminals OUT and OUTB of the transmission unit 2, and a reference voltage Vr from a reference voltage generation circuit 113 is applied to a connection between the resistances 111 and 112.
[0080]
From the pair of currents output from the transmission unit 2, small-amplitude differential output voltages are generated by the resistors 111 and 112 and the reference voltage generation circuit 113 and input to the reception unit 3. As described above, the current output from the transmission unit 2 and the center voltage of the voltage amplitude generated by the resistors 111 and 112 are stabilized at the reference voltage Vr, and the load on the reception unit 3 can be reduced.
[0081]
Further, in the case of the configuration of the third embodiment, the configuration shown in FIG. 9 may be employed. In FIG. 9, the reference voltage generation circuit 113 controls the output of the reference voltage Vr in response to an external current control signal Sc. When the current control signal Sc is a voltage near the first power supply voltage V1, the reference voltage generation circuit 113 stops outputting the reference voltage Vr, thereby irrespective of the signal input to the transmission unit 2. Each output terminal OUT and OUTB of the transmission unit 2 can be set to a high impedance state by the control signal Sc. 8 and 9 show an example in which a series circuit of the resistors 111 and 112 is used as a terminating resistor. However, a series circuit of the resistors 111 and 112 is connected in parallel with the terminating resistor 4 shown in FIG. In this case, the resistors 111 and 112 may be provided inside or outside the signal transmission device.
[0082]
As described above, in the signal transmission device according to the fourth embodiment, the series circuit of the resistors 111 and 112 is connected between the output terminals OUT and OUTB of the transmission unit 2, and the connection between the resistors 111 and 112 is based on the reference. The reference voltage Vr from the voltage generation circuit 113 is applied. Accordingly, a signal having a stable amplitude centered on the predetermined reference voltage can be input to the receiving unit.
[0083]
In a CMOS, a salicide technique is used in a high-speed and miniaturization process, a metal is deposited on the surface of a transistor, and the resistance values of a source and a drain are reduced. For this reason, since a transistor directly connected to the outside has a weak withstand voltage against static electricity such as surge, a transistor around the pad is generally a non-salicide transistor. Therefore, in each of the first to fourth embodiments, the MOS transistors directly connected to the outside, that is, the MOS transistors connected to the output terminals OUT and OUTB shown in FIG. 3, FIG. 5, and FIG. In order to improve the withstand voltage against static electricity, an I / O transistor that does not use salicide may be used.
[0084]
In each of the second and third embodiments, the PMOS transistors 86 and 88 and the NMOS transistors 96 and 98 shown in FIGS. 5 and 7 constitute a current mirror circuit. By using I / O transistors that do not use salicide for the NMOS transistors 95 and 97, the withstand voltage against static electricity such as surge can be further improved, and the constant current characteristics can be further improved.
[0085]
【The invention's effect】
As is clear from the above description, according to the signal transmission device of the present invention, the operation range of each of the first to fourth transistors constituting the output transistor can be widely used, and low-voltage operation can be easily realized. In addition, the effect of switching on the output can be suppressed, and a stabilizing capacitor is not required. Therefore, the chip area can be reduced, and the effect of charging / discharging current on the stabilizing capacitor can be eliminated. . Further, by dividing the power supply from the differential amplifier circuit, it is possible to reduce current consumption.
[0086]
In addition, the first to fourth transistors forming the output transistor become a part of the corresponding differential amplifier circuit portion, and can discharge and sink a constant current by a current mirror circuit configuration. The suction current value can be easily equalized.
[0087]
On the other hand, by inputting an external control signal independent of the input signal to each of the first and second current control circuits, the current output from each of the first to fourth current mirror circuits can be stopped. Thus, current consumption can be reduced. Further, since the control signal is generated and input through a path different from the signal output from the timing adjustment logic circuit section, the current input / output of the current input / output circuit section can be stopped at high speed, and the timing adjustment logic circuit can be stopped. The circuit section can also have a simple configuration.
[0088]
Each transistor connected to an output terminal through which a current from the current input / output circuit unit is input / output, and, when the transistor connected to the output terminal constitutes a current mirror circuit, each transistor constituting the current mirror circuit Since an I / O transistor is used for each transistor, surge withstand voltage can be improved.
[0089]
Further, a predetermined reference voltage is applied to two output terminals of the current input / output circuit unit through which the first and second currents are input / output via a resistor. Can be made stable around the reference voltage.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating an example of a signal transmission device according to a first embodiment of the present invention.
FIG. 2 is a diagram illustrating a configuration example of a transmission unit 2 in FIG. 1;
FIG. 3 is a diagram showing a circuit example of first and second differential amplifier circuits 21 and 22 in the current input / output circuit 12 of FIG. 2;
FIG. 4 is a diagram illustrating an example of a signal transmission device according to a second embodiment of the present invention.
FIG. 5 is a diagram showing a circuit example of a current input / output circuit 51 in FIG. 4;
FIG. 6 is a diagram illustrating an example of a signal transmission device according to a third embodiment of the present invention.
7 is a diagram showing a circuit example of a current input / output circuit 51a in FIG.
FIG. 8 is a diagram illustrating an example of a signal transmission device according to a fourth embodiment of the present invention.
FIG. 9 is a diagram illustrating another example of the signal transmission device according to the fourth embodiment of the present invention.
FIG. 10 is a diagram illustrating a configuration example of a transmission unit in a conventional signal transmission device.
11 is a diagram showing a circuit example of a current input / output circuit 203 in FIG.
12 is a diagram illustrating another example of the current input / output circuit 203 in FIG. 10;
[Explanation of symbols]
1,110 signal transmission device
2 Transmission section
3 Receiver
4 Terminating resistor
11 Timing adjustment logic circuit
12, 51, 51a Current input / output circuit
21, 52, 52a First differential amplifier circuit
22, 53, 53a Second differential amplifier circuit
23,24 PMOS transistor
25,26 NMOS transistor
61 First differential pair
62, 62a First current control circuit
63 First Current Mirror Circuit
64 Second current mirror circuit
65 First constant current source
71 Second differential pair
72, 72a Second current control circuit
73 Third current mirror circuit
74 Fourth current mirror circuit
75 Second constant current source
111,112 resistance
113 Reference voltage generation circuit

Claims (7)

A timing adjustment circuit for generating a plurality of logic signals from the input signals, adjusting the timing of each logic signal and outputting the signals, and a pair of first and second signals from the signals output from the timing adjustment circuit; In a signal transmission device that converts a pair of currents output from a transmission unit having a current input / output circuit unit that generates and inputs each current to a voltage by a terminating resistor and outputs the voltage to a reception unit,
The current input / output circuit unit includes:
First and second transistors connected in series between a predetermined first power supply voltage and a predetermined second power supply voltage;
Third and fourth transistors connected in series between the first power supply voltage and the second power supply voltage;
A first differential amplifier circuit that controls operation of the first and second transistors in accordance with a corresponding logic signal output from the timing adjustment circuit unit;
A second differential amplifier circuit that controls the operation of each of the third and fourth transistors according to a corresponding logic signal output from the timing adjustment circuit;
With
The input and output of the first current from the connection between the first transistor and the second transistor, and the input and output of the second current from the connection between the third transistor and the fourth transistor. Characteristic signal transmission device. A timing adjustment circuit for generating a plurality of logic signals from the input signals, adjusting the timing of each logic signal and outputting the signals, and a pair of first and second signals from the signals output from the timing adjustment circuit; In a signal transmission device that converts a pair of currents output from a transmission unit having a current input / output circuit unit that generates and inputs each current to a voltage by a terminating resistor and outputs the voltage to a reception unit,
The current input / output circuit unit includes:
First and third transistors for inputting and outputting the first and second currents, respectively, and the first and third transistors are provided in accordance with corresponding logic signals output from the timing adjustment circuit unit. A first differential amplifier circuit for controlling the operation of each transistor of
Second and fourth transistors for inputting and outputting the first and second currents, respectively, according to the corresponding logic signals output from the timing adjustment circuit unit; A second differential amplifier circuit section that controls the operation of each transistor of
With
The first and second transistors are connected in series between a predetermined first power supply voltage and a predetermined second power supply voltage, and the third and fourth transistors are connected to the first and second transistors, respectively. A signal transmission device connected in series between a power supply voltage and a second power supply voltage. The first differential amplifier circuit section includes:
A first differential pair to which a corresponding logic signal output from the timing adjustment circuit unit is input;
A first constant current source that supplies a predetermined current to the first differential pair;
A first current mirror circuit forming a load on one of the transistors in the first differential pair, wherein the first transistor is a transistor on the output side;
A second current mirror circuit forming a load on the other transistor in the first differential pair, wherein the third transistor forms an output-side transistor;
A first current control circuit that controls current output of each of the first and second current mirror circuits according to a logic signal input to the first differential pair;
With
The second differential amplifier circuit section includes:
A second differential pair to which a corresponding logic signal output from the timing adjustment circuit unit is input;
A second constant current source for supplying a predetermined current to the second differential pair;
A third current mirror circuit forming a load on one of the transistors in the second differential pair, wherein the second transistor forms an output-side transistor;
A fourth current mirror circuit forming a load on the other transistor in the second differential pair, wherein the fourth transistor forms an output-side transistor;
A second current control circuit that controls current output of each of the third and fourth current mirror circuits according to a logic signal input to the second differential pair;
The signal transmission device according to claim 2, further comprising: The first current control circuit controls the current output of each of the first and second current mirror circuits in response to a control signal input from the outside, and the second current control circuit controls the current output from the outside. 4. The signal transmission device according to claim 3, wherein a current output control of each of the third and fourth current mirror circuits is performed according to an input control signal. The signal transmission device according to claim 1, wherein each of the first to fourth transistors is an I / O transistor. 5. The I / O transistor according to claim 3, wherein each of the first to fourth transistors and each of the transistors forming a current mirror circuit with the corresponding first to fourth transistors are I / O transistors. The signal transmission device according to claim 1. A plurality of resistors connected in series between a first output terminal for inputting / outputting the first current and a second output terminal for inputting / outputting the second current, and the resistors connected in series 7. The signal transmission device according to claim 1, further comprising a reference voltage generation circuit for applying a predetermined reference voltage to a connection between the signal transmission devices.

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