JP2004104136A - Method for manufacturing semiconductor integrated circuit device, and method for generating mask pattern - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a large power supply stabilizing capacitor without increasing the area and wiring. <P>SOLUTION: A capacitor C for stabilizing the power supply is formed on a part in which wiring aligned by a first potential Vss of a fifth wiring layer M5 and wiring aligned by a second potential Vdd of a fourth wiring layer M4 are crossed, and a part in which wiring aligned by the second potential Vdd of the fifth wiring layer M5 and wiring aligned by the first potential Vss of the fourth wiring layer M4 are crossed. The capacitor C is formed by substantially uniformly dispersing in an at least inner region 1a of a semiconductor substrate 1 (chip). <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and more particularly, to a technique which is effective when applied to stabilize power supply and reduce power supply noise of a high-performance semiconductor integrated circuit device.

(4) With the advancement of performance and miniaturization of semiconductor integrated circuit devices, multilayer wiring technology has become an indispensable technology for manufacturing semiconductor integrated circuit devices. For example, as a method of forming a wiring layer in a semiconductor integrated circuit, a high melting point metal thin film such as an aluminum (Al) alloy or tungsten (W) is formed on an insulating film, and then a wiring pattern is formed on the wiring thin film by a photolithography process. A method is known in which a resist pattern having the same shape as the above is formed and a wiring pattern is formed by a dry etching process using the same as a mask. However, in the method using an Al alloy or the like, there is a problem that the wiring resistance is remarkably increased as the wiring is miniaturized, the wiring delay is increased, and the performance of the semiconductor integrated circuit device is reduced. Particularly in a high-performance logic LSI, a serious problem has arisen as a performance hindrance factor.

For this reason, for example, after a wiring metal having copper (Cu) as a main conductor layer is buried in a groove formed in an insulating film, excess metal outside the groove is removed by using a CMP method (chemical mechanical polishing method). Accordingly, a method of forming a wiring pattern in a groove (a so-called damascene method) is being studied.

On the other hand, there is a problem of wiring capacitance as an element that causes an operation delay of the semiconductor integrated circuit device together with the wiring resistance. High integration and miniaturization of the semiconductor integrated circuit device are not preferable because the size between wirings is reduced, so that the capacitance between wirings is increased and the delay in circuit operation is increased. Therefore, a low dielectric constant material, for example, a silicon oxide film or the like is generally used for an interlayer insulating film for insulating between wirings.

However, the present inventors have recognized that the occurrence of AC noise at the time of circuit operation becomes a problem as the degree of integration, speed, and voltage of semiconductor integrated circuit devices increase. That is, when a miniaturized circuit element operates at a high speed in a specific portion, a phenomenon occurs in which the power supply impedance of the portion locally decreases. This is observed as a local decrease in the power supply voltage supplied to the circuit, and is observed as a time-varying voltage, so that it is recognized as the occurrence of local AC noise. In a circuit driven at a low voltage, the influence of such AC noise is particularly large, which may cause instability of the circuit operation and, in a remarkable case, a malfunction.

According to the study of the present inventors, as a countermeasure against the occurrence of such AC noise, an appropriate capacitance element (power supply stabilizing capacitance) is connected between power supply lines (Vdd, Vss, (Vdd> Vss)). It is possible. Although not a known technique, the following means were examined as specific measures.

The first means is that, when the semiconductor integrated circuit device is a cell-based integrated circuit (CBIC) such as a standard cell system, a power supply stabilization is performed in a certain area in the IC using a gate insulating film or the like. This is a measure for separately forming the capacitive element (MIS capacitive element) and connecting it to the power supply line. That is, as shown in FIG. 34A, a capacitance cell C is separately provided, and as shown in FIG. 34C, the gate electrode length L and width of a MISFET (Metal Insulator Semiconductor Field Effect Transistor) in the capacitance cell. By increasing W, a sufficient capacitance value can be obtained. FIGS. 34A and 34B are diagrams for explaining the problem of the present invention. FIG. 34A is a plan view of a semiconductor integrated circuit device in which a standard cell is formed in an internal region, and FIG. FIG. 34C is an enlarged plan view, FIG. 34C is a plan view illustrating the capacitor cell in an enlarged manner, and FIG. 34D is a sectional view taken along line dd ′ in FIG. As described above, for example, the power supply line Vdd is electrically connected to the gate electrode of the MISFET in the capacitor cell to serve as one electrode of the capacitor, and the p-well region (Vss potential) and the source / drain region are used as the other electrode of the capacitor. A capacitor is formed using the electrodes as gate electrodes and the gate insulating film as a dielectric film of the capacitor. A power supply line Vss is electrically connected to the gate electrode of the pMISFET in the capacitance cell to form one electrode of the capacitance element, and the n-well region (Vdd potential) and the source / drain region are defined as the other electrodes of the capacitance element. The capacitor is formed using the gate insulating film as a dielectric film of the capacitor. According to this measure, since a dedicated capacity cell is arranged in the semiconductor integrated circuit device, there is an advantage that a relatively large stabilized capacity can be obtained.

However, this measure requires a dedicated capacitance element for stabilizing the power supply, and thus requires an extra area for forming the capacitance element, which hinders high integration. In addition, as shown in FIG. 34B, since the formation position of the capacitance cell C is limited to a specific position in the chip, for example, the generation of AC noise such as the logic block R, that is, a stabilization capacitance is required. The capacitance cell is formed at a position distant from the region to be formed. For this reason, the position where the AC noise is generated is different from the position where the stabilizing capacitor is formed, and there is a possibility that the noise cannot be removed effectively.

The second means is to use an unused basic (basic) cell as a capacitance element (MIS capacitance element) when the semiconductor integrated circuit device is a gate array circuit, and to connect this between power supply lines. is there. That is, as shown in FIG. 35B, a measure is to use a MISFET constituting a basic cell as a stabilizing capacitance. FIG. 35 is another drawing for explaining the problem of the present invention, in which (a) shows a plan view of a semiconductor integrated circuit device having a gate array formed in an internal region, and (b) shows a gate array. FIG. 2 is a plan view showing a basic cell. In the semiconductor integrated circuit device adopting the gate array system as described above, an unused basic cell is used instead of a dedicated capacitance cell as in a cell-based IC (CBIC), and FIG. A capacitance element (MIS capacitance element) similar to the capacitance element (MIS capacitance element) shown in FIG. According to this measure, since an unused basic cell is used, there is an extra increase in wiring (wiring overhead), but no extra area (area overhead) for stabilizing capacitance is required. This is advantageous for integration.

However, in this measure, as shown in FIG. 35 (b), since the existing basic cell is used, the gate electrode length L is generally short, and the capacitance per MOS transistor is small, so that a large stabilized capacitance can be obtained. It is difficult. In addition, since the formation position of the basic cell that can be used as the stabilizing capacitor is limited to a specific position in the chip, the basic cell cannot always be arranged in the vicinity of the region where AC noise is generated. For this reason, the position where the AC noise is generated is different from the position where the stabilizing capacitor is formed, and there is a possibility that the noise cannot be removed effectively.

An object of the present invention is to provide a structure and a manufacturing method of a semiconductor integrated circuit device capable of obtaining a large power supply stabilizing capacitance without increasing the area and wiring.

Another object of the present invention is to add a large stabilizing capacitance between power supply lines (Vdd and Vss), reduce AC noise, and improve the operation stability and operation reliability of the semiconductor integrated circuit device.

Another object of the present invention is to provide a technique capable of uniformly arranging stabilizing capacitors in a chip. That is, even if local AC noise is generated, a technique is provided to effectively remove noise by a stabilizing capacitor arranged near the noise generating portion and further improve the stability of the semiconductor integrated circuit device. It is in.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

The following is a brief description of an outline of typical inventions disclosed in the present application.
1. The semiconductor integrated circuit device of the present invention has a plurality of wiring layers, and includes an arbitrary first wiring layer excluding the uppermost layer among the wiring layers, and an optional second wiring layer above the first wiring layer. Wherein a capacitive element is formed in an intersection region between a first power supply wiring at a first potential included in the first wiring layer and a second power supply wiring at a second potential included in the second wiring layer. Features.
2. 2. The semiconductor integrated circuit device according to the above item 1, wherein the capacitance elements are dispersedly formed in an element formation region of the semiconductor substrate.
3. 3. The semiconductor integrated circuit device according to item 1 or 2, wherein the first power supply wiring and the second power supply wiring are formed in a mesh shape when viewed from above, and a capacitive element is formed at an intersection of the meshes.
4. 4. The semiconductor integrated circuit device according to any one of the above items 1 to 3, wherein the first and second wiring layers are arranged in an upper layer of the plurality of wiring layers.
5. 5. The semiconductor integrated circuit device according to any one of the items 1 to 4, wherein the capacitive element has the first power supply line as one electrode and is integrated with the second power supply line below the second power supply line. A conductive member formed by electrical connection is used as the other electrode, and a dielectric film formed between the one and the other electrodes. The dielectric film has a thickness of the first and second wirings. The thickness is smaller than the thickness of the interlayer insulating film between the layers.
6. 5. The semiconductor integrated circuit device according to any one of the items 1 to 4, wherein the capacitive element has the first power supply line as one electrode and is integrated with the second power supply line below the second power supply line. The conductive member formed by electrical connection is used as the other electrode, and a dielectric film formed between the one and the other electrodes. The dielectric constant of the dielectric film is the first and second wirings. It is higher than the dielectric constant of the interlayer insulating film between the layers.
7. 7. The semiconductor integrated circuit device according to item 5 or 6, wherein the dielectric film is a tantalum oxide film, a silicon nitride film, or a stacked film of a tantalum oxide film and a silicon nitride film.
8. 8. The semiconductor integrated circuit device according to the above item 5, 6, or 7, wherein the conductive member is formed in the same step as a connecting member for electrically connecting the first and second wiring layers.
9. 9. The semiconductor integrated circuit device according to any one of the items 5 to 8, wherein the conductive member is formed integrally with the second power supply wiring by using a dual damascene method.
10. 10. The semiconductor integrated circuit device according to any one of items 5 to 9, wherein the conductive member is formed by burying the conductive member in a hole formed in an interlayer insulating film that insulates the first and second wiring layers. It is.
11. 11. The semiconductor integrated circuit device according to any one of the above items 5 to 10, wherein the surface of the first power supply line and the bottom surface of the conductive member face each other to form a capacitance element, and the width of the first power supply line is smaller than that of the first power supply line. The width is wider than the width of the second power supply wiring.
12. 12. The semiconductor integrated circuit device according to any one of the above items 1 to 11, wherein the first and second wiring layers are disposed in an upper layer portion of the plurality of wiring layers, and a lower layer of the plurality of wiring layers. The line width of the power supply line arranged in the portion is configured to be smaller than the line widths of the first and second power supply lines.
13. A method for manufacturing a semiconductor integrated circuit device according to the present invention includes a method for manufacturing a semiconductor integrated circuit device, comprising: a first wiring layer having a plurality of wiring layers except for an uppermost layer; (A) forming an interlayer insulating film covering the first wiring layer and forming a hole in the interlayer insulating film on the wiring forming the first wiring layer; Forming a mask film covering a part of the holes, and (c) performing an etching process in the presence of the mask film to remove the insulating film formed on the interlayer insulating film including the bottoms of the holes or the inner surfaces of the holes. (D) removing the mask film and forming a conductive member inside the hole.
14． 14. The method for manufacturing a semiconductor integrated circuit device according to the item 13, wherein the insulating film is formed on the first wiring layer before the formation of the interlayer insulating film, or a hole is formed in the interlayer insulating film. Thereafter, it is formed by any one of a second process and a second process which is formed on the entire surface of the interlayer insulating film including the inner surface of the hole.
15. 15. The method for manufacturing a semiconductor integrated circuit device according to the above item 13 or 14, wherein the conductive member is formed in a first step integrally formed with a wiring constituting the second wiring layer, or in a conductive film filling a hole. After the formation, it is formed by any one of a second step formed by removing a conductive film on the interlayer insulating film other than the holes.
16. A method for manufacturing a semiconductor integrated circuit device according to the present invention includes a method for manufacturing a semiconductor integrated circuit device, comprising: a first wiring layer having a plurality of wiring layers except for an uppermost layer; (A) a step of sequentially depositing a first insulating film, a second insulating film, and a third insulating film on a first wiring layer, and (b) a hole formed on the third insulating film. Patterning a first mask film having an opening in a region to be etched, and etching a third insulating film in the presence of the first mask film; (c) removing the first mask film and forming a third insulating film on the third and second insulating films (D) patterning a second mask film having an opening in a region where a groove is to be formed on the fifth insulating film, thereby forming a second mask film on the fifth insulating film. Etching the fifth insulating film below, and (e) a fourth insulating film using the second mask film or the fifth insulating film as a mask. The film is etched to form a groove patterned in the fifth insulating film in the fourth insulating film, and further, the second insulating film is etched using the third insulating film as a mask to form a hole patterned in the third insulating film. Forming the second insulating film, (f) removing the third insulating film and the first insulating film exposed at the bottom of the groove and the hole, and (g) forming the first and second insulating films on the entire surface of the semiconductor substrate including the inner surface of the groove and the hole. Depositing a sixth insulating film, (h) patterning a third mask film covering a part of the hole, (i) etching the sixth insulating film in the presence of the third mask film, (j). Removing the third mask film and forming a conductive film filling the trench and the hole, (k) removing the conductive film in a region other than the groove and forming a wiring and a conductive member constituting the second wiring layer; including.
17. A method for manufacturing a semiconductor integrated circuit device according to the present invention includes a method for manufacturing a semiconductor integrated circuit device, comprising: a first wiring layer having a plurality of wiring layers except for an uppermost layer; and a second wiring layer above the first wiring layer. (A) a step of sequentially depositing a first insulating film, a second insulating film, and a third insulating film on a first wiring layer, and (b) a method of manufacturing a semiconductor integrated circuit device. Patterning a first mask film having an opening in a region where a hole is to be formed, and etching a third insulating film in the presence of the first mask film; (c) removing the first mask film; And sequentially depositing a fourth insulating film and a fifth insulating film on the second insulating film, and (d) patterning a second mask film having an opening in a region where a groove is formed on the fifth insulating film; Etching the fifth insulating film in the presence of the second mask film, (e) the second mask film or the fifth insulating film; The fourth insulating film is etched using the film as a mask to form a groove patterned in the fifth insulating film in the fourth insulating film, and further, the second insulating film is etched using the third insulating film as a mask to form a third insulating film. Forming a hole patterned in the film in the second insulating film, (f) patterning a third mask film covering a part of the hole, (g) forming a third mask film and a patterned fifth insulating film. A step of etching the first insulating film at the bottom of the hole and the third insulating film at the bottom of the groove in the presence; (h) a step of removing the third mask film to form a conductive film filling the groove and the hole; (i) Removing the conductive film in a region other than the groove and forming a wiring and a conductive member constituting the second wiring layer.
18. A method for manufacturing a semiconductor integrated circuit device according to the present invention includes a method for manufacturing a semiconductor integrated circuit device, comprising: a first wiring layer having a plurality of wiring layers except for an uppermost layer; and a second wiring layer above the first wiring layer. (A) a step of sequentially depositing a first insulating film, a second insulating film, a third insulating film, a fourth insulating film, and a fifth insulating film on the first wiring layer; 5 A first mask film having an opening in a region where a hole is formed is patterned on the insulating film, and the fifth, fourth, third, and second insulating films are etched in the presence of the first mask film to form a hole. (C) removing the first mask film, forming a second mask film on the fifth insulating film, exposing a region where the groove is to be formed, developing the second mask film, Leaving the second mask film in a region other than the region where the first mask film is formed and in the hole, and (d) performing the fifth and fourth insulation in the presence of the second mask film. Forming a groove, (e) removing the second mask film and patterning a third mask film covering a part of the hole, and (f) forming a bottom of the hole in the presence of the third mask film. Etching the first insulating film, (g) removing the third mask film and forming a conductive film to fill the trench and the hole, and (h) removing the conductive film in a region other than the trench to form a second wiring. Forming a wiring and a conductive member constituting a layer.
19. 19. The method for manufacturing a semiconductor integrated circuit device according to item 17 or 18, further comprising, before forming the third mask film, further depositing a sixth insulating film on the entire surface of the semiconductor substrate including the inner surfaces of the grooves and the holes. In the step of etching the first insulating film at the bottom of the hole, the sixth insulating film that is not covered with the third mask film is removed together with the first insulating film.
20. A method for manufacturing a semiconductor integrated circuit device according to the present invention includes a method for manufacturing a semiconductor integrated circuit device, comprising: a first wiring layer having a plurality of wiring layers except for an uppermost layer; and a second wiring layer above the first wiring layer. (A) depositing a seventh insulating film covering the first wiring layer, and (b) forming a first mask film having an opening in a region where a hole is formed on the seventh insulating film. Patterning, etching the seventh insulating film in the presence of the first mask film, and removing the seventh insulating film on the wiring constituting the first wiring layer; (c) removing the semiconductor substrate including the inner surface of the hole; Depositing a sixth insulating film on the entire surface, (d) patterning a third mask film covering a part of the hole, (e) etching the sixth insulating film in the presence of the third mask film, (F) removing the third mask film and forming a conductive film for filling the hole, and (g) conductive film in a region other than the hole. Removing and forming a conductive member connected to the wiring constituting the second wiring layer; (h) depositing a second conductive film on the entire surface of the semiconductor substrate and patterning the second conductive film to form the second wiring layer Forming a step.
21. 21. The method for manufacturing a semiconductor integrated circuit device according to any one of Items 16 to 20, wherein the first and third insulating films are made of a material having an etching selectivity with respect to the second and fourth insulating films. In this case, the thickness of the first insulating film is equal to the thickness of the third insulating film.
22. 22. The method of manufacturing a semiconductor integrated circuit device according to any one of the items 16 to 21, wherein the thickness of the first or sixth insulating film is smaller than the thickness of the second insulating film.
23. 23. The method for manufacturing a semiconductor integrated circuit device according to any one of the above items 16 to 22, wherein a dielectric constant of the first or sixth insulating film is higher than a dielectric constant of the second insulating film.
24. A mask pattern generation method according to the present invention includes a semiconductor having a plurality of wiring layers and including an arbitrary first wiring layer excluding an uppermost layer among the wiring layers, and an optional second wiring layer above the first wiring layer. A first power supply line to which a first potential is assigned among power supply lines forming a first wiring layer and a first potential among power supply lines forming a second wiring layer, which are used for manufacturing an integrated circuit device. A first step of determining an intersection area where a second power supply wiring to which a second potential different from the potential is assigned intersects; a second step of generating a hole pattern in the intersection area; And a third step of extending the wiring pattern so as not to reach the wiring regions of the first and second wiring layers adjacent to the hole pattern.
25. 13. The semiconductor integrated circuit device according to any one of the above items 1 to 12, comprising a capacity cell.
26. 26. In the semiconductor integrated circuit device according to any one of the above items 1 to 12 or 25, the second wiring layer is an uppermost wiring layer.
27. 5. The semiconductor integrated circuit device according to any one of the items 1 to 4, wherein the capacitive element has the first power supply line as one electrode and is integrated with the second power supply line below the second power supply line. A conductive member formed by electrical connection is used as the other electrode, and a dielectric film formed between the one and the other electrodes, and an interlayer insulating film between the first and second wiring layers is made of a dielectric material. An insulating film having a dielectric constant lower than the dielectric constant of the body film is included.
28. 28. The semiconductor integrated circuit device according to any one of the above items 1 to 12 or 25 to 27, wherein the capacitive elements are formed separately on the memory block and the logic block.
29. 26. The semiconductor integrated circuit device according to the item 25, wherein the capacitance cell forms an MIS capacitance element.
30. 30. The semiconductor integrated circuit device according to any one of the above items 1 to 12 or 25 to 29, wherein a connection hole for electrically connecting the wirings of the first wiring layer and the second wiring layer is formed. Using the process, a hole is formed in the intersection region, and the conductive member formed in the hole is electrically connected to the second power supply wiring and acts as one electrode of the capacitive element. It functions as the other electrode of the element.

The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
(1) A semiconductor integrated circuit device capable of obtaining a large power supply stabilizing capacitance without increasing the area and wiring can be realized.
(2) A large stabilizing capacitance is added between the power supply lines (Vdd and Vss) to reduce AC noise and improve operation stability and operation reliability of the semiconductor integrated circuit device.
(3) The stabilizing capacitors can be uniformly arranged in the chip, and even if local AC noise occurs, noise can be effectively removed by the stabilizing capacitors arranged near the noise generating portion. Thereby, the stability of the semiconductor integrated circuit device can be further improved.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals in principle, and the repeated description thereof will be omitted.

(Embodiment 1)
FIGS. 1A and 1B are plan views showing an example of a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 1A is a plan view showing an entire chip, and FIG. FIG.

As shown in FIG. 1A, in a semiconductor integrated circuit device according to the present embodiment, an internal region 1a is provided at a central portion of a semiconductor substrate 1, an I / O region 1b for input / output control is provided at an outer peripheral portion thereof, and a peripheral portion. A lead take-out pad (external terminal) 1c is arranged at the portion. For example, a logic circuit, a memory circuit (memory block) such as a RAM (Random Access Memory) or a ROM (Read Only Memory), a clock circuit, and the like are arranged in the internal area 1a, and an input / output circuit is arranged in the I / O area 1b. Be placed. A logic circuit, a memory circuit, an input / output circuit, and the like are formed using, for example, basic cells formed of semiconductor elements, and the basic cells and the semiconductor elements are connected by wiring. A wiring layer is formed in an upper layer portion of the internal region 1a. In FIG. 1B, a fifth wiring layer M5, which is the uppermost layer, and a fourth wiring layer M4 below the fifth wiring layer M5 are shown. In the present embodiment, a five-layer wiring whose uppermost layer is the fifth wiring layer M5 is illustrated, but may have five or more wiring layers, or may have four or less wiring layers. However, since it is necessary to have a multilayer wiring, it is necessary to have a wiring structure of two or more layers.

As shown in FIG. 1B, for example, among the wirings forming the fifth wiring layer M5, the power supply wiring has a first potential Vss or a second potential Vdd at a predetermined interval My. Assigned as follows. Similarly, for example, the first potential Vss or the second potential Vdd is also assigned to the power supply wiring configuring the fourth wiring layer M4 so as to have a predetermined interval Mx. In FIG. 1B, wiring other than the power supply wiring is omitted for easy viewing. The first potential Vss is, for example, 0 V as a reference potential, and the second potential Vdd is higher than the first potential Vss, for example, 1.5 to 3.3 V.

Further, as shown in FIG. 1B, the fifth wiring layer M5 and the fourth wiring layer M4 are formed in a mesh shape when viewed from above, and the wiring to which the first potential Vss of the fifth wiring layer M5 is assigned. Where the second potential Vdd of the fourth wiring layer M4 intersects with the first potential Vss of the fourth wiring layer M4 and the wiring of the fifth wiring layer M5 to which the second potential Vdd is allocated. A capacitor (capacitance element) C for stabilizing the power supply is formed at a portion where the wiring intersected by the symbol. In the present embodiment, as shown in FIG. 1B, the capacitors C are formed so as to be substantially uniformly dispersed in at least the internal region 1a of the semiconductor substrate 1 (chip) as viewed from the top. That is, the capacitance elements C are substantially uniformly dispersed in the entire region on the internal region 1a. For this reason, even if the power consumption locally increases in an arbitrary region of the internal region 1a and a factor that induces the instability of the power supply voltage occurs, the capacitor C in the vicinity thereof effectively operates, and the power supply voltage is quickly reduced. And the generation of AC noise can be effectively suppressed.

FIG. 2 is a plan view in which the internal region of FIG. 1B is further enlarged, and FIG. 3 is a sectional view taken along line III-III of FIG.

In the fifth wiring layer M5, a wiring M5s to which the first potential Vss is allocated and a wiring M5d to which the second potential Vdd is allocated are formed as the above-mentioned power supply wiring, and a signal wiring to which signals are allocated. M5sig is formed. In the fourth wiring layer M4, a wiring M4s to which the first potential Vss is allocated and a wiring M4d to which the second potential Vdd is allocated are formed as the power supply wiring, and the signal wiring M4sig to which signals are allocated is formed. Is formed.

A connecting member P is formed at a portion where the wiring M5s and the wiring M4s intersect and a portion where the wiring M5d and the wiring M4d intersect, and the upper and lower layers are electrically connected to each other via the connecting member P. You. As shown in FIG. 3, the connection member P is formed integrally with the wiring M5s, and can be a conductive member formed by a so-called dual damascene method.

The capacitor C is formed at a portion where the wiring M5s intersects with the wiring M4d and a portion where the wiring M5d intersects with the wiring M4s. The capacitor C has a conductive member Me formed integrally with the wiring M5s or M5d as one electrode and the wiring M4d or M4s as the other electrode. Then, a capacitor insulating film Ic, which is a dielectric film, is formed between the two electrodes (the conductive member Me and the wiring M4d or the wiring M4s), and the two electrodes are insulated by the capacitor insulating film Ic to form the capacitor C.

Wirings (wirings M5s, M5d, M4s, M4d, signal wirings M5sig, M4sig) constituting the fifth wiring layer M5 and the fourth wiring layer M4 are formed in grooves of a wiring-forming insulating film, and are formed in the main conductive layer Mm. And the barrier layer Mb. The main conductive layer Mm is made of copper (Cu), and the barrier layer Mb can be made of, for example, titanium nitride (TiN). Barrier layer Mb is formed to prevent diffusion of copper from the main conductive layer. The connection member P and the conductive member Me are formed in a hole formed below the wiring, and are formed integrally with the wirings M5s and M5d as described above. The connection member P and the conductive member Me also include the main conductive layer Mm and the barrier layer Mb. The main conductive layer Mm includes copper, and the barrier layer Mb includes titanium nitride.

Capacitor insulating film Ic is made of, for example, tantalum oxide (TaO _x ). The relative dielectric constant of tantalum oxide is as large as 20 or more, and a sufficiently large capacitance value of the capacitor C can be secured. The thickness tc of the capacitor insulating film Ic is determined by the thickness t (t <tc) of the interlayer insulating film between the fifth wiring layer M5 and the fourth wiring layer M4 on which the connecting member P and the conductive member Me are formed. And a sufficiently large capacitance value can be secured.

Note that a low dielectric constant material can be used as the material of the insulating film and the interlayer insulating film for forming the wiring. For example, a silicon oxide film can be used as a main constituent material. By insulating the wires with a low dielectric constant material, the capacitance between the wires can be reduced, and the signal transmission speed can be improved.

As described above, in the present embodiment, a material having a low dielectric constant, such as a low dielectric constant SOG (Spin On Glass) film or a silicon oxide film, is used for insulation between the wirings, whereby the response speed to the signal (signal transmission speed) is achieved. ) Is maintained at a high quality, a high dielectric constant material such as tantalum oxide is used as the material of the capacitor insulating film Ic, and the thickness of the capacitor insulating film Ic is reduced. By increasing the voltage, it is possible to stabilize the power supply voltage and remove AC noise.

{Circle around (2)} The capacitor C of the present embodiment is formed between different voltage power supply wirings between different wiring layers, and there is no need to separately provide a capacity cell on the semiconductor substrate 1. Therefore, there is no area overhead for forming a capacitor for stabilizing the power supply, which is advantageous for high integration. Further, it is not necessary to form an extra wiring for connecting to the capacitor for stabilizing the power supply, and the overhead of the wiring can be prevented.

Further, since the capacitor C of the present embodiment has a structure capable of securing a large capacitance value as described above, there is a concern that the capacitance value may be insufficient as in the case where the unused basic cells of the gate array are used to form the capacitor. You don't have to. That is, it is possible to suppress the area and the overhead of the wiring and to secure a large power stabilizing capacitance.

Moreover, since the capacitor C of the present embodiment is formed substantially uniformly distributed over the entire chip (semiconductor substrate 1), power consumption is locally increased at an arbitrary position and voltage instability ( Even if a factor of (AC noise generation) occurs, the power supply voltage can be quickly stabilized by the capacitor C present in the vicinity thereof, and the generation of AC noise can be suppressed effectively.

The power supply wirings M5d and M5s and the signal wiring M5sig formed in the fifth wiring layer M5 are arranged to extend mainly in the X direction (first direction), and the power supply wiring M4d formed in the fourth wiring layer M4 , M4s and the signal wiring M4sig are arranged to extend mainly in the Y direction (second direction) intersecting with the X direction. Further, the power supply wirings M3d and M3s and the signal wiring M3sig formed in the third wiring layer M3 are arranged to extend mainly in the X direction, and the power supply wirings M2d and M2s formed in the second wiring layer M2 and The signal wiring M2sig is arranged to extend mainly in the Y direction. Power supply wirings M1d and M1s and signal wiring M1sig are formed in the first wiring layer M1, and the power supply wirings M1d and M1s are arranged to extend mainly in the X direction. Power supply wiring M1s is electrically connected, for example, to the source region of n-channel MISFET Qn, and power supply wiring M1d is electrically connected, for example, to the source region of p-channel MISFET Qp. The power lines M5d, M4d, M3d, M2d, and M1d are electrically connected to each other, and the second potential Vdd is supplied from the power line M5d to the power line M1d. The power wirings M5s, M4s, M3s, M2s, and M1s are electrically connected to each other, and the first potential Vss is supplied from the power wiring M5s to the power wiring M1s. The inside of the basic cell is mainly connected by the signal wiring M1sig, and the basic cells are mainly connected by the signal wirings M1sig, M2sig, M3sig, M4sig, and M5sig.

In the present embodiment, for example, power supply wirings M5d, M5s formed in fifth wiring layer M5, which is an upper layer, and power supply wirings M4d, M4s formed in fourth wiring layer M4, are first wiring layers, which are lower layers. The wiring width is wider than the power wirings M1d and M1s formed in M1, the power wirings M2d and M2s formed in the second wiring layer M2, and the power wirings M3d and M3s formed in the third wiring layer M3. In the present embodiment, since the capacitor C is configured using the power supply wirings M5d, M5s, M4d, and M4s in the upper layer, which has a wider wiring width than the lower layer, the capacitance of the capacitor C can be reduced while suppressing an increase in the number of processes. Can be larger. Further, the signal wirings M3sig, M2sig, and M1sig are densely formed by reducing the wiring widths of the power supply wirings M1d, M1s, M2d, M2s, M3d, and M3s in the lower layer portion, so that the connections within the basic cells and between the basic cells are formed. The degree of freedom can be improved and logic can be highly integrated.

As described above, by using the power supply wirings M5d, M5s, M4d, and M4s of the fifth wiring layer M5 and the fourth wiring layer M4, which are the upper layers, and forming the capacitor C therebetween, power supply is stabilized. And the capacitance of the capacitor can be increased. Further, an increase in the number of processes can be minimized.

Although the present embodiment has been described using a five-layer wiring as an example, in the case of a seven-layer wiring structure, for example, a capacitor C is formed by using a seventh wiring layer M7 and a sixth wiring layer M6 as upper wirings. Can be configured.

By forming the capacitor C in the upper wiring layer having the wide power supply wiring, the logic is highly integrated, the capacitance of the capacitor C is increased, and voltage instability (AC noise generation) is reduced. it can. Further, in the present embodiment, two layers of the uppermost layer and the wiring layer therebelow are used as the upper layer portion, but it is a matter of course that three layers may be used.

In this embodiment, the pad 1c is used as an external terminal. However, the present invention is not limited to this, and a bump electrode (external terminal) electrically connected to the fifth wiring layer M5 may be formed on the fifth wiring layer M5. A structure provided on the final passivation film may be used. Power supply wiring and signal bump electrodes may be provided on the internal region 1a.

The wiring structure below the third wiring layer and the structure of the MISFET and the like formed on the main surface of the semiconductor substrate 1 will also be described in the following description of the manufacturing method.

FIGS. 4 to 19 are sectional views showing an example of a method for manufacturing the semiconductor integrated circuit device of the present embodiment in the order of steps. The steps will be described below in the order of steps using the drawings.

First, as shown in FIG. 4, a semiconductor substrate 1 made of, for example, p ^- type single crystal silicon is prepared, and an element isolation region 2 is formed on a main surface of the semiconductor substrate 1. The element isolation region 2 can be formed, for example, as follows. First, a silicon oxide film (SiO) and a silicon nitride film (SiN) are sequentially formed on the main surface of the semiconductor substrate 1, and this silicon nitride film is etched using a patterned photoresist film. A shallow groove is formed in the semiconductor substrate 1 using the nitride film as a mask. Thereafter, an insulating film for filling the shallow groove, for example, a silicon oxide film is deposited, the silicon oxide film in a region other than the shallow groove is removed by using a CMP (Chemical Mechanical Polishing) method, and a silicon nitride film is formed by a wet etching method or the like. Remove. Thereby, the element isolation region 2 is formed.

Next, impurities are ion-implanted using the patterned photoresist film as a mask to form a p-well 3 and an n-well 4. An impurity having a p-type conductivity such as boron (B) is ion-implanted into the p-well 3, and an impurity having a n-type conductivity such as phosphorus (p) is ion-implanted into the n-well 4. Thereafter, impurities for controlling the threshold value of the MISFET may be ion-implanted into each well region.

Next, a silicon oxide film serving as the gate insulating film 5, a polycrystalline silicon film serving as the gate electrode 6, and a silicon oxide film serving as the cap insulating film 7 are sequentially deposited to form a laminated film, and photolithography is performed. The laminated film is etched using the resist film as a mask. Thus, a gate insulating film 5, a gate electrode 6, and a cap insulating film 7 are formed. The gate insulating film 5 can be formed by, for example, a thermal CVD method, and the gate electrode 6 can be formed by a CVD (Chemical Vapor Deposition) method. In order to reduce the resistance value of the gate electrode 6, an n-type or p-type impurity may be doped according to the channel type of the MISFET. That is, the gate electrode of the n-channel MISFET may be doped with an n-type impurity, and the gate electrode of the p-channel MISFET may be doped with a p-type impurity. In this case, an ion implantation method can be used. The upper the WSi _x of the gate electrode 6, MoSi _x, TiSi _x, may be laminated refractory metal silicide film such as TaSi _x, titanium nitride, metals such as tungsten over the barrier metal layer such as tungsten nitride A layer may be formed. Thereby, the sheet resistance value of the gate electrode 6 can be reduced, and the operation speed of the MISFET can be improved. The cap insulating film 7 can be deposited by, for example, a CVD method.

Next, after depositing a silicon oxide film on the semiconductor substrate 1 by, for example, the CVD method, the silicon oxide film is anisotropically etched to form a sidewall spacer 8 on the side wall of the gate electrode 6. Thereafter, using the photoresist film as a mask, an n-type impurity (for example, phosphorus or arsenic) is ion-implanted into the p-well 3 to form an n-type semiconductor region 9 on both sides of the gate electrode 6 on the p-well 3. N-type semiconductor region 9 is formed in a self-aligned manner with respect to gate electrode 6 and sidewall spacer 8. Further, the n-type semiconductor region 9 functions as a source / drain region of the n-channel MISFET Qn. Similarly, a p-type impurity (for example, boron) is ion-implanted into n-well 4 using the photoresist film as a mask, and p-type semiconductor regions 10 are formed on both sides of gate electrode 6 on n-well 4. The p-type semiconductor region 10 is formed in a self-aligned manner with respect to the gate electrode 6 and the sidewall spacer 8, and functions as a source / drain region of the p-channel MISFET Qp.

Note that a low-concentration impurity semiconductor region may be formed before the formation of the sidewall spacer 8, and a high-concentration impurity semiconductor region may be formed after the formation of the sidewall spacer 8, to form a so-called LDD (Lightly Doped Drain) structure.

Next, as shown in FIG. 5, after a silicon oxide film is deposited on the semiconductor substrate 1 by a sputtering method or a CVD method, the silicon oxide film is polished by, for example, a CMP method to thereby flatten the surface. One interlayer insulating film 11 is formed.

Next, a connection hole 12 is formed in the first interlayer insulating film 11 by using a photolithography technique. The connection hole 12 is formed in a necessary portion on the n-type semiconductor region 9 or the p-type semiconductor region 10.

Next, the plug 13 is formed in the connection hole 12 as follows, for example. First, a titanium nitride (TiN) film is formed on the entire surface of the semiconductor substrate 1 including the inside of the connection hole 12. The titanium nitride film can be formed by, for example, a CVD method. Since the CVD method is excellent in step coverage of the film, a titanium nitride film having a uniform thickness can be formed even in the fine connection hole 12. Next, a tungsten (W) film filling the connection hole 12 is formed. The tungsten film can be formed by, for example, a CVD method. In the case of the CVD method, similarly, the inside of the fine connection hole 12 can be filled with tungsten. Next, the plug 13 can be formed by removing the titanium nitride film and the tungsten film in regions other than the connection holes 12 by, for example, a CMP method. Before the formation of the titanium nitride film, for example, a titanium (Ti) film may be deposited, and heat treatment may be performed to silicide the semiconductor substrate (n-type or p-type semiconductor regions 9 and 10) at the bottom of the connection hole 12. . By forming such a silicide layer, the contact resistance at the bottom of the connection hole 12 can be reduced.

Next, a tungsten film is formed on the entire surface of the semiconductor substrate 1, and the tungsten film is patterned by using a photolithography technique to form the wiring 14 of the first wiring layer. The tungsten film can be formed by a CVD method or a sputtering method.

Next, as shown in FIG. 6, an insulating film covering the wiring 14 such as a silicon oxide film is formed, and the insulating film is planarized by the CMP method to form the second interlayer insulating film 15.

Next, a photoresist film having an opening in a region where a connection hole is to be formed is formed on the second interlayer insulating film 15, and etching is performed using the photoresist film as a mask. Thereby, a connection hole 16 is formed in a predetermined region of the second interlayer insulating film 15.

Next, a plug 17 is formed in the connection hole 16. The plug 17 can be formed as follows. First, a barrier layer is formed on the entire surface of the semiconductor substrate 1 including the inside of the connection hole 16, and a copper (Cu) film filling the connection hole 16 is formed. After that, the copper film and the barrier film in the region other than the connection hole 16 are removed by the CMP method to form the plug 17.

The barrier layer has a function of preventing copper from diffusing into the periphery of the second interlayer insulating film 15 and the like, and may be, for example, a titanium nitride film. The metal film is not limited to the titanium nitride film, but may be another metal film as long as it has a copper diffusion preventing function. For example, tantalum (Ta) or tantalum nitride (TaN) can be used instead of titanium nitride. The barrier layer in the next step and subsequent steps will be described using a titanium nitride film as an example. However, it can be replaced with tantalum, tantalum nitride, or the like as described above.

The copper film functions as a main conductive layer and can be formed by, for example, a plating method. Before forming a plating film, a thin copper film can be formed as a seed film by a sputtering method. Further, the copper film may be formed by a sputtering method. In this case, after the copper film is formed by sputtering, the copper film may be fluidized by heat treatment to improve the filling characteristics in the connection hole or the wiring groove. The case where the copper film in the next step and thereafter is formed by a plating method is exemplified, but the sputtering method may be used in the same manner as described above.

Next, as shown in FIG. 7, a stopper insulating film 18 is formed on the second interlayer insulating film 15, and further an insulating film 19 for forming a second wiring layer is formed. The stopper insulating film 18 is a film serving as an etching stopper when a groove is formed in the insulating film 19, and is made of a material having an etching selectivity with respect to the insulating film 19. The stopper insulating film 18 is, for example, a silicon nitride film. The insulating film 19 is made of a material having a small dielectric constant in order to reduce the line capacitance between the wirings. The insulating film 19 is, for example, a silicon oxide film. Note that a second-layer wiring described below is formed on the stopper insulating film 18 and the insulating film 19. Therefore, the total film thickness is determined by the design film thickness required for the second wiring layer. In consideration of reducing the capacitance between wirings, it is desirable that the stopper insulating film 18 made of a silicon nitride film having a high dielectric constant be as thin as possible as long as the stopper insulating film 18 is thick enough to achieve the stop function.

Next, a photoresist film having an opening formed in a wiring pattern is patterned on the insulating film 19, and first etching is performed using the photoresist film as a mask. By the first etching, a part of the wiring groove 20 is formed in the insulating film 19. In this etching, a condition is selected in which the silicon oxide film is easily etched and the silicon nitride film is hardly etched. Thus, the stopper insulating film 18 (silicon nitride film) is used as an etching stopper. Thereafter, a condition for etching the silicon nitride film is selected, and a second etching is performed. As described above, since the stopper insulating film 18 is formed to be sufficiently thin, overetching in the second etching may be small, and excessive etching of the second interlayer insulating film 15 can be suppressed. By using the two-stage etching as described above, the depth of the wiring groove 20 can be formed uniformly and reliably.

Next, the wiring 21 of the second wiring layer is formed inside the wiring groove 20. The wiring 21 includes a barrier layer and a main conductive layer. The barrier layer is, for example, a titanium nitride film, and the main conductive layer is, for example, copper. The formation of the wiring 21 is performed as follows. First, a titanium nitride film is formed on the entire surface of the semiconductor substrate 1 including the inside of the wiring groove 20, and then a copper film filling the wiring groove 20 is formed. For example, a CVD method is used to form the titanium nitride film, and a plating method is used to form the copper film. Before the formation of the copper film by the plating method, a copper seed film can be formed by, for example, a sputtering method. Thereafter, the wiring 21 can be formed by removing the copper film and the titanium nitride film in the region other than the wiring groove 20 by the CMP method. The point that the titanium nitride film can be replaced with another material and the point that the copper film can be formed by another manufacturing method such as a sputtering method are as described above.

Next, as shown in FIG. 8, a stopper insulating film 22, an interlayer insulating film 23, a stopper insulating film 24 for forming a wiring, and an insulating film 25 for forming a wiring are formed on the wiring 21 and the insulating film 19 of the second wiring layer. Form sequentially. The stopper insulating films 22 and 24 are made of a material having an etching selectivity with respect to the interlayer insulating film 23 or the insulating film 25, and may be, for example, a silicon nitride film. On the other hand, the interlayer insulating film 23 or the insulating film 25 can be a silicon oxide film.

Next, a photoresist film having an opening formed in the wiring pattern of the third wiring layer is patterned on the insulating film 25, and the insulating film 25 is etched using the photoresist film as a mask. In this etching, a condition is selected in which the silicon nitride film is hardly etched and the silicon oxide film is easily etched. Thus, the insulating film 25 can be etched using the stopper insulating film 24 as an etching stopper. Further, the conditions for etching the silicon nitride film are selected, and the stopper insulating film 24 is etched. Thereby, the wiring groove 26 is formed in the wiring pattern of the third wiring layer. The point that excessive etching of the interlayer insulating film 23 can be suppressed by the two-stage etching is the same as the case of the wiring groove 20 of the second wiring layer described above.

Next, the interlayer insulating film 23 and the stopper insulating film 22 are etched using the photoresist film formed in the pattern of the connection hole connecting the third wiring layer and the second wiring layer as a mask. This etching is performed in two stages in the same manner as described above. When the interlayer insulating film 23 is etched (first etching), the stopper insulating film 22 functions as an etching stopper, and then the stopper insulating film 22 is etched (second etching). I do. Thereby, the connection hole 27 is formed.

Next, the wiring 28 of the third wiring layer is formed inside the wiring groove 26 and the connection hole 27. A connecting member for connecting the wiring 28 and the wiring 21 as a lower layer wiring is formed integrally with the wiring 28. That is, the wiring 28 is formed by a so-called dual damascene method. The wiring 28 is formed, for example, as follows. First, a titanium nitride film serving as a barrier layer is formed on the entire surface of the semiconductor substrate 1 including the inside of the wiring groove 26 and the connection hole 27 by, for example, a CVD method, and then a copper film filling the wiring groove 26 and the connection hole 27 is formed by, for example, a plating method. Formed by After that, the copper film and the titanium nitride film in the region other than the wiring groove 26 are removed by using the CMP method, and the wiring 28 formed integrally with the connecting member is formed.

Note that a so-called single damascene method in which a connection member (plug) is formed first, and then the wiring 28 is formed in the wiring groove, like the second wiring layer described above, may be used. In the case of the dual damascene method, the method of forming the connection hole 27 after forming the wiring groove 26 (first groove method) has been described. However, the connection hole 27 is formed first by photolithography, and then the wiring groove 26 is formed. The wiring groove 26 and the connection hole 27 may be formed by a method of forming (a first hole method) by photolithography.

Next, as shown in FIG. 9, a stopper insulating film 29, an interlayer insulating film 30, a stopper insulating film 31 for forming a wiring, and an insulating film 32 for forming a wiring are sequentially formed on the insulating film 25 and the wiring. These insulating films 29 to 32 are the same as the stopper insulating film 22, the interlayer insulating film 23, the stopper insulating film 24 for forming the wiring, and the insulating film 25 for forming the wiring, respectively. Further, a connection hole for a connection member is formed in the stopper insulating film 29 and the interlayer insulating film 30, and a wiring groove is formed in the stopper insulating film 31 and the insulating film 32 in the same manner as in the case of the third wiring layer. A wiring 33 in the fourth wiring layer is formed in the same manner as the wiring 28 in the layer. As described above, the wiring 33 is formed by a dual damascene method integrally formed with a connection member connected to the lower wiring 28, but may be formed by a single damascene method in which the connection member and the wiring are formed separately. This is the same as in the case of the third wiring layer.

Note that the methods of forming the insulating films 29 to 32, the connection holes, the wiring grooves, and the wirings 33 are the same as those of the corresponding members of the third wiring layer, and thus description thereof is omitted. However, since it is formed above the third wiring layer, the design rule can be relaxed, and as shown in the cross-sectional view of FIG. 10, the wiring width and other dimensions are formed larger than the third wiring layer. However, it is needless to say that the present embodiment is not limited to the point where the size is increased, and may be formed with the same size (design rule) as the wiring 28 of the third wiring layer.

Next, as shown in FIG. 10, insulating films 34, 35 and 36 are sequentially formed on the wiring 33 and the insulating film 32 of the fourth wiring layer.

The insulating film 34 is made of a material having an etching selectivity with respect to the insulating film 35, and is made of, for example, a silicon nitride film. The insulating film 34 functions as an etching stopper when etching the insulating film 35 as described later. The film thickness of the insulating film 34 needs to be sufficient to function as an etching stopper, but is preferably thin from the viewpoint of reducing the line capacitance. The thickness of the insulating film 34 may be, for example, 50 nm.

(4) The insulating film 35 functions as an interlayer insulating film that insulates the fourth and fifth wiring layers. For this reason, a material having a small dielectric constant is used as the material of the insulating film 35, and for example, a silicon oxide film can be applied. As a material having a smaller dielectric constant, the insulating film 35 may be a silicon oxide film to which fluorine is added or an SOG (Spin On Glass) film. As will be described later, a connecting member for connecting the wiring 33 of the fourth wiring layer and the wiring of the fifth wiring layer, and a conductive member serving as an electrode forming the capacitor C are formed on the insulating film 35. The thickness of the insulating film 35 is, for example, 400 nm.

The insulating film 36 is made of a material having an etching selectivity with respect to the insulating film (silicon oxide film) formed thereon and the insulating film 35. For example, a silicon nitride film can be exemplified. The thickness of the insulating film 36 may be any thickness as long as it can function as an etching stopper when etching the upper insulating film (silicon oxide film). On the other hand, the thickness of the insulating film 36 is preferably small from the viewpoint of reducing the inter-wiring capacitance of the insulating film 36 and the fifth wiring layer formed on the insulating film thereabove. The thickness of the insulating film 36 is, for example, 50 nm.

Next, as shown in FIG. 11, a photoresist film 37 having an opening in a region where a connection member or a conductive member is to be formed is formed on the insulation film 36, and the insulation film 36 is etched using the photoresist film 37 as a mask. . This etching condition is a condition for etching the insulating film 36 (for example, a silicon nitride film), and is generally a condition for etching a silicon oxide film. Since the insulating film 35 is sufficiently thinner, there is no fear that the insulating film 35 is excessively etched. As will be described later, the patterned insulating film 36 is used as an etching mask when forming a connection hole or a hole for forming a conductive member in the insulating film 35. Note that a mask used for this photolithography can be used in combination with a mask for forming a connection member and a mask for forming a conductive member (capacitor C).

Next, as shown in FIG. 12, an insulating film 38 and an insulating film 39 are formed on the patterned insulating film 36.

(4) The insulating film 38 is an insulating film for forming the wiring of the fifth wiring layer by a damascene method, and is made of, for example, a silicon oxide film. The insulating film 38 also has a function of insulating the wirings of the fifth wiring layer from each other. Therefore, the insulating film 38 is preferably made of a material having a low dielectric constant, and a silicon oxide film satisfies the condition. The insulating film 38 may be made of a silicon oxide film or SOG film containing fluorine having a lower dielectric constant. The film thickness of the insulating film 38 is determined by the film thickness required for the wiring of the fifth wiring layer in design, and can be, for example, 1000 nm when the fifth wiring layer M5 is the uppermost layer.

(4) The insulating film 39 is used as a hard mask used for forming a wiring groove for forming a wiring of the fifth wiring layer. The insulating film 39 preferably has an etching selectivity with respect to the insulating film 38. For example, using a TEOS (tetraethoxysilane) gas as a source gas, a silicon oxide film (hereinafter referred to as a TEOS oxide film) formed by a plasma CVD method. ) Can be used.

Next, as shown in FIG. 13, a photoresist film 40 is formed. The photoresist film 40 has an opening in a region where the wiring of the fifth wiring layer is formed. The insulating film 39 is etched using the photoresist film 40 as a mask, and the insulating film 39 is patterned.

Next, as shown in FIG. 14, the insulating film 38 is etched using the photoresist film 40 or the insulating film 39 as a mask. Thereby, the wiring groove 41 is formed. Further, etching is continuously performed, and the insulating film 35 is etched using the patterned insulating film 36 as a mask. Thus, a part of the connection hole 42 and the hole 43 for forming the conductive member are formed. In this etching, a condition is selected in which the silicon oxide film is easily etched and the silicon nitride film is hardly etched. By selecting such conditions, the insulating film 36 made of a silicon nitride film functions as an etching stopper when forming the wiring groove 41 and at the same time functions as a mask when forming the connection holes 42 and the holes 43.

Next, the photoresist film 40 is removed, and the exposed insulating film 36 is removed by etching as shown in FIG. In this etching, conditions for etching the silicon nitride film are selected. By etching the extra silicon nitride film (insulating film 36) in this manner, the capacitance between lines can be reduced, and the response speed of the semiconductor integrated circuit device can be improved.

Next, as shown in FIG. 16, a tantalum oxide film 44 is formed on the entire surface of the semiconductor substrate 1. The tantalum oxide film 44 functions as a capacitor insulating film of the capacitor C. The tantalum oxide film 44 has a higher relative dielectric constant of 20 or more than a silicon nitride film or the like, and can obtain a large capacitor capacity even with a small occupied area. Although tantalum oxide is illustrated here, a material having a higher dielectric constant such as BST or PZT may be used. The thickness of the tantalum oxide film 44 is such that no leak current occurs, and is preferably as thin as possible. For example, 50 nm can be exemplified. The tantalum oxide film 44 is formed by, for example, a CVD method. Since the film is formed by the CVD method, a film having excellent step coverage can be formed. In addition, a film formed by a CVD method is generally amorphous in an as-deposited state. Therefore, a heat treatment for crystallizing the tantalum oxide film 44 may be performed. The relative permittivity of the crystallized tantalum oxide film is further increased to about 40, and the capacitance of the capacitor can be further increased. Further, in the as-deposited state or the crystallized state, tantalum oxide may have oxygen defects, and such oxygen defects may cause a leak current. Therefore, heat treatment in an oxidizing atmosphere for recovering oxygen defects in the tantalum oxide film 44 may be performed. Since the thickness of the tantalum oxide film 44 from which oxygen defects have been recovered can be reduced, a larger capacitor capacity can be secured.

Next, as shown in FIG. 17, a photoresist film 45 is formed on the tantalum oxide film 44. The photoresist film 45 is formed so as to cover a region where the capacitor C is formed. In this case, as the photolithography mask, the mask for forming the conductive member used in FIG. 11 can be used. Since the photoresist is formed in a pattern opposite to that of the step of FIG. 11, the photoresist is used in a manner opposite to the positive or negative photoresist. In this step, the pattern of the photoresist film 45 is formed to be slightly wider than the mask pattern. By forming the photoresist film 45 pattern large in this way, the misalignment of the mask can be compensated and the capacitor insulating film can be reliably formed. Such expansion of the photoresist pattern can be performed by adjusting the exposure conditions.

Next, the tantalum oxide film 44 is etched using the photoresist film 45 as a mask to form a capacitor insulating film Ic.

Next, as shown in FIG. 18, the photoresist film 45 is removed, and a titanium nitride film 47 is formed on the entire surface of the semiconductor substrate 1. The titanium nitride film 47 functions as a copper diffusion barrier film, and serves as the barrier layer Mb described above. The material is not limited to titanium nitride and may be made of tantalum, tantalum nitride, or the like, as long as it has a function of preventing diffusion of copper. The titanium nitride film 45 is formed by, for example, a CVD method. According to the CVD method, a film having excellent step coverage can be formed, and no void or the like is formed at the bottom corner of the connection hole 42 or the hole 43, and a blocking film excellent in preventing copper diffusion can be formed.

Next, as shown in FIG. 19, a copper film 48 is formed on the entire surface of the semiconductor substrate 1. The copper film 48 is to be the main conductive layer Mm described above. By using copper, the wiring resistance can be reduced, the response speed of the semiconductor integrated circuit device can be improved, and the performance can be improved.

Then, the copper film 48 and the titanium nitride film 47 are polished by the CMP method to remove the copper film 48 and the titanium nitride film 47 on the insulating film 39. Thereby, the semiconductor integrated circuit device as shown in FIG. 3 is almost completed. The semiconductor integrated circuit device is completed through processes such as formation of a passivation film and a bonding pad portion, and packaging, but subsequent processes are omitted.

According to the semiconductor integrated circuit device of the present embodiment, since the capacitor C is formed between the power supply wiring of the fifth wiring layer and the power supply wiring of the fourth wiring layer, even if the power supply voltage fluctuates, the fluctuation occurs. And the occurrence of AC noise can be suppressed to improve the operation reliability of the semiconductor integrated circuit device. Further, since the capacitor C is formed between the wiring layers, there is no increase in the occupied area of the semiconductor substrate for forming the capacitor, and the structure is easy to integrate the semiconductor integrated circuit device. Furthermore, since the capacitors C are uniformly distributed over substantially the entire surface of the semiconductor substrate 1, even if a local increase in power consumption or the like occurs in a specific location, any one of the capacitors C in the vicinity is effective. And the AC noise can be effectively reduced.

In the present embodiment, the case where the connecting member P and the conductive member Me between the fifth wiring layer and the fourth wiring layer are formed in a single hole is illustrated, but as shown in FIG. , Connecting members P _{1 to} P ₄ and conductive members Me _{1 to} Me ₄ . In the case where a connection member or a conductive member is formed by forming a plurality of small hole patterns in this manner, since the hole processing can be performed according to the same design rules as the hole pattern of the lower layer, the conditions of photolithography can be shared, and the process development can be performed. This has the effect of shortening the period and improving the stability of the process. On the other hand, since a large number of holes are formed, there is no increase in connection resistance or decrease in the capacity of the capacitor C. It is needless to say that the number of divisions is not limited to four, and may be smaller (such as two) or larger (such as nine).

In the present embodiment, the case where the tantalum oxide film 44 is formed of one layer is described, but the tantalum oxide film 44 may be formed of a multilayer film of two or more layers. In this case, the leak current of the tantalum oxide film 44 can be reduced. That is, when the tantalum oxide film 44 is formed of a polycrystalline film, it is considered that the leakage path is mostly present at the crystal grain boundary. In such a case, if the tantalum oxide film 44 is composed of one layer, a leak path will be formed penetrating in the film thickness direction. On the other hand, when the tantalum oxide film 44 is composed of two layers, the grain boundaries become discontinuous at the interface, and the leakage path is cut off. This has the effect of reducing the leakage current.

(Embodiment 2)
21 to 23 are sectional views showing a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention in the order of steps. The manufacturing method of the present embodiment is the same as the steps up to FIG. 14 in the first embodiment.

後 After removing the photoresist film 40 in FIG. 14, a photoresist film 50 is formed as shown in FIG. The photoresist film 50 is similar to the photoresist film 45 in FIG. 17 of the first embodiment. That is, it is formed so as to cover the hole 43 in the region where the capacitor C is formed.

(4) An etching process is performed by selecting conditions for etching the silicon nitride film in the presence of the photoresist film 50. As shown in FIG. 22, an insulating film 34, which is a silicon nitride film, remains at the bottom of the hole 43 in the region where the capacitor C is formed, and the insulating film 34 functions as the capacitor insulating film Ic of the capacitor C. On the other hand, the insulating film 34 at the bottom of the connection hole 42 is etched to expose the wiring surface of the fourth wiring layer. Further, the insulating film 36 (silicon nitride film) at the bottom of the wiring groove 41 is also removed by etching.

Thereafter, a titanium nitride film and a copper film are formed in the same manner as in the first embodiment, and thereafter, unnecessary titanium nitride film and copper film are removed by a CMP method to form wirings M5s, M5sig, and M5d of the fifth wiring layer. .

According to the present embodiment, the insulating film 34 can be used as the capacitor insulating film, and the manufacturing process can be simplified.

(Embodiment 3)
24 and 25 are sectional views showing a method of manufacturing a semiconductor integrated circuit device according to still another embodiment of the present invention in the order of steps. The manufacturing method of the present embodiment is the same as the steps up to FIG. 14 in the first embodiment.

After removing the photoresist film 40 in FIG. 14, a tantalum oxide film 51 is formed as shown in FIG. 24 without etching the insulating film 34. By leaving the insulating film 34 made of a silicon nitride film under the tantalum oxide film 51 in this manner, the heat treatment (oxidation reforming process) of the tantalum oxide film 51 in an oxidizing atmosphere can be sufficiently performed. That is, the insulating film 34 can be used as an oxygen blocking film at the time of the oxidation reforming process of the tantalum oxide film 51. Therefore, the leakage current of the tantalum oxide film 51 can be reduced, and the thin tantalum oxide film 51 can be formed. Therefore, the capacitance of the capacitor C can be increased. Further, the dielectric constant of the tantalum oxide film 51 can be improved, and the capacitance of the capacitor C can be increased. Further, when the insulating film 34 does not exist, there is a concern that the metal of the lower wiring layer is oxidized and the adhesiveness between the metal and the tantalum oxide film 51 is reduced. However, in the present embodiment, it becomes an oxygen blocking film. Since the insulating film 34 exists, there is no such concern.

Next, as shown in FIG. 25, an etching process is performed in the presence of the photoresist film 52 to remove the tantalum oxide film 51, the insulating film 34, and the insulating film 36. Thus, a capacitor insulating film Ic including the tantalum oxide film 51 and the insulating film 34 is formed. Subsequent steps are the same as in the first embodiment.

According to the present embodiment, by using the insulating film 34 as the oxygen blocking film, the leak characteristics of the tantalum oxide film 51 and the dielectric constant can be improved. Further, the bonding stability of the tantalum oxide film 51 can be improved. With these effects, the reliability of the semiconductor integrated circuit device can be improved, and stable operation can be improved.

(Embodiment 4)
26 to 30 are sectional views showing a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention in the order of steps. The manufacturing method of the present embodiment is the same as the steps up to FIG. 9 in the first embodiment.

After forming the fourth wiring layer shown in FIG. 9, insulating films 61 to 65 are sequentially formed as shown in FIG. 26, and a conductive member Me to be one electrode of the capacitor C is formed on the insulating film 65. A photoresist film 66 having an opening in the region where the connection member P is to be formed is formed. The photoresist film 66 is the same as the photoresist film 37 of the first embodiment.

Insulating film 61 is made of, for example, a silicon nitride film, and is similar to insulating film 34 in the first embodiment. The insulating film 62 is made of, for example, a silicon oxide film, and is similar to the insulating film 35 of the embodiment. Insulating film 63 is made of, for example, a TEOS oxide film. Insulating film 64 is made of, for example, a silicon oxide film, and is similar to insulating film 38 of the first embodiment. The insulating film 65 is similar to the insulating film 39 of the first embodiment.

Next, as shown in FIG. 27, the insulating films 65, 64, 63, and 62 are etched using the photoresist film 66 as a mask. At this time, conditions are selected such that the silicon oxide film is etched and the silicon nitride film is hardly etched so that the insulating film 61 acts as an etching stopper. Thereby, a hole 67 in which the conductive member Me is formed and a part of the connection hole 68 in which the connection member P is formed are formed.

Next, as shown in FIG. 28, after removing the photoresist film 66 and forming a new photoresist film, the photoresist film 66 is formed so that an opening is formed in a region of the fifth wiring layer where wiring is formed. Is exposed. Thereafter, the photoresist film is developed so that the exposed portion is removed, and a patterned photoresist film 69 is formed. During this patterning, the photoresist film inside the hole 67 and the connection hole 68 is not sufficiently exposed, and the photoresist film 69 remains in the hole.

Next, as shown in FIG. 29, the insulating film 65 and the insulating film 64 are etched in the presence of the photoresist film 69. When the insulating film 64 is etched, the insulating film 63 located thereunder functions as an etching stopper. Thus, the wiring groove 70 is formed.

Next, as shown in FIG. 30, the photoresist film 69 is removed, and a photoresist film 71 covering the hole 67 in which the conductive member Me is formed is formed similarly to the photoresist film 45 of the first embodiment. An etching process is performed by selecting conditions for etching the silicon nitride film in the presence of the photoresist film 71. Thus, the insulating film 61 (silicon nitride film) at the bottom of the connection hole 68 is removed, exposing the wiring surface of the lower wiring layer. Further, the insulating film 61 remains at the bottom of the hole 67 where the conductive member Me is formed, and forms the capacitor insulating film Ic of the capacitor C. Subsequent steps are the same as in the first embodiment.

According to the manufacturing method of the present embodiment, unlike the first to third embodiments, the connection hole 68 and the hole 67 are formed first, and then the wiring groove 70 is formed. For this reason, even if the mask alignment between the wiring groove 70 and the connection holes 68 and the holes 67 is misaligned, the openings of the connection holes 68 and the holes 67 are secured. Therefore, a contact area below the connection hole 68 is secured, and there is no increase in contact resistance. In addition, a facing area of the conductive member Me serving as an electrode of the capacitor C is secured, and a capacitance value of the capacitor can be secured.

In this embodiment, as in the third embodiment, a tantalum oxide film is formed on the entire surface of the semiconductor substrate 1 before the formation of the photoresist film 71, and the tantalum oxide film and the insulating film 61 are used as a capacitor insulating film. Ic may be configured.

(Embodiment 5)
31 and 32 are sectional views showing a method of manufacturing a semiconductor integrated circuit device according to still another embodiment of the present invention in the order of steps. The manufacturing method of the present embodiment is the same up to the formation of the fourth wiring layer of the first embodiment. In FIGS. 31 and 32, the structure below the fourth wiring layer is omitted because it is almost the same as in the first to fourth embodiments. The left side of the drawing shows the area where the capacitor C is formed, and the right side shows the area where the connecting member P is formed.

(4) After forming the wirings M4d, M4sig, and M4s of the fourth wiring layer, an interlayer insulating film 80 covering the fourth wiring layer is formed as shown in FIG. The interlayer insulating film 80 is made of, for example, a silicon oxide film and can be formed by a CVD method or a sputtering method.

Next, as shown in FIG. 31B, a photoresist film 81 is formed on the interlayer insulating film 80. The photoresist film 81 is patterned so as to have openings in a region where a connection hole is formed and a region where a capacitor C is formed. After that, the interlayer insulating film 80 is etched using the photoresist film 81 as a mask to expose the surfaces of the wirings M4d and M4s of the fourth wiring layer.

Next, after removing the photoresist film 81, as shown in FIG. 31C, an insulating film 82 having a high dielectric constant, for example, a tantalum oxide film is formed. The formation of the tantalum oxide film is the same as in the first embodiment.

Next, as shown in FIG. 31D, a photoresist film 83 is formed so as to cover a region where the capacitor C is to be formed, and the insulating film 82 is etched using the photoresist film 83 as a mask. As a result, the insulating film 82 having a high dielectric constant remains in the region where the capacitor C is formed to form a capacitor insulating film, and the surface of the lower wiring is exposed in the region where the connecting member is formed. The formation of the photoresist film 83 is the same as that of the photoresist film 45 of the first embodiment.

Next, after removing the photoresist film 83, a metal film 84 is formed on the entire surface as shown in FIG. The metal film 84 can be, for example, a tungsten film formed by a CVD method, and titanium, titanium nitride, or a stacked film thereof can be applied as a barrier metal below the tungsten film.

Next, as shown in FIG. 32 (f), the unnecessary metal film 84 on the interlayer insulating film 80 is removed by etch back or CVD to form a conductive member Me to be an electrode of the plug P and the capacitor C. Further, a metal film 85 is formed on the entire surface. The metal film 85 is to be the wiring of the fifth wiring layer, and may be, for example, an aluminum film. As the upper layer or the lower layer of the aluminum film, titanium, titanium nitride, or a stacked film thereof can be used as a cap film or a base film.

Next, as shown in FIG. 32 (g), a photoresist film 86 patterned into a wiring pattern is formed, and using this photoresist film 86 as a mask, a metal film 85 is formed as shown in FIG. 32 (h). Etch. Thus, the wiring M5s of the fifth wiring layer is formed.

５The fifth wiring layer can be formed by patterning with a photoresist film without using the damascene method as in the present embodiment, and the capacitor C of the present invention can be applied to wiring formation by patterning which has been often used conventionally.

(Embodiment 6)
FIG. 33 is a plan view showing an example of a pattern generation method according to another embodiment of the present invention.

First, as shown in FIG. 33A, the wiring pattern 90 of the fifth wiring layer and the capacitor pattern 91 in the region where the capacitor C is formed are extracted. Here, the width (both the vertical and horizontal widths) of the capacitor pattern 91 is enlarged in a range that does not make contact with another wiring pattern adjacent to the wiring pattern 90.

Next, a graphic operation is performed on the wiring pattern 90 and the capacitor pattern 91 to generate an AND pattern 92 of both patterns. This AND pattern 92 is used as a mask pattern of the fifth wiring layer.

On the other hand, as shown in FIG. 33B, the wiring pattern 93 of the fourth wiring layer and the capacitor pattern 91 are extracted. Here, the width of the capacitor pattern 91 (both the vertical and horizontal widths) is enlarged in a range that does not contact another wiring pattern adjacent to the wiring pattern 93.

Next, a graphic operation is performed on the wiring pattern 93 and the capacitor pattern 91 to generate an AND pattern 94 of both patterns. This AND pattern 94 is used as a mask pattern of the fourth wiring layer.

In the first to fifth embodiments, the AND patterns 92 and 94 and the capacitor pattern 91 thus generated are used as patterning masks of the fifth and fourth wiring layers, respectively, and the electrodes of the capacitor C and When the present invention is applied to the hole formation pattern for forming the conductive member Me, as shown in FIG. 33C, the formation region 95 of the capacitor C is formed in an enlarged manner, and the capacitance of the capacitor C can be increased.

As described above, the invention made by the inventor has been specifically described based on the embodiment of the invention. However, the invention is not limited to the embodiment and can be variously modified without departing from the gist thereof. Needless to say, there is.

For example, in the above-described embodiment, up to the fifth layer has been exemplified, but a wiring layer having more layers may be provided. Further, a lower wiring layer (however, two or more layers) may be used.

Further, in the above-described embodiment, the case of the gate array is described, but the present invention is not limited to this, and the present invention can be applied to a cell-based IC (CBIC) such as a standard cell. For example, in a semiconductor integrated circuit device employing a cell-based IC (CBIC) shown in FIG. 34A, a logic block and a memory block (RAM, ROM) are arranged in an internal area surrounded by an I / O area. In the upper layer portion of the wiring layer on the internal region including the logic block and the memory block, similarly to the first to sixth embodiments, a power supply line having a wiring width wider than that of the lower layer power supply line is viewed from the upper layer. And a capacitance element (capacitor) C is formed at each intersection of the mesh.

{Circle around (4)} The capacitive element (capacitor) C according to the present invention may be used in combination with the MIS capacitive element using the capacitive cells shown in FIGS. 34 (a), (b), (c) and (d). In this case, a large stabilizing capacity can be provided without increasing the area by providing the capacity cell in an empty area between blocks such as a logic block and a memory block.

{Circle around (4)} The capacitive element (capacitor) C according to the present invention may be used in combination with an MIS capacitive element using an unused basic cell shown in FIGS. 35 (a) and (b). That is, in Embodiments 1 to 6, an unused basic cell is used as a capacitance cell to configure a capacitance element. Thereby, a large stabilizing capacitance can be provided without increasing the area.

In the above embodiment, the case where the capacitor C is formed between the uppermost layer and the lower layer has been described. In such a case, the wiring design rule is relaxed for the upper layer wiring, and the wiring size is formed larger. Therefore, forming the capacitor C between the upper wirings has an effect that it is easy to obtain a large capacitor capacity. In addition, the higher the upper layer wiring, the more often it is allocated to the power supply wiring, and this also has the effect that the number of capacitors can be increased. However, it is needless to say that the present invention is not limited to the configuration in which the capacitor C is formed between the upper-layer wirings, and that the capacitor may be formed between the lower-layer wirings.

In the above embodiment, the MISFET is exemplified as the semiconductor integrated circuit element (semiconductor element), but it goes without saying that a bipolar transistor or a Bi-CMOS transistor may be used.

Further, in the above-described embodiment, the case where there are two types of power supply lines, that is, the case of a single power supply, has been described. In this case, a capacitor is formed between wirings of different voltages.

As described above, the semiconductor integrated circuit device, the method of manufacturing the same, and the method of generating a mask pattern according to the present invention have a capacitor which is effective when applied to the reduction of AC noise of the semiconductor integrated circuit device. A large capacitance value can be obtained without increasing the wiring.

1A is a plan view showing an example of a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 1A is a plan view showing an entire chip, and FIG. It is a top view. FIG. 2 is a plan view in which the internal region of FIG. 1B is further enlarged. FIG. 3 is a sectional view taken along line III-III of FIG. 2. FIG. 5 is a cross-sectional view showing an example of the method for manufacturing the semiconductor integrated circuit device of the first embodiment in the order of steps. FIG. 5 is a cross-sectional view showing an example of the method for manufacturing the semiconductor integrated circuit device of the first embodiment in the order of steps. FIG. 5 is a cross-sectional view showing an example of the method for manufacturing the semiconductor integrated circuit device of the first embodiment in the order of steps. FIG. 5 is a cross-sectional view showing an example of the method for manufacturing the semiconductor integrated circuit device of the first embodiment in the order of steps. FIG. 5 is a cross-sectional view showing an example of the method for manufacturing the semiconductor integrated circuit device of the first embodiment in the order of steps. FIG. 5 is a cross-sectional view showing an example of the method for manufacturing the semiconductor integrated circuit device of the first embodiment in the order of steps. FIG. 5 is a cross-sectional view showing an example of the method for manufacturing the semiconductor integrated circuit device of the first embodiment in the order of steps. FIG. 5 is a cross-sectional view showing an example of the method for manufacturing the semiconductor integrated circuit device of the first embodiment in the order of steps. FIG. 5 is a cross-sectional view showing an example of the method for manufacturing the semiconductor integrated circuit device of the first embodiment in the order of steps. FIG. 5 is a cross-sectional view showing an example of the method for manufacturing the semiconductor integrated circuit device of the first embodiment in the order of steps. FIG. 5 is a cross-sectional view showing an example of the method for manufacturing the semiconductor integrated circuit device of the first embodiment in the order of steps. FIG. 5 is a cross-sectional view showing an example of the method for manufacturing the semiconductor integrated circuit device of the first embodiment in the order of steps. FIG. 5 is a cross-sectional view showing an example of the method for manufacturing the semiconductor integrated circuit device of the first embodiment in the order of steps. FIG. 5 is a cross-sectional view showing an example of the method for manufacturing the semiconductor integrated circuit device of the first embodiment in the order of steps. FIG. 5 is a cross-sectional view showing an example of the method for manufacturing the semiconductor integrated circuit device of the first embodiment in the order of steps. FIG. 5 is a cross-sectional view showing an example of the method for manufacturing the semiconductor integrated circuit device of the first embodiment in the order of steps. FIG. 4 is a plan view showing another example of the semiconductor integrated circuit device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view showing an example of a method for manufacturing a semiconductor integrated circuit device of the second embodiment in the order of steps. FIG. 10 is a cross-sectional view showing an example of a method for manufacturing a semiconductor integrated circuit device of the second embodiment in the order of steps. FIG. 10 is a cross-sectional view showing an example of a method for manufacturing a semiconductor integrated circuit device of the second embodiment in the order of steps. FIG. 14 is a cross-sectional view showing an example of a method for manufacturing a semiconductor integrated circuit device of Embodiment 3 in the order of steps. FIG. 14 is a cross-sectional view showing an example of a method for manufacturing a semiconductor integrated circuit device of Embodiment 3 in the order of steps. FIG. 14 is a cross-sectional view showing an example of a method for manufacturing a semiconductor integrated circuit device of the fourth embodiment in the order of steps. FIG. 14 is a cross-sectional view showing an example of a method for manufacturing a semiconductor integrated circuit device of the fourth embodiment in the order of steps. FIG. 14 is a cross-sectional view showing an example of a method for manufacturing a semiconductor integrated circuit device of the fourth embodiment in the order of steps. FIG. 14 is a cross-sectional view showing an example of a method for manufacturing a semiconductor integrated circuit device of the fourth embodiment in the order of steps. FIG. 14 is a cross-sectional view showing an example of a method for manufacturing a semiconductor integrated circuit device of the fourth embodiment in the order of steps. (A)-(e) is sectional drawing which showed the manufacturing method of the semiconductor integrated circuit device of Embodiment 5 in order of process. (F)-(h) is sectional drawing which showed the manufacturing method of the semiconductor integrated circuit device of Embodiment 5 in order of process. (A)-(c) is a plan view showing an example of a pattern generation method according to another embodiment of the present invention. 4A and 4B are drawings for explaining the problem of the present invention, wherein FIG. 4A is a plan view of a semiconductor integrated circuit device in which a standard cell is formed in an internal region, and FIG. FIG. 3C is a plan view showing the enlarged capacity cell, and FIG. 3D is a sectional view taken along line dd of FIG. 4A and 4B are other drawings for explaining the problem of the present invention, wherein FIG. 4A is a plan view of a semiconductor integrated circuit device having a gate array formed in an internal region, and FIG. It is a top view.

Explanation of reference numerals

1 semiconductor substrate 1a internal area 1b I / O area 1c pad (external terminal)
Reference Signs List 2 element isolation region 3 p-well 4 n-well 5 gate insulating film 6 gate electrode 7 cap insulating film 8 sidewall spacer 9 n-type semiconductor region 10 p-type semiconductor region 11 first interlayer insulating film 12 connection hole 13 plug 14 wiring 15 2 interlayer insulating film 16 connecting hole 17 plug 18 stopper insulating film 19 insulating film 20 wiring groove 21 wiring 22 stopper insulating film 23 interlayer insulating film 24 stopper insulating film 25 insulating film 26 wiring groove 27 connecting hole 28 wiring 29 to 32 insulating film 33 Wirings 34 to 36 Insulating film 37 Photoresist films 38 and 39 Insulating film 40 Photoresist film 41 Wiring groove 42 Connection hole 43 Hole 44 Tantalum oxide film 45 Photoresist film 47 Titanium nitride film 48 Copper film 50 Photoresist film 51 Tantalum oxide film 52 Photoresist films 61 to 65 Insulating film 66 Photoresist film 6 7 Hole 68 Connection Hole 69 Photoresist Film 70 Wiring Groove 71 Photoresist Film 80 Interlayer Insulation Film 81 Photoresist Film 82 Insulation Film 83 Photoresist Film 84, 85 Metal Film 86 Photoresist Film 90 Wiring Pattern 91 Capacitor Pattern 92 AND Pattern 93 Wiring pattern 94 AND pattern C Capacitor Ic Capacitor insulating film P Connection member

Claims (12)

A method for manufacturing a semiconductor integrated circuit device, comprising: a plurality of wiring layers; and an arbitrary first wiring layer excluding the uppermost layer among the wiring layers; and an optional second wiring layer above the first wiring layer. So,
(A) forming an interlayer insulating film covering the first wiring layer, and forming a hole in the interlayer insulating film on a wiring constituting the first wiring layer;
(B) forming a mask film covering some of the holes;
(C) performing an etching process in the presence of the mask film to remove an insulating film formed on the interlayer insulating film including a bottom of the hole or an inner surface of the hole;
(D) removing the mask film and forming a conductive member inside the hole;
A method for manufacturing a semiconductor integrated circuit device, comprising: 2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein
The insulating film may be formed on a first step formed on the first wiring layer before the formation of the interlayer insulating film, or on an interlayer insulating film including an inner surface of the hole after forming a hole in the interlayer insulating film. A method of manufacturing a semiconductor integrated circuit device, which is formed by any one of the second step formed on the entire surface of the semiconductor integrated circuit device. 3. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein
The conductive member is formed in a first step integrally with a wiring constituting the second wiring layer, or after forming a conductive film filling the hole, the conductive film is formed on the interlayer insulating film other than the hole. A method of manufacturing a semiconductor integrated circuit device, which is formed by any one of the steps of: A method for manufacturing a semiconductor integrated circuit device, comprising: a plurality of wiring layers; and an arbitrary first wiring layer excluding the uppermost layer among the wiring layers; and an optional second wiring layer above the first wiring layer. So,
(A) sequentially depositing a first insulating film, a second insulating film, and a third insulating film on the first wiring layer;
(B) patterning a first mask film having an opening in a region where a hole is to be formed on the third insulating film, and etching the third insulating film in the presence of the first mask film;
(C) removing the first mask film and sequentially depositing a fourth insulating film and a fifth insulating film on the third and second insulating films;
(D) patterning a second mask film having an opening in a region where a groove is formed on the fifth insulating film, and etching the fifth insulating film in the presence of the second mask film;
(E) etching the fourth insulating film using the second mask film or the fifth insulating film as a mask to form a groove patterned in the fifth insulating film in the fourth insulating film; Forming a hole patterned in the third insulating film in the second insulating film by etching the second insulating film using the third insulating film as a mask;
(F) removing the third insulating film and the first insulating film exposed at the bottom of the groove and the hole;
(G) depositing a sixth insulating film on the entire surface of the semiconductor substrate including the inner surfaces of the grooves and holes;
(H) patterning a third mask film covering a part of the hole;
(I) etching the sixth insulating film in the presence of the third mask film;
(J) removing the third mask film and forming a conductive film filling the trench and the hole;
(K) removing the conductive film in a region other than the groove to form a wiring and a conductive member constituting the second wiring layer;
A method for manufacturing a semiconductor integrated circuit device, comprising: A method for manufacturing a semiconductor integrated circuit device, comprising: a plurality of wiring layers; and an arbitrary first wiring layer excluding the uppermost layer among the wiring layers; and an optional second wiring layer above the first wiring layer. So,
(A) sequentially depositing a first insulating film, a second insulating film, and a third insulating film on the first wiring layer;
(B) patterning a first mask film having an opening in a region where a hole is to be formed on the third insulating film, and etching the third insulating film in the presence of the first mask film;
(C) removing the first mask film and sequentially depositing a fourth insulating film and a fifth insulating film on the third and second insulating films;
(D) patterning a second mask film having an opening in a region where a groove is formed on the fifth insulating film, and etching the fifth insulating film in the presence of the second mask film;
(E) etching the fourth insulating film using the second mask film or the fifth insulating film as a mask to form a groove patterned in the fifth insulating film in the fourth insulating film; Forming a hole patterned in the third insulating film in the second insulating film by etching the second insulating film using the third insulating film as a mask;
(F) patterning a third mask film covering a part of the hole;
(G) etching the first insulating film at the bottom of the hole and the third insulating film at the bottom of the groove in the presence of the third mask film and the patterned fifth insulating film;
(H) removing the third mask film and forming a conductive film filling the grooves and holes;
(I) removing the conductive film in a region other than the groove to form a wiring and a conductive member constituting the second wiring layer;
A method for manufacturing a semiconductor integrated circuit device, comprising: A method for manufacturing a semiconductor integrated circuit device, comprising: a plurality of wiring layers; and an arbitrary first wiring layer excluding the uppermost layer among the wiring layers; and an optional second wiring layer above the first wiring layer. So,
(A) sequentially depositing a first insulating film, a second insulating film, a third insulating film, a fourth insulating film, and a fifth insulating film on the first wiring layer;
(B) patterning a first mask film having an opening in a region where a hole is to be formed on the fifth insulating film, and forming the fifth, fourth, third and second films in the presence of the first mask film; A step of forming a hole by etching the insulating film,
(C) after removing the first mask film, forming a second mask film on the fifth insulating film, exposing a region where a groove is to be formed, and developing the second mask film to form the groove. Leaving the second mask film in a region other than the region to be formed and in the hole,
(D) etching the fifth and fourth insulating films in the presence of the second mask film to form a groove;
(E) removing the second mask film and patterning a third mask film covering a part of the hole;
(F) etching the first insulating film at the bottom of the hole in the presence of the third mask film;
(G) removing the third mask film and forming a conductive film filling the grooves and holes;
(H) removing the conductive film in a region other than the groove to form a wiring and a conductive member constituting the second wiring layer;
A method for manufacturing a semiconductor integrated circuit device, comprising: The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein:
A step of depositing a sixth insulating film on the entire surface of the semiconductor substrate including the inner surface of the groove and the hole before forming the third mask film, wherein the step of etching the first insulating film at the bottom of the hole includes And removing the sixth insulating film that is not covered with the third mask film together with the first insulating film. A method for manufacturing a semiconductor integrated circuit device, comprising: a plurality of wiring layers; and an arbitrary first wiring layer excluding the uppermost layer among the wiring layers; and an optional second wiring layer above the first wiring layer. So,
(A) depositing a seventh insulating film covering the first wiring layer;
(B) patterning a first mask film having an opening in a region where a hole is formed on the seventh insulating film, and etching the seventh insulating film in the presence of the first mask film; Removing the seventh insulating film on the wiring constituting one wiring layer;
(C) depositing a sixth insulating film on the entire surface of the semiconductor substrate including the inner surface of the hole;
(D) patterning a third mask film covering a part of the hole;
(E) etching the sixth insulating film in the presence of the third mask film;
(F) removing the third mask film and forming a conductive film filling the hole;
(G) removing the conductive film in a region other than the hole and forming a conductive member connected to a wiring constituting the second wiring layer;
(H) depositing a second conductive film on the entire surface of the semiconductor substrate and patterning the second conductive film to form the second wiring layer;
A method for manufacturing a semiconductor integrated circuit device, comprising: A method for manufacturing a semiconductor integrated circuit device according to claim 4, wherein:
The first and third insulating films are made of a material having an etching selectivity with respect to the second and fourth insulating films, and the thickness of the first insulating film is equal to the thickness of the third insulating film. A method of manufacturing a semiconductor integrated circuit device. A method for manufacturing a semiconductor integrated circuit device according to claim 4, wherein:
The method of manufacturing a semiconductor integrated circuit device, wherein a thickness of the first or sixth insulating film is smaller than a thickness of the second insulating film. A method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein:
A method of manufacturing a semiconductor integrated circuit device, wherein a dielectric constant of the first or sixth insulating film is higher than a dielectric constant of the second insulating film. Used for manufacturing a semiconductor integrated circuit device having a plurality of wiring layers and including an arbitrary first wiring layer excluding the uppermost layer among the wiring layers, and an optional second wiring layer above the first wiring layer. A method of generating a mask pattern,
A first power supply wiring to which a first potential is assigned among power supply wirings constituting the first wiring layer, and a second potential different from the first potential among power supply wirings constituting the second wiring layer are assigned. A first step of determining an intersection area where the second power supply wiring intersects;
A second step of generating a hole pattern in the intersection area;
A third step of expanding the width of the hole pattern so as not to reach the wiring regions of the first and second wiring layers adjacent to the hole pattern;
A method of generating a mask pattern, comprising:

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