JP2004054344A - Data transfer device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data transfer device for improving a processing capability by starting the transmission of a transmission packet early and for suppressing the occurrence of a data error packet. <P>SOLUTION: An arithmetic circuit 34 outputs, from a data bus CSTV [15:0] to a comparator 32, data automatically changed to an optimum value based on a signal PIRDYB indicating whether or not a PCI master controller is capable of transferring data and transmitted from the PCI master controller and a signal PTRDYB indicating whether or not a memory 8 is capable of transferring data and transmitted from a chip set 6. An output signal FREQB of the comparator 32 is asserted when satisfying DTC[15:0]≥DL[15:0] and/or DTC[15:0]≥CSTV[15:0], and request the transmission to a transmission FIFO 15. A transmission DMAC 14 automatically changes a transmission start time of the packet according to a processing condition of reading data from a PCI bus 5. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a data transfer device used in IEEE 1394 or the like using a storage device such as a FIFO for data transmission, and more particularly to a data transfer device forming a LINK device conforming to the OHCI (Open Host Controller Interface) standard.
[0002]
[Prior art]
Conventionally, in a data transfer device that uses a storage device such as a FIFO for data transmission and conforms to the IEEE 1394 standard, there is a problem that if packet transmission start timing is late, transfer performance is reduced. Such a problem is particularly noticeable when a hard disk device (hereinafter, referred to as an HDD device) is connected to a personal computer (hereinafter, referred to as a PC) having an interface conforming to the IEEE 1394 standard (hereinafter, referred to as an IEEE 1394 interface). And data transfer between them.
[0003]
In such a case, the PC and the HDD device use an asynchronous packet among an isochronous packet and an asynchronous packet specified by the IEEE 1394 standard. Also, among the asynchronous packets, a Physical Request packet prepared for performing high-speed data transfer using only hardware without software is transmitted from the HDD device to the PC. Then, the IEEE 1394 interface device in the PC executes a process on the received physical request packet, and then transmits a physical response (Physical Response) packet.
[0004]
The IEEE 1394 interface device of the PC and the HDD device are connected by a bus conforming to the IEEE 1394 standard (hereinafter, referred to as an IEEE 1394 bus), and the IEEE 1394 interface device is connected to the CPU of the PC via the PCI bus. A data flow in such an IEEE 1394 interface device in the PC will be described. FIG. 15 is a diagram showing a schematic timing example in the data flow on the IEEE 1394 bus and the PCI bus.
[0005]
As shown in FIG. 15, in the period A, a physical read request packet is transmitted from the HDD device to the PC on the IEEE 1394 bus. Next, in period B, the IEEE 1394 interface device in the PC reads data from the memory unit in the PC via the PCI bus and the chipset, and completes the data reading from the memory unit, and transfers the packet to the transmission FIFO. prepare. Next, in period C, a physical read response packet is transmitted from the PC to the HDD device on the IEEE 1394 bus.
[0006]
In such a state, the data transfer request from the HDD device to the PC is made with a physical read request packet, and the data transfer is attempted at high speed only by hardware without software, as shown in FIG. Even if the data reading process in the period B is not completed, since the first data of the transmission packet is prepared in the transmission FIFO, a method of improving the processing capability by speeding up the start of the period C can be considered. .
[0007]
[Problems to be solved by the invention]
However, according to the IEEE 1394 standard, once a packet starts to be transmitted, its data transmission cannot be stopped. For this reason, in the method for improving the processing capability as described above, if the transmission start time is too early, as shown in FIG. 17, data readout on the PCI bus side cannot be completed in time, and the physical data transmitted on the IEEE1394 bus cannot be read out. There is a problem that the data of the response packet is interrupted, and the hatched portion in FIG. 17 becomes an incomplete data portion, resulting in an incomplete packet.
[0008]
Further, even when the transmission start time is not too short, various devices are connected to the PCI bus, and the access of these devices shortens the PCI bus use time allocated to the IEEE 1394 interface device, In some cases, the last data in the transmission packet could not be prepared. In such a case, the IEEE 1394 protocol has a problem in that the HDD device transmits the same physical request packet again as described above and reprocessing is started, so that the processing capacity is reduced.
[0009]
SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and it is possible to improve the processing performance by earliering the transmission start timing of a transmission packet, and to suppress the occurrence of an incomplete data error packet. It is an object of the present invention to obtain a data transfer device that can perform the data transfer.
[0010]
[Means for Solving the Problems]
A data transfer device according to the present invention is a data transfer device that performs data transfer between an external system device and an internal system device, wherein a first interface circuit unit that interfaces with the internal system device; A second interface circuit unit for performing an interface of the first interface circuit unit, temporarily stores data input from the internal system device via the first interface circuit unit, and stores the stored data in response to an input control signal. A transmission data storage unit for transmitting to the external system device via the second interface circuit unit, and monitoring a data amount stored in the transmission data storage unit, and when the monitored data amount exceeds a predetermined value, Transmitting data stored in the transmission data storage unit to the second interface circuit unit; A control circuit unit for controlling the operation of the data storage unit, the control circuit unit changes the predetermined value according to the data transfer capability of the internal system device, the monitored data amount is less than the predetermined value If the data amount is less than the data amount requested to be transmitted from the external system device, the transmission data storage unit is prohibited from transmitting data to the second interface circuit unit.
[0011]
Specifically, the control circuit unit adds a preset value to the predetermined value when the data transfer capability of the internal system device is reduced and the data transfer from the internal system device is stopped. .
[0012]
Further, the control circuit unit may stop adding the preset value to the predetermined value while data transfer is being performed from the internal system device.
[0013]
On the other hand, when the control circuit unit is performing data transmission from the transmission data storage unit to the second interface circuit unit, the data transmission from the internal system device is not in time, and the data transmission from the transmission data storage unit is not completed. When the data transfer is performed again from the internal system device, if the monitored data amount becomes the data amount requested to be transmitted from the external system device, the second data is transmitted to the transmission data storage unit. Data transmission to the 2 interface circuit unit may be performed.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, the present invention will be described in detail based on an embodiment shown in the drawings.
First embodiment.
FIG. 1 is a block diagram illustrating an example of a data transfer device according to the first embodiment of the present invention. FIG. 1 shows an example in which an HDD device compliant with the IEEE 1394 standard is connected to a PC compliant with the IEEE 1394 standard, and data transfer is performed between the PC and the HDD device. The arrows between the blocks shown in FIG. 1 indicate only the flow of data.
[0015]
In FIG. 1, a data transfer device 1 is provided in a PC 2 as an IEEE 1394 interface device, and is connected to an HDD device 4 conforming to the IEEE 1394 standard via an IEEE 1394 bus 3. Further, the data transfer device 1 is connected to a chipset 6 via a PCI bus 5 in the PC 2, and the chipset 6 is connected to a CPU 7 and a memory unit 8, respectively. The chipset 6 interfaces the PCI bus 5 with the CPU 7 and the memory unit 8. Note that the HDD device 4 forms an external system device, and the PCI bus 5, the chipset 6, the CPU 7, and the memory unit 8 form an internal system device.
[0016]
On the other hand, the data transfer device 1 includes a LINK / PHY circuit 11 in which a link (LINK) layer and a physical (PHY) layer based on the IEEE 1394 standard are formed, a reception FIFO 12, and a reception memory controller (DMAC). 13, a transmission DMAC 14, a transmission FIFO 15, and a PCI interface control circuit 16 that controls data transmission and reception between the PCI bus 5. The LINK / PHY circuit 11 forms a second interface circuit, the PCI interface control circuit 16 forms a first interface circuit, the transmission DMAC 14 forms a control circuit, and the transmission FIFO 15 forms a transmission data storage. Eggplant
[0017]
The LINK / PHY circuit 11 temporarily stores data input from the HDD device 4 via the IEEE 1394 bus 3 in the reception FIFO 12, and the reception DMAC 13 reads out the data stored in the reception FIFO 12 (hereinafter, referred to as the “reception FIFO 12”). The data read is called a read), and the data is output to the DMAC for transmission 14 or the PCI interface control circuit 16 according to the read data. The PCI interface control circuit 16 outputs the input data to the chipset 6 via the PCI bus 5. On the other hand, the transmission DMAC 14 temporarily stores the data input to the PCI interface control circuit 16 in the transmission FIFO 15, and transfers the data stored in the transmission FIFO 15 to the IEEE 1394 bus 3 via the LINK / PHY circuit 11. Is output.
[0018]
When performing data transfer between the PC 2 and the HDD device 4, the asynchronous packet is used among the isochronous packet and the asynchronous packet defined by the IEEE1394 standard. Also, among the asynchronous packets, a physical request packet prepared for high-speed data transfer only by hardware without software is transmitted from the HDD device 4 to the PC 2. Then, the data transfer device 1 in the PC 2 transmits a physical response packet to the HDD device 4 after executing the processing for the received physical request packet.
[0019]
The data flow in the data transfer device 1 in such a case will be described in more detail. First, a physical request packet is transmitted from the HDD device 4 to the PC 2 via the IEEE 1394 bus 3. The physical request packet is stored in the receiving FIFO 12 via the LINK / PHY circuit 11. Then, the receiving DMAC 13 reads the physical request packet from the receiving FIFO 12, and when determining that the read packet is not a simple asynchronous packet but a physical packet, transfers the packet to the transmitting DMAC 14.
[0020]
Next, the transmission DMAC 14 reads desired data from the memory unit 8 via the chipset 6 connected to the PCI bus 5 and stores it in the transmission FIFO 15 in accordance with the contents of the input packet. When predetermined data is read from the memory unit 8 via the PCI bus 5 and the number of physical response packets corresponding to the number of register values built in the transmission DMAC 14 can be prepared in the transmission FIFO 15, the transmission DMAC 14 / PHY circuit 11 is enabled with a control signal indicating that transmission is ready, and the LINK / PHY circuit 11 transmits the physical response packet to the HDD device 4 via the IEEE1394 bus 3.
[0021]
On the other hand, when the internal data of the memory unit 8 is read using the PCI bus 5, the time required for data reading is constantly changed depending on the availability of the PCI bus 5 and whether data is prepared in the memory unit 8. And change. The transmitting DMAC 14 determines the change from the signal indicating the state of the PCI bus 5 and changes the value of a built-in register (not shown). For example, if data cannot be read because the PCI bus 5 is not empty, the register value is increased. If the PCI bus 5 is empty and data can be read smoothly, the register value is decreased.
[0022]
By doing so, the start time of the period C shown in FIG. 16 automatically fluctuates in accordance with the data read situation via the PCI bus 5, and the state shown in FIG. be able to. Further, the present invention can be used not only to start transmission of a physical response packet for a received physical request packet at an optimal time but also to start transmission of a simple asynchronous packet at an optimal time.
[0023]
Here, FIG. 2 is a diagram showing a schematic configuration example of a packet of the IEEE 1394 standard. As shown in FIG. 2, an IEEE 1394 packet is composed of a header section containing information such as the type and address of a packet, where 1 word is composed of 32 bits and 4 words or less, and data composed of 1 word is composed of 32 bits and 2048 words or less. Is roughly divided into the data section containing In addition, some packets have no data part depending on the type of the packet.
[0024]
The transmission DMAC 14 uses data called a descriptor similar to a program for creating a transmission packet. FIG. 3 is a diagram showing a schematic configuration example of such a descriptor. As shown in FIG. 3, one descriptor is 32 bits, 4 words is one basic unit, and one descriptor is composed of a maximum of 8 words. In the descriptors Descriptor0 to Descriptor3, a control part including a descriptor type, a memory address for creating a data part, a next descriptor memory address, and the like are written in the descriptors Descriptor4 to Descriptor7 to the transmission FIFO 15 (hereinafter, referred to as “descriptor”). Data writing is called a write.) Data of a header portion of a transmission packet is stored.
[0025]
Next, FIG. 4 is a block diagram showing a configuration example of the transmission DMAC 14. As shown in FIG. 4, the transmission DMAC 14 includes a register 21 for storing a descriptor, such as a program for creating a transmission packet, or a physical read request packet as described above. The register 21 is 32 bits × 8 words. Of the register. The physical read request packet is input from the receiving DMAC 13 from the data bus REQD [31: 0], and the descriptor is sent from the PCI master controller (not shown) in the PCI interface control circuit 16 to the read data bus MD [31: 0]. ].
[0026]
Further, the transmission DMAC 14 includes a multiplexer (MUX) 22. The multiplexer 22 transmits the header data in the transmission packet input from the register 21 or the transmission data input from the read data bus MD [31: 0]. Any one of the data in the data portion in the trust packet is exclusively selected and output to the transmission FIFO 15 via the data bus FD [31: 0]. Further, the transmission DMAC 14 includes a timing control circuit unit 23 that generates all timing control signals in the transmission DMAC 14. A signal REQWRB indicating the data write period of the physical read request packet is input to the timing control circuit unit 23 from the receiving DMAC 13.
[0027]
The timing control circuit unit 23 sends the address to the PCI master controller to the data bus MA [31: 0] and the data indicating the data length value of the read request to the data bus ML [15: 0] to the PCI master controller. ], And outputs a signal MREQ indicating the start of a read request and a signal MRDB indicating that data is to be read. The signal MREQ becomes active at a high level, and the signal MRDB becomes active at a low level.
[0028]
The timing control circuit 23 receives a signal MEMP indicating that no data has been read into a FIFO (not shown) in the PCI master controller. The timing control circuit unit 23 is connected to an input / output data bus SD [31: 0] connected to a PCI slave controller (not shown) in the PCI interface control circuit 16, and receives a write request from the PCI slave controller. The signal SWRB is input, and writing to the start register 31 in the timing control circuit unit 23 is realized.
[0029]
The timing control circuit unit 23 receives data necessary for performing the timing control from the register 21 via the data bus DD # [31: 0] (# indicates that there are four buses of 0 to 3). Is entered. Further, the timing control circuit unit 23 can prepare a signal FEOP indicating the last data of the write packet to the transmission FIFO 15, a write request signal FWRB to the transmission FIFO 15, and prepare the data in the transmission FIFO 15, and a LINK / PHY circuit. 11 outputs a signal FREQB requesting the start of transmission.
[0030]
The signal FREQB is output from the comparator 32, and the comparator 32 outputs an output data bus DTC [from the data up counter 33 that counts the number of words that have written the data of the data part of the transmission packet to the transmission FIFO 15 as input. 15: 0], and data from the data bus DL [15: 0] for transmitting the requested number-of-bytes data from the data bus DD # [31: 0].
[0031]
Further, the comparator 32 automatically outputs the data output from the start register 31 that can be set from the outside via the output data bus STV [15: 0] to the optimum value from the signals PIRDYB and PTRDYB by the arithmetic circuit 34. The changed data is input via data bus CSTV [15: 0]. The signal PIRDYB is a signal output from the PCI master controller indicating whether or not the PCI master controller is ready for data transfer, and the signal PTRDYB is used to determine whether or not the memory unit 8 is in a state where data transfer is possible. 4 is a signal output from the chipset 6 shown in FIG.
[0032]
If the output signal FREQB of the comparator 32 is (data from the data bus DTC [15: 0]) ≧ (data from the data bus DL [15: 0]) and / or (data from the data bus DTC [15: 0]) ) ≧ (data from the data bus CSTV [15: 0]), the signal is asserted at a low level, and a transmission request is made to the transmission FIFO 15. The transmission DMAC 14 automatically changes the transmission start time of the packet according to the processing status of the data read from the PCI bus 5 necessary for preparing the response packet.
[0033]
FIG. 5 is a block diagram showing an example of the internal configuration of the arithmetic circuit 34. As shown in FIG. 5, the arithmetic circuit 34 includes a 16-bit register 41, and receives data from a multiplexer (MUX) 42. The multiplexer 42 receives the data bus STV [15: 0] and the addition result output from the adder 43. The multiplexer 42 outputs the data bus STV [15: 0] when the signal MREQ is at a high level. ], The output signal of the adder 43 is selected and output when the signal MREQ is at a low level. The adder 43 adds the data output from the register 41 via the data bus CSTV [15: 0] and the data output from the multiplexer (MUX) 44 and outputs the result.
[0034]
The signal PIRDYB is input to the inverter 45, and the output signal of the inverter 45 and the output signal of the AND circuit 46 to which the signal PTRDYB is input are input as the select signal of the multiplexer 44. The multiplexer 44 selects and outputs a predetermined value "0004h" when the select signal is at a high level, and outputs a predetermined value "0000h" when the select signal is at a low level.
[0035]
Next, FIGS. 6 to 10 show timing examples until the transmission DMAC 14 writes a transmission packet to the transmission FIFO 15 and issues a packet read request to the LINK / PHY circuit 11. The operation of the data transfer device 1 at the time of packet transmission will be described in more detail with reference to FIGS.
When transmitting a packet, first, it is necessary to write either a descriptor or a physical read request packet to the register 21 as information for creating a transmission packet.
[0036]
FIG. 6 is a timing chart showing signals for writing the descriptor to the register 21.
In FIG. 6, at timing T2, a signal MREQ indicating a read request to the PCI master controller goes high and is asserted. At the same time, the signal MREQ is stored in a register (not shown) in the timing control circuit unit 23 of FIG. The memory address register value of the descriptor is output to data bus MA [31: 0], and data “0020h” is output to data bus ML [15: 0] to read 32 bytes of data.
[0037]
When the PCI master controller in the PCI interface control circuit 16 can read data from the PCI bus 5, the FIFO (not shown) in the PCI master controller has an empty state in which there is no data to be stored. , The signal MEMP goes low. When the signal MEMP goes low, the timing control circuit 23 sets the data read request signal MRDB to the PCI master controller to low level. Next, the descriptor data S0 to S7 sequentially read via the read data bus MD [31: 0] are stored in the register 21.
[0038]
Next, FIG. 7 is a timing chart showing the timing for writing the physical read request packet to the register 21.
As shown in FIG. 7, during the timing T6 to T9, the signal REQWRB goes low from the receiving DMAC 13 and the physical read request packets P0 to P3 are read from the data bus REQD [31: 0]. Is written. As described above, either the descriptor or the physical read request packet is written to the register 21, and the preparation for writing the transmission packet to the transmission FIFO 15 is completed.
[0039]
Next, FIG. 8 is a timing chart showing a timing example of writing the header portion of the transmission packet to the transmission FIFO 15.
FIG. 8 shows that the signal FWRB is at the low level during the period from the timing T6 to the timing T9, and data is written to the transmission FIFO 15. In this case, the DMAC for transmission 14 sets the signal FWRB to low level, and outputs the data of the header portion already stored in the register 21 to the data bus FD [31: 0]. Since the last data of the packet at this time is not yet written, the signal FEOP remains at the low level. In this way, the transmission DMAC 14 writes the packet header into the transmission FIFO 15.
[0040]
Next, FIGS. 9 and 10 are timing charts showing timing examples when the transmission DMAC 14 writes the data portion to the transmission FIFO 15 based on the data stored in the register 21 at the timing of FIG. 6 or 7. It is a chart. The signals PFRMB, PIRDYB, PTRDYB, PSTOPB and the data bus PAD [31: 0] shown in FIGS. 9 and 10 are signals connected to the PCI bus 5. In the terms “initiator” and “target” used in the PCI standard, only the data read from the PCI bus 5 is described here. Therefore, the initiator is the data transfer device 1 and the target is the memory unit 8.
[0041]
9 and 10, a signal PFRMB is a signal indicating whether or not a bus cycle of the PCI bus 5 is being executed, and is output from the chipset 6. The signal PSTOPB is a signal asserted by the chipset 6 when the target requests the initiator to stop the transaction currently being executed, and the data bus PAD [31: 0] And a data input / output bus.
[0042]
In FIG. 9, at timing T1, the transmitting DMAC 14 raises the signal MREQ to a high level and issues a read request to the PCI master controller. At the same time, the transmission DMAC 14 prepares the memory address data MSA on the data bus MA [31: 0] and, for example, when preparing data of “30h” byte, the data “0030h” on the data bus ML [15: 0]. Is output. In response to this, the PCI master controller sets the signal PFRMB to low level and asserts it from timing T2, and outputs the memory address data MSA for the memory unit 8 to the data bus PAD [31: 0].
[0043]
Next, at timing T3, the PCI master controller sets the signal PIRDYB to low level and asserts it to notify the chipset 6 that data read is possible. Then, the chipset 6 asserts the signal PTRDYB to a low level from the timing T4 to indicate that data transmission is possible, and simultaneously outputs data to the data bus PAD [31: 0]. At timing T10, the signal PSTOPB becomes low level by the chipset 6 to be asserted and a request to stop data transfer occurs. At timing T11, the signal PTRDYB becomes high level and is deasserted by the chipset 6. The PCI master controller deasserts the signal PFRMB at a timing T11 and the signal PIRDYB at a high level at a timing T12 to suspend the data transfer.
[0044]
However, since the read request from the DMAC for transmission 14 to the PCI master controller is “30h” byte, the PCI master controller makes the read request by resetting the signal PFRMB to the low level again from the timing T13, and performs the read request at the timing T13. The address “MSA + 1Ch” following the previous data read is output to the data bus PAD [31: 0].
[0045]
The chipset 6 sets the signal PTRDYB to low level at timing T15 and asserts it, and sequentially outputs data from the memory unit 8 to the data bus PAD [31: 0] at timings T15 to T19. In addition, the PCI master controller sets the signal PFRMB to high level and deasserts it to notify the chipset 6 of the end of the transaction because the data read of a total of “30h” bytes ends at the timing T19. The signals PIRDYB and PTRDYB become high level from the timing T20 and are deasserted.
[0046]
For this reason, at timings T5 to T11 and timings T16 to T20, the signal MEMP input from the PCI master controller to the transmission DMAC 14 becomes low level. Therefore, the transmission DMAC 14 sets the signals MRDB and FWRB to low level at the timing T5, sequentially writes data to the transmission FIFO 15, and sets the signal FEOP to high level at the timing T20 because it is the final data. Data is written.
[0047]
The data from the data bus DTC [15: 0] indicating the number of bytes written to the transmission FIFO 15 is set to data “0h” at the data write start timing at the timing T2, and then the data is transferred to the transmission FIFO 15. It is incremented by 4 each time it is written. When the data output from the start register 31 to the data bus STV [15: 0] is “14h”, the arithmetic circuit 34 transfers the data bus STV [15: 0] to the data bus CSTV [15: 0] at timing T2. ] Is output.
[0048]
When the signal PIRDYB is at a low level and the signal PTRDYB is at a high level, and the timing indicates a period during which data is to be read but no data comes from the target side, that is, at timings T3 and T14, the data "0004h" is output from the multiplexer 44. Is output, and the data on the data bus CSTV [15: 0] is incremented by 4 by the adder 43. At timing T11, the comparison result of the comparator 32 in FIG. 4 changes, so that the signal FREQB goes low at timing T12 and is asserted, and a packet read request is made to the LINK / PHY circuit 11.
[0049]
9 is a timing example similar to that of FIG. 9 except that the signal PIRDYB is at a low level and the signal PTRDYB is at a high level, and the timing indicating a period in which data is to be read but no data comes from the target side is longer than in FIG. Is shown in FIG.
As shown in FIG. 10, there are periods during which no data comes at timings T3, T4, T14, and T15. At these times, the data on the data bus CSTV [15: 0] is sequentially incremented by four. Since the comparison result of the comparator 32 in FIG. 4 changes at the timing T20, the signal FREQB becomes low level and is asserted at the timing T21, and a packet read request is made to the LINK / PHY circuit 11.
[0050]
As described above, the data transfer device according to the first embodiment has a lower data transfer capability to the target PCI bus 5 in FIG. 10 than in FIG. 9, and in FIG. In FIG. 10, the transmission DMAC 14 makes a packet read request to the LINK / PHY circuit 11 when the data of the “24h” byte is ready. From this, it is possible to automatically change the transmission packet read request timing according to the state of the target and the transfer capability in the transaction of the PCI bus 5.
[0051]
Second embodiment.
FIG. 11 is a diagram illustrating a configuration example of an arithmetic circuit of a data transfer device according to the second embodiment of the present invention. In the block diagram showing an example of the data transfer device according to the second embodiment of the present invention, the transmission DMAC 14 in FIG. 1 is replaced by a transmission DMAC 14a, and the data transfer device 1 in FIG. 1 is replaced by a data transfer device 1a. Other than that is the same as FIG. 4 is the same as that of FIG. 4 except that the timing control circuit unit 23 in FIG. 4 is replaced by a timing control circuit unit 23a. 11, the same components as those in FIG. 5 are denoted by the same reference numerals. The transmission DMAC 14a forms a control circuit unit.
[0052]
As shown in FIG. 11, the arithmetic circuit 34a includes a 16-bit register 41, and data is input from a multiplexer 42. Data from the data bus STV [15: 0] and the addition result output from the adder 43 are input to the multiplexer 42. The multiplexer 42 selects the data from the data bus STV [15: 0] when the signal MREQ is at a high level or when the comparison result of the comparator 51 is at a high level by the OR circuit 52; The data output from 43 is selected. The comparator 51 compares the data from the data bus STV [15: 0] with the data output from the adder 43, and outputs the data from the data bus STV [15: 0] to the data output from the adder 43. If it is smaller than this, it outputs a high-level signal; otherwise, it outputs a low-level signal.
[0053]
To the adder 43, the data output from the register 41 via the data bus CSTV [15: 0] and the data output from the multiplexer 44 are added and output. The output signal of the NOR circuit 53 input to the input terminals corresponding to the signals PIRDYB and PTRDYB is input as a select signal of the multiplexer 44. The multiplexer 44 selects and outputs a predetermined value “FFFCh” when the select signal is at a high level, and outputs a predetermined value “0004h” when the select signal is at a low level.
[0054]
In such a configuration, FIG. 12 is a timing chart showing a timing example from when the transmission DMAC 14a writes a transmission packet to the transmission FIFO 15 and issues a packet read request to the LINK / PHY circuit 11.
FIG. 12 is substantially the same as the timing shown in FIG. 10, but differs from FIG. 10 in that the data from the data bus STV [15: 0] is “1Ch” and the data bus CSTV [15 : 0]. After the data from the data bus CSTV [15: 0] is set to “1Ch” which is the value of the data bus STV [15: 0] at the timing T2, the data is actually transferred on the PCI bus 5 It is decremented by 4 at each of T5 to T10 and at timings T16 to T21, and is incremented by 4 at other timings when data transfer is not executed.
[0055]
However, at timings T9 to T11 and timing T22, the output of the comparator 51 becomes high level, so that the multiplexer 42 selects data from the data bus STV [15: 0], and outputs data from the register 41 to the data bus CSTV [15: 0]. ] Remains the data “1Ch” from the data bus STV [15: 0]. Since the comparison result of the comparator 32 shown in FIG. 4 changes at the timing T20, the signal FREQB becomes low level and is asserted at the timing T21, and a packet read request is output from the transmission DMAC 14a to the LINK / PHY circuit 11.
By doing so, the data transfer device according to the second embodiment can achieve the same effects as those of the first embodiment.
[0056]
Third embodiment.
FIG. 13 is a diagram illustrating a configuration example of a transmitting DMAC of a data transfer device according to the third embodiment of the present invention. In the block diagram showing an example of the data transfer device according to the third embodiment of the present invention, the transmission DMAC 14 in FIG. 1 is replaced by a transmission DMAC 14b, and the data transfer device 1 in FIG. 1 is replaced by a data transfer device 1b. Other than that is the same as FIG. 13, the same components as those in FIG. 4 are denoted by the same reference numerals, and the description thereof will be omitted, and only the differences from FIG. 4 will be described. The transmitting DMAC 14b forms a control circuit unit.
[0057]
13 differs from FIG. 4 in that a multiplexer (MUX) 61, a D-type flip-flop 62, an AND circuit 63, and an inverter 64 are added. Accordingly, the transmission DMAC 14 in FIG. It is to have done.
In FIG. 13, the data prepared in the transmission FIFO 15 is transmitted from the LINK / PHY circuit 11 to the IEEE 1394 bus 3 in the inverter 64, but the transmission packet cannot be transmitted in time because the data in the transmission FIFO 15 cannot be prepared in time. A signal UNDERTM, which goes high when a data error occurs, is input from the transmission FIFO 15.
[0058]
The data from the data bus DL [15: 0] and the data from the data bus CSTV [15: 0] are input to the multiplexer 61, respectively. The multiplexer 61 compares one of the data from the data bus DL [15: 0] and the data from the data bus CSTV [15: 0] with a comparator according to the output signal from the output terminal QB of the D-type flip-flop 62. Output to 32 corresponding inputs. The power supply voltage VDD is input to the D input terminal of the D-type flip-flop 62, and the output signal of the inverter 64 is input to the reset terminal RB. The output signal of the AND circuit 63 is input to the clock signal input terminal of the D-type flip-flop 62, and the signal output from the D-type flip-flop 62 and the signal FREQB correspond to each input terminal of the AND circuit 63. Has been entered.
[0059]
FIG. 14 is a timing chart showing a timing example of each signal in FIG. 13 in such a configuration. In FIG. 14, a packet is written to the transmission FIFO 15 at timings T1 to T6 and timings T8 to T13. Also, at timing T3, the signal FREQB becomes low level and is asserted, and packet transmission from the transmission FIFO 15 to the IEEE 1394 bus 3 via the LINK / PHY circuit 11 is started. The signal UNDERTM goes high because preparation is not in time. Accordingly, the output terminal QB of the D-type flip-flop 62 rises to a high level at a timing T5. Therefore, the multiplexer 61 selects data from the data bus DL [15: 0] and outputs the data to the corresponding input terminal of the comparator 32 via the data bus NSTV [15: 0].
[0060]
Therefore, the comparator 32 compares the data from the data bus DTC [15: 0] with the data from the data bus DL [15: 0]. For this reason, a transmission request is made for the next packet in which a data error has occurred, only when data is always prepared in the transmission FIFO 15. However, once the packet transmission has been reliably performed, the output terminal of the AND circuit 63 rises from the low level to the high level at the timing T18, and the output terminal QB of the D-type flip-flop 62 goes to the low level.
[0061]
Therefore, the data from the data bus CSTV [15: 0] is selected and output from the multiplexer 61, and the comparator 32 outputs the data bus DTC [15: 0], the data bus DL [15: 0], and the data bus CSTV. A signal FREQB indicating the result of comparison of each data from [15: 0] is output. Accordingly, the timing at which data transfer from the transmission FIFO 15 to the LINK / PHY circuit 11 starts is the timing at which the function of the arithmetic circuit 34 operates.
[0062]
As described above, the data transfer device according to the third embodiment can obtain the same effects as those of the first embodiment, and can also provide a data transfer device when a data error occurs during packet transmission. Since the transmission of the next transmission packet can be reliably performed, the stability on the system can be improved.
[0063]
In each of the first to third embodiments, a signal with a B at the end of the code, a signal input end and a signal output end are active at a low level, and the B is added at the end of the code. The absence signal, the signal input terminal, and the signal output terminal indicate that they become active at a high level, respectively.
[0064]
【The invention's effect】
As is apparent from the above description, according to the data transfer device of the present invention, even if the packet transmission timing is advanced in order to improve the processing capability of the data transfer device, it is necessary to prepare the transmission data. Since the transmission start timing can be automatically changed according to the state of the internal system device, the occurrence of a transmission packet in which a data error has occurred can be reduced, and the data transfer processing capability can be further improved. Also, if the transmission packet has a data error when the transmission start timing is advanced to improve the data transfer processing capability, when retransmitting the transmission packet with the data error, the processing to advance the transmission start timing is performed. By disabling, reliable data transfer becomes possible.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating an example of a data transfer device according to a first embodiment of the present invention.
FIG. 2 is a diagram illustrating an example of a schematic configuration of an IEEE 1394 standard packet;
FIG. 3 is a diagram showing a schematic configuration example of a descriptor.
FIG. 4 is a block diagram showing a configuration example of a transmission DMAC 14 of FIG. 1;
FIG. 5 is a block diagram showing an example of an internal configuration of an arithmetic circuit 34 in FIG. 4;
FIG. 6 is a timing chart showing signals for writing a descriptor to a register 21;
FIG. 7 is a timing chart showing a timing for writing a physical read request packet to a register 21;
FIG. 8 is a timing chart showing a timing example of writing a header portion of a transmission packet to a transmission FIFO 15;
FIG. 9 is a timing chart showing a timing example of each signal shown in FIGS. 4 and 5 when writing a data portion to the transmission FIFO 15;
FIG. 10 is a timing chart showing another example of timing of each signal shown in FIGS. 4 and 5 when writing a data portion to the transmission FIFO 15;
FIG. 11 is a diagram illustrating a configuration example of an arithmetic circuit of a data transfer device according to a second embodiment of the present invention.
FIG. 12 is a timing chart showing a timing example of each signal from when a transmission packet is written to the transmission FIFO 15 to when a packet read request is issued to the LINK / PHY circuit 11;
FIG. 13 is a diagram illustrating a configuration example of a transmission DMAC of a data transfer device according to a third embodiment of the present invention.
FIG. 14 is a timing chart showing a timing example of each signal of FIG. 13;
FIG. 15 is a diagram showing a schematic timing example in a data flow on the IEEE 1394 bus and the PCI bus.
FIG. 16 is a diagram illustrating another schematic timing example in the data flow on the IEEE 1394 bus and the PCI bus.
FIG. 17 is a diagram showing another schematic timing example in the data flow on the IEEE 1394 bus and the PCI bus.
[Explanation of symbols]
1,1a, 1b data transfer device
2 PC
3 IEEE 1394 bus
4 HDD device
5 PCI bus
6 chipset
7 CPU
8 Memory section
11 LINK / PHY circuit
12 FIFO for reception
13 DMAC for reception
14,14b DMAC for transmission
15 Transmission FIFO
16 Interface control circuit
21, 41 registers
22,42,44,61 Multiplexer
23, 23b timing control circuit section
31 Start register
32,51 comparator
33 Data Up Counter
34, 34a arithmetic circuit
43 Adder
45,64 inverter
46,63 AND circuit
52 OR circuit
53 NOR circuit
62 D-type flip-flop

Claims (4)

In a data transfer device that performs data transfer between an external system device and an internal system device,
A first interface circuit unit that interfaces with the internal system device;
A second interface circuit unit that interfaces with the external system device;
The system temporarily stores data input from the internal system device via the first interface circuit unit, and stores the stored data in the external system via a second interface circuit unit in response to an input control signal. A transmission data storage unit for transmitting to the device;
Monitoring the amount of data stored in the transmission data storage unit, and when the monitored data amount exceeds a predetermined value, causing the data stored in the transmission data storage unit to be transmitted to the second interface circuit unit; A control circuit unit for controlling the operation of the transmission data storage unit;
With
The control circuit unit changes the predetermined value according to the data transfer capability of the internal system device, and the monitored data amount is less than the predetermined value and less than the data amount requested to be transmitted from the external system device. The data transfer device according to claim 1, wherein the transmission data storage unit is prohibited from transmitting data to the second interface circuit unit. 2. The control circuit unit according to claim 1, wherein when a data transfer capability of the internal system device is reduced and data transfer from the internal system device is stopped, a predetermined value is added to the predetermined value. A data transfer device according to claim 1. 3. The data transfer device according to claim 2, wherein the control circuit unit stops adding the preset value to the predetermined value while data transfer is being performed from the internal system device. . The control circuit unit, when performing data transmission from the transmission data storage unit to the second interface circuit unit, fails to transmit data from the internal system device in time and fails to transmit data from the transmission data storage unit. Then, when the data amount monitored is equal to the data amount requested to be transmitted from the external system device when the data transfer is performed again from the internal system device, the second interface is transmitted to the data storage unit for transmission. 4. The data transfer device according to claim 1, wherein data transmission to the circuit unit is performed.

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