JP2004053292A - Interposer substrate continuity inspection method - Google Patents

Abstract

An object of the present invention is to provide a method for inspecting continuity of an interposer substrate such that a continuity inspection of a wiring layer of an interposer substrate such as a two-metal BGA can be inspected on the same surface.
A via hole is formed at a predetermined position of a copper foil of a copper-clad laminate in which copper foil having a thickness of 12 μm is bonded to both surfaces of an insulating base material 11 by laser processing or the like, and electrolytic copper plating is performed. A thick conductor layer and a filled via 22 are formed, and the conductor layer is patterned to provide a substrate connection electrode 23, common measurement electrodes 51 and 52, a wiring layer 21, an IC chip connection electrode 24, and a measurement wiring lead 25. The continuity inspection interposer substrate 50 is manufactured. Further, the measurement / inspection probe 101 is pressed against the substrate connection electrode 23, and the measurement / inspection probes 102a and 102b are pressed against the common measurement electrodes 51 and 52, and the continuity and short circuit of the wiring layer 21 are determined by the inspection apparatus 100.
[Selection diagram] FIG.

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a continuity inspection method of an interposer substrate for inspecting a continuity state of a wiring layer of an interposer substrate used as a member of a semiconductor package for mounting a semiconductor element on a printed wiring board.
[0002]
[Prior art]
In electronic devices such as personal computers, office automation equipment, home appliances, audio equipment, and game machines, it is difficult to mount semiconductor elements directly on a printed wiring board. In most cases, semiconductor elements are mounted on a substrate called an interposer. The semiconductor package is mounted on an electronic device after the semiconductor package is mounted.
In recent years, these electronic devices have been steadily reduced in size and performance, and demands for further downsizing and higher-density wiring of semiconductor packages have been increasing.
[0003]
In a semiconductor package, a wiring layer for establishing electrical continuity is provided on a surface of an insulating base material on an electronic circuit board on which a semiconductor element is mounted. An electronic circuit board starts with a wiring layer formed on one side of an insulating base material, and as the density of the wiring layers increases, a double-sided wiring board or a multilayer wiring board in which insulating layers and wiring layers are alternately stacked Is being created.
As a typical electronic circuit board, there is a tape made of an insulating material represented by polyimide or a wiring board made of a board material as a core material. In recent years, a tape-shaped double-sided wiring board (interposer board) having a wiring layer on both sides, The demand for the so-called two-metal TAB is increasing.
[0004]
Compared to a single-sided wiring board, a double-sided wiring board is characterized in that it not only has a wiring layer on both sides but also has a structure called a via hole for electrically connecting the front and back wiring layers.
When forming a wiring layer on a double-sided copper foil laminate in which copper foil is attached to both sides of an insulating base material, first, a via hole is formed in the insulating base material and the copper foil by laser processing or the like. It is formed by embedding a conductor layer in the via hole by electrolytic copper plating or the like, and electrically connects the copper foil on the front and back of the insulating base material. After that, a wiring layer and an electrode are formed by patterning the front and back copper foils, thereby obtaining a two-metal interposer substrate.
[0005]
The wiring layer of the interposer board electrically connects between a board connecting electrode to be mounted on a printed wiring board and an IC chip connecting electrode. Usually, from the mounting mode, an IC chip connection electrode and a wiring layer are formed on one surface of the insulating base material, and a substrate connection electrode is formed on the other surface of the insulating base material. The connection electrodes are electrically connected through via holes. If this wiring layer breaks in the middle or short-circuits with an adjacent wiring layer, the value as a product is lost. Therefore, appearance inspection, electrical inspection, etc. are performed before shipment.
[0006]
[Problems to be solved by the invention]
In a method of inspecting the continuity of a wiring layer, a needle-shaped inspection probe is brought into contact with both ends of the wiring layer to measure and determine the electric resistance.
When the wiring layer is a one-metal BGA substrate having only one surface, the electrodes for connecting the substrate and the electrodes for connecting the IC chip are on the same surface. Therefore, the inspection probe is arranged on one surface side and brought into contact with each electrode. Electrical testing is often done.
On the other hand, in the case of a two-metal BGA substrate, in the case of a fan-out type in which an IC chip is mounted at the center of an interposer substrate and substrate connection electrodes are arranged outside the IC chip, the number of wiring layers is increased as much as possible. In many cases, a substrate connection electrode is arranged on the side opposite to the connection electrode.
[0007]
In such a case, it is necessary to arrange the inspection probes on both sides and press them against the respective electrodes. At this time, if the thickness of the interposer substrate is 100 μm or less, it is difficult to accurately press the inspection probe against the front and back electrodes because of the flexibility. This makes the device complicated and very expensive.
[0008]
In recent years, the size of a semiconductor package has been reduced, while the number of electrodes has been increasing. For this reason, the electrode for connecting the IC chip has become 30 to 100 μm square, and there is a problem that it is difficult to accurately contact the inspection probe.
In addition, in order to efficiently and accurately perform a continuity test of an interposer substrate with an increase in the number of electrodes and miniaturization, a large number of test electrodes are arranged on an insulating base material from a continuity test using a conventional test probe. A method of conducting a continuity test using an inspection jig has been introduced. Also in this case, there is a problem that it is difficult to accurately align the inspection electrode with the front and back electrodes.
[0009]
The present invention has been devised in view of the above problems, and has as its object to provide a continuity inspection method for an interposer substrate that enables a continuity inspection of a wiring layer of an interposer substrate such as a two-metal BGA to be performed on the same surface. .
[0010]
[Means for Solving the Problems]
In order to achieve the above object in the present invention, first, in claim 1, a wiring layer and an IC having a substrate connection electrode on one surface of an insulating base material and a via connection with the substrate connection electrode on the other surface are provided. A method for inspecting continuity of said wiring layer of an interposer substrate on which a chip connection electrode is formed, wherein said wiring layer is via-connected to an IC chip mounting region of said insulating substrate on the same surface as said substrate connection electrode. A continuity inspection method for an interposer substrate, wherein a common measurement electrode is provided, a measurement inspection probe is pressed against the substrate connection electrode and the common measurement electrode, and the continuity state of the wiring layer is inspected. Things.
[0011]
According to a second aspect of the present invention, there is provided the interposer substrate conduction inspection method according to the first aspect, wherein at least two or more of the common measurement electrodes are provided.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
The continuity inspection method for an interposer substrate according to the present invention includes providing a common measurement electrode on an IC chip mounting portion of the continuity inspection interposer substrate as an intermediate product, pressing a measurement inspection probe on the same surface of the continuity inspection interposer substrate, and wiring. This allows the conduction state of the layer to be inspected.
In the continuity test of the continuity test interposer substrate, the ends of a plurality of wiring layers are connected to a common measurement electrode to determine the continuity of each wiring layer and the short circuit between the wiring layers. Any number can be used, but in order to efficiently and accurately detect a short circuit between wiring layers, it is necessary to determine whether adjacent wiring layers are short-circuited by connecting adjacent wiring layers to different common measurement electrodes. It is preferred to provide two common measuring electrodes that can be used.
At the time when the continuity test is completed, the common measurement electrode is cut out of the IC chip mounting area and the common measurement electrode with a mold to form a device hole, or the common measurement electrode is removed by etching or the like. Obtain an interposer substrate in a product state.
[0013]
Hereinafter, a method for inspecting the continuity of the interposer substrate will be described.
First, a via hole is formed at a predetermined position of a copper foil of a copper-clad laminate in which a 12-μm-thick copper foil is attached to both sides of an insulating base material 11 made of a 50-μm-thick polyimide substrate by laser processing or the like. Plating is performed to form a conductor layer and filled via 22 having a predetermined thickness, a photoresist is applied on the conductor layer to form a photosensitive layer, and a series of patterning processes such as pattern exposure and development are performed to connect the substrate. The electrode 23, the common measurement electrodes 51 and 52, the wiring layer 21, the IC chip connection electrode 24, and the measurement wiring lead 25 are respectively formed, and after forming a solder resist pattern, nickel and gold plating are performed, and the insulating base material 11 is formed. Of the two-metal BGA continuity inspection interposer substrate 50 having the substrate connection electrode 23 and the common measurement electrodes 51 and 52 on the same surface (FIGS. 1A and 1B). And (c)).
Here, the common measurement electrodes 51 and 52 are formed in the IC chip mounting area, and the common measurement electrodes 51 and 52 are electrically connected to the IC chip connection electrodes 24 via the measurement wiring leads 25 and the filled vias 22. ing.
[0014]
Next, the measurement and inspection probes 101 are pressed against the substrate connection electrodes 23 of the continuity inspection interposer substrate 50, and the measurement and inspection probes 102a and 102b are pressed against the common measurement electrodes 51 and 52, and the continuity of the wiring layer 21 is set between the wiring layers 21. Is determined by the inspection apparatus 100 (see FIG. 2). Here, the measurement / inspection probes 101 are sequentially moved while the measurement / inspection probes 102a and 102b remain as they are to inspect the continuity of all wiring layers.
[0015]
Hereinafter, a continuity inspection method for determining the continuity of the wiring layer and the normality / abnormality of the short-circuit between the wiring layers by using two common measurement electrodes of the continuity inspection interposer substrate 50 will be described.
FIG. 3 shows an example in which there is no disconnection or short circuit in the wiring layers 21a and 21b. The measurement / inspection probe 101 is connected to the substrate connection electrode 23a, and the measurement / inspection probe 102a is connected to the common measurement electrode 51. When the continuity test is performed by connecting the probe 102b to the common measurement electrode 52, there is no disconnection or short circuit in the wiring layers 21a and 21b, so that the short-circuit indicator is turned off, the continuity indicator is turned on, and the wiring layer 21a is turned off. The inspection device 100 determines that the conduction state is normal and the short circuit between the wiring layers 21a and 21b is normal (see FIG. 3). Further, the measurement inspection probe 101 is sequentially moved to conduct a continuity inspection of all wiring layers.
[0016]
FIG. 4 shows a case where the wiring layer 21a is disconnected and there is no short circuit between the wiring layer 21a and the wiring layer 21b. When the probe 102a is connected to the common measurement electrode 51 and the measurement test probe 102b is connected to the common measurement electrode 52 to perform a continuity test, the continuity indicator is turned off, the short-circuit indicator is turned off, and the wiring layer 21a is in a conductive state. Is abnormal, and the inspection device 100 determines that the short circuit between the wiring layers 21a and 21b is normal (see FIG. 4).
[0017]
FIG. 5 shows a case where a short circuit occurs between the wiring layer 21a and the wiring layer 21b, and there is no disconnection between the wiring layer 21a and the wiring layer 21b. The measurement / inspection probe 101 is connected to the substrate connection electrode 23a. When the continuity test is performed by connecting the measurement test probe 102a to the common measurement electrode 51 and the measurement test probe 102b to the common measurement electrode 52, the continuity indicator is turned on, the short-circuit indicator is turned on, and the wiring layer 21a is turned off. The conduction state is normal, and the short circuit between the wiring layers 21a and 21b is determined to be abnormal by the inspection apparatus 100 (see FIG. 5).
[0018]
After conducting the continuity inspection of all the wiring layers of the continuity inspection interposer substrate 50, the common measurement electrodes 51 and 52 in the IC chip mounting area and the measurement wiring leads 25 are determined for the continuity inspection interposer substrate 50 which is determined to be non-defective. The insulating substrate on which is formed is punched out by a mold to produce an interposer substrate 60 having a device hole 41 at the center as shown in FIGS. 6 (a), 6 (b) and 6 (c).
[0019]
【The invention's effect】
By applying the continuity inspection method of the interposer substrate of the present invention, continuity inspection using a measurement probe on the same surface becomes possible, and furthermore, by providing a plurality of common measurement electrodes, the wiring layer of the interposer substrate can be inspected. The continuity and the short-circuit state between the wiring layers can be efficiently and accurately inspected, and an excellent practical effect in the continuity inspection field is exhibited.
[Brief description of the drawings]
FIG. 1A is a schematic plan view showing the surface of an example of a continuity inspection interposer substrate used in the continuity inspection method for an interposer substrate according to the present invention.
(B) is a schematic configuration sectional view of (a) cut along the line AA '.
(C) is a schematic plan view showing the back surface of an example of the continuity inspection interposer substrate used in the continuity inspection method of the interposer substrate of the present invention.
FIG. 2 is an explanatory diagram showing a state in which a continuity test is being performed using a continuity test interposer substrate.
FIG. 3 is an explanatory diagram showing a state where a continuity test is performed using a common measurement electrode and a substrate connection electrode.
FIG. 4 is an explanatory diagram showing a state in which a continuity test is performed using a common measurement electrode and a substrate connection electrode.
FIG. 5 is an explanatory diagram showing a state where a continuity test is performed using a common measurement electrode and a substrate connection electrode.
FIG. 6A is a schematic plan view showing a surface of an interposer substrate in a state where a continuity test is completed and a common measurement electrode and a measurement wiring lead are removed.
(B) is a schematic configuration sectional view of (a) cut along the line AA '.
(C) is a schematic plan view showing the back surface of the interposer substrate in a state where the continuity test has been completed and the common measurement electrode and the measurement wiring lead have been removed.
[Explanation of symbols]
11 Insulating base material 21, 21a, 21b Wiring layer 22 Filled via 23, 23a, 23b Board connecting electrode 24 IC chip connecting electrode 25 Measurement wiring lead 41 Device hole 50 continuity inspection interposer substrates 51, 52 common measurement electrode 60 interposer substrate 100 inspection devices 101, 102a, 102b measurement inspection probe

Claims (2)

A continuity test of the wiring layer of the interposer substrate in which an electrode for substrate connection is formed on one surface of the insulating base material and a wiring layer and an electrode for IC chip connection are formed on the other surface with the electrode for substrate connection via connection. A method, comprising: providing a common measurement electrode via-connected to the wiring layer in an IC chip mounting area of the insulating base on the same surface as the substrate connection electrode, and providing the substrate connection electrode and the common measurement electrode A continuity inspection method for an interposer substrate, wherein a continuity state of the wiring layer is inspected by pressing a measurement inspection probe. 2. The method according to claim 1, wherein at least two common measurement electrodes are provided.

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