JP2004014662A - Semiconductor device having Schottky barrier - Google Patents

Abstract

It is difficult to achieve a high breakdown voltage of a Schottky barrier diode while suppressing an increase in a forward voltage drop and an increase in a reverse recovery time.
A semiconductor substrate having an N type semiconductor region and a cathode side N ⁺ type semiconductor region is prepared. A plurality of inner P ⁺ -type semiconductor regions 16 are formed in a region of the substrate 10 where the first electrode 11 functioning as a Schottky barrier electrode is to be formed, and an outer P ⁺ -type semiconductor region functioning as a guard ring is formed in a portion surrounding these regions. 17 is formed. An anode-side N ⁺ -type semiconductor region 18 is arranged between the plurality of inner P ⁺ -type semiconductor regions 16. The first electrode 11 is brought into ohmic contact with the inner P ⁺ -type semiconductor region 16 and is brought into Schottky barrier contact with the anode-side N ⁺ -type semiconductor region 18. The second electrode 12 is not brought into contact with the outer P ⁺ type semiconductor region 17.
[Selection] Fig. 2

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device having a Schottky barrier such as a Schottky barrier diode.
[0002]
[Prior art]
As shown in FIG. 1, a conventional Schottky barrier diode includes an N ⁺ type semiconductor region 1, an N type semiconductor region 2 formed on one main surface thereof, and a P type semiconductor region formed in the N type semiconductor region 2. And a guard ring region 3 made of a semiconductor region.
An insulating film 4 is formed on one main surface of the semiconductor substrate, and the upper surface of the N-type semiconductor region 2 is exposed from an opening provided on the center side of the insulating film 4. The anode electrode 5 formed in the opening of the insulating film 4 contacts one main surface of the N-type semiconductor region 2 and forms a Schottky barrier at the interface. Further, a cathode electrode 6 is formed on the other main surface of the semiconductor substrate, and has a low resistance contact (ohmic contact) with the other main surface of the N ⁺ type semiconductor region 1.
[0003]
[Problems to be solved by the invention]
A typical Schottky barrier diode having no guard ring region 3 has a lower forward voltage drop than a high-speed recovery diode using a PN junction or the like, and has a very short reverse recovery time trr because it is a majority carrier device. It has the advantage that it can be made smaller. On the other hand, the Schottky barrier diode has the disadvantage that it is difficult to increase the breakdown voltage as compared with the PN junction diode, and that the reverse current tends to increase due to the electric field concentration at the interface between the insulating film and the anode electrode.
For this reason, as shown in FIG. 1, the guard ring region 3 is formed so as to include the boundary between the insulating film 4 and the anode electrode 5, thereby improving the peripheral breakdown voltage of the Schottky barrier and suppressing the reverse current.
However, in the Schottky barrier diode in which such a guard ring region 3 is formed, the breakdown voltage is determined when the depletion layer extending from the guard ring region 3 reaches the N ⁺ type semiconductor region 1. That is, the extension of the depletion layer is limited by the N ⁺ type semiconductor region 1, and the improvement of the breakdown voltage is also limited. Therefore, in order to increase the breakdown voltage, it is necessary to increase the specific resistance of the N-type semiconductor region 2 and increase the thickness of the N-type semiconductor region 2. However, when the specific resistance of the N-type semiconductor region 2 is increased and the thickness of the N-type semiconductor region 2 is increased so as to obtain a high breakdown voltage, the high-frequency characteristics (switching characteristics), which are the advantages of the Schottky barrier diode, are reduced. The forward characteristics are significantly impaired.
[0004]
Therefore, an object of the present invention is to provide a semiconductor device having a Schottky barrier that can improve both the forward characteristics and the breakdown voltage characteristics.
[0005]
[Means for Solving the Problems]
The present invention for solving the above problems and achieving the above object includes a semiconductor substrate and first and second electrodes, wherein the substrate has a portion exposed on one main surface of the substrate. A first semiconductor region of the first conductivity type disposed and a higher impurity concentration than the first semiconductor region, the first semiconductor region being disposed between the first semiconductor region and the other main surface of the substrate; A second semiconductor region of the first conductivity type having a predetermined cross-sectional shape, the cross-sectional shape of the second semiconductor region extending from one main surface of the substrate into the first semiconductor region; A third semiconductor region of a second conductivity type including a plurality of regions or a plurality of portions, and a region outside the third semiconductor region in a plan view continuously or intermittently via the first semiconductor region. And surrounding the first semiconductor from one main surface of the substrate. A fourth semiconductor region of the second conductivity type extending into the region and at least a portion between the plurality of third semiconductor regions or between the plurality of portions of the third semiconductor region. A fifth semiconductor region of a first conductivity type, which is arranged to be filled and has a higher impurity concentration than the first semiconductor region, wherein the first electrode is provided in the fifth semiconductor region And is formed on one main surface of the substrate so as to make a Schottky contact with the third semiconductor region and an ohmic contact with the third semiconductor region, and not to contact the fourth semiconductor region. The present invention relates to a semiconductor device having a Schottky barrier, which is electrically connected to the second semiconductor region.
[0006]
It is preferable that the first electrode is in contact with the first semiconductor region inside the fourth semiconductor region.
Preferably, the fifth semiconductor region is formed at a depth equal to or less than the depth of the third semiconductor region.
Preferably, the depth of the third and fifth semiconductor regions is at least 1/6 of the thickness of the first semiconductor region.
According to a fifth aspect of the present invention, the mutual interval between the third semiconductor regions is determined so as to be filled with a depletion layer when a rated reverse voltage is applied between the first and second electrodes. Is desirable.
[0007]
【The invention's effect】
The invention of each claim of the present application has the following effects.
(1) The depletion layer expands when a reverse voltage is applied to the fifth semiconductor region surrounded by the third semiconductor region when viewed in plan, and the first semiconductor region adjacent to the third semiconductor region. The depletion layer also extends to the area surrounding the fourth semiconductor region. Therefore, the reverse breakdown voltage is determined by the combination of the plurality of depletion layers, and a semiconductor device with excellent reverse breakdown voltage can be provided.
(2) The fifth semiconductor region serving as a passage for majority carriers flowing through the Schottky barrier when a forward voltage is applied has a higher impurity concentration and a lower resistivity than the first semiconductor region. The forward voltage drop in the passage is reduced.
(3) The fourth semiconductor region is not connected to the first electrode. Therefore, when a reverse voltage is applied, the PN junction between the fourth semiconductor region and the first semiconductor region and the change in the electric field intensity in the vicinity thereof become more gradual than in the case of the conventional structure of FIG. Will be better.
[0008]
[First Embodiment]
Next, a first embodiment of the present invention will be described with reference to FIGS.
As shown in FIG. 1, a diode having a Schottky barrier as a semiconductor device according to the first embodiment of the present invention includes a semiconductor substrate 10 such as silicon or a Group 3-5 compound semiconductor and first and second electrodes 11 and 12. And an insulating film 13.
[0009]
The semiconductor substrate 10 includes an N-type semiconductor region 14 as a first semiconductor region, a cathode-side N ⁺ type semiconductor region 15 as a second semiconductor region, and an inner P ⁺ type semiconductor region 16 as a third semiconductor region. And an outer P ⁺ -type semiconductor region 17 as a fourth semiconductor region or a guard ring region, and an anode-side N ⁺ -type semiconductor region 18 as a fifth semiconductor region.
[0010]
The N-type semiconductor region 14 is formed on the upper surface of the cathode-side N ⁺ -type semiconductor region 15 by well-known epitaxial growth. The specific resistance of the N-type semiconductor region 14 is 2.5 Ωcm, which is higher than the specific resistance (4.5 Ωcm) of the N-type semiconductor region of a diode having a conventional JBS structure, that is, a diode in which Schottky junctions and PN junctions are alternately arranged. Is also getting smaller. This is because the diode in FIG. 2 does not have a structure in which the breakdown voltage is determined by the depletion layer extending from the guard ring reaching the N ⁺ -type semiconductor region 15 as in the conventional diode. a structure breakdown voltage by a depletion layer is borne to be formed so as to fill the formed on one main surface 19 side a and the P ⁺ -type semiconductor regions 16, 17 N ⁺ -type semiconductor region 18, anode-side N ⁺ -type semiconductor This is because the specific resistance of the region 18 and the N-type semiconductor region 14 can be set relatively small.
In FIG. 2, the thickness of the N-type semiconductor region 14 from one main surface 19 of the substrate 10 is determined to be relatively thin, 12 μm. This is because the diode of FIG. 2 does not have a structure in which the breakdown voltage is determined by the depletion layer extending from the guard ring region 3 reaching the N ⁺ type semiconductor region 1 as in the conventional diode of FIG.
[0011]
Cathode-side N ⁺ -type semiconductor region 15 has a higher impurity concentration and lower resistivity than N-type semiconductor region 14, and is arranged between N-type semiconductor region 14 and the other main surface 20 of substrate 10. Have been.
[0012]
As shown in FIG. 3, the inner P ⁺ type semiconductor region 16 is composed of a plurality (25) of regions that are dispersed and viewed in plan. Each of the inner P ⁺ -type semiconductor regions 16 is regularly arranged in five rows and five columns with a predetermined mutual interval W1, for example, 2.94 μm in the planar shape of FIG. Also in the cross-sectional shape of FIG. 2, the inner P ⁺ type semiconductor regions 16 are juxtaposed with a predetermined interval. The depth of each inner P ⁺ -type semiconductor region 16 is set to be equal to or more than ６ of the thickness Wn of the N-type semiconductor region 14 from one main surface 19 of the substrate 10 and less than Wn. That is, the P ⁺ type semiconductor region 16 has a depth of, for example, Wn / 4 = 2.96 μm that does not reach the cathode side N ⁺ type semiconductor region 15. The preferred depth of the P ⁺ type semiconductor regions 16 and 17 is 1/6 to 1/2 of the thickness Wn of the first semiconductor region 14, and the more preferred depth is 1/5 to 1/3 of Wn. The width of each inner P ⁺ type semiconductor region 16 is, for example, 3.06 μm.
[0013]
The outer P ⁺ -type semiconductor region 17 is annularly arranged at a position separated by a predetermined distance W2 from the outermost envelope in plan view of the plurality of inner P ⁺ -type semiconductor regions 16 so as to function as a guard ring region. Have been. The outer P ⁺ type semiconductor region 17 is formed to have the same depth, the same width, and the same impurity concentration as the inner P ⁺ type semiconductor region 16 except for the plane pattern. The surface of the outer P ⁺ type semiconductor region 17 is covered with the insulating film 13 and is not connected to the first electrode 11.
When simultaneously forming the inner and outer P ⁺ -type semiconductor regions 16 and 17, a diffusion mask made of a silicon oxide film or the like formed by a known photolithography technique is used, and the N-type semiconductor region 14, that is, one main surface of the substrate 10 is used. 19, a P-type impurity is selectively ion-implanted and thermally diffused (drived). P-type impurity concentration of the inner and outer ^{P +} -type semiconductor regions 16 and 17 is higher than the N-type impurity concentration of the N-type semiconductor region 14, the surface impurity concentration of the inner and outer ^{P +} -type semiconductor regions 16 and 17, for example 3. It is 5 × 10 ¹⁶ cm ⁻³ .
[0014]
The anode-side N ⁺ -type semiconductor regions 18 are arranged between the inner peripheral side P ⁺ -type semiconductor regions 16 and are formed in a mesh-like or lattice-like pattern in the planar shape of FIG. Anode N ⁺ -type N-type impurity concentration of the semiconductor region 18 is lower than the P-type impurity concentration of the N-type semiconductor region 14 of the N-type impurity concentration and higher than the inner P ⁺ type semiconductor region 16, the anode-side N ⁺ -type The N-type surface impurity concentration of the semiconductor region 18 is, for example, 1.3 × 10 ¹⁶ cm ⁻³ .
In FIG. 2, the depth of the anode-side N ⁺ type semiconductor region 18 from one main surface 19 of the substrate 10 is 2.71 μm, which is slightly smaller than the depth of the P ⁺ type semiconductor region 16. The preferred depth of the anode-side N ⁺ type semiconductor region 18 is 1/6 to 1/2 of Wn, and the more preferred depth is 1/5 to 1/3 of Wn. The width of the anode-side N ⁺ type semiconductor region 18 is 2.94 μm, which is the same as the mutual interval W1 of the P ⁺ type semiconductor region 16.
The width of the anode-side N ⁺ type semiconductor region 18 can be made slightly smaller than the mutual interval W1 of the P ⁺ type semiconductor region 16. In this case, both the N ⁺ -type semiconductor region 18 and the N-type semiconductor region 14 are arranged between the P ⁺ -type semiconductor regions 16.
[0015]
When the anode side N ⁺ type semiconductor region 18 is formed, a well-known photolithography technique is applied to the main surface of the N type semiconductor region 14, that is, one main surface 19 of the substrate 10, similarly to the formation of the P ⁺ type semiconductor regions 16 and 17. A diffusion mask made of a silicon oxide film or the like is formed by using the mask, and an N-type impurity is selectively ion-implanted using the mask and thermally diffused (driven in).
[0016]
The anode or first electrode 11 is made of a metal (for example, titanium and aluminum) capable of generating a Schottky barrier for the N-type semiconductor region 14 and the N ⁺ -type semiconductor region 18. 2 and 3, the first electrode 11 is disposed on one main surface 19 of the substrate 10, makes Schottky contact with the N ⁺ -type semiconductor region 18 and the N-type semiconductor region 14, ^It has low resistance contact with the ⁺ type semiconductor region 16. However, the first electrode 11 is not connected to the outer P ⁺ type semiconductor region 17. The surface of the outer P ⁺ -type semiconductor region 17 and the exposed surface of the N-type semiconductor region 14 on one main surface 19 of the substrate 10 are covered with an insulating film 13 made of, for example, a silicon oxide film.
In FIG. 2, the outer peripheral end of the first electrode 11 is disposed between the outer P ⁺ type semiconductor region 17 and the inner P ⁺ type semiconductor region 16, but on the insulating film 13 as shown by a dotted line. It can be extended as a field plate.
[0017]
The cathode electrode or second electrode 12 is disposed on the other main surface 20 of the substrate 10 and is connected to the N ⁺ type semiconductor region 15 with a low resistance contact, that is, electrically.
[0018]
When a forward voltage, that is, a voltage at which the potential of the first electrode 11 becomes higher than the potential of the second electrode 12, is applied between the first and second electrodes 11 and 12 to the Schottky barrier diode of FIG. A current based on majority carriers passing through a Schottky barrier flows through a path including the electrode 11, the anode-side N ⁺ -type semiconductor region 18, the N-type semiconductor region 14, the cathode-side N ⁺ -type semiconductor region 15, and the second electrode 12, In addition, a current flowing through the PN junction flows through a path including the first electrode 11, the inner P ⁺ type semiconductor region 16, the N type semiconductor region 14, the cathode side N ⁺ type semiconductor region 15, and the second electrode 12.
[0019]
When a reverse voltage in which the potential of the first electrode 11 is lower than the potential of the second electrode 12 is applied between the first and second electrodes 11 and 12, the inner P ⁺ -type semiconductor region 16 and the N ⁺ -type semiconductor The PN junction formed at the interface with the region 18, the PN junction formed at the interface between the inner P ⁺ -type semiconductor region 16 and the N-type semiconductor region 14, and the PN junction between the first electrode 11 and the N ⁺ -type semiconductor region 18. The depletion layers spread from the Schottky junction formed at the interface and the PN junction between the outer P ⁺ -type semiconductor region 17 and the N-type semiconductor region 14, respectively. When a rated reverse voltage or a maximum allowable reverse voltage is applied between the first and second electrodes 11 and 12, the depletion layer extending from each of the above junctions is continuously integrated as shown by a dotted line 21 in FIG. Be converted to The depletion layer spreads between the inner P ⁺ -type semiconductor regions 16, that is, the entirety of the anode-side N ⁺ -type semiconductor region 18. Since the N-type semiconductor region 14 having a relatively low impurity concentration is located between the outermost inner P ⁺ -type semiconductor region 16 and the outermost P ⁺ -type semiconductor region 17, the depletion layer is easily extended. Buried. The outer P ⁺ -type semiconductor region 17 is not connected to the first electrode 11, but a potential obtained by dividing the voltage between the first and second electrodes 11 and 12 by resistance is applied to the outer P ⁺ -type semiconductor region 17. The depletion layer also extends to the N-type semiconductor region 14 surrounding the outer P ⁺ -type semiconductor region 17. In FIG. 2, the depletion layer indicated by the dotted line 21 extends only in the N-type semiconductor region 14. However, when the reverse voltage is large, the depletion layer may spread to reach or enter the cathode-side N ⁺ -type semiconductor region 15. .
[0020]
According to the present embodiment, the following effects can be obtained.
(1) Since not only the outer P ⁺ -type semiconductor region 17 functioning as a guard ring region but also a plurality of inner P ⁺ -type semiconductor regions 16 connected to the first electrode 11 are provided, the central portion of the substrate 10 is flat. It is possible to obtain a depletion layer that has good properties and gradually narrows in the peripheral portion of the substrate 10, and can stably achieve a high breakdown voltage.
That is, in the conventional Schottky barrier diode of FIG. 1, P ⁺ -type continuity of the depletion layer extending from the guard ring region 3 and the depletion layer extending from the Schottky junction is poor, contrary to the depletion layer extending from the P ⁺ -type guard ring region 3 Directional voltage is intensively applied, and breakdown may occur pinpointly in this region. For this reason, it is difficult to increase the breakdown voltage of the Schottky barrier diode, and the variation in breakdown voltage during mass production has increased. On the other hand, in the Schottky barrier diode of FIG. 2 according to the present invention, when a reverse voltage is applied, the depletion layer indicated by the dotted line 21 can be formed in an ideal state or a state close to the ideal state where local electric field concentration can be prevented. Thus, a high withstand voltage is achieved, and variations in the withstand voltage during mass production are reduced. The prevention of breakdown on the outer peripheral side of the substrate 10 is achieved by not connecting the outer P ⁺ type semiconductor region 17 to the first electrode 11. That is, the voltage between the first and second electrodes 11 and 12 is directly applied to the PN junction between the inner P ⁺ -type semiconductor region 16 and the N-type semiconductor region 14, and the depletion layer spreads relatively large. , the outer P ⁺ -type semiconductor region 17 PN between the outer P ⁺ -type semiconductor region 17 and the N-type semiconductor region 14 to be applied by dividing the voltage between the first and second electrodes 11 and 12 The expansion of the depletion layer from the junction is smaller than the expansion of the depletion layer from the inner P ⁺ type semiconductor region 16, and a depletion layer gradually narrowing toward the periphery of the substrate 10 can be obtained, and the withstand voltage characteristics are improved. .
(2) If the withstand voltage is the same as that of the conventional example shown in FIG. 1, the thickness of the N-type semiconductor region 14 can be made smaller (for example, 1/4) than in FIG.
(3) Despite the provision of the inner P ⁺ -type semiconductor region 16 to improve the breakdown voltage, an N ⁺ -type semiconductor having a lower resistivity than the N-type semiconductor region 14 between the inner P ⁺ -type semiconductor regions 16. Since the region 18 is provided, a forward voltage drop can be reduced.
(4) The switching characteristics of the diode become relatively good. That is, in the diode of FIG. 2, the impurity concentration is relatively lower than that of the N-type semiconductor region 14 between the inner P ⁺ -type semiconductor region 16 for obtaining the PN junction forming the depletion layer that achieves good electric field relaxation. A high N ⁺ type semiconductor region 18 is formed. Therefore, although the area of the P ⁺ -type semiconductor regions 16 and 17 as compared to the Schottky barrier diode having a conventional guard ring region 3 of FIG. 1 is increased, a large part of the inner P ⁺ type semiconductor region 16 Since it is in contact with the N ⁺ type semiconductor region 18 having a relatively high impurity concentration, the injection amount of minority carriers from the inner P ⁺ type semiconductor region 16 is suppressed, and the conductivity modulation is suppressed. As a result, the amount of the minority carriers accumulated in the N ⁺ -type semiconductor region 18 at the end of the forward voltage application, that is, at the start of the reverse voltage application, is reduced, as compared with the case where the anode-side N ⁺ -type semiconductor region 18 is not provided. The reverse recovery time is shorter, and the switching speed is faster.
(5) Since the impurity concentration of the N-type semiconductor region 14 is determined to be lower than that of the conventional JBS structure and the thickness Wn is as small as 12 μm, minority carriers from the inner P ⁺ -type semiconductor region 16 to the N-type semiconductor region 14 Injection is less than in the conventional JBS structure, the reverse recovery time is shorter, and the switching speed is faster. Also, the forward voltage drop is smaller than that of the conventional JBS structure.
(6) Since a depletion layer is formed below the insulating film 13 around the first electrode 11 of the substrate 10, the leakage current when a reverse voltage is applied can be reduced.
[0021]
[Second embodiment]
Next, a Schottky barrier diode according to a second embodiment will be described with reference to FIG. However, in FIG. 4 and FIG. 5, which will be described later, portions that are substantially the same as those in FIGS. 2 and 3 are denoted by the same reference numerals, and description thereof is omitted.
[0022]
The Schottky barrier diode of the second embodiment has the same configuration as that of FIGS. 2 and 3 except that the outer P ⁺ type semiconductor region 17 of FIGS. 2 and 3 is modified to 17a. A plurality (24) of the outer P ⁺ type semiconductor regions 17a in FIG. 4 is provided. The plurality of outer P ⁺ -type semiconductor regions 17a in FIG. 14 are distributed at the same positions as the outer P ⁺ -type semiconductor regions 17 in FIG. That is, the outer P ⁺ -type semiconductor regions 17a are intermittently arranged with an interval W1 such that when a rated reverse voltage is applied, the N-type semiconductor regions 14 therebetween are filled with a depletion layer. .
[0023]
Even when the outer P ⁺ type semiconductor region 17a is formed as shown in FIG. 4, a depletion layer similar to that shown in FIG. 2 can be obtained when a reverse voltage is applied. Therefore, the same effects as in the first embodiment can be obtained also in the second embodiment.
[0024]
[Modification]
The present invention is not limited to the above embodiment, and for example, the following modifications are possible.
(1) As shown in FIG. 5, the inner P ⁺ -type semiconductor region 16 and the anode-side N ⁺ -type semiconductor region 18 can be formed in a ring shape. Also in this case, the interval between the plurality of P ⁺ -type semiconductor regions 16 is set to be filled with the depletion layer. Thereby, the same effect as in the first and second embodiments can be obtained.
(2) A plurality of the inner P ⁺ type semiconductor regions 16 in FIG. 3 are formed in a lattice shape, a mesh shape, or a comb shape, and are juxtaposed at predetermined mutual intervals in the cross section of the grid, the mesh shape, or the comb shape. The anode-side N ⁺ type semiconductor region 18 can be arranged between the portions. That is, generally to replace the portion of the N ⁺ -type semiconductor region 18 in FIG. 3 to the third P ⁺ type semiconductor region 16 serving as the semiconductor region, a portion of the P ⁺ -type semiconductor region 16 in FIG. 3 N ⁺ -type The semiconductor region 18 can be replaced. In this case, the inner P ⁺ -type semiconductor region becomes one continuous one, and this one inner P ⁺ -type semiconductor region has a plurality of portions facing each other.
(3) The extension of the cathode-side N ⁺ type semiconductor region 15 is led out to one main surface 19 of the substrate 10, and the second electrode 12 can be connected thereto.
(4) The depth of the P ⁺ type semiconductor regions 16 and 17 and the depth of the N ⁺ type semiconductor region 18 can be arbitrarily changed. However, the depths of the P ⁺ -type semiconductor regions 16 and 17 and the N ⁺ -type semiconductor region 18 formed on one main surface 19 of the semiconductor substrate 10 make it possible to favorably concentrate the electric field on one main surface side of the semiconductor substrate 10. In order to form a depletion layer that can be relaxed, it is desirable that the thickness is set to 1/6 or more, preferably 1/5 or more of the thickness of the N-type semiconductor region 14. On the other hand, if the P ⁺ -type semiconductor regions 16 and 17 and the N ⁺ -type semiconductor region 18 are too deep, the depletion layer reaches the cathode-side N ⁺ -type semiconductor region 15 in a point manner, and a high breakdown voltage can be stably obtained. Absent. Therefore, it is desirable to set the thickness of the N-type semiconductor region 14 to 以下 or less, preferably １ ／ or less.
(5) The impurity concentration of each region can be arbitrarily changed. However, when a predetermined reverse voltage is applied, in order to obtain a continuous depletion layer as indicated by a dotted line 21 in FIG. 2, the impurities in the P ⁺ -type semiconductor regions 16 and 17 and the anode-side N ⁺ -type semiconductor region 18 are removed. The concentration is preferably set to 5 to 100 times the impurity concentration of the N-type semiconductor region 14.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a conventional Schottky barrier diode.
FIG. 2 is a cross-sectional view showing the Schottky barrier diode according to the first embodiment of the present invention at a portion corresponding to FIG. 3A-A.
FIG. 3 is a plan view showing the surface of the semiconductor substrate of FIG. 2;
FIG. 4 is a plan view showing a substrate of a Schottky barrier diode according to a second embodiment, similarly to FIG.
FIG. 5 is a plan view showing a part of a substrate of a Schottky barrier diode according to a modified example.
[Explanation of symbols]
Reference Signs List 10 Substrates 11, 12 First and second electrodes 14 N-type semiconductor region 15 Cathode-side N ⁺ -type semiconductor region 16 Inside P ⁺ -type semiconductor region 17 Outside P ⁺ -type semiconductor region 18 Anode-side N ⁺ -type semiconductor region

Claims (5)

A semiconductor substrate and first and second electrodes,
The substrate is
A first conductivity type first semiconductor region disposed so as to have a portion exposed on one main surface of the substrate;
A second semiconductor region of a first conductivity type disposed between the first semiconductor region and the other main surface of the substrate and having a higher impurity concentration than the first semiconductor region;
In the cross-sectional shape, a second conductive type of a plurality of regions or a plurality of portions formed to extend from one main surface of the substrate into the first semiconductor region and have a predetermined mutual interval. A third semiconductor region;
The first semiconductor region is disposed so as to continuously or intermittently surround the outside of the third semiconductor region via the first semiconductor region when viewed in a plan view, and from one main surface of the substrate to the first semiconductor region. A fourth semiconductor region of the second conductivity type extending therein;
The semiconductor device is disposed so as to fill at least a part between the plurality of third semiconductor regions or between the plurality of portions of the third semiconductor region, and has a higher impurity concentration than the first semiconductor region. A fifth semiconductor region of the first conductivity type, the first electrode being in Schottky contact with the fifth semiconductor region, being in ohmic contact with the third semiconductor region, and being in contact with the third semiconductor region. 4 is formed on one main surface of the substrate so as not to contact the semiconductor region,
The semiconductor device having a Schottky barrier, wherein the second electrode is electrically connected to the second semiconductor region. 2. The semiconductor device according to claim 1, wherein the first electrode is in contact with the first semiconductor region inside the fourth semiconductor region. The semiconductor device according to claim 1, wherein the fifth semiconductor region is formed at a depth equal to or less than a depth of the third semiconductor region. 4. The semiconductor device according to claim 1, wherein a depth of the third and fifth semiconductor regions is equal to or more than ６ of a thickness of the first semiconductor region. 5. The distance between the plurality of third semiconductor regions or the distance between the plurality of portions of the third semiconductor region is filled with a depletion layer when a rated reverse voltage is applied between the first and second electrodes. The semiconductor device according to claim 1, 2, 3, or 4, wherein the value is determined so as to be determined.

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