JP2004012890A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a partial display by selecting an optional partial display area, and to reduce the power consumption. <P>SOLUTION: A mask circuit 210, which supplies video signals to each pixel of the partial display area selected in accordance with display area selection signals DS' and also masks the supply of the video signals to each pixel of a background display area is provided. Thus, the display device capable of partially displaying an optional pattern at an optional position can be realized. An inversion control circuit 250, which inverts the background display signals supplied to each pixel of the background display area at every one frame in accordance with display area selection signals DS' is also provided. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a display device such as a liquid crystal display device, and more particularly to a display device capable of displaying only a necessary minimum portion of a display screen and capable of partial display.
[0002]
[Prior art]
In mobile devices, further reduction in power consumption is required, and in display devices, further reduction in power consumption is also required. Therefore, a display device capable of performing a partial display in which only a necessary minimum portion of the screen is displayed at the time of power saving is conventionally known. In such a partial display, for example, a fixed pattern display area for displaying the remaining battery power and time is provided in a part of the display area of the liquid crystal display device, and a plurality of pixels are arranged in a matrix in the other area. This can be realized by configuring an area for displaying an arbitrary pattern and driving only the fixed pattern display area during power saving to display a fixed pattern.
[0003]
[Problems to be solved by the invention]
As described above, if a plurality of regions that can be individually driven are provided on the same display panel and driving is separately controlled, only a part of the region can be displayed as required. However, even during power saving, there is a demand to display at an arbitrary position or to display an arbitrary pattern, and a display device that individually controls display areas divided in advance cannot meet this demand.
[0004]
Further, since the display contents and display position at the time of power saving are different depending on the model in which the display device is mounted, the structure of the display panel and the drive circuit must be developed exclusively according to the request.
[0005]
With a matrix type display device, an arbitrary display can be displayed at an arbitrary position.However, even when only a part of the pattern is displayed in the partial display, the other regions can be driven as usual. Since this is necessary, the effect of reducing the power consumption by the partial display is low.
[0006]
In order to solve the above-described problems, an object of the present invention is to provide a display device that can partially display an arbitrary pattern at an arbitrary position and that can reduce power consumption at that time as needed.
[0007]
[Means for Solving the Problems]
A feature of the present invention is to provide a plurality of pixels, supply a desired video signal to a selected partial display area to perform a partial display, and supply a background display signal to a background display area other than the partial display area to supply a background display signal. A display device that performs display, and supplies the video signal to each pixel of the partial display area selected according to a display area selection signal, and supplies the video signal to each pixel of the background display area. It is to have a mask circuit for masking.
[0008]
This makes it possible to realize a display device that can partially display an arbitrary pattern at an arbitrary position.
[0009]
Another feature of the present invention is that, in addition to the above-described features, an inversion control circuit that inverts a background display signal supplied to each pixel of the background display area for each frame according to the display area selection signal.
[0010]
Thus, power consumption in the partial display can be reduced.
[0011]
Still another feature of the present invention is that, in addition to the above features, the video signal is amplified, and the amplifier has a gain that can be variably controlled in accordance with a display area selection signal. It is to lower the gain.
[0012]
Thereby, the power consumption in the partial display can be further reduced.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
FIG. 1 is a configuration diagram of a display device according to the first embodiment of the present invention. The liquid crystal panel 100 includes a plurality of pixels arranged in a matrix of n rows and m columns, and each pixel includes a pixel selection transistor, a liquid crystal, and an auxiliary capacitance.
[0014]
A gate line 110 extending in the row direction is connected to the gate of the pixel selection transistor, and a drain line 120 extending in the column direction is connected to its drain. A gate scanning signal is sequentially supplied to a gate line 110 of each row from a vertical scanner (V scanner) 130, and a pixel selection transistor is selected accordingly. Further, an RGB video signal is supplied to the drain line 120 in accordance with a drain scanning signal from a horizontal scanner (H scanner) 140, and is applied to the liquid crystal through a pixel selection transistor.
[0015]
Further, a peripheral drive circuit 200 that supplies power and various drive signals to the liquid crystal panel 100 is provided. The peripheral drive circuit 200 includes a mask circuit 210 for masking RGB video data (digital data) in accordance with the display area selection signal DS ′, and a DA for converting the RGB video data passed through the mask circuit 210 into an analog video signal. A converter 220 and an amplifier 230 for amplifying the video signal from the DA converter 220 are included. The RGB video signal amplified by the amplifier 230 is supplied to the LCD panel 100.
[0016]
Here, the mask circuit 210, for example, passes the incoming RGB video data as it is when the display area selection signal DS ′ is HIGH, and masks the incoming RGB video data when the display area selection signal DS ′ is LOW, The preset background display data is output. In the latter case, the mask circuit 210 forcibly sets, for example, all bits of the RGB video data to HIGH in correspondence with, for example, white display or black display, and outputs the data.
[0017]
The peripheral drive circuit 200 includes a timing controller 240 (T / C). The timing controller 240 supplies timing signals necessary for the operations of the vertical scanner 130 and the horizontal scanner 140 of the LCD panel 100 based on timing signals such as the dot clock DOTCLK, the horizontal synchronization signal Hsync, and the vertical synchronization signal Vsync. Further, the timing controller 240 adjusts the timing of the external display area selection signal DS.
[0018]
This timing adjustment is, for example, a timing adjustment for synchronizing the display area selection signal DS with the RGB video data. The display area selection signal DS ′ whose timing has been adjusted is supplied to the mask circuit 210. Note that this timing adjustment is unnecessary depending on the system configuration, and the display area selection signal DS may be supplied to the mask circuit 210 directly without passing through the timing controller 240 or at all.
[0019]
As described above, in the display device having the above-described configuration, the display mode is switched between the partial display mode and the normal display mode using the display area selection signal DS from the outside. For example, if the display area selection signal DS is HIGH over the entire pixel area, the normal display mode is set.
[0020]
In the partial display mode, partial display (normal display) is performed while the display area selection signal DS is HIGH, and background display is performed by masking the RGB video data by the mask circuit 210 while the display area selection signal DS is LOW. . However, since the display area selection signal DS is supplied from outside the display device, it is inconvenient since the display device cannot determine whether the display mode is the partial display mode or the normal display mode.
[0021]
Therefore, there is provided a display mode determination circuit 300 that detects the signal level of the display area selection signal DS ′ from the timing controller 240 and determines whether the display mode is the partial display mode or the normal display mode.
[0022]
Next, a liquid crystal panel 100 including pixels in an n-row m-column matrix will be described as an example. Here, an example will be described in which n = 220 and m = 176. FIG. 2 is a waveform diagram of the display area selection signal DS ′, and FIG. 3 is a diagram showing a display state of the liquid crystal panel 100. As shown in FIG. 2A, when viewed in the horizontal scanning system (H system), the display area selection signal DS 'is HIGH only during a period necessary for scanning 176 columns during the 1H period. In this case, the RGB video signal is written to each pixel through the drain line 120 of each column, and normal display is performed.
[0023]
On the other hand, in the waveform of the vertical scanning system (V system) in FIG. 2B, in the normal display mode, the display area selection signal DS ′ scans all 220 rows during one frame period to drive all pixels. Is high only for the necessary period. However, this is a macroscopic view, and is actually LOW during the blanking period as shown in FIG.
[0024]
As described above, in the normal display mode, 220 rows of gate lines are sequentially selected during one frame period, and at the same time, a desired RGB video signal is supplied to 176 columns of drain lines 120, and the RGB video signals are supplied to the pixels corresponding to each row. Is written, all the pixels are displayed as shown in FIG.
[0025]
On the other hand, in the partial display mode, as shown in FIG. 2B, the display area selection signal DS 'is HIGH only during a period necessary for scanning a predetermined row during one frame period, and is LOW during other periods. become. Thus, an arbitrary partial display area 101 is selected. For example, the desired partial display is performed in the first 30 rows × 176 columns as the partial display area 101, and the remaining area is the background display area 102, and the background display is performed. Further, an arbitrary area can be set as the partial display area 101 by controlling the timing of setting the display area selection signal DS ′ to HIGH.
[0026]
Specifically, in the background display area 102, white is displayed in the case of a normally white liquid crystal panel 100 in which white is displayed when the voltage applied to the liquid crystal is 0V (although it is actually several V). (See FIG. 3 (b)). Further, in the case of the normally black liquid crystal panel 100 in which black is displayed when the voltage applied to the liquid crystal is 0 V (although it is actually several V), black is displayed. Then, when returning to the normal display mode, all pixels are displayed as shown in FIG.
[0027]
As described above, an arbitrary partial display area 101 can be selected and partial display can be realized only by using one signal called the display area selection signal DS ′. The problem is how to reduce the power consumption during a certain period. Generally, in a liquid crystal panel, a so-called line inversion drive for inverting the polarity of a video signal for each line is used in order to prevent deterioration of liquid crystal. However, each time the polarity of the video signal is inverted, charging and discharging are repeated in the opposite polarity, so that the power consumption of the peripheral driving circuit increases.
[0028]
Therefore, in the present invention, in order to reduce power consumption, {circle around (1)} a method of inverting the background display signal not by line inversion driving but by frame inversion driving (inverting the polarity of the video signal for each frame). (2) A method of using a precharge signal generally used in a liquid crystal panel as a background display signal is further proposed. Specific embodiments will be described in detail in the second and third embodiments.
[0029]
The above-described display mode determination is performed by the display mode determination circuit 300. Specifically, in the above-described example, if the display area selection signal DS ′ maintains HIGH during the scanning period of 220 rows. It is determined that the display mode is the normal display mode, and if the HIGH period is shorter, the display mode is determined to be the partial display mode. Alternatively, if the display area selection signal DS 'is HIGH at a timing corresponding to a specific row (for example, 100 rows), it is determined that the display mode is the normal display mode. If the display area selection signal DS' is LOW at that timing, the partial display mode is selected. Mode is determined. As a result, the display mode determination circuit 300 outputs an inversion control signal IS for switching between frame inversion driving and line inversion driving in the partial display mode, as described later.
[0030]
[Second embodiment]
In the present embodiment, in order to reduce power consumption in the partial display mode, during the background display period in which the display selection signal DS 'is LOW, the polarity of the background display signal is inverted for each frame.
[0031]
FIG. 4 shows the configuration of the display device of the present embodiment. An inversion control circuit 250 for inverting and controlling the video signal analog-converted by the DA converter 220 is provided. The inversion control circuit 250 drives the video signal in line inversion while the display area selection signal DS ′ is HIGH (partial display period), and converts the video signal into a frame while the display selection signal DS ′ is LOW (background display period). Drive in reverse.
[0032]
The video signal from the inversion control circuit 250 is applied to an amplifier 230A whose gain can be variably controlled. The amplifier 230A performs an amplification operation with a gain G1 when the display selection signal DS 'is HIGH, and performs an amplification operation with a gain G2 (G2 <G1) lower than G1 when the display region selection signal DS' is LOW. . During the period when the display area selection signal DS 'is LOW (background display period), the video signal is subjected to frame inversion driving. Therefore, there is no problem even if the gain required for the amplifier 230A is smaller than that in line inversion driving. Therefore, only during this period, the gain of the amplifier 230A is reduced to reduce power consumption.
[0033]
FIG. 5 shows a waveform diagram in the partial display mode. During one frame period, during the background display period in which the display selection signal DS ′ is LOW, the background display signal is, for example, 5 V which is lower by 1 V than the video center 6 V, and during the background display period of the next one frame period, the video signal is Is 7V which is higher than the video center 6V by 1V, for example, and in the partial display mode, the polarity of the background display signal is inverted for each frame. During the partial display period in which the display area selection signal DS 'is HIGH, the video signal is line-inverted as shown in FIG. The inversion control signal IS in FIG. 5 is a signal for controlling an inversion operation of an inversion control circuit 250 described later. When the display area selection signal DS ′ is LOW, the inversion is repeated every frame period, and While the selection signal DS ′ is HIGH, the signal is a signal that repeats inversion every 1H period.
[0034]
In this example, the background display signal is a signal of ± 1 V with respect to the video center, becomes a white display signal in a normally white liquid crystal panel, and becomes a black display signal in a normally black liquid crystal panel.
[0035]
Next, a specific configuration example of the mask circuit 210, the inversion control circuit 250, and the amplifier 230A whose gain can be variably controlled will be described. FIG. 6 shows a circuit diagram of the mask circuit 210. This figure shows a mask circuit for R data in RGB video data. Other GB video data mask circuits have the same configuration. In addition, it is assumed that each of RGB is 3 bits.
[0036]
The 3-bit R video data R0-2 is applied to one input terminal of each of the OR circuits 211, 212, and 213, and the inverted signal * DS 'of the display area selection signal DS' is applied to the other input terminals. Have been. In the partial display period in which the display area selection signal DS 'is HIGH, the R video data R0-2 is passed through the mask circuit as it is, but in the background display period in which the display area selection signal DS' is LOW, the R video data R0-2 is output. All bits of the data R0-2 are forcibly set to HIGH and output from the output terminals OUT0-2 as background display data.
[0037]
FIG. 7 shows a circuit example of the inversion control circuit 250. The circuit of FIG. 7A includes a non-inverting amplifier 251 and an inverting 252. The video signal output from the DA converter 220 is input from the input terminal 253 and applied to the non-inverting amplifier 251 and the inverting 252. In this circuit, the output of the non-inverting amplifier 251 or the output of the inverting 252 is switched to either one according to the above-mentioned inverting control signal IS. In the partial display period in which the display area selection signal DS 'is HIGH, the outputs of the non-inverting amplifier 251 and the inverting 252 are switched for each line, and line inversion driving is performed. On the other hand, during the background display period in which the display area selection signal DS ′ is LOW, the outputs of the non-inverting amplifier 251 and the inverting 252 are switched for each frame, and the frame inversion driving of the background display signal output from the DA converter 220 is performed. Done.
[0038]
FIG. 7B shows another circuit example. In this circuit, the DA converter 220 has a signal inversion function. That is, one of the positive black reference voltage Vref (B) + and the negative black reference voltage Vref (B) − is switched by the inversion control signal IS, and one end of the resistor string 255 is used as a black reference voltage. Supplied. One of the positive white reference voltage Vref (W) + and the negative white reference voltage Vref (W)-is switched by the inversion control signal IS, and the other end of the resistor string 255 is connected to the white reference voltage. Supplied as Then, by turning on / off the switch group 256 in accordance with the RGB video data, the voltage at each connection point of the resistor string 255 is selected. Therefore, according to this circuit, DA conversion and inversion of signal polarity can be performed.
[0039]
FIG. 8 shows a circuit diagram of an amplifier 230A whose gain can be variably controlled. 8B includes an amplifier 231, a switch 232 inserted between the amplifier 231 and its power supply VDD, and a switch 233 provided between the input and output of the amplifier 231. In the partial display period in which the display area selection signal DS 'is HIGH, the switch 232 is closed and the switch 233 is opened.
[0040]
As a result, the video signal input from the input terminal 234 is amplified by the gain G1 of the amplifier 231. On the other hand, in the background display period in which the display area selection signal DS ′ is LOW, the switch 232 is opened and the switch 233 is closed. As a result, the background display signal input from the input terminal 234 is output as it is through the switch 233. In this case, the gain G2 is 1, which is smaller than the gain 1 of the amplifier 231. At this time, since the amplifier 231 is disconnected from the power supply VDD, the total power consumption is reduced by the static power consumption of the amplifier 230A.
[0041]
As another circuit configuration example, as shown in FIG. 8B, an amplifier 235 having a gain G2 (G2 <G1) is provided instead of the switch 233. In the partial display period in which the display area selection signal DS 'is HIGH, the switch 232 is closed and the switch 236 is opened. Thus, the video signal input from the input terminal 234 is amplified by the gain G1 of the amplifier 231. In the background display period in which the display area selection signal DS 'is LOW, the switch 232 is opened and the switch 236 is closed. As a result, the video signal input from the input terminal 234 is amplified by the gain G2 of the amplifier 235.
[0042]
[Third Embodiment]
In the present embodiment, in order to reduce power consumption in the partial display mode, the precharge signal PCD used in the liquid crystal panel 100 is used as a background display signal.
[0043]
FIG. 9 shows the configuration of the display device of the present embodiment. The liquid crystal panel 100A is provided with a precharge circuit 150 that outputs a precharge signal PCD to the drain line 120. In an active matrix type liquid crystal panel, during a 1H period, a corresponding gate line 110 is selected to turn on a pixel transistor, and at that time, a video signal applied to a drain line 120 is written to each pixel via the pixel transistor. Display is performed for each pixel.
[0044]
However, in the case of the line inversion driving method, in particular, the polarity of the video signal applied to the drain line 120 is inverted every 1H, so that after the 1H switching, the voltage of the drain line 120 is surely displayed next. It is desirable that the voltage of the video signal should be. Therefore, precharging is performed in which a voltage close to a video signal to be written to the drain line 120 is written to each drain line 120 in the following 1H.
[0045]
In the present embodiment, background display is performed using the precharge signal PCD as a background display signal. During the background display period in which the display area selection signal DS ′ is LOW, a DA converter 220 that converts the video data from the mask circuit 210 into an analog signal, an amplifier 230 that amplifies the analog-converted video signal, and a horizontal signal The operation of the scanner 140 is stopped to reduce power consumption.
[0046]
Specifically, during the background display period, there is no need to operate the DA converter 220, the amplifier 230, and the horizontal scanner. Therefore, switches SW1, SW2, and SW3 for disconnecting these circuits from the power supply VDD are provided in each circuit. When the display area selection signal DS 'is LOW, these switches SW1, SW2, and SW3 are opened to disconnect from the power supply VDD.
[0047]
FIG. 10 shows a detailed circuit configuration of the liquid crystal panel 100A. The horizontal scanner 140 has a shift register 141 for sequentially shifting the vertical start pulse STH based on a shift clock, and a sampling TFT 142 to which a sampling clock output from each shift register 141 is applied to a gate. The RGB video signals are sequentially output to the drain line 120 according to the sampling clock. The precharge circuit 150 that outputs a precharge signal PCD to the drain line 120 has a precharge TFT 151 controlled by a precharge control signal PCG. When the precharge control signal PCG becomes HIGH, the precharge TFT 151 is turned on, and the precharge signal PCD is output to all the drain lines 120.
[0048]
FIG. 11 shows an operation waveform diagram of the display device of the present embodiment. In the partial display period, as shown in FIG. 11A, the precharge control signal PCG becomes HIGH immediately before the 1H period, and the drain line 120 is precharged to 7V in advance.
Thereafter, the video signal is supplied to the drain line 120 via the sampling TFT 142, and is written to each pixel of the corresponding row. Immediately before the next 1H period, the video center is precharged to 5 V whose polarity is inverted.
[0049]
On the other hand, in the background display period, as shown in FIG. 11B, the precharge control signal PCG becomes HIGH immediately before the 1H period, and the drain line 120 is precharged to 7V in advance. Then, in the subsequent 1H period, the video signal is masked,
The precharge level 7V is written to each pixel in the corresponding row. Immediately before the next 1H period, the video center is precharged to 5 V whose polarity is inverted. In the next 1H period, the video signal is masked, and a precharge level of 5 V is written to each pixel of the corresponding row. In this background display period, the operations of the DA converter 220, the amplifier 230, and the horizontal scanner 140 are further stopped. Thereby, power consumption is reduced.
[0050]
In this example, the precharge signal PCD is a signal that changes by ± 1 V with respect to the video center, and becomes a white display signal in a normally white liquid crystal panel and a black display signal in a normally black liquid crystal panel.
[0051]
FIG. 12 shows another operation waveform diagram of the display device of the present embodiment. This operation waveform diagram is a waveform diagram viewed in a vertical scanning system (V system), and shows operation waveforms of a partial display mode and a background display using a precharge signal PCD in a partial display mode.
[0052]
In the present embodiment, the signal level of the precharge signal PCD in the partial display period (or the normal display period) and the signal level of the precharge signal PCD in the background display period have been described as being the same, but they are not necessarily the same. The signal level of the precharge signal PCD may be different in order to optimize the display for each period.
[0053]
Further, when the background is set to the intermediate color during the partial display, the precharge signal PCD is set to the halftone voltage, so that the intermediate color background display can be performed while the scanner is stopped.
[0054]
【The invention's effect】
According to the present invention, by using one signal called a display region selection signal, an arbitrary partial display region can be selected from among the pixel regions of the display device, and partial display can be realized. In the case of background display, power consumption can be reduced by performing frame inversion driving for inverting the background display signal for each frame.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a display device according to a first embodiment of the present invention.
FIG. 2 is a waveform diagram of a display area selection signal DS ′.
FIG. 3 is a diagram showing a display state of the liquid crystal panel 100.
FIG. 4 is a configuration diagram of a display device according to a second embodiment of the present invention.
FIG. 5 is a waveform chart in a partial display mode.
FIG. 6 is a circuit diagram of the mask circuit 210.
FIG. 7 is a circuit diagram of the inversion control circuit 250.
FIG. 8 is a circuit diagram of an amplifier 230A whose gain can be variably controlled.
FIG. 9 is a configuration diagram of a display device according to a third embodiment of the present invention.
FIG. 10 is a detailed circuit diagram of the liquid crystal panel 100A.
FIG. 11 is an operation waveform diagram of the display device according to the third embodiment of the present invention.
FIG. 12 is another operation waveform diagram of the display device according to the third embodiment of the present invention.
[Explanation of symbols]
REFERENCE SIGNS LIST 100 liquid crystal panel 110 gate line 120 drain line 130 vertical scanner 140 horizontal scanner 210 mask circuit 220 DA converter 230 amplifier 230A amplifier 240 timing controller 300 display mode discrimination circuit

Claims (8)

A display device comprising a plurality of pixels, performing a partial display by supplying a desired video signal to a selected partial display area, and supplying a background display signal to a background display area excluding the partial display area to perform a background display. So,
A mask circuit that supplies the video signal to each pixel of the partial display area selected according to a display area selection signal and masks the supply of the video signal to each pixel of the background display area. Display device. 2. The display device according to claim 1, further comprising an inversion control circuit that inverts the polarity of the background display signal supplied to each pixel of the background display area for each frame in accordance with the display area selection signal. The inversion control circuit includes a non-inversion amplifier to which the video signal is input, an inversion amplifier to which the video signal is input, and a switch that switches an output of the non-inversion amplifier or the inversion amplifier according to the display area selection signal. The display device according to claim 2, comprising: The display device according to claim 2, wherein the background display signal is a white display signal or a black display signal. 3. The amplifier according to claim 2, further comprising an amplifier that amplifies the video signal and has a gain that can be variably controlled in accordance with the display area selection signal, and reduces the gain of the amplifier during the background display. Display device. A partial display mode in which a desired video signal is supplied to a partial display area selected according to a display area selection signal to perform a partial display, and a background display signal is supplied to a background display area other than the partial display area to provide a background display. And a normal display mode in which a desired video signal is supplied to all pixel regions selected according to the display region selection signal to perform display. A display mode discriminating circuit for discriminating between a partial display mode and a normal display mode by detecting a signal level of the display device. 7. The display according to claim 6, wherein the display mode determination circuit determines whether the display mode is the partial display mode or the normal display mode by detecting a magnitude of a period when the display area selection signal is at a predetermined signal level. apparatus. 7. The display device according to claim 6, wherein the display mode determination circuit determines a partial display mode or a normal display mode by determining a signal level of the display area selection signal at a predetermined timing.

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