JP2003510683A - A RAID storage controller and method comprising an ATA emulation host interface. - Google Patents

Abstract

(57) Summary The RAID storage controller (70) provides a host interface (56) for joining the controller to a host system bus. Since the host interface is separated from the storage device to be connected, for example, an IDE disk drive, the number of drives to be actually connected is not limited in the number or interface protocol. Various device ports can be equipped and various RAID strategies, for example, level 3 and level 5, can be used. In all of the above cases, the host interface provides a standard uniform interface to the host, namely ATA interfaces (82, 84 and 86), and preferably a dual channel ATA interface. The host interface emulates a single or dual channel interface in ATA and emulates one or two attached IDE devices per channel, regardless of the actual number of devices physically connected to the controller. Rate it. Therefore, in the RAID level 5 protocol, it is possible to equip 5 or 7 IDE drives without changing the standard BIOS of the PCI host system. Thus, the RAID controller is transparent to a standard dual channel ATA controller board.

Description

Detailed Description of the Invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to computer data storage device controllers, and more particularly to RAID controllers having a host interface that emulates an ATA standard controller and an attached IDE device. Related Applications This application is US Provisional Patent Application No. 60 / 156,0 filed September 22, 1999.
This is a continuation application of No. 01, and claims the priority right of the application.

BACKGROUND OF THE INVENTION The first IBM PCs and their compatibles had only floppy disk drives for mass storage. Subsequent XT and AT models included an adapter for 5.25-inch fixed disk (non-removable) connection for bulk data storage. These early adapters have read signals and
Most of the low level control signals were provided to the drive which included a data separation circuit for the precompensated write signal. Including these features in the adapter avoids duplication on a pair of drives that are only accessed one at a time. Unfortunately, the 5 Mbit read / write channel on this adapter has improved the technology, but it has not been possible to connect faster drives.

This problem was solved by moving the “real time” aspect of the controller to the drive side. Integrated drive electronics, or IDE drives, read from or write to the drive,
It contains all of the control and data channels needed to transfer data between the local buffer and the medium. The manufacturer can choose the data rate. A new interface, ATA (AT Attachment with Packet Interface Extensions (ATA / ATAPI-4)) (IBM AT Attachment Interface), has been defined for the attachment of data storage devices to a host system. The first IDE interfaces contained at most address decoding and buffering between the ISA bus and ATA cable connectors. The interface protocol used programmed I / O commands to access the IDE device registers. The data transfer used the host processor's input string and output string commands to match the transfer speed of the attached drive. These transfer rates reached 16 megabytes per second in subsequent specification revisions. This is the transfer rate between the storage buffer and the memory on the ISA bus. The transfer rate between the medium and the buffer was much lower.

With the advent of the PCI bus, Intel Corp.
Controller specification, revised 1.0 edition, 3/4/94) was issued. This is a PC
A standard mapping of a conventional ISA bus compliant host interface to the I-bus has been provided. The standard described a dual IDE channel controller. It became possible to connect a pair of devices consisting of a master and a slave to each channel. The device was still accessed as a PCI bus target for data transfer.

Intel Corporation has also issued a Bus Master IDE document (Programming Interface for Bus Master IDE Controller, Rev 1.0, 5/16/94). This document defines a standard for incorporation of DMA devices into IDE channels. With this bus master interface, the IDE channel
As a bus master (PCI bus activation device), it has become possible to transfer data to and from system memory via the PCI bus. Peak transfer rate for a 32-bit / 33MHz PCI bus is 133 / s
It is megabytes.

A revision of the ATA specification defined a new transfer mode, Ultra DMA. Conventional transfer rate improvements have been obtained by truncating settings and hold times required for data transfer on the cable. At 16 megabytes per second, the read transfer rate was severely limited by the orbiting movement of sending the read strobe signal, accessing the data, and returning the data. The Ultra DMA protocol initially preserved the electrical properties of all signals and cables and redefined their function for three of the signals to provide a new protocol. In this protocol, the strobe signal, which provides the data timing, is sent from the same terminal as the data, ie, the controller for writing and the device for reading. In this configuration, the transfer rate is limited only by the cable skew of a single transfer of the cable, or the shift in the signal within the cable. The first UDMA device doubled the programmed IO transfer rate to 33 megabytes per second. Subsequent revisions doubled the initial transfer rate to 66 megabytes per second, including alternating signal conductors and ground conductors, 8
It required the use of a ribbon cable consisting of zero conductors. The current revision supports a transfer rate of 100 megabytes per second. Currently, there is a move to replace the ATA parallel interface with a high speed serial link, but yet another parallel speed increase may be released first.

Problem A typical PC consists of a processor, a DRAM interface, various input / output adapters, and a motherboard designed around a chipset containing a BIOS ROM. IO adapters typically include an IDE interface. The features of the current version of the IDE controller are that each pair of I
Including a pair of IDE ports connectable to DE storage devices. These devices typically include one or more IDE hard disks, a CD ROM, a DVD.
Includes ROM or CD WORM drive. Basic input / output system or B
IOS is a program used to boot the PC and supply low level IO routines to the adapter on the motherboard. Virtually all of these PCs can be booted and run from the IDE hard disk using the motherboard BIOS.

Personal computers are also increasingly equipped with server or workstation applications in the SOHO (small office / home business) market. Historically, hard disks with a Small Computer System Interface (SCSI) have provided some performance gains for these relatively demanding applications. However, now that more than 85% of all drives are produced as IDE drives, SCSI drives are
Costs tend to increase significantly when built with write heads with little or no performance gain. Another widely used alternative is the redundant array of cheap disks first proposed by Patterson (
There is a method of using RAID (D. Patterson et al., “A Ca
se for Redundant Arrays of Inexpensi
ve Disks (RAID) ”(Univ. Cal. Report N
o. UCB / CSD87 / 391, December 1987). RAID systems are aimed at solving both reliability and performance problems. First, reliability is 2
Storing data redundantly on more than one drive ensures that no data is lost if a single drive is lost. Second, the collective performance of the array provides performance improvements over a single drive. It is possible to read different sections of the redundantly stored data from two drives at the same time. Furthermore, since the data can be written in stripes across all currently available drives, an intensive transfer rate can be achieved when reading the data back. A RAID array controller is disclosed in US Pat.
No. 018,778 for further details.

Unfortunately, some currently available RAID solutions have drawbacks. Characterizing one class of RAID solutions is the use of local intelligence and SCSI disk drives. This class offers high performance, but at the cost of both the drive and the controller. Another class of common RAID solutions is characterized by the use of IDE drives and lack of local intelligence or buffering. This is effectively a software solution.
Disk drives on the processor or system bus because all the software needed to control multiple drives to maintain redundancy or to arrange data in stripes must run on the host system. Greatly increase the incidental part. Thus, the benefits of RAID are achieved at the expense of reduced system performance due to this additional augmentation. Both of the above solutions share yet another problem. These RAID controllers are based on BI on the motherboard.
Not directly supported by the OS. Requires additional software drivers. These drivers are operating systems such as Windows (registered trademark), Windows (registered trademark) NT, UNIX (registered trademark), and L.
Since it may vary as a function of INUX, etc., the controller manufacturer
It imposes an extra burden on EM, sales organizations and system integrators.

Therefore, there is still a need for RAID storage controllers that do not require special software to run on the host computer, and thus require additional software drivers or changes to the BIOS. BI
A RAID controller that does not require changes to the OS is considered to have the advantage of providing "stick-and-go" compatibility with almost any standard, as-purchased computer with an ATA-compatible interface. Since this RAID controller is transparent to the host, it can be used to equip a large number of storage devices (not limited to four) in any device interface coupling, and thus to the host. It would be possible to introduce RAID mirror image processing, striped arrangements, etc. without adding. Such a RAID controller would provide RAID performance to all PC users with a low cost and extremely simple installation method.

SUMMARY OF THE INVENTION The present invention uses a standard IDE controller or IDE drive to drive any P
Equipped with a RAID controller compatible with all operating systems that can be booted and operated on the C motherboard. The present invention achieves this compatibility by emulating a standard controller and an attached drive. For example, any given system may require a pair of drives in RAID 1, ie, a "mirroring" configuration for reliability. When connected to the controller described in the present invention, the BIOS will see a single, extremely reliable drive. This same system
It may require an array of three drives configured as either RAID 3 or RAID 5 configurations. This provides twice the transfer rate with high reliability for any of the three drives. Again, in this case of the invention, this array of three drives reports to BIOS twice the capacity of any of the three drives and doubles the transfer with high reliability. Looks like a single drive, showing speed. In any case, this RAID is transparent to the existing drivers in BIOS.

The controller of the present invention emulates a standard 2-channel IDE controller. Like a standard controller, that controller is logically connected to the PCI bus. It may be physically on the motherboard and integrated within the motherboard chipset, or it may be on a plug-in card in a PCI slot. It may emulate all four devices connected to a standard controller. Each of these logic devices has the potential to provide an interface to an array of physical devices connected to this controller. Although this embodiment provides an ATA port for physical drive connection, other types of interfaces or combinations of interfaces can be used.

Other objects and advantages of the present invention will become apparent from the following detailed description of the preferred embodiments of the invention, which proceeds with reference to the accompanying drawings.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The upper half of FIG. 1 is an ATA controller 10 for a personal computer, which illustrates typical prior art operation of an ATA controller that provides an interface between a system bus 12 and a storage device 14. Show. The system bus 12 is a PCI bus. Although logically connected to the PCI bus, the ATA controller is typically integrated into the motherboard chipset. In any given operation, another or additional controller may be added to the PCI bus slot (not shown) on the motherboard.
It is possible to plug in. The PCI bus provides a configuration mechanism through which each controller is assigned a unique address. A typical controller 10 provides two channels terminating in a pair of connectors 16, 18 identified as primary and secondary IDE connectors.
Each channel supports a pair of storage devices that share a cable with the connector. For example, in FIG. 1, the secondary channel cable 19 is connected to the master storage device 20.
And the slave storage device 22. Another pair of drives is similarly connected to the primary channel cable 24. In this way, the two-channel controller 10 supports a total of four devices as shown in FIG.

The lower half of FIG. 1 shows the IDE controller and drive programming interface as viewed from the PCI bus. The physical address of each block is
It is assigned through the controller's PCI bus configuration space as is commonly known in the industry and as described in the Intel PCI IDE Controller Specification document mentioned above. Another aforementioned Intel document, Bus Master ID
Programming Interfaces for E-Controllers describes programming interfaces for Bus Master IDE Controllers. Prior to standardization of this mechanism, storage data was typically transferred through programmed I / O. In this I / O, the loading and saving required for data transfer was performed by the system processor. Although the programmed I / O mechanism is still supported, the bus master interface allows the ATA controller to directly access system memory, ie transfer data through DMA. The Bus Master IDE Controller document defines a 16-byte block of registers, one pair for the primary ATA channel and one for the secondary ATA channel, supporting a pair of bus master controllers. This register block is physically part of the controller. This is shown in two parts, 30 and 32, each associated with each channel.

The ATA specification defines a programming interface for a storage device. This interface consists of two register blocks, a command block and a control block. The command block is an 8-byte block consisting of byte-wide registers. All the details of the introduction of these registers are published in the ATA specification.

The right side of FIG. 1 shows four sets of command and control register blocks, one set corresponding to each of the four attached storage devices. For example, the set of register blocks 36 comprises a command block 38 and a corresponding control block 40. These registers are physically part of the corresponding storage device shown in the upper half of FIG. Therefore, register set 36 (primary channel) is located in master storage 25. If any storage device is not connected, its command and control register block will not appear in the programming interface.

The ATA specification further defines the protocols supported by these storage devices. Generally, access commands and all relevant parameters are loaded into the command block registers. The storage device then executes the command. For device writes, the device first requests write data. For programmed I / O operations, the host processor reads data from system memory and uses a portion of the command block to write it to a buffer (not shown) in the device as a 16-bit window in the buffer. A for bus master DMA operation
The TA controller directly accesses the data in system memory based on the configuration of the bus master controller register block for that channel. The storage device then accesses the storage medium to transfer data between the medium and a local buffer. For medium reads, the data in the local buffer is then transferred to system memory using either programmed I / O or the bus master DMA described above. Finally, the storage device indicates to the host system either through polling of the status register or through the ATA controller to the host system.

When the power is turned on, the personal computer executes the code physically stored in the non-volatile memory on the motherboard. This basic input / output system or BIOS code loads the operating system of the personal computer from the ATA storage that connects to the ATA controller and provides the low level I / O system drivers for those storages.

Since the present invention emulates the ATA controller shown in FIG. 1 and described above, it is fully compatible with the controller at the programming level. Referring now to FIG. 2, the upper half of FIG.
FIG. 3 is a block diagram of a controller that can be configured as an AID controller. The left side of the controller block 50 connects to the PCI bus instead of the standard dual channel ATA controller and emulates 1 to 4 attached ATA storage devices. This emulation of the ATA storage device is described in more detail below, but this is significant in the type and number of device interfaces provided since it separates the controller's host interface from the physical device interface. Will be allowed. For example, one operation of the present invention is X SCSI ports and / or Y ATA ports, where X and Y are not limited to 4 logical drives visible to the host, Introduce such a port. FIG. 2 is an example of introducing N + 1 ATA ports numbered from 0 to N-1.

The lower half of FIG. 2 shows the programming interface of the present invention. The host interface 56 comprises all of the register blocks visible from the standard ATA controller's PCI bus side. That is, dual channel bus master controller blocks 58, 60, and four sets of command and control register blocks, numbered 62, 64, 66 and 68. The host interface block 56 emulates the registers of the ATA controller and ATA storage device to the level required to support the ATA specification protocol.

The block 70 at the bottom of FIG. 2 shows the main components of the controller block 50.
In addition to host interface block 56, controller 70 includes RAM buffer cache 72, DMA channel 74, and processor 80, as described below. Controller block 70 further includes a plurality of ATA port interfaces, eg, interfaces 82, 84 and 86. Each AT
The A port interface provides a standard interface connection for IDE type storage devices such as disk drives. As mentioned above, each storage device includes a command and control register block on the board. These are, for example:
Although shown as a command register block 90 and a control block 92, both are associated with a single device, the master drive, which is connected to the ATA port interface 82, standard connection cable 96.
The control block 70 provides a standard dual channel controller interface 56 for the host PCI bus 12 while being configurable to include any desired number of ATA ports.

A detailed block diagram of the presently preferred embodiment of the present invention is shown in FIG.
This system is an application specific IC (AS) in a 0.18 micron CMOS process.
IC). The device is logically divided into four modules, each module having an associated port on the outside of the device.

The host interface 100 is built around a PCI core 104 made of in-silicon. This CS6464AF is both 32-bit and 64-bit PC
It is a soft core (a Verilog source that is synthesized for a specific application) that supports the I bus at a PCI bus clock speed of 33MHZ or 66MHZ. This core supports both master and target operations. The target function 106 provides access to the ATA compatibility register file described above. Master performance 10
8 is used to emulate the bus master DMA performance of the ATA controller. The PCI core includes a configuration space that emulates the configuration space 110 of a dual port ATA controller.

The DRAM interface block 120 is an externally connected SDRAM.
Supports 122. This 64-bit wide, 100 MHZ single data rate port 124 supports a peak transfer rate of 800 megabytes per second. Locally, this DRAM interface is shared by interacting with the PCI bus via the host interface 100, interacting with the disk drive via the drive interface 130, and accessed by a local processor in the processor block 150. To be done.

The drive interface block 130 supports, for example, five ATA ports, and each port supports one master drive and one slave drive. Each port supports programmed input / output (PIO) at transfer rates up to 16 megabytes per second, while Ultra DMA transfers at transfer rates up to 100 megabytes per second.

The processor block is an EZ4102 TinyR composed of LSI logic.
Built around the ISC core 160. This processor is a variant of the MIPS processor. When powered on, the processor loads code from external flash memory 162, which is accessed via expansion bus port 166. This code is stored in the SRAM block 170 in the same processor block.
Transferred to. Processor 160 configures each of the other modules and accesses the PCI bus, SDRAM, or ATA drive through these modules. Generally, the transfer rate of the system is enhanced by not requiring the processor to process the data. This processor is a drive and DSRAM
In the meantime, the DMA engines 136 and 146 are configured in those blocks to execute the loading and unloading of the FIFO 148 between the blocks, thereby conducting the data movement between the blocks. Similarly, the processor configures the DMA engine 172, 102 for the DRAM interface and the host interface between the SDRAM and the PCI bus target to enable the FIFO 174 between blocks.
Command the transfer between both blocks by loading and unloading.

FIG. 4 shows the details of the ATA register file equipment. All registers have dual port functionality and can be accessed by the host system via the PCI bus or by the local processor 160. Seen from the PCI bus, each ATA channel has two blocks of registers associated with it. Command block 208 is in the 8-byte range of the byte-wide register.
The control block 210 is in the 4-byte range, of which only a single location is used. As mentioned above, a single ATA port can be used to access a pair of devices connected to a common cable. Each device has its own command and control register block. The device is physically configured with jumpers that display one as a master and the other as a slave. A particular device is selected by writing 1 byte of data to the Device Head register at command block address offset 6. If bit 4 is acknowledged, the slave device is selected and the master is deselected for subsequent operation. Clearing bit 4 and writing to the same register will select the master device and deselect the slaves. In the present invention, both sets of master and slave registers are equipped to emulate this behavior. In addition, a single bit slave register 230 is provided which records the most recently written bit 4 for the device head register. This slave register controls read multiplexing and write address decoding from the PCI bus,
This ensures that the appropriate pair of register blocks are accessed based on the latest device selection.

After power on or reset, the ATA device is initially busy. This busy state can be detected by reading the state register at address offset 7 of the command block or the alternate state register block of the control block. While one device is busy, it cannot access any of the other registers. In the present invention, a single bit busy register 232 is provided to emulate this behavior. This register is
Set by a write to a soft reset in the device control register of the control block, or by a reset from the PCI bus when the address offset 7 of the command register block is written in the command register. The local processor can clear the busy register.

Each ATA device can claim an interrupt request to the host system if an interrupt becomes possible inside the ATA device. To emulate this behavior, single bit interrupt request 234 and interrupt enable 236 registers are provided to both master and slave devices. Interruptability is controlled through device control of each device. Each device can assert an interrupt request to the host system to transfer data or return an exit status. In the present invention, the interrupt request can be set or released by the local processor. Interrupt requests are also cleared by the device's status register (but not the alternate status register), as described above in the ATA specification protocol. The interrupt request / interrupt enable state in the master / slave device is independently maintained so that proper behavior is executed when the host changes the device selection.

The command and control register files of the master and slave devices are slave,
All are duplicated for the secondary channel, including busy and interrupt "side effects". Four
The command and control register files for all these devices are all linearly mapped into the address space of the local processor.

Shared Dual Channel Bus Master Control Block 25
0 is accessible from either the PCI bus or the local processor.

According to the ATA protocol, a device is selected and all parameters needed for any command are loaded into the command register, then the register at offset 7 is loaded with the command itself. As mentioned above, this sets the channel to busy. A busy rising edge causes an interrupt to the local processor, which responds by interpreting the command and its parameters. Many directives are remapped for access to the attached physical device array. These accesses are for RAID levels 0, 1, 3, and 5
Can be used to implement any of the common RAID protocols including, but not limited to. The local processor may also choose to read more data than requested. This extra data is cached in SDRAM in anticipation of subsequent reads. The local processor uses programmed IO or DMA, as claimed in the instructions,
Arrangements can be made to exchange data between the SDRAM and the host system.

Briefly summarized, the present invention includes a RAID storage controller that provides a host interface for bonding the controller to a host system bus. Since this host interface is separate from the attached storage device, for example the IDE disk device, the actual attached drive is not limited in number or interface protocol.
Various device ports can be introduced, and various RAID measures, such as level 3 and level 5, can be used. In either case, the host interface provides a standard uniform interface to the host, an ATA interface, preferably a dual channel ATA interface.
This host interface emulates an ATA single or dual channel interface and emulates one or two attached IDE devices per channel, regardless of the actual number of devices physically connected to its controller. . Thus, for example, 5 to 7 IDE drives can be equipped during a RAID level 5 protocol without changing the standard BIOS in the PCI host system. Therefore, this RAID controller is transparent to a standard dual channel ATA controller board.

It will be apparent to those skilled in the art that many modifications can be made to the details of the above-described embodiments of the present invention without departing from the underlying principles of the invention. Therefore, the scope of the invention should be determined solely by the appended claims.

[Brief description of drawings]

FIG. 1 A of the prior art showing physical and software / register images.
It is the block diagram which simplified TA dual channel controller operation | use.

FIG. 2A is a simplified block diagram of a RAID controller with ATA port emulation according to the present invention.

FIG. 2B is a simplified block diagram of a RAID controller with ATA port emulation according to the present invention.

FIG. 3 is a high level block diagram of a presently preferred commercial implementation of a RAID controller with ATA port emulation.

4 is a block diagram showing further details of one implementation example of the ATA register file of the controller of FIG. 3. FIG.

─────────────────────────────────────────────────── ─── Continuation of front page (81) Designated countries EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE ), OA (BF, BJ, CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG), AP (GH, GM, KE, LS, MW, MZ, SD, SL, SZ, TZ, UG, ZW), EA (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM), AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, BZ, CA, CH, CN, CR, CU, CZ, DE, DK, DM, DZ, EE, ES, FI, GB, GD, GE, GH , GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NO, NZ, PL, PT, RO, RU, SD, SE, SG, SI, SK, SL, TJ, TM, TR, TT, TZ, UA, UG, US, UZ , VN, YU, ZA, ZW [Continued Summary] It is possible to equip 5 or 7 IDE drives without any changes to the quasi-BIOS. Therefore, this RAID controller is transparent to the standard dual channel ATA controller board.

Claims (20)

[Claims] 1. A storage device controller, a host interface for joining the controller to a host system bus, to emulate a standard IDE channel and further as if connected to the standard IDE channel. And a host interface that emulates a storage device controller and at least one physical interface that connects the storage device controller to a physical storage device. 2. The storage device controller according to claim 1, wherein at least one of the physical interfaces is equipped with an ATA port for connecting an ATA compatible storage device to the controller. 3. The storage controller according to claim 1, wherein the host interface emulates at least one primary channel and one secondary channel. 4. The storage device controller according to claim 3, wherein the host interface emulates a single IDE device connected to each of the primary and secondary channels. 5. A host IDE storage device and a slave IDE, both of which are connected to one of the primary and secondary channels.
Storage device controller according to claim 3, characterized in that it emulates both storage devices. 6. The storage controller according to claim 3, further comprising means for emulating a bus master DMA controller of a standard dual port IDE controller. 7. The storage device controller according to claim 1, wherein the host interface emulates a single IDE device connected to the IDE channel. 8. The storage device controller according to claim 1, wherein the host interface emulates both a master IDE storage device and a slave IDE storage device connected to the IDE channel. 9. A storage controller according to claim 1, further comprising means for emulating a bus master DMA controller of a standard dual port IDE controller. 10. A RAID storage controller, comprising: a host interface for joining the controller to a host system bus, the host interface emulating at least one ATA controller channel; And a control register block to further emulate at least one IDE device as if connected to the emulated IDE channel, host interface, connecting the storage device controller to a plurality of storage devices At least two physical interfaces, and a local processor mounted on the controller for controlling a physical memory access operation. RAID storage controller that. 11. A RAID storage controller according to claim 10, further comprising means for emulating a bus master DMA controller of a standard dual port IDE controller. 12. A RAID storage device controller according to claim 10, wherein a buffer memory buffers data transfer between a host system bus and a connected storage device, and between the host interface and the buffer memory. A RAID storage controller, further comprising a DMA engine arranged to transfer data. 13. A RAID storage controller according to claim 12, including a DMA engine arranged to transfer data between the buffer memory and the port interface. . 14. The host interface comprises a primary ATA channel and a secondary A
A RAID storage controller according to claim 10, characterized in that it emulates both the TA channel. 15. The host interface emulates a single IDE device connected to each of the primary and secondary channels,
A RAID storage controller according to claim 14. 16. The method according to claim 14, wherein the host interface emulates both a master IDE storage device and a slave IDE storage device connected to at least one of the primary and secondary channels. RAID storage controller. 17. The RAID storage controller according to claim 10, wherein the host interface emulates both a master IDE device and a slave IDE device connected to the IDE channel. 18. The RA according to claim 10, wherein the host interface emulates a single IDE device connected to the IDE channel.
ID storage device controller. 19. The RAID storage controller according to claim 10, wherein the host interface emulates both a master IDE device and a slave IDE device connected to the IDE channel. 20. R without modification of existing host BIOS software
A method of bonding an AID storage device controller to a PCI bus host, wherein the controller emulates an ATA controller bonding to the host; in the controller, the IDE storage device as if connected to the ATA controller. Providing at least two physical port interfaces for connecting one physical storage device to the controller; and decoupling the controller's host interface from the physical storage device. The storage device controller thereby allows the storage device controller to host the physical port regardless of the actual number and type of interfaces of the physical storage devices that are actually connected to the physical port interface of the controller. To an IDE device connected via an ATA interface so that it is visually uncoupled.