JP2003347338A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device excellent in the adhesiveness of a bonding pad to a second wiring layer and an insulation film while preventing the generation of cracks in the insulation film between the bonding pad and the second wiring layer or the disconnection of the second wiring layer due to a force impressed on the bonding pad. <P>SOLUTION: The semiconductor device is provided with a semiconductor substrate 1 on which an operation region is formed; a first wiring layer 3 formed on the semiconductor substrate 1; a second wiring layer 5 formed on the first wiring layer 3 via an interlayer insulation film 4; and a bonding pad 6 formed so as to be superposed on the operation region. The second wiring layer 5 is provided with a plurality of wirings below the bonding pad 6, and a part of the wirings is connected to the bonding pad 6 while an inorganic insulation film 8 is formed between other wirings and the bonding pad. A coated silicon oxide film 10 for burying and flattening a recess 8a of the inorganic insulation film 8, which is produced by the section wiring layer 5, is formed. <P>COPYRIGHT: (C)2004,JPO

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a bonding pad formed above an active region on a surface of a semiconductor substrate.

[0002]

As electronic devices such as portable telephones and personal digital assistants have become smaller and lighter, the density of electronic components mounted on those devices has been increasing. As a result, the degree of integration of semiconductor devices increases, and the chip size of each semiconductor device tends to increase. On the other hand, miniaturization of processing dimensions is required in order to reduce the size and size of semiconductor devices, and design rules are being reduced.

[0003] Semiconductor devices can be broadly classified into internal operating regions (active regions) and pad regions formed on the surface of the semiconductor device. The operation region is a region (so-called active region) in which semiconductor elements such as transistors and diodes are formed, and a region (wiring region) such as a metal wiring connecting these semiconductor elements, for example, an aluminum (Al) wiring. The pad region is a region where bonding pads for connecting the semiconductor element to external terminals are formed. When the semiconductor device is, for example, a liquid crystal driver, an IC (Integrat
It is mainly used in a mounting method for mounting an ed circuit (integrated circuit) chip on a flexible printed circuit (FPC), a so-called COF (Chip On FPC) mounting method. In the case of LCD driver, the pad area is
This is an area for inputting and outputting signals for driving the liquid crystal.

Here, the COF mounting method will be described with reference to FIG.

In FIG. 4A, a semiconductor element (IC chip) 301, an input / output terminal electrode 302 formed on the surface of the semiconductor element 301, and a bonding pad 303 provided on the input / output terminal electrode 302 , An insulating film substrate 304, a metal wiring pattern 305 formed on the surface of the insulating film substrate 304, and a bonding tool 306.

The semiconductor element 301 generally has an input / output terminal electrode 302 such as an aluminum pad formed on the surface thereof, and further has a bonding pad 303 having a thickness of about 10 μm to 18 μm on the input / output terminal electrode 302.
Are formed. On the other hand, the flexible printed wiring board on which the semiconductor element 301 is mounted has a structure in which a metal wiring pattern 305 is formed on an insulating film substrate (film substrate) 304 mainly made of a plastic insulating material such as polyimide resin or polyester. ing.

First, in the COF mounting method, the semiconductor element 301 on which the bonding pads 303 are formed is connected to a metal wiring pattern 305 formed on an insulating film substrate 304 as shown in FIG. Align. That is, positioning is performed so that the bonding pad 303 matches a predetermined position on the metal wiring pattern 305.

Here, the metal wiring pattern 305 is mainly made of a conductive material such as copper (Cu), and the surface of the conductive material is plated with tin (Sn) or gold (Au). Have been. The metal wiring pattern 305 includes types such as an inner lead, an outer lead, and an intermediate lead. However, since the type is not related to the present invention, a detailed description is omitted.

[0009] The insulating film substrate 304 has a strip shape and is also called a tape carrier.
Feed holes are provided at predetermined intervals on both side edges, and are movable in the longitudinal direction.

After the positioning of the insulating film substrate 304 and the semiconductor element 301 is performed, the bonding pads 303 and the metal wiring patterns 305 formed on the surface of the insulating film substrate 304 are connected to each other as shown in FIG. As shown in (1), bonding is performed by thermocompression bonding using a bonding tool 306. This connection method is generally called inner lead bonding (ILB).

After performing the inner lead bonding, the semiconductor element 301 is resin-sealed with a material such as an epoxy resin or a silicone resin (not shown). Resin sealing is performed by a method in which a resin is applied around a semiconductor element by a nozzle, and the resin is cured by applying heat by a reflow method or the like. After that, the portion on which the semiconductor element 301 is mounted is punched out of the insulating film substrate 304 and mounted on a liquid crystal display panel or the like as an individual semiconductor device (integrated circuit).

As described above, a method for packaging a semiconductor element to form a semiconductor device has been described.

In a conventional ordinary semiconductor device, a bonding pad is not formed in an operation area, but is provided in a peripheral portion of the operation area. This is to prevent a mechanical pressure at the time of joining the Au bump and the external connection terminal or a stress due to thermal stress or the like from being applied to the operation region via the bonding pad. At present, the bonding pads of the liquid crystal driver and the like are typically 50 to 10
It is formed around the semiconductor element at a pitch (interval) of 0 μm, and typically depends on the pitch, but is typically 40 × 90 μm.
Is a rectangle.

At present, a semiconductor device tends to have a complicated metal pattern connecting elements due to an increase in density and an increase in the degree of integration, and a multi-layer wiring structure in which a number of wiring layers are stacked has become mainstream. ing. Accordingly, the number of terminals for connecting the semiconductor device to external terminals has reached 500. Therefore, if the region of the bonding pad (pad region), which is a terminal, exists outside the operation region, the area of the region other than the operation region increases as the number of terminals increases, and the size of the semiconductor device also increases. Personal Dig
It goes against the miniaturization of ital Assistants (portable information devices).

Therefore, as a method of reducing the size of a semiconductor device, a method of forming a bonding pad in an operation region of a semiconductor element has been proposed. This method is called “area pad”. Hereinafter, the bonding pad formed in the operation region of the semiconductor element is referred to as “area pad”.

The prior art relating to the area pad will be described below.

US Patent Publication US2002-0043
No. (Released on April 18, 2002; Japanese Patent Application 2001-200)
An example of forming an area pad in a semiconductor device having a two-layer wiring structure disclosed in US Pat.

As shown in FIG. 5, a silicon substrate 101 having an active region (operation region) in which a semiconductor element 120 is formed, and a silicon substrate 101 formed on the silicon substrate 101,
First wiring layer 102 electrically connected to the active region
A second wiring layer 107 formed on the first wiring layer 102 with an interlayer insulating film 106 interposed therebetween, and a second wiring layer 107 formed at a position where at least a part thereof overlaps the active region, for electrical connection to the outside. And a bonding pad 114. The lower end of the bonding pad 114 (the second wiring layer 1)
A barrier film is formed in the vicinity of the bonding surface with the layer 07). The semiconductor element 120 is a MOS (Metal Oxide Sem).
iconductor; metal oxide semiconductor
It comprises an impurity diffusion layer functioning as a source region formed on the surface layer of the silicon substrate 101, an impurity diffusion layer functioning as a drain region, and the like.

Since the structure of the semiconductor element 120 is not directly related to the features of the present invention, a detailed description will be omitted, and only the other components will be described in detail. That is, here, the first region electrically connected to the active region is used.
Only the wiring layer 102 and each component formed thereon will be described in detail.

The first wiring layer 102 is a single layer or a multiple layer made of a conductor such as aluminum. The first wiring layer 102 is formed on the active region via an insulating film and includes a plurality of wirings. Part of the wiring of the first wiring layer 102 is connected to the active region via a contact hole. Over the first wiring layer 102, an interlayer insulating film 106 is formed to insulate (electrically disconnect) the first wiring layer 102 and the second wiring layer 107.

The interlayer insulating film 106 is laminated in the order of silicon oxide film 106a / SOG film 106b / silicon oxide film 106c from the silicon substrate 1 side. SOG film 1
06b is formed to flatten the surface irregularities generated by the first wiring layer 102. Silicon oxide film 10
6a and 106c are formed with a thickness of, for example, about 500 nm.

The second wiring layer 107 is also formed of a conductor such as aluminum similarly to the first wiring layer 102.
Consists of a single layer or multiple layers. The second wiring layer 107
A plurality of wires insulated from each other are provided in a region overlapping the bonding pad 114. Also, the second wiring layer 10
Part of the wiring 7 is connected to part of the first wiring layer 102 via a via hole in the interlayer insulating film 106.

The second wiring layer 107 and the bonding pad 1
14, the protective film 108 and the polyimide film 110
Are formed, and the protective film 108 and the polyimide film 1
An opening is provided in 10 for joining with a part of the second wiring layer 107.

The bonding pad 114 is connected to a part of the second wiring layer 107 through these openings.
Also, the second pad connected to the bonding pad 114
The bonding surface of the wiring layer 107 is considerably smaller than the plane size of the bonding pad 114 (the size of the orthogonal projection projected on the silicon substrate 1). For this reason, it is possible to arrange the wiring of the second wiring layer 107 in a region other than the bonding surface between the second wiring layer 107 and the bonding pad 114 in a region below the bonding pad 114. In a conventional semiconductor device having an area pad, the bonding area between the wiring layer and the bonding pad (projecting electrode) is substantially equal to the cross-sectional area of the bonding pad. On the other hand, in the semiconductor device described in Japanese Patent Application No. 2001-200098, the second wiring layer 107 and the bonding pad 11
4, the degree of freedom of wiring of the second wiring layer 107 is increased.

The bonding pads 114 other than the bonding surface between the second wiring layer 107 and the bonding pads 114
A protective film 108 and a polyimide film 110 are formed between the first wiring layer 107 and the second wiring layer 107 to insulate them (electrically disconnect them). The shape of the polyimide film 110 is inclined toward the outer periphery of the bonding pad 114 from the bonding surface between the second wiring layer 107 and the bonding pad 114.

The polyimide film 110 is formed on the second wiring layer 1
07 as an insulating film that electrically insulates the bonding pad 114 from the bonding pad 114.
The first wiring layer 1 below the bonding pad 114 can reduce stress due to load, pressure, and the like when mounted on an OF or the like.
02 and the second wiring layer 107 as a buffer for preventing damage.

[0027]

However, in the semiconductor device having a two-layer wiring structure disclosed in U.S. Patent Publication No. US2002-0043, the protection film 108 between the second wiring layer 107 and the bonding pad 114 is not provided. As a result, unevenness is formed according to the shape of the second wiring layer 107. Therefore, a concave portion is formed in the protective film 108. If the protective film 108 has a concave portion, the protective film 108 may be cracked when a stress is applied from above. If a crack is formed in the protective film 108, moisture penetrates, and a current flows in a portion where the moisture penetrates, so that the protection film 108 may be corroded and eventually broken.

The polyimide film 110 formed on the second wiring layer 107 has a shape that is inclined from the bonding surface between the second wiring layer 107 and the bonding pad 114 toward the outer periphery of the bonding pad 114. Has become. Therefore, the shape of the lower surface of the bonding pad 114 above the polyimide film 110 is high at the outside and low at the center. If the lower surface of the bonding pad 114 is not flat, the bonding pad 114 and the second
Good connection with the wiring layer 107 becomes impossible.

Since the polyimide film 110 is an organic insulating material, the polyimide film 110 has low adhesion to the barrier metal 112.
Therefore, the bonding pad 114 is
At the interface between the polyimide film 110 and the polyimide film 110, there is a possibility that the film will be peeled off by external pressure.

In order to avoid the above problem, the polyimide film 1
Although it is conceivable that the layer 10 is not formed, there is no buffer material for buffering the stress applied to the second wiring layer 107 and the like from above. As a result, the stress at the time of COF mounting or the like may damage the second wiring layer 107 and the like below the bonding pad 114, and may cause disconnection in the second wiring layer 107 and the like.

The present invention has been made in view of the above-mentioned conventional problems, and has as its object to provide a bonding pad and a second pad.
Good adhesion to the wiring layer and the insulating film, and C
Provided is a semiconductor device capable of preventing a crack in an insulating film between a bonding pad and a second wiring layer and a disconnection of the second wiring layer due to a force applied to the bonding pad during bonding such as OF mounting. Is to do.

[0032]

According to the present invention, there is provided a semiconductor device comprising:
In order to solve the above problems, a semiconductor substrate having an operation region that is a region where a semiconductor element is formed, a first wiring layer formed on the semiconductor substrate and electrically connected to the operation region, A second wiring layer formed on the first wiring layer via an interlayer insulating film; and a bonding pad for electrical connection to the outside, the bonding pad being formed so as to at least partially overlap the operation region. The second wiring layer has a plurality of wirings in a space below the bonding pad, and a part of the wiring is bonded to the bonding pad, while an insulating film is formed between the other wiring and the bonding pad. In a semiconductor device, wherein a recess is formed on a surface of an insulating film due to a gap between wirings in a second wiring layer,
For the recesses on the surface of the insulating film, a flattening film for filling and flattening the recesses is formed, and the flattening film is
It is characterized by being an inorganic insulating film different from the above insulating film.

When the insulating film is formed with a substantially uniform thickness by the deposition method, irregularities are generated on the surface of the insulating film while keeping the shape of the second wiring layer. Therefore, when a polyimide film is formed on the entire surface of the insulating film as in the conventional case, the shape of the lower surface of the bonding pad is such that the outside is high and the center is low, and the bonding pad and the second wiring layer are separated. Adhesion is more difficult, and the connection between the bonding pad and the second wiring layer becomes better.

According to the present invention, the recess formed on the surface of the insulating film due to the formation of the second wiring layer is formed by a flat insulating film different from the insulating film for insulating the second wiring layer and the bonding pad. By filling with the oxide film, the film between the second wiring layer and the bonding pad can be flattened. Thereby, the shape of the surface of the bonding pad on the second wiring layer side is flattened as compared with the case where the polyimide film is formed on the entire surface of the insulating film. Therefore, the bonding pad and the second wiring layer are more likely to be in close contact with each other, and better connection between the bonding pad and the second wiring layer is possible.

Further, according to the present invention, by filling the concave portion, it is possible to avoid damage to the insulating film due to stress from the upper portion of the bonding pad, which is generated at the time of COF mounting or the like. This makes it difficult for a crack to be formed in the insulating film between the bonding pad and the second wiring layer, so that the problem that moisture penetrates from the crack in the insulating film caused by stress and the second wiring layer is disconnected can be reduced.

Further, according to the present invention, since the planarizing film is interposed between the bonding pad and the second wiring layer, the stress applied to the second wiring layer from above the bonding pad by the buffering action of the planarizing film. Can be alleviated. Thereby, the disadvantage that the second wiring layer is disconnected can be reduced.

In addition, according to the present invention, since the flattening film is an inorganic insulating film, the flattening film has a higher adhesion to the bonding pad than an organic insulating film such as a polyimide film.
Therefore, the adhesion between the bonding pad and the semiconductor device body is not impaired. Therefore, it is possible to provide a semiconductor device in which the adhesion between the bonding pad and the insulating film is good and the bonding pad is hard to peel off.

In the specification of the present application, "below the bonding pad" means a space between the semiconductor substrate and the bonding pad. Further, “overlap” means that the orthogonal projections projected on the semiconductor substrate match. In addition, "inorganic insulating film"
In addition to an insulating film made of an inorganic insulating material containing no organic component, an insulating film made of an insulating material mainly composed of an inorganic component modified with an organic group (eg, polysiloxane containing an organic group) is included.

The flattening film is preferably a coated silicon oxide film, that is, a so-called "SOG (Silicon On Glass) film".

As a result, the flexibility of the flattening film is increased, so that a greater buffering action can be obtained against the stress applied to the protective film, the second wiring layer, and the like from above the bonding pad during COF mounting or the like. Therefore, disconnection of the second wiring layer can be more reliably prevented. Further, the coated silicon oxide film is formed to be thicker in the concave portion than in the convex portion on the surface of the protective film due to surface tension, and thus is suitable for flattening.

In a preferred embodiment of a method of manufacturing a semiconductor device according to the present invention, a step of forming a semiconductor element on a semiconductor substrate and a step of forming a first wiring layer so as to partially join the semiconductor element are performed. Performing, forming an interlayer insulating film having a via hole on the first wiring layer, forming a second wiring layer including a plurality of wirings on the interlayer insulating film and in the via hole, On the second wiring layer,
Forming an insulating film so as to cover the plurality of wirings, so that only a part of the wiring covered with the insulating film is exposed,
Forming an opening in the insulating film, and on the insulating film and in the opening, at least a portion overlaps the semiconductor element, and overlaps at least one of the wirings covered with the insulating film, Forming a bonding pad for electrical connection to the outside, the method comprising the step of forming a bonding pad due to a gap between wirings in the second wiring layer before the step of forming the bonding pad. A flattened film made of an insulating material is formed by applying a solution obtained by dissolving an insulating material in a solvent on the insulating film and then curing the solution so as to fill and flatten the concave portions generated on the insulating film surface. And etching back the insulating film and the planarizing film so that the insulating film is exposed. By this etch-back, a substantially flat insulating film (a combination of the insulating film and the flattening film) is formed in which the concave portion of the insulating film is filled with the flattening film.

[0042]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Regarding one embodiment of the present invention,
This will be described below with reference to FIG.

FIG. 1 shows one cell of a semiconductor integrated circuit as a semiconductor device according to the present invention. Hereinafter, the extraction of one cell of the semiconductor integrated circuit will be described.

The semiconductor integrated circuit as a semiconductor device according to the present invention has a region in which a semiconductor element 2 having a transistor called an active region is formed on a silicon substrate 1 as a semiconductor substrate. In the semiconductor integrated circuit, a first wiring layer 3 is formed on a semiconductor element 2 and
A second wiring layer 5 is formed on the wiring layer 3 with an interlayer insulating film 4 interposed therebetween. The second wiring layer 5 is connected to a bonding pad 6 as an external connection terminal formed at least in a region overlapping the active region. The bonding pad 6 is a connecting portion for connecting to the metal wiring pattern of COF described above.

The semiconductor element 2 is a MOS transistor, and although not shown, the surface of the silicon substrate 1 has
There is an active region consisting of a source region and a drain region. The configuration of the semiconductor element 2 is not directly related to the characteristic portion of the present invention, and is a general configuration, so that detailed description will be omitted.

In the following description, only the first wiring layer 3 electrically connected to the active region and each component thereon will be described. The first wiring layer 3 is a single layer or a multiple layer made of a conductor such as aluminum.
In the case of multiple layers, for example, 300n from the silicon substrate 1 side
A TiW layer of about m and an AlSi layer of about 600 nm are formed in this order.

In the first wiring layer 3, the silicon substrate 1
A plurality of wirings are formed on the active region through an insulating film, and a part of the wirings is connected to the active region, ie, the semiconductor element 2 through a contact hole provided in the insulating film.
Is electrically connected to

An interlayer insulating film 4 is formed on the first wiring layer 3 in order to make the first wiring layer 3 and the second wiring layer 5 electrically insulated (not connected). Also, the interlayer insulating film 4
Is provided with a via hole 7 for electrically connecting the first wiring layer 3 and the second wiring layer 5.

The interlayer insulating film 4 is formed from the silicon substrate 1 side.
Silicon oxide film 4a, coated silicon oxide film (SOG film)
4b and a silicon oxide film 4c. The coated silicon oxide film (SOG film) 4b is formed to flatten the unevenness generated by the first wiring layer 3. The silicon oxide films 4a and 4c are formed by CVD (Chemical Vapor Depth).
osition (chemical vapor deposition) method, etc.
It is formed with a thickness of about 00 nm.

The second wiring layer 5 is also formed of a conductor such as aluminum and has a single layer or multiple layers. In the case of multiple layers, for example, 15
A TiW layer of about 0 nm and an AlSi layer of about 1000 nm are formed in this order. The second wiring layer 5 also has a plurality of wirings, some of which are in the first wiring layer 3.
Are electrically connected via the via holes 7.

The second wiring layer 5 has a region overlapping with the bonding pad 6 (a space below the bonding pad 6).
And a plurality of wirings insulated from each other. Also,
A part of the wiring in this region is connected to the first wiring layer 3 through the via hole of the interlayer insulating film 4, while the remaining wiring in this region is insulated from the first wiring layer 3.

An inorganic insulating film (insulating film) 8 and coated silicon as a planarizing film are used as a protective film for electrically disconnecting a part of the wiring of the second wiring layer 5 from the bonding pad 6. Oxide film (hereinafter abbreviated as SOG film) 1
0 is formed.

An inorganic insulating film 8 is formed on the second wiring layer 5. The inorganic insulating film 8 is a deposited film such as a silicon oxide film or a silicon nitride film formed by a deposition method such as a CVD method. The inorganic insulating film 8 has a thickness of, for example, 40
It is formed of two layers of a 0 nm SiO ₂ film and a 720 nm thick SiN film.

An opening 8 b for connecting a part of the wiring of the second wiring layer 5 to the bonding pad 6 is formed at the bonding portion between the inorganic insulating film 8 and the bonding pad 6. In the region of the inorganic insulating film 8 corresponding to the plurality of wirings of the second wiring layer 5 located in the region overlapping with the bonding pad 6, the opening 8b is formed only at a position corresponding to a part of the wirings, It is not formed in a region corresponding to the remaining wiring. Therefore, the second in the opening 8b
The cross-sectional area (the cross-sectional area along a plane parallel to the silicon substrate 1) at the end on the wiring layer 5 side is smaller than the area of the upper surface of the bonding pad 6. The cross-sectional area of the opening 8b at the end on the second wiring layer 5 side is more preferably in the range of 60% to 100% of the square of the wiring width of the second wiring layer 5.

On the upper surface of the inorganic insulating film 8, SO
A G film 10 is formed, and a barrier metal 9 is further formed thereon.
Are formed. The bonding pad 6 is formed via a barrier metal 9 formed on the inorganic insulating film 8.
It is joined to the second wiring layer 5. The barrier metal 9 is a refractory metal that prevents the material of the second wiring layer 5 from reacting with the material of the bonding pad 6 such as gold.

Hereinafter, the present invention will be described in more detail with reference to FIG. 2, which is an enlarged view of a portion 11 near the junction between the second wiring layer 5 and the bonding pad 6 in FIG.

Since the inorganic insulating film 8 is formed over the entire surface with a substantially uniform thickness, the surface of the inorganic insulating film 8 has an uneven shape having a height difference (a shape having a height difference) according to the shape of the second wiring layer 5. ). Therefore, a concave portion 8 a is formed on the surface of the inorganic insulating film 8 due to the gap between the wires in the second wiring layer 5. As shown in FIG. 3, the concave portion 8a of the inorganic insulating film 8 is very weak against stress from above. Therefore, if the barrier metal 9 is formed directly on the concave portion 8a, it will When the stress is applied, a crack 12 is formed in the concave portion 8a of the inorganic insulating film 8.

Therefore, in the semiconductor integrated circuit according to the present invention, as shown in FIG.
The protective film (the inorganic insulating film 8 and S
OG film 10) is planarized. By flattening the surface of the protective film, the protective film has no portions that are vulnerable to stress, so that the protective film is less likely to crack. In addition, since the SOG film 10 is formed of a material that is softer than the inorganic insulating film 8, the SOG film 10 also acts as a buffer against stress applied to the inorganic insulating film 8 from above.

The SOG film 10 is a film formed by applying an insulating film material dissolved in an organic solvent on the inorganic insulating film 8 and then curing the applied material. The SOG forming the SOG film 10 may be an inorganic SOG or an organic SOG. The main inorganic SOG includes, for example, silicate, alkoxysilicate, polysilazane, H
SQ (Hydrogensilsesquioxane), porous silica and the like. Silicate or alkoxysilicate, H
Curing of the SQ is performed by dehydration condensation by heat treatment at about 350 ° C. to 450 ° C. On the other hand, the curing of the polysilazane-based material is performed by a hydrolytic reaction by a heat treatment in oxygen containing water vapor. Organic SOG is a SOG having a Si—C bond in a film, typically polymethylsiloxane.
It is.

Next, a method for burying the SOG film 10 in the recess 8a of the inorganic insulating film 8 will be described.

First, a solution in which a material for forming the SOG film 10 is dissolved in an organic solvent is applied to the entire surface of the inorganic insulating film 8 by a spin coating method (spin coating) or the like, and then cured to form the SOG film 10. . The surface of the SOG film 10 formed here becomes substantially flat without depending much on the shape of the underlying step. The SOG film 10 is formed to be thicker in the concave portion than in the convex portion of the surface to be coated due to surface tension, and thus is suitable for flattening. Next, dry etching is performed on the entire surface of the SOG film 10 and the inorganic insulating film 8 by an etch-back method in which etching (constant-speed etching) is performed under the condition that the etching rates of the SOG film 10 and the underlying film (the inorganic insulating film 8) become substantially equal. Then, the SOG film 10 is left only in the recess 8a.
Thereby, the concave portion 8a on the surface of the inorganic insulating film 8 is
A flat protective film filled with 0 is formed.

Further, by flattening the shape of the protective film below the bonding pad 6, the bonding pad 6
Is also flattened, and better bonding, for example, the above-described COF mounting and the like is performed favorably.

As described in the section of the prior art, when an organic polymer film such as a polyimide film is used as a protective film under the bonding pad, the unevenness on the outermost surface cannot be reduced. The shape of the surface of the polymer film remains the same as that of the lower layer. Therefore, the height of the lower surface of the bonding pad is increased by the thickness of the organic polymer film on the outer periphery, and a relatively large height difference, for example, a height difference of about 2 to 3 μm occurs. Therefore, good bonding between the bonding pad and the second wiring layer becomes impossible.

In this embodiment, the opening 8 of the inorganic insulating film 8
Although the height difference occurs on the lower surface of the bonding pad 6 due to the step of b, the SOG film 10 is formed only in the concave portion 8a and the protection film under the bonding pad 6 is relatively thin. It is as small as about 12 μm.
This level difference is absorbed by the bonding pad 6 biting during the bonding of the bonding pad 6, so that the bonding pad 6 is sufficiently adhered to the second wiring layer 5, and the problem of adhesion is also solved. You. in this way,
In the present embodiment, since the shape and material of the protective film below the bonding pad 6 are different from those of the conventional technique, good bonding between the bonding pad and the second wiring layer can be achieved.

Although the SOG film has been used for flattening conventionally, in the prior art, the first wiring layer and the second wiring layer are not used.
It is used as an interlayer insulating film between the first wiring layer and the second wiring layer.

On the other hand, in the present embodiment, the SO
The point that the G film 10 is formed on the outermost surface layer so as to be flattened is different from the conventional SOG film. Also, SOG film 1
The number 0 is used for alleviating unevenness due to the effect of the lower film (second wiring layer 5) formed on the surface.

In the present embodiment, the SOG film 1
0 is formed of the same material and the same manufacturing method as the SOG film 4b formed between the first wiring layer 3 and the second wiring layer 5. Therefore, a new device is not required for forming the SOG film 10, and the SOG film 10 can be formed by an existing device used for the shape of the SOG film 4b. Therefore, material costs and equipment costs are reduced, and costs can be reduced.

[0068]

As described above, the semiconductor device of the present invention has the following features.
A semiconductor substrate having an operation region in which a semiconductor element is formed; a first wiring layer formed on the semiconductor substrate and electrically connected to the operation region; and an interlayer insulating layer formed on the first wiring layer A second wiring layer formed through the film, and a bonding pad for electrical connection to the outside, the bonding pad being formed so as to at least partially overlap the operation region;
The second wiring layer has a plurality of wirings in a space below the bonding pad, and a part of the wiring is bonded to the bonding pad, while an insulating film is formed between another wiring and the bonding pad. In the semiconductor device in which the concave portion is formed on the surface of the insulating film due to the gap between the wirings in the second wiring layer,
A flattening film for filling and flattening the recess is formed, and the flattening film is different from the insulating film and is an inorganic insulating film.

Since the insulating film between the second wiring layer and the bonding pad can be flattened, the shape of the surface of the bonding pad on the second wiring layer side is flattened. Therefore, the present invention has an effect that the bonding pad and the second wiring layer are more easily brought into close contact with each other, and a better connection between the bonding pad and the second wiring layer becomes possible.

According to the above structure, the concave portion of the insulating film between the second wiring layer and the bonding pad is filled,
There is no portion with low strength in the insulating film. Therefore, the present invention also has an effect that it is possible to prevent the insulating film between the bonding pad and the second wiring layer from being cracked by the force applied to the bonding pad during bonding such as COF mounting. As a result, it is possible to reduce a problem that moisture penetrates from a crack in the insulating film caused by stress and the second wiring layer is disconnected.

Further, according to the above configuration, the stress applied to the second wiring layer from above the bonding pad can be reduced by interposing the flattening film between the bonding pad and the second wiring layer. Therefore, the present invention
There is also an effect that disconnection of the second wiring layer can be prevented by a force applied to the bonding pad during bonding such as COF mounting.

In addition, according to the above configuration, the flattening film is
Since it is an inorganic insulating film, the adhesive strength with the bonding pad is larger than that of an organic insulating film such as a polyimide film. Therefore, the present invention also has the effect of providing a semiconductor device having good adhesion between the bonding pad and the insulating film and in which the bonding pad is not easily separated.

The present invention also has an effect that the disconnection of the second wiring layer can be more reliably prevented if the flattening film is a coated silicon oxide film.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is an enlarged cross-sectional view showing a main part of the semiconductor device in FIG. 1;

FIG. 3 is a diagram for explaining a crack generation mechanism.

4A and 4B are diagrams for explaining inner lead bonding, in which FIG. 4A is a cross-sectional view showing a semiconductor device before bonding;
(B) is a sectional view showing the semiconductor device after bonding.

FIG. 5 is a cross-sectional view illustrating an example of a conventional semiconductor device.

[Explanation of symbols]

1 Silicon substrate 2 Semiconductor elements 3 First wiring layer 4 Interlayer insulation film 4a Silicon oxide film 4b SOG film 4c silicon oxide film 5 Second wiring layer 6 Bonding pad 7 Beer Hall 8 Inorganic insulating film 9 Barrier metal 10 SOG film

Claims (2)

[Claims] A semiconductor substrate having an operation region in which a semiconductor element is formed; a first wiring layer formed on the semiconductor substrate and electrically connected to the operation region; A second layer formed on the layer via an interlayer insulating film
A wiring layer, at least a portion of which is formed so as to overlap the operation region;
A bonding pad for electrical connection to the outside, wherein the second wiring layer has a plurality of wirings in a space below the bonding pad, and a part of the wiring is bonded to the bonding pad. A semiconductor device in which an insulating film is formed between another wiring and a bonding pad, and a concave is formed on the surface of the insulating film due to a gap between the wirings in the second wiring layer; A semiconductor device, wherein a flattening film for filling and flattening the recess is formed, and the flattening film is different from the insulating film and is an inorganic insulating film. . 2. The semiconductor device according to claim 1, wherein said flattening film is a coated silicon oxide film.