JP2003332579A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that can be suppressed easily in characteristic variation caused by substrate floating effects even when the thickness of a semiconductor layer is reduced without increasing a device area. <P>SOLUTION: In this semiconductor device, a semiconductor layer 3 formed on an embedded insulating film 2 has a first-conductivity body region 10, a second-conductivity source region 9a, and second-conductivity drain regions 8 and 9b, and a channel is formed in the body region 10 between the drain regions 8 and 9b. The source region 9a is formed to a depth not reaching the embedded insulating film 2 in the semiconductor layer 3 and has a source electrode 12a embedded in the semiconductor layer 3 so that the electrode 12a reaches the body region 10 between the source region 9a and the insulating film 2 through the source region 9a. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SOI (Silicon On Insulator) type semiconductor device manufactured by, for example, forming a source region, a body region and a drain region in a semiconductor layer on an insulating film.

[0002]

2. Description of the Related Art FIG. 8 is a sectional view of a semiconductor device formed of an n-channel MOS transistor as a typical example of a conventional SOI type MOS transistor. In the semiconductor device shown in FIG. 8, a semiconductor layer (SOI layer) 103 made of a single crystal silicon film formed via a buried insulating film 102 is formed on a support substrate 101 made of silicon or the like. N in which phosphorus or arsenic is added to 103 at a high concentration
A mold source region 104 and a drain region 105 are formed.

A p-type body region 106 to which boron is added is formed between the source region 104 and the drain region 105. A gate electrode 108 made of n-type polycrystalline silicon is formed right above the body region 106 via a gate insulating film 107. Also, the source region 104
A source electrode 109 and a drain electrode 110 are provided to apply a potential to the drain region 105 and the drain electrode 105, respectively.

Here, the source electrode 109 and the gate electrode 1
It is assumed that OV is applied to 08 and a positive voltage is applied to the drain electrode 110. This state corresponds to the state in which the gate of the n-channel MOS transistor is forcibly turned off. In this case, the pn junction composed of the p-type body region 106 and the n-type drain region 105 is biased in the reverse direction, and due to a known mechanism, electrons and positive electrons are depleted in the depletion layer of high electric field. A pair of holes is generated.

At this time, since there is a potential gradient from the drain region 105 to the body region 106, electrons move to the drain region 105 and holes move to the body region 106. The holes moved to the body region 106 are the source region 10
However, the holes are accumulated in the body region 106 because the potential barrier is formed because the source region 104 is n-type. Therefore, the potential of the body region 106 rises according to the amount of accumulated holes,
As a result, the threshold voltage (Vth) of the n-channel MOS transistor is lowered.

In order to suppress the characteristic variation due to the substrate floating effect, the potential of the body region 106 may be set to the ground potential. However, for example, a dedicated electrode is provided in the body region 106, and this is used as the source electrode 109.
This structure is not usually adopted because a short circuit to the device leads to an increase in the area occupied by the device.

As a conventional structure for suppressing the characteristic variation due to the substrate floating effect without providing a dedicated electrode in the body region 106, the structure shown in FIG. 9 and FIGS.
The structure shown in is shown as an example.

FIG. 9 (a) is a plan view of an SOI type semiconductor device according to a conventional example, and FIG. 9 (b) is BB 'of FIG. 9 (a).
It is sectional drawing in a line. In the semiconductor device shown in FIGS. 9A and 9B, the support substrate 201 made of silicon or the like is used.
The element isolation insulating film 2 is formed on the upper surface of the element isolation insulating film 2 with the buried insulating film 202 interposed therebetween.
P-type semiconductor layer (SOI
Layer) 203 is formed, and the gate insulating film 205, the gate electrode 206, and the sidewall insulating film 2 are formed on the semiconductor layer 203.
07 are formed.

A buried insulating film 20 is formed on the semiconductor layer 203.
2 is formed, and an n-type semiconductor region 213 that does not reach the buried insulating film is formed, and n-type extension regions 209a and 209b are formed inside the n-type semiconductor regions 213 and 208. . p
In the n-type semiconductor layer 203, an n-type semiconductor region 208,
213 and n-type extension regions 209a and 209
The region where b is not formed becomes the body region 210.

The n-type semiconductor region 213 and the n-type extension region 209a constitute a source region,
The n-type semiconductor region 208 and the n-type extension region 209b form a drain region. Also,
A p-type semiconductor region 214 is formed on the element isolation insulating film 203 side of the n-type semiconductor region 213 forming the source region.

The exposed surfaces of the semiconductor layer 203 and the gate electrode 206 are silicidized to form a silicide layer 212.
a, 212b, and 212c are formed, and the silicide layer 212a connected to the p-type semiconductor region 214 and the n-type semiconductor region 213 forming the source region forms the source electrode and the n-type semiconductor region forming the drain region. 20
The silicide layer 212b connected to 8 forms a drain electrode.

In the semiconductor device having the above structure, the silicide layer 212a serving as the source electrode constitutes the source region.
P-type semiconductor region 2 connected to the p-type semiconductor region 213
Since it is also connected to 14, the holes accumulated in the body region 210 will escape to the silicide layer 212a serving as the source electrode through the p-type semiconductor region 214.

FIG. 10 is a plan view of an SOI type semiconductor device according to a conventional example, FIG. 11 (a) is a sectional view taken along the line CC 'of FIG. 10, and FIG. 11 (b) is of FIG. D-
It is sectional drawing in a D'line. The same components as those in FIG. 9 are designated by the same reference numerals, and the description thereof will be omitted.

In the SOI type semiconductor device shown in FIGS. 10 and 11, a convex portion projecting toward the n-type semiconductor region 208a forming the source region is formed at the end of the gate electrode 206a. A p-type semiconductor region 214 is formed between the n-type semiconductor regions 208a.

Therefore, the cross-sectional structure taken along the line CC 'of the central portion in the width direction of the gate electrode 206a is shown in FIG.
As shown in FIG. 11A, the sectional structure is similar to that of the conventional SOI semiconductor device, but the sectional structure taken along the line DD ′ in which the convex portion of the gate electrode 206 a is formed is shown in FIG.
In the body region 210, as shown in FIG.
The silicide layer 212a, which is the source electrode, is connected via the electrode 4.

In the semiconductor device having the above structure, the gate electrode 2
Since the silicide layer 212a serving as the source electrode is connected via the p-type semiconductor region 214 to the body region 210 corresponding to the end where the convex portion of 06a is formed,
The holes accumulated in the body region 210 will escape to the silicide layer 212a that is the source electrode through the p-type semiconductor region 214 in the body region 210 corresponding to this end portion.

[0017]

However, as shown in FIG.
In the SOI semiconductor device shown in (a) and (b), when the n-type semiconductor region 213 forming the source region reaches the buried insulating film 202, the body region 210 and the p-type semiconductor region 214 outside the source region are separated. Since the connection is lost, it is necessary to form the n-type semiconductor region 213 so as not to reach the buried insulating film 202. On the other hand, the n-type semiconductor region 208 forming the drain region needs to be formed so as to reach the buried insulating film 202 from the viewpoint of reducing the load capacitance. Therefore, the n-type semiconductor region 21
3 is required to be controlled with high precision, and the resistance of the n-type semiconductor region 213 serving as the source region is lowered,
There is a problem that the thickness of the semiconductor layer 3 must be secured to a certain extent or more in order to open an appropriate space between the n-type semiconductor region 213 and the buried insulating film 202.

The SOI type semiconductor device shown in FIG. 10 does not have the above-mentioned problem, but has a problem that the effective gate width W in the element forming region becomes small and the driving capability is deteriorated. Therefore, in order to secure the same effective gate width W as that of the conventional structure, the element area is substantially increased.

The present invention has been made in view of the above circumstances, and an object thereof is to easily suppress the characteristic variation due to the substrate floating effect without increasing the element area and reducing the film thickness of the semiconductor layer. An object of the present invention is to provide a semiconductor device that can be manufactured.

[0020]

In order to achieve the above-mentioned object, a semiconductor device of the present invention has a semiconductor layer formed on an insulating film, in which a first conductivity type body region and a second conductivity type source region are provided. And a drain region, wherein a channel is formed in the body region between the source region and the drain region, wherein the source region has a depth that does not reach the buried insulating film. The source electrode is formed in a layer and penetrates through the source region and is embedded in the semiconductor layer so as to reach the body region between the source region and the embedded insulating film.

The source electrode is formed by silicidizing the semiconductor layer so as to penetrate the source region and reach the body region between the source region and the buried insulating film.

The semiconductor device further includes a first conductivity type semiconductor region formed between the source electrode and the body region and containing a first conductivity type impurity at a higher concentration than that of the body region.

The drain region is formed to a depth reaching the buried insulating film.

The drain region contains an impurity of the second conductivity type, and the second conductivity type semiconductor region is formed to a depth reaching the buried insulating film, and the concentration of the second conductivity type semiconductor region is lower than that of the second conductivity type semiconductor region. A low-concentration second-conductivity-type semiconductor region containing a second-conductivity-type impurity and formed to a depth that does not reach the buried insulating film, and the low-concentration second-conductivity-type semiconductor region is also formed on the source side. As a result, the source region is formed.

According to the above semiconductor device of the present invention, the first
Charges generated in the depletion layer formed between the conductive type body region and the second conductive type drain region are embedded in the semiconductor layer so as to reach the body region when the charge moves to the body region. The charge is prevented from being accumulated in the body region because it moves to the source electrode which is formed and escapes to the outside. Further, since the source electrode is provided so as to penetrate the source region formed in the semiconductor layer to a depth that does not reach the embedded insulating film, it is also electrically connected to the source region and is connected to the source region during operation. The desired potential is applied.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a semiconductor device of the present invention will be described below with reference to the drawings.

FIG. 1A is a plan view of the SOI semiconductor device according to this embodiment, and FIG. 1B is a sectional view taken along the line AA ′ of FIG. In the semiconductor device shown in FIGS. 1A and 1B, for example, a semiconductor layer (SOI layer) 3 formed on a support substrate 1 made of silicon or the like with a buried insulating film 2 interposed therebetween is used as an element isolation insulating film 4. The semiconductor layer 3 is isolated by the element, and, for example, a p-type impurity is introduced into the semiconductor layer 3, and the gate electrode 6 is formed via the gate insulating film 5.

On the drain formation side of the semiconductor layer 3, an n-type semiconductor region 8 containing an n-type impurity at a high concentration is formed with a depth reaching the buried insulating film 2. An n-type extension region 9b containing an n-type impurity at a concentration lower than that of the n-type semiconductor region 8 at a depth that does not reach the embedded insulating film 2 on the inside of the n-type semiconductor region 8 and on the side facing each other with the gate electrode 6 interposed therebetween. , 9a are formed. The n-type extension regions 9b and 9a are conventionally provided to reduce the electric field strength.

The n-type extension region 9b and the n-type semiconductor region 8 outside thereof form a drain region, and the n-type extension region 9a forms a source region. That is, in the present embodiment, conventionally, the n-type extension region 9a is used as the source region without forming the n-type semiconductor region forming the source region. In the p-type semiconductor layer 3, the region where the n-type source region and the drain region are not formed becomes the body region 10, and a channel is formed in the body region 10 between the source region and the drain region.

N-type extension regions 9a, 9b and p
P-type impurities are formed at a higher concentration than the body region 10 in order to prevent the depletion layer from protruding directly below the gate electrode 6 from the source and drain regions. Having a semiconductor region 11,
It has a structure that suppresses the short channel effect.

On the exposed surfaces of the semiconductor layer 3 and the gate electrode 6, silicide layers 12a, 12 which are silicided are formed.
b and 12c are formed. Silicide layers 12a-1
2c, the silicide layer 12a penetrates the extension region 9a serving as the source region, and the p-type semiconductor region 11 is formed.
Has been silicided to a depth of up to. The silicide layer 12a forms the source electrode, and the silicide layer 12b forms the drain electrode.

In the above description, the n-channel MOS is
Although the example in which the transistor is formed in the p-type semiconductor layer 3 has been described, a pMOS transistor is obtained by changing the source region, the body region, and the drain region from n-type to p-type and from p-type to n-type. May be formed in the n-type semiconductor layer.

In the SOI semiconductor device according to the present embodiment described above, for example, the silicide layer 1 serving as the source electrode is used.
It is assumed that Oa is applied to 2a and the gate electrode 6, and a positive voltage is applied to the silicide layer 12b that becomes the drain electrode. This state corresponds to the state in which the gate of the n-channel MOS transistor is forcibly turned off. In this case, the pn junction between the p-type body region 10 and the drain region composed of the n-type extension region 9b and the n-type semiconductor region 8 is biased in the opposite direction, which is due to a known mechanism. Electron-hole pairs are generated in the high electric field depletion layer.

At this time, the n-type extension region 9b
Since there is a potential gradient from the drain region including the n-type semiconductor region 8 to the body region 10, electrons move to the drain region and holes move to the body region 106.

The holes that have moved to the body region 106 flow to the p-type semiconductor region 11 on the source side having a low resistance in which the p-type impurity is introduced at a higher concentration than the body region 106, and the p-type semiconductor region 11 has Silicide layer 1 that directly serves as the source electrode
Since 2a is connected, it can be extracted to the silicide layer 12a without passing through the pn junction, and the potential of the body region 10 can be made constant, so that the threshold voltage (Vth) of the transistor is prevented from lowering. be able to.

As described above, according to the SOI type semiconductor device of this embodiment, the silicide layer 12a is formed deeply so as to penetrate the n type extension region 9a and reach the p type semiconductor region 11. Since the silicide layer 12a serving as the source electrode is connected to the n-type extension region 9a and the p-type semiconductor region 11, it is possible to suppress the characteristic variation due to the substrate floating effect without separately providing the contact electrode to the body region. can do. Therefore, there is no problem such as an increase in capacitance and element area due to the independent provision of the contact electrode to the body region.

Further, although there is no n-type semiconductor region corresponding to the conventional buried insulating film 2 on the source side, a silicide layer 12a formed by being buried in the semiconductor layer 3 is formed on the source side. Since the source electrode is formed, there is no problem of increase in resistance, and the film thickness of the semiconductor layer 3 can be reduced. Therefore, it is effective in manufacturing a fine SOI semiconductor device having excellent roll-off characteristics. is there. Further, unlike the conventional example shown in FIG. 10 to FIG. 11, there is no problem that the driving capability is reduced due to the reduction of the effective gate width.

Next, the SOI according to this embodiment having the above structure
A method of manufacturing the semiconductor device will be described with reference to FIGS.

First, as shown in FIG. 2A, an SOI substrate in which a semiconductor layer (SOI layer) 3 is formed on a support substrate 1 made of, for example, silicon or the like with a buried insulating film 2 made of silicon oxide or the like interposed therebetween. To prepare. In addition, this SOI
The method of manufacturing the substrate is not limited, and for example, known SI
Those manufactured by the MOX (Separation by IMplanted OXygen) method, the wafer bonding method or the like can be used. Here, for example, the film thickness of the semiconductor layer 3 is 30 to 5
It is about 0 nm.

Next, as shown in FIG. 2B, the above S
A thermal oxide film 21 for reducing stress is formed on the surface of the semiconductor layer 3 of the OI substrate by a thermal oxidation method to have a thickness of about 10 nm.
As a P (Chemical Mechanical Polishing) protective film, L
PCVD (Low Pressure Chemical Vapor Deposition)
A protective film 22 made of silicon nitride (Si ₃ N ₄ ) is formed by, for example, about 100 nm. LP at this time
The conditions for forming Si ₃ N ₄ by the CVD method are, for example, gas: SiH ₂ Cl ₂ / NH ₃ / N ₂ = 50/200/2.
00 sccm, pressure: 70 Pa, substrate heating temperature: 760
It can be set to about ° C.

Next, as shown in FIG. 3C, element formation is performed.
A resist film (not shown) having an area pattern is lithographed.
It is formed by the Luffy technique and the resist film is used as a mask.
Etching the silicon nitride film of the protective film 22
Then, the protective film 22 in the element isolation region and the thermal oxide film 21 are removed.
Then, the semiconductor layer 3 is removed to form the groove M.
It Silicon nitride (Si₃ N_Four ) Membrane etch
For example, the gasing condition is gas: CF_Four / Ar = 100/9
00sccm, pressure: 105Pa, RFPower: 6
The temperature may be 00 W and the substrate temperature may be about 10 ° C. Well
Also, the etching conditions for the silicon (Si) of the semiconductor layer 3
Is, for example, gas: C _Four F₈ / O₂ / Ar = 5/4/1
00sccm, pressure: 53Pa, RFPower: 40
The temperature may be 0 W and the substrate temperature may be about 10 ° C.

Next, as shown in FIG. 3D, after oxidizing the inner wall of the groove M by about 5 nm, an insulating film such as a silicon oxide (SiO ₂ ) film is formed by, for example, 30 by LPCVD.
The groove M is formed to a thickness of about 0 nm and the groove M is buried and annealed. Subsequently, the surface of the insulating film is polished by the CMP method using the protective film 22 as a stopper to remove the insulating film made of silicon oxide deposited in the area other than the element isolation region, and the element isolation insulating film 4 is formed.
To form. The conditions for forming the silicon oxide (SiO ₂ ) film by the LPCVD method at this time are, for example, gas: SiH.
₄ / O ₂ / N ₂ = 250/250/100 sccm,
The pressure can be 133 Pa and the substrate heating temperature can be about 520 ° C. The annealing conditions for the insulating film (SiO ₂ ) may be, for example, annealing temperature: 1000 ° C. and annealing time: about 30 min.

Next, as shown in FIG. 4E, the protective film 22 made of a silicon nitride film is removed by a wet treatment with heated phosphoric acid to form a p-type for forming a body region in the semiconductor layer 3. Impurity is obliquely ion-implanted. The ion implantation conditions at this time can be: implantation impurities: BF ₂ ⁺ , implantation energy: 20 keV, dose amount: 3 × 10 ¹² / cm ² , implantation angle: about 7 °.

Next, as shown in FIG. 4 (f), the thermal oxide film 21 is removed, and the silicon oxide film 1.
The gate insulating film 5 is formed to a thickness of about 8 nm.

Next, as shown in FIG. 5G, polysilicon is deposited on the gate insulating film 5 by, for example, the LPCVD method.
A film having a thickness of about 50 nm is formed, a resist film (not shown) having a gate electrode pattern is formed on the polysilicon by a lithography technique, and the polysilicon film is patterned using the resist film as a mask to form the gate electrode 6. After that, the resist film (not shown) is removed. The deposition conditions for the polysilicon film to be the gate electrode 6 by the LPCVD method are, for example, gas: SiH ₄ / N ₂ / H.
e = 100/200/400 sccm, pressure: 70P
a, substrate heating temperature: about 610 ° C.
Further, the etching conditions for the polysilicon film to be the gate electrode 6 are as follows: gas: C ₂ Cl ₃ F ₃ / SF ₆ = 60 / 10s
ccm, pressure: 13 Pa, RFPower: 150 W,
Substrate temperature: Can be set to about 20 ° C.

Next, as shown in FIG. 5 (h), arsenic is ion-implanted into the gate electrode 6 as an n-type impurity to make it n-type, and the gate electrode 6 is used as a mask to form the semiconductor layer 3 first. The p-type impurity is introduced at a higher concentration than the ion-implantation of the p-type impurity by oblique ion implantation to form the p-type semiconductor region 11. Ion implantation conditions for forming the p-type semiconductor region at this time are, for example, implantation impurities: B ⁺ ,
Injection energy: 12 keV, Dose amount: 6 × 10 ¹² /
cm ² × 8 times, injection angle: about 30 °.

Next, as shown in FIG. 6I, using the gate electrode 6 as a mask, the semiconductor layer 3 is ion-implanted with, for example, an n-type impurity to form an n-type extension region 9a,
9b is formed. After the introduction of the n-type impurity, short-time heat treatment (RTA: Rapid Th
ermal Anneal). As a result, a source region including the n-type extension region 9a is formed on the source side. Ion implantation conditions at this time are, for example, implantation impurity: As ⁺ , implantation energy: 2.5 k.
eV, dose amount: 1 × 10 ¹⁵ / cm ² , implantation angle: 0 °
It can be a degree. The RTA condition after introducing the second conductivity type impurity is, for example, annealing temperature: 950.
° C., annealing time: 5 sec, can be carried out in an N ₂ atmosphere.

Next, as shown in FIG. 6 (j), LPCV
For example, a silicon nitride (Si ₃ N ₄ ) film is formed into 50 by the D method.
After forming a film having a thickness of about nm, the side wall insulating film 7 is formed on the side portion of the gate electrode 6 by etching back the silicon nitride film. The film forming conditions of the silicon nitride (Si ₃ N ₄ ) film by the LPCVD method at this time are, for example, gas: SiH ₂ Cl ₂ / NH ₃ / N ₂ = 50/20.
0/200 sccm, pressure: 70 Pa, substrate heating temperature:
It can be about 760 ° C.

Next, as shown in FIG. 7K, a resist mask R having an opening only on the drain formation side is formed by a photolithography technique such as resist coating, exposure, and development. Then, using the resist mask R, the gate electrode 6, and the sidewall insulating film 7 as a mask, n-type impurities are ion-implanted at a higher concentration than the n-type extension regions 9a and 9b, and a short time for activation is obtained. The heat treatment is performed to reach the buried insulating film 2 with a depth of n.
The type semiconductor region 8 is formed only on the drain side. As a result, the n-type semiconductor region 8 and the n-type extension region 9b are formed.
A drain region having is formed. The ion implantation conditions at this time are, for example, implantation impurity: P ⁺ , implantation energy: ¹⁵ keV, dose amount: 1 × 10 ¹⁵ / cm ² × 4.
Time, injection angle: about 7 °. The RTA condition after introducing the second conductivity type impurity can be performed in an N ₂ atmosphere with an annealing temperature of 1000 ° C. and an annealing time of 5 sec.

Next, as shown in FIG. 7L, a film of cobalt (Co) having a thickness of about 5 nm is formed by a sputtering method.
By heat treatment (RTA), only the cobalt (Co) film formed on the Si film of the semiconductor layer 3 and the gate electrode 6 in the source and drain is silicidized (CoSi) to form the silicide layers 12a, 12b, 12c, respectively. Form. After that, the other cobalt (Co) films formed on the element isolation insulating film 4 and the sidewall insulating film 11 are selectively removed by a mixed solution of sulfuric acid and hydrogen peroxide. The sputtering conditions for the cobalt (Co) film are, for example, gas: Ar = 100 sccm, pressure: 0.4 Pa,
DCPower: 0.8 kW, substrate heating temperature: 450 ° C
It can be a degree. The RTA conditions may be annealing temperature: 550 ° C., annealing time: 30 sec, and N ₂ or N ₂ / Ar atmosphere.

Then, by heat treatment again, silicide is formed.
The (CoSi) layers 12a to 12c are made sufficiently low in resistance. This
The CoSi film further reacts with Si by the treatment of
Si ₂ It becomes a film. The RTA condition at this time is the annealing temperature.
Degree: 700 ° C., annealing time: 30 sec, N₂ Or
N₂ / Ar atmosphere can be used. In addition, the above
Cobalt (Co) film formed by salicide process
Consumes a silicon (Si) layer that is 3.64 times thicker than
3.52 times thicker CoSi₂ Form a film. Therefore,
By controlling the film thickness of this cobalt (Co) film,
As shown in FIG. 7 (l), the n-type energy forming the source region is formed.
The p-type semiconductor region 1 is penetrated through the tension region 9a.
To form a silicide layer 12a having a depth so as to connect to 1
You can

As the subsequent steps, the same steps as the conventional ones are performed. For example, after that, a silicon oxide (SiO ₂ ) film is formed, for example, by a CVD method to form an interlayer insulating film, and the silicide layers 12a to
A contact hole reaching 12c is formed. continue,
After forming an adhesion layer having a laminated structure of titanium and titanium nitride by sputtering in the contact hole of the interlayer insulating film, tungsten (W) is deposited on the entire surface of the interlayer insulating film so as to fill the contact hole by the CVD method, Etch back is performed to form a conductive plug made of tungsten (W). Then, by forming a wiring layer made of aluminum or the like connected to the conductive plug, S
A MOS transistor formed on the OI substrate is manufactured.

According to the method for manufacturing an SOI type semiconductor device according to the present embodiment described above, in the step shown in FIG. 7K, a resist mask R having an opening only on the drain side is formed and an n type impurity is ionized. By injecting, the n-type semiconductor region 8 is formed only in the semiconductor layer 3 on the drain side.
In the step shown in (l), the n-type extension region 9a serving as the source region is formed by forming the silicided semiconductor layer 3 to be thicker than the conventional one.
Can be manufactured by penetrating through and forming a silicide layer 12a serving as a source electrode connected to the p-type semiconductor region 11, and can be easily manufactured without increasing manufacturing steps.

The semiconductor device of the present invention is not limited to the description of the above embodiment. For example, in the present embodiment, the example in which the MOS transistor is formed on the SOI substrate in which the semiconductor layer 3 made of single crystal silicon is formed on the support substrate 1 with the embedded insulating film 2 interposed therebetween has been described.
May be polysilicon or the like instead of single crystal silicon.

Further, in this embodiment, CoSi₂ Using
The full salicide structure is shown as an example.
The material is not limited. In addition, this embodiment
Then, S formed by the thermal oxidation method as the gate insulating film 5
iO ₂ Although the film has been described as an example, the invention is not limited to this.
It is a compound of Si such as SiN, SiON, and SiOF.
Edge material and Ta₂ O_Five High dielectric constant film such as
It can also be formed by a laminated film of.

In the present embodiment, a polycrystalline silicon film is used as an example of the gate electrode 6, but the gate electrode 6 is not limited to this. For example, a polycrystalline silicon film containing impurities such as B, As and P or an amorphous silicon film. , W, Mo, Ta, T
Refractory metal film such as i, WSi ₂ , MoSi ₂ , TiSi ₂
, CoSi ₂ , NiSi, or other metal silicide, WN,
It can also be formed by a metal nitride such as TaN or TiN, or a laminated film thereof.

Further, in the present embodiment, B, P, As and the like have been described as examples of impurities introduced into the semiconductor layer, but the present invention is not limited to this, and various group III and V materials such as In and Sb can be used. Similarly, it can be introduced as a conductivity type impurity. Besides, various modifications can be made without departing from the scope of the present invention.

[0058]

According to the semiconductor device of the present invention, it is possible to easily suppress the characteristic variation due to the substrate floating effect without increasing the element area and reducing the film thickness of the semiconductor layer.

[Brief description of drawings]

1A is a plan view of an SOI semiconductor device according to the present embodiment, and FIG. 1B is a sectional view taken along the line AA ′ of FIG.

FIG. 2 is a process cross-sectional view showing a manufacturing process of the SOI semiconductor device according to the present embodiment.

FIG. 3 is a process cross-sectional view showing a manufacturing process of the SOI semiconductor device according to the present embodiment.

FIG. 4 is a process cross-sectional view showing a manufacturing process of the SOI semiconductor device according to the present embodiment.

FIG. 5 is a process cross-sectional view showing a manufacturing process of the SOI semiconductor device according to the present embodiment.

FIG. 6 is a process cross-sectional view showing a manufacturing process of the SOI semiconductor device according to the present embodiment.

FIG. 7 is a process cross-sectional view showing a manufacturing process of the SOI semiconductor device according to the present embodiment.

FIG. 8 is a cross-sectional view for explaining a substrate floating effect of an SOI type semiconductor device according to a conventional example.

9A is a plan view of a conventional SOI type semiconductor device for suppressing a substrate floating effect, and FIG. 9B is a cross-sectional view taken along line BB ′ of FIG. 9A. Is.

FIG. 10 is a plan view of an SOI type semiconductor device according to another conventional example for suppressing the substrate floating effect.

11A is a sectional view taken along the line CC ′ of FIG. 10, and FIG. 11B is a sectional view taken along the line DD ′ of FIG.

[Explanation of symbols]

1 ... Support substrate, 2 ... Embedded insulating film, 3 ... Semiconductor layer, 4
... element isolation insulating film, 5 ... gate insulating film, 6 ... gate electrode, 7 ... sidewall insulating film, 8 ... n-type semiconductor region,
9a, 9b ... N-type extension region, 10 ... Body region, 11 ... P-type semiconductor region, 12a, 12a, 12c
... silicide layer, 21 ... thermal oxide film, 22 ... protective film, 10
DESCRIPTION OF SYMBOLS 1 ... Support substrate, 102 ... Buried insulating film, 103 ... Semiconductor layer, 104 ... Source region, 105 ... Drain region, 1
06 ... Body region, 107 ... Gate insulating film, 108 ... Gate electrode, 109 ... Source electrode, 110 ... Drain electrode, 201 ... Support substrate, 202 ... Buried insulating film, 20
3 ... Semiconductor layer, 204 ... Element isolation insulating film, 205 ... Gate insulating film, 206, 206a ... Gate electrode, 207 ... Sidewall insulating film, 208, 208a, 208b ... N
N type extension regions, 210 ... body regions, 212a, 212b,
212c ... silicide layer, 213 ... n-type semiconductor region, 2
14 ... p-type semiconductor region, M ... groove, R ... resist mask.

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 4M104 AA01 AA09 BB01 BB02 BB14                       BB16 BB17 BB18 BB20 BB21                       BB25 BB26 BB28 BB30 BB32                       BB33 BB40 CC01 CC05 DD04                       DD16 DD37 DD43 DD55 DD64                       DD65 DD80 DD84 FF17 FF18                       GG09 GG10 GG14                 5F110 AA15 CC02 DD05 DD13 EE01                       EE04 EE05 EE08 EE09 EE14                       EE32 EE41 EE45 FF01 FF02                       FF03 FF04 FF09 FF23 GG02                       GG12 GG13 GG25 GG32 GG34                       GG36 GG37 GG52 HJ01 HJ13                       HJ14 HJ23 HK05 HK40 HL01                       HL03 HL04 HL11 HL23 HL24                       HM05 HM12 HM15 NN02 NN23                       NN35 NN62 NN65 QQ08 QQ11

Claims (5)

[Claims] 1. A semiconductor layer formed on an insulating film has a body region of a first conductivity type and a source region and a drain region of a second conductivity type, and the semiconductor device is provided between the source region and the drain region. A semiconductor device having a channel formed in a body region, wherein the source region is formed in the semiconductor layer to a depth that does not reach the embedded insulating film, and penetrates the source region to form the source region and the source region. A semiconductor device having a source electrode formed by being buried in the semiconductor layer so as to reach the body region between the buried insulating film. 2. The source electrode is formed by silicidizing the semiconductor layer so as to penetrate through the source region and reach the body region between the source region and the buried insulating film. Item 1. The semiconductor device according to item 1. 3. The semiconductor device according to claim 1, further comprising a first conductivity type semiconductor region formed between the source electrode and the body region and containing a first conductivity type impurity in a higher concentration than the body region. Semiconductor device. 4. The semiconductor device according to claim 1, wherein the drain region is formed to a depth reaching the buried insulating film. 5. The second conductivity type semiconductor region, wherein the drain region contains a second conductivity type impurity, is formed to a depth reaching the buried insulating film, and has a lower concentration than the second conductivity type semiconductor region. A low-concentration second-conductivity-type semiconductor region containing the second-conductivity-type impurity and formed to a depth that does not reach the buried insulating film. The semiconductor device according to claim 1, wherein the source region is formed by also forming.