JP2003324338A - Current clamp circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the temperature dependency of a clamp current. <P>SOLUTION: When the drain current ID of a MOSFET 15 increases and a detected voltage Va exceeds a reference voltage Vr, an operational amplifier 29 sucks a current ID corresponding to a voltage (Va-Vr) and a gate capacitor is charged with a current (Ig-Id). Consequently, the drain current ID is clamped to a clamp current ID(CL) corresponding to a reference current Ir. Resistances 17 and 25 are composed of resistance elements of the same kind and the temperature coefficient of the reference current Ir is nearly 0. In this case, resistance values Rs and Ron(s) are so set that (dRs/dT)×Ron(s)=(dRon(s)/dT)×Rs), where Rs is the resistance value of the resistance 17 and Ron(s) is the ON resistance value of the MOSFET 16. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an output MOSFE.
The present invention relates to a current clamp circuit that clamps a current flowing in T, and particularly to a current clamp circuit that detects a current by a detection MOSFET connected in parallel with the output MOSFET.

[0002]

FIG. 7 is a schematic view of Japanese Patent Laid-Open No. 10-
The electrical configuration of the load drive circuit disclosed in Japanese Patent No. 32475 is shown. The load drive circuit 1 shown in FIG.
Is an output MOSFET 3 that supplies current to the load 2.
And a detection MO connected in parallel with the MOSFET 3.
The SFET 4 is provided. The drains of these MOSFETs 3 and 4 are connected to each other, and the diode 5 of the illustrated polarity is connected between the gates of the MOSFETs 3 and 4.

Between the source of the MOSFET 4 and the ground and between the gate of the MOSFET 3 and the ground,
Transistors 6 and 7 forming the current mirror circuit 8 are connected to each other. The constant current circuit 9 operates so as to charge the gate capacitances of the MOSFETs 3 and 4 when a load drive command is issued. According to this configuration, since the temperature characteristics of the transistors 6 and 7 cancel each other out, the temperature dependence of the current limit value (clamp current) is higher than that of the load drive circuit used before the load drive circuit 1. Has a characteristic that becomes smaller.

However, while the temperature coefficient of the on-resistance of the MOSFETs 3 and 4 is positive, the temperature coefficient of the base-emitter voltage Vf of the transistor 6 is negative, so that the current flowing through the MOSFET 3 and the MOSFET 4 and the transistor 6 are negative. The ratio of the current flowing in the series circuit (shunt ratio) changes depending on the temperature. Therefore, it was not possible to further reduce the temperature dependence of the clamp current.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a current clamp circuit in which the temperature dependence of the clamp current is further reduced.

[0006]

According to the means described in claim 1, the detection MOSFET is provided with the output MOSFE.
A current that depends on the cell ratio flows with respect to the load current flowing through T. With this current, a detection voltage corresponding to the current flowing through the output MOSFET is generated in the detection resistance circuit. On the other hand, a reference voltage is generated in the reference resistance circuit by the reference current supplied from the reference current output circuit. Since the gate voltage limiting circuit limits the gate voltage of the output MOSFET and the detection MOSFET based on the detection voltage and the reference voltage, for example, when the load is short-circuited, the current flowing through the output MOSFET is equal to the reference voltage ( It is limited to the clamp current corresponding to the reference current).

This clamp current ID (CL) is the MO for detection.
The ON resistance value of the SFET is Ron (s), the resistance value of the detection resistance circuit is Rs, the resistance value of the reference resistance circuit is Rr, and the cell ratio N
If the shunt ratio determined more is M and the reference current is Ir, (R
r / Rs) · Ir · M. This clamp current ID (C
The differential of L) with the temperature T is dominated by the temperature differential term of the shunt ratio M because the temperature characteristics of the detection resistance circuit and the reference resistance circuit are close to each other and the temperature fluctuation of the reference current is small. Since the diversion ratio M is N · (1 + Rs / Ron (s)), the condition of dM / dT = 0 (dRs / dT)
Ron (s) = (dRon (s) / dT) .Rs. By setting the resistance values Rs and Rr so as to satisfy this relational expression, the temperature dependence of the clamp current can be further reduced as compared with the conventional current limiting circuit.

According to the second aspect of the invention, the voltage amplifier circuit of the operational amplifier used in the gate voltage limiting circuit has a one-stage configuration, and the open loop gain is set lower than that of the general-purpose operational amplifier. Accordingly, the primary pole is used as a circuit connected to the output of the operational amplifier, and the gate capacitance is positively used for phase compensation, whereby the clamp operation is stabilized. Further, a phase compensating capacitor is not required for the operational amplifier, and the chip area can be reduced and the cost can be reduced.

According to the means described in claim 3, when the current flowing through the output MOSFET is equal to or less than the clamp current when the load drive command is issued, the gate capacitances of the output MOSFET and the detection MOSFET are charged by a predetermined charging current. Then, these MOSFETs are turned on. On the other hand, when the current flowing through the output MOSFET exceeds the clamp current when the load drive command is issued, the gate voltage limiting circuit controls the discharge current according to the current deviation, so the current flowing through the output MOSFET matches the clamp current. To be controlled.

According to the means described in claim 4, since the voltage drop circuit for causing a voltage drop equal to the detection voltage is provided between the gate of the detection MOSFET and the gate of the output MOSFET, the detection MOSFET and Output MOS
The drain-source voltages of the FETs become equal and the operating points coincide. As a result, it is possible to reduce the error in the shunt ratio M and thus the error in the clamp current.

According to the means described in claim 5, since both the detection resistance circuit and the reference resistance circuit are composed of MOSFETs, both circuits have substantially equal temperature coefficients, and the temperature of the clamp current is substantially the same. The fluctuation can be further reduced.

According to the means described in claim 6, since the reference resistance circuit is composed of a plurality of cascade-connected MOSFETs, the resistance value of the reference resistance circuit can be increased, and the reference current output circuit. The reference current output by can be reduced.

According to the means described in claim 7, since the reference current output circuit is configured to generate the reference current based on the bandgap reference voltage, the temperature dependence of the reference current is small and the clamp current is small. The temperature fluctuation can be further reduced.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) A first embodiment of the present invention will be described below with reference to FIGS. FIG. 1 shows an electrical configuration of a load drive circuit including a current clamp circuit. The load drive circuit 11 shown in FIG. 1 is a vehicle (automobile) ECU (Electronic).
It is built in an IC 12 mounted in a c Control Unit) and drives a load 13 such as a relay coil or an LED provided in the vehicle. In the actual IC 12, a plurality of channels of load drive circuits 11 corresponding to the number of loads 13 to be driven are formed. The positive terminal and the negative terminal of the battery 14 are connected to the power terminal 12a and the ground terminal 12b of the IC 12, respectively, and the load 1 is provided between the power terminal 12a and the output terminal 12c of the IC 12.
3 is connected.

The load drive circuit 11 in the IC 12 is constructed as follows. Output terminal 12c and ground terminal 1
An N-channel MOSFET 15 (corresponding to an output MOSFET) is connected between 2b and 2b and constitutes a low side switch for the load 13. Further, an N channel type MOSF is provided between these terminals 12c and 12b.
A current detection means composed of a series circuit of an ET 16 (corresponding to a detection MOSFET) and a resistor 17 (corresponding to a detection resistance circuit) is connected. The gates of the MOSFETs 15 and 16 are connected to each other, and the MOSFETs 15 and 16 are connected in parallel. The MOSFETs 15 and 1
A gate protection circuit 20 in which zener diodes 18 and 19 are connected in series with opposite polarities is connected between the gate of 6 and the ground terminal 12b.

Regarding the number of cells indicating the drain area and the source area of the MOSFETs 15 and 16, the number of cells of the MOSFET 16 is, for example, 1/100 of the number of cells of the MOSFET 15.
(= 1 / N, N: cell ratio). As a result, the drain current of the MOSFET 16 is
It is almost 1/100 of the drain current ID of 15. Since the voltage across the resistor 17 is designed to be about 0.1 V when the drain current ID is the rated load current, the deviation of the shunt ratio due to the difference between the drain-source voltages of the FETs 15 and 16 is small. ing.

Power supply terminal 12a and MOSFETs 15 and 16
A constant current circuit 21 that outputs a charging current Ig to the gate capacitances of the MOSFETs 15 and 16, and
A switch circuit 22 that is turned on when the drive command signal Sa is at H level is connected in series. Also, power supply terminal 1
A constant current circuit 23 that outputs a reference current Ir (corresponding to a reference current output circuit) is provided between 2a and the ground terminal 12b.
A switch circuit 24 that is turned on when the drive command signal Sa is at H level and a resistor 25 (corresponding to a reference resistance circuit) are connected in series. Here, the resistors 17 and 25 are composed of the same type of resistive elements, and the constant current circuit 23
Generates a reference current Ir having a small temperature coefficient based on the bandgap reference voltage.

A resistor 26 and a switch circuit 27 are connected in series between the gates of the MOSFETs 15 and 16 and the ground terminal 12b in order to discharge the gate charge. The switch circuit 27 is turned on when the drive prohibition signal Sb obtained by inverting the drive command signal Sa by the inverter 28 is at the H level.

In the IC 12, from the voltage VB (battery voltage) at the terminal 12a to the control power supply voltage Vcc (for example, 5V).
A power supply circuit (not shown) for generating is generated, and the operational amplifier 29 (corresponding to a gate voltage limiting circuit) is operated by receiving the supply of the power supply voltage Vcc. The non-inverting input terminal of the operational amplifier 29 has a switch 24 and a resistor 2
It is connected to the common connection point with 5, and the inverting input terminal is MOSF
It is connected to a common connection point between the source of the ET 16 and the resistor 17. The output terminal of the operational amplifier 29 is a MOSF.
It is connected to the gates of ET15 and ET16. The current clamp circuit 30 includes the MOSFET 16 and the resistor 1 described above.
7, a constant current circuit 23, a switch circuit 24, a resistor 25, and an operational amplifier 29.

FIG. 2 shows a detailed electrical configuration of the operational amplifier 29. A differential amplifier circuit 38 including transistors 33 to 36 and a constant current circuit 37 is formed between the power supply line 31 that supplies the power supply voltage Vcc and the ground line 32. A level shift transistor 39 is provided between the differential input transistor 33 and the non-inverting input terminal and between the differential input transistor 34 and the inverting input terminal, respectively.
And 40 are connected, and constant current circuits 41 and 42 are connected between the power supply line 31 and the emitters of the transistors 39 and 40, respectively.

Transistors 35 and 43, transistors 46 and 47, and power supply line 3 which are grounded to the ground line 32.
Transistors 44 and 45, which are grounded to 1, constitute current mirror circuits 48, 50 and 49, respectively. The collector of the transistor 47 at the final stage is connected to the output terminal, and the current mirror circuits 49 and 50 have n transistors, respectively.
Double and m-fold current amplification is performed. When the differential amplifier circuit 38 is balanced, the output current Is of the constant current circuit 37 flows equally divided into the transistors 33 and 34,
The following equation (1) is established. m · n · Is / 2 = Ig (1)

As described above, in the operational amplifier 29 used in this embodiment, the voltage amplifying stage is composed of only one stage of the differential amplifying circuit 38, and there is no phase compensating capacitor in the circuit. The open loop gain is suppressed to be lower than that of a general-purpose ordinary operational amplifier (for example, about 1/2 in decibel), and the frequency characteristic (cutoff frequency) is increased. . The reason for using such an operational amplifier 29 is as follows.

That is, a general-purpose ordinary operational amplifier has, for example, two voltage amplifying stages, and the gain and the phase compensating capacitor set a large time constant of the primary pole of the differential pair for phase compensation. Is going. However, when this operational amplifier is used in this embodiment, the MOSFET 15
Since the gate capacitance of 16 is used as a load, the time constant of the secondary pole approaches the primary pole, contrary to the idea of pole separation, and the phase margin decreases. Therefore, a circuit in which the primary pole is connected to the output of the operational amplifier 29 by adopting the operational amplifier 29 having the above configuration (collector circuit of the transistor 47, that is, MOS circuit)
FETs 15 and 16 are used as gates), and the gate capacitance is positively used for phase compensation to stabilize the clamp operation.

Next, the operation of this embodiment will be described. When the drive command signal Sa is at the L level (OFF command), the switch circuits 22 and 24 are turned off, the switch circuit 27 is turned on, and the gate voltage VGS becomes 0V.
T15 and T16 are turned off. When the drive command signal Sa changes to the H level (ON command) from this state, the switch circuits 22 and 24 are turned on, the switch circuit 27 is turned off, and the charging current Ig flows from the constant current circuit 21 to the gate capacitance. As a result, the gate voltage VGS changes to the gate protection circuit 2
The protection voltage rises to 0, and the MOSFETs 15 and 16 are turned on in the linear region. Further, the reference voltage Vr is generated across the resistor 25.

When the load 13 is short-circuited or the voltage VB rises during the driving of the load, the drain current ID of the MOSFET 15 increases. When the voltage across the resistor 17 (hereinafter, referred to as the detection voltage Va) exceeds the voltage across the resistor 25 (reference voltage Vr), the operational amplifier 29 outputs (V
The current Id corresponding to the voltage of a-Vr) is output (sucked). By the feedback control by the operational amplifier 29, the gate capacitance is charged by the current (Ig-Id), so that the detection voltage Va and the reference voltage Vr match, in other words, the drain current I of the MOSFET 15.
The gate voltage VGS is controlled so that D is clamped to the clamp current ID (CL) corresponding to the reference current Ir. At this time, the MOSFETs 15 and 16 are turned on in the saturation region.

Next, the temperature characteristics of the clamp current ID (CL) of the MOSFET 15 will be described with reference to FIGS. 3 and 4. FIG. 3 shows an equivalent circuit of a circuit portion including the MOSFETs 15 and 16 and the resistor 17. The symbols used in this equivalent circuit and in the following description are as follows. Ron (m) ... ON resistance value of MOSFET 15 Ron (s) ... ON resistance value of MOSFET 16 Rs ... Resistance value of resistor Rr ... Resistance value of resistor 25 M ... Diversion ratio (= ID (MOSFET15) / ID (MOSFET16))

While the clamp operation by the operational amplifier 29 is being performed, the following expression (2) is established. Rs · ID (CL) / M = Rr · Ir (2) From this equation (2), the clamp current ID (CL) is derived as in the following equation (3). ID (CL) = (Rr / Rs) · Ir · M (3)

Resistors 17 and 2 composed of the same type of resistive elements
Since 5 has the same temperature coefficient and the temperature coefficient of the reference current Ir is almost 0, the following expressions (4) and (5) are established for the differentiation of the temperature T. d (Rr / Rs) / dT = 0 (4) dIr / dT = 0 (5)

As a result, the temperature differential of the clamp current ID (CL) is expressed by the following equation (6). dID (CL) / dT = (Rr / Rs) .Ir.dM / dT (6) Here, the diversion ratio M is expressed by the following equation (7) from the equivalent circuit shown in FIG.

M = N · (1 + Rs / Ron (s)) (7) However, N = Ron (s) / Ron (m) From this, the temperature differential of the diversion ratio M is expressed by the following equation (8). become. dM / dT = N. ((dRs / dT) .Ron (s)-(dRon (s) / dT) .Rs) / Ron (s) ² (8)

In order to make the temperature differential of the clamp current ID (CL) to 0, dM / dT = 0 is set, and as a result, the following relational expression (9) is obtained. (DRs / dT) .Ron (s) = (dRon (s) / dT) .Rs (9) Therefore, if the formulas (4) and (5) are satisfied, the formula (9) is satisfied. Resistance value Rs of resistor 17 and MOSFET1
By setting the on-resistance value Ron (s) of 6, the temperature coefficient of the clamp current ID (CL) can be reduced.

FIG. 4 shows the temperature of the clamp current ID (CL) when CrSi resistors (temperature coefficient = 100 ppm / ° C.) and diffusion resistors (temperature coefficient = 2540 ppm / ° C.) are used for the resistors 17 and 25. It is a simulation result which shows a characteristic. The horizontal axis represents the ambient temperature Ta [° C]. The temperature coefficient of the ON resistance of the MOSFET 16 is 4000.
Since it is ppm / ℃, when using diffusion resistance (9)
Ron (s) / Rs satisfying the formula is calculated as follows. Ron (s) / Rs = (dRon (s) / dT) / (dRs / dT) = 4000/2540 = 1.6

Therefore, in FIG. 4, a simulation was performed under the following conditions based on the above calculation results. Ron (s) /Rs=1.6 Rs = 100Ω Rr = 3 kΩ Ir = 100 μA N = 1325

As a result, when diffusion resistors are used for the resistors 17 and 25, the temperature change from -40 ° C to 25 ° C, 2
Clamp current ID for temperature change from 5 ℃ to 150 ℃
Temperature coefficient of (CL) is -71ppm / ℃, -47p
It was pm / ° C, and a sufficient improvement effect could be confirmed. On the other hand, since the temperature coefficient of CrSi resistance is as low as 100 ppm / ° C., when CrSi resistance is used for the resistors 17 and 25, a sufficient improvement effect does not appear if simulation is performed under the same conditions. However, if Ron (s) / Rs is set so as to satisfy the equation (9) for CrSi resistance,
The same effect can be obtained.

As described above, according to the load drive circuit 11 of the present embodiment, when the load 13 is short-circuited, the current clamp circuit 30 changes the drain current ID of the MOSFET 15 into the clamp current ID (CL). Since the clamp is performed, the MOSFET 15 and the load 13 can be protected from overheating or destruction due to overcurrent.

In the current clamp circuit 30, the detection resistor 17 and the reference resistor 25 are composed of the same type of resistance element, and the constant current circuit 23 is a circuit having a small temperature dependence. ) So that the resistance value Rs of the resistor 17 and the on-resistance value Ron of the MOSFET 16 are
Since (s) is set, the temperature dependence of the clamp current ID (CL) becomes very small. Therefore, the current clamp circuit 3
0 is a circuit suitable for the load drive circuit 11 used in the vehicle ECU in which the temperature easily changes over a wide range.

Further, the current clamp circuit 30 has only one stage of voltage amplifying circuit to suppress the open loop gain, and the MOSF
An operational amplifier 29 having a configuration in which the gate capacitances of the ETs 15 and 16 are positively used for phase compensation is used. This eliminates the need for a phase compensation capacitor in the operational amplifier 29,
In particular, when the multi-channel load drive circuit 11 is formed in the IC 12, the effect of reducing the chip area becomes large, and the cost can be reduced accordingly.

Further, the detection voltage V generated in the resistor 17
Since a and the reference voltage Vr generated in the resistor 25 are input to the operational amplifier 29 using the level shift circuit including the PNP transistors 39 and 40 in the input section, the reference voltage Vr is lowered to about 0.1V. Even if set, it can operate. As a result, the drains of MOSFETs 15 and 16
Since the voltages between the sources are substantially equal to each other, it is possible to reduce the error of the shunt ratio M and the error of the clamp current ID (CL).

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIGS. 5 and 6, the same components as those in FIGS. 1 and 2 are denoted by the same reference numerals, and different components will be described here.

The load drive circuit 51 shown in FIG. 5 is built in the IC 52, and the clamp operation signal Sc which becomes H level during the clamp operation is output to the terminal 52d thereof. In the current clamp circuit 53, MO
Between the source of the SFET 16 and the ground terminal 52b, an N-channel type MOSFE functioning as a detection resistor.
T54 is connected, and N-channel MOSFETs 55, 56, 57 functioning as reference resistors are cascade-connected between the switch circuit 24 and the ground terminal 52b. These MOSFETs 54 to 57 have the same size, and their gates are commonly connected. Power terminal 52
Between a and the common gate, a constant current circuit 58,
A switch circuit 59 that is turned on when the drive command signal Sa is at H level is connected in series.

Gate of MOSFET 16 and MOSFET
A resistor 60 (corresponding to a voltage drop circuit) is connected to the gate of 15. This resistor 60 is a MOSFET
It is provided in order to compensate the drain-source voltage difference between 15 and 16, and the resistance value Rg is MOSFET.
If the combined ON resistance of 55 to 57 is Rr, the following (10)
It is set to the value shown in the formula. Rg = Rr · Ir / Ig (10)

The operational amplifier 61 (corresponding to a gate voltage limiting circuit) operates by receiving the power supply voltage Vcc, and its non-inverting input terminal is connected to the drain of the MOSFET 55.
The inverting input terminal is connected to the drain of the MOSFET 54. Further, the operational amplifier 61 outputs the above-mentioned clamp operation signal Sc, and the buffer circuit 62 is connected between the signal output terminal and the terminal 52d.

FIG. 6 shows a detailed electrical configuration of the operational amplifier 61. The transistors 36 and 63 form a current mirror circuit 64, and the collector of the transistor 63 is a signal output terminal of the clamp operation signal Sc and is connected to the power supply line 31 via the constant current circuit 65. A resistor 66 and a transistor 67 are connected between the common base of the transistors 44 and 45 and the ground line 32, and these transistors 44, 45 and 6 are connected.
A current mirror circuit 68 is configured by 7 and the resistor 66. Similarly, the power line 31 and the transistors 46, 4
Resistor 69 and transistor 7 between the common base of 7
0 is connected to these transistors 46, 47,
A current mirror circuit 71 is configured by 70 and the resistor 69.

Between the power line 31 and the ground line 32,
The transistor 73 and the diode-connected transistors 74 and 75 are connected in series. Transistor 7
The base and emitter of the transistor 72 are connected between the collectors of the transistors 3, 74 and the collector of the transistor 47, and the collector of the transistor 72 is connected to the output terminal of the operational amplifier 61.

Since the basic operation of the current clamp circuit 53 of this embodiment is similar to that of the current clamp circuit 30 described in the first embodiment, the same operation and effect as those of the first embodiment can be obtained. it can. Since the resistor 60, which is the voltage drop circuit, is provided in the present embodiment, the drain-source voltages of the MOSFETs 15 and 16 become equal during the clamp operation, the operating points of the MOSFETs 15 and 16 coincide, and the error of the shunt ratio M increases. Can be reduced.

Further, since the detection resistance circuit and the reference resistance circuit both utilize the on resistance of the MOSFET, both circuits have substantially equal temperature coefficients, so that the clamp current ID (CL) changes with temperature. It can be further reduced. Then, the on-resistance Rs of the MOSFET 54 and the MOSFET
Since the on-resistance Ron (s) of 16 has an approximate temperature coefficient, the on-resistance Rs and Ron (s) required to set dM / dT = 0 are calculated according to the above equation (9). It can be set to almost the same value, which is suitable for actual design. Further, since the MOSFETs 55 to 57 are connected in cascade to increase the resistance value Rr of the reference resistor, the reference current Ir can be reduced and the current consumption can be reduced.

Since the operational amplifier 61 is configured to output the clamp operation signal Sc indicating that the clamp operation is in progress, other control circuits detect the state of the load drive circuit 51 or the load 13 by referring to the clamp operation signal Sc. It becomes possible to do. Further, since the base current supply circuit is added to the current mirror circuits 68 and 71 of the operational amplifier 61, the accuracy of the current amplification degree can be improved. Furthermore, the transistors 73 to 75 are provided at the output of the operational amplifier 61.
Is added, the Early effect of the transistor 47 is suppressed.

(Other Embodiments) The present invention is not limited to the embodiments described above and shown in the drawings, and can be modified or expanded as follows, for example.
Compared to the first embodiment, the power supply terminal 12a and the output terminal 12
It is also possible to adopt a circuit configuration of a high-side switch in which a MOSFET is connected between the output terminal 12c and the ground terminal 12b and a load 13 is connected between the output terminal 12c and the ground terminal 12b. The same applies to the second embodiment.

If an increase in chip area is permitted, a general-purpose operational amplifier having a phase compensation capacitor may be used instead of the operational amplifiers 29 and 61. The voltage drop circuit is
A diode may be used instead of the resistor.
Constant current circuit 23 for driving the gates of MOSFETs 15 and 16
However, instead of this, a circuit that outputs a voltage may be used.

The present invention is premised on that the detection resistance circuit and the reference resistance circuit have similar temperature characteristics and that the temperature fluctuation of the reference current is small. However, when these conditions cannot be satisfied, the temperature differential of the clamp current ID (CL) shown in the equation (3) is d (Rr / Rs) /
It suffices to derive the differentiation result in consideration of dT and dIr / dT and set each resistance value based on the derived result.

[Brief description of drawings]

FIG. 1 is an electrical configuration diagram of a load drive circuit showing a first embodiment of the present invention.

FIG. 2 is a detailed electrical configuration diagram of an operational amplifier.

FIG. 3 is an equivalent circuit diagram of a circuit portion including MOSFETs 15 and 16 and a resistor 17.

FIG. 4 is a diagram showing temperature characteristics of clamp current ID (CL).

FIG. 5 is a view corresponding to FIG. 1 showing a second embodiment of the present invention.

FIG. 6 is a view corresponding to FIG.

FIG. 7 is a diagram corresponding to FIG. 1 showing a conventional technique.

[Explanation of symbols]

15 is a MOSFET (output MOSFET), 16 is an M
OSFET (detection MOSFET), 17 is a resistance (detection resistance circuit), 23 is a constant current circuit (reference current output circuit), 25 is a resistance (reference resistance circuit), 29 and 61 are operational amplifiers (gate voltage limiting circuit) , 30 and 53 are current clamp circuits, 54 is a MOSFET (detection resistance circuit),
55, 56 and 57 are MOSFETs (reference resistance circuits),
Reference numeral 60 is a resistor (voltage drop circuit).

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5J030 CB07 CC03 CC06                 5J055 AX15 AX34 AX64 BX16 CX13                       DX13 DX22 DX54 DX55 EX01                       EX10 EY01 EY13 EY21 EZ04                       EZ07 EZ09 EZ11 EZ16 EZ51                       FX04 FX19 FX32 GX01 GX06

Claims (7)

[Claims] 1. An output MOSFE for supplying a current to a load.
It has a predetermined cell ratio to T and its output MO
A detection MOSFET connected in parallel with the SFET and having gates connected to each other, a detection resistance circuit connected in series with the detection MOSFET, and a reference resistance circuit having temperature characteristics similar to those of the detection resistance circuit. A reference current output circuit for supplying a reference current having a small temperature fluctuation to the reference resistance circuit, and a detection voltage generated in the detection resistance circuit and a reference voltage generated in the reference resistance circuit. A gate voltage limiting circuit for limiting the gate voltage of the output MOSFET and the detection MOSFET, wherein the ON resistance value Ron (s) of the detection MOSFET and the resistance value Rs of the detection resistance circuit are (dRs / dT ) ・ Ron (s) = (dRon (s) / dT) ・ Rs However, d / dT must be set to a value that satisfies the relational expression of differential calculation by temperature. Current clamp circuit according to claim. 2. The gate voltage limiting circuit, wherein the voltage amplifying circuit has a one-stage configuration, the open loop gain is set lower than that of a commonly used operational amplifier, and there is no phase compensation capacitor in the circuit. The current clamp circuit according to claim 1, wherein the current clamp circuit is configured by an operational amplifier, and the phase compensation is executed by the gate capacitances of the output MOSFET and the detection MOSFET connected to the output terminal of the operational amplifier. 3. The output MOSFE when a load drive command is issued.
The gate capacitances of the T and the detection MOSFET are configured to be charged by a predetermined charging current, and the gate voltage limiting circuit includes the output MOSFET and the detection MOSFET when the detection voltage exceeds the reference voltage. The current clamp circuit according to claim 1 or 2, wherein the current clamp circuit is configured to control a discharge current from a gate capacitance of the MOSFET for use. 4. A voltage drop circuit for producing a voltage drop equal to the detection voltage is provided between the gate of the detection MOSFET and the gate of the output MOSFET. The current clamp circuit according to any one of claims. 5. The current clamp circuit according to claim 1, wherein the detection resistance circuit and the reference resistance circuit are configured by MOSFETs. 6. The current clamp circuit according to claim 5, wherein the reference resistance circuit includes a plurality of MOSFETs connected in cascade. 7. The current clamp circuit according to claim 1, wherein the reference current output circuit is configured to generate a reference current based on a bandgap reference voltage.