JP2003322876A - Liquid crystal display - Google Patents

Abstract

(57) Abstract: A waveform delay generated in a video signal supplied to a drain signal line is suppressed. SOLUTION: A plurality of gate signal lines arranged in parallel and a plurality of gate signals arranged in parallel to intersect with these gate signal lines are formed on a liquid crystal side surface of one of the substrates opposed to each other with a liquid crystal interposed therebetween. A drain signal line is formed, and a switching element that is activated by a scanning signal from the gate signal line and a video signal from the drain signal line are supplied to the pixel region surrounded by each signal line via the switching element. A pixel electrode, and a counter electrode to which a reference signal is supplied to the pixel electrode.
The counter electrode is formed above the gate signal line with an insulating film interposed therebetween, and the counter electrode includes one formed so as to be superposed on the drain signal line with a second insulating film interposed therebetween. In the region where the drain signal line is formed, at least the region excluding the intersection with the gate signal line has a removed portion.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device called a lateral electric field type.

[0002]

2. Description of the Related Art A liquid crystal display device called a horizontal electric field type is
A pixel electrode and a counter electrode for generating an electric field between the pixel electrode and the pixel electrode on the liquid crystal side surface of one of the substrates arranged to face each other through the liquid crystal are provided. The liquid crystal behaves by the parallel components. Then, an application of such a structure to an active matrix type is such that a plurality of gate signal lines arranged in parallel with each other on the liquid crystal side surface of the one substrate are crossed with each other. Each region surrounded by a plurality of drain signal lines arranged in parallel is defined as the pixel region. Then, in each of these pixel regions, a switching element operated by a scanning signal from the gate signal line, the pixel electrode to which a video signal from the drain signal line is supplied via the switching element, and the video signal The counter electrode is supplied with a reference signal.

Here, the pixel electrode and the counter electrode are formed as a strip-shaped pattern extending in one direction, and the electrodes are usually arranged alternately.

Further, in such a structure, the counter electrode is formed on the upper surface of the insulating film which is formed so as to cover the drain signal line, and the central axis of the drain signal line and the central axis of the drain signal line are substantially aligned with each other. A structure having a width larger than the width and formed along the drain signal line is also known. This is because it is easy for the line of electric force from the drain signal line to terminate at the counter electrode thereabove and to prevent termination at the pixel electrode. This is because if the lines of electric force terminate at the pixel electrode, it becomes noise.

Each counter electrode is formed in the same layer as and integrally with the counter voltage signal line formed on the upper surface of the insulating film formed so as to cover the gate signal line as well, and via the counter voltage signal line. A reference signal is supplied to each counter electrode.

[0006]

However, in the liquid crystal display device having such a structure, a parasitic capacitance is formed between the drain signal line and the counter electrode, and the parasitic capacitance forms a video signal supplied to the drain signal line. It has been pointed out that waveform delay is likely to occur. The waveform delay of such a video signal has become a problem to be solved with the recent trend toward higher definition of liquid crystal display devices. The present invention has been made in view of such circumstances, and an object thereof is to provide a liquid crystal display device in which a waveform delay occurring in a video signal supplied to a drain signal line is suppressed.

[0007]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows. Means 1. In the liquid crystal display device according to the present invention, for example, a plurality of gate signal lines juxtaposed to each other on the liquid crystal side surface of one of the substrates opposed to each other with the liquid crystal interposed therebetween and the gate signal lines intersecting with the gate signal lines. A plurality of drain signal lines arranged in parallel are formed, and in a pixel region surrounded by each of these signal lines, a switching element that operates by a scanning signal from the gate signal line and a drain signal line through the switching element And a counter electrode to which a reference signal is supplied to the pixel electrode. The drain signal line is formed above the gate signal line via the first insulating film. And the counter electrode is formed so as to be overlapped with the drain signal line via a second insulating film, and the first insulating film is formed on the drain signal line. A region excluding the intersection of at least the gate signal line A is and is characterized by having a removed portion.

Means 2. The liquid crystal display device according to the present invention is, for example, on the premise of the constitution of means 1, characterized in that the counter electrode is formed integrally with the same material layer formed above the gate signal line. .

Means 3. The liquid crystal display device according to the present invention is, for example, on the premise of the constitution of the means 2, characterized in that the counter electrode and the same material layer formed integrally with the counter electrode are formed of a translucent conductive material. Is.

Means 4. In the liquid crystal display device according to the present invention, a plurality of gate signal lines arranged in parallel and a plurality of gate signal lines arranged in parallel to each other are arranged on the liquid crystal side surface of one of the substrates opposed to each other with the liquid crystal interposed therebetween. A plurality of drain signal lines are formed, and in the pixel region surrounded by these signal lines,
An electric field is formed between a switching element that operates by a scanning signal from the gate signal line, a pixel electrode to which a video signal from the drain signal line is supplied via this switching element, and the pixel electrode that is connected to the counter voltage signal line. And a counter electrode for causing the drain signal line to be
The drain signal line is formed in a layer above the gate signal line and the counter voltage signal line formed in the same layer as the gate signal line through an insulating film, and the counter electrode is formed through a second insulating film in the drain signal line. The first insulating film is formed in a region where the drain signal line is formed and at least a region except each intersection with the gate signal line and the counter voltage signal line has a removed portion. It is characterized by having.

Means 5. In the liquid crystal display device according to the present invention, for example, the counter electrode is formed integrally with the same material layer formed above the gate signal line and the counter voltage signal line based on the configuration of the means 4, and The counter voltage signal line is electrically connected to the counter voltage signal line through a through hole formed in the second insulating film and the first insulating film.

Means 6. The liquid crystal display device according to the present invention is, for example, on the premise of the constitution of the means 5, characterized in that the counter electrode and the same material layer integrally formed with the counter electrode are formed of a translucent conductive material. Is.

Means 7. The liquid crystal display device according to the present invention is, for example, on the premise of the constitution of means 1 or 4, characterized in that the second insulating film is constituted by a protective film made of an organic material.

Means 8. In the liquid crystal display device according to the present invention, for example, on the premise of the configuration of the means 1 or 4, the second insulating film is formed of a sequentially laminated body of a protective film made of an inorganic material and a protective film made of an organic material. It is characterized by.

The present invention is not limited to the above construction,
Various modifications can be made without departing from the technical idea of the present invention.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a liquid crystal display device according to the present invention will be described below with reference to the drawings. << Overall Configuration >> FIG. 2 is a configuration diagram showing an embodiment of a liquid crystal display device according to the present invention. Although this figure is shown as an equivalent circuit diagram, it is drawn corresponding to the actual geometrical arrangement.
In the figure, there are a pair of transparent substrates SUB1 and SUB2 arranged to face each other with a liquid crystal interposed therebetween, and the liquid crystal is sealed by a seal material SL which also fixes one transparent substrate SUB1 to the other transparent substrate SUB2. The one transparent substrate SUB1 surrounded by the sealing material SL
The gate signal line GL extending in the x direction and juxtaposed in the y direction and the drain signal line DL extending in the y direction and juxtaposed in the x direction are formed on the liquid crystal side surface of the. . A region surrounded by each gate signal line GL and each drain signal line DL constitutes a pixel region, and a matrix-shaped aggregate of these pixel regions constitutes a liquid crystal display section AR.

A common counter voltage signal line CL running in each pixel region is formed in each of the pixel regions arranged in parallel in the x direction. The counter voltage signal line CL serves as a signal line for supplying a reference voltage for a video signal to a counter electrode CT described later in each pixel region.

In each pixel region, a thin film transistor TFT operated by a scanning signal from the gate signal line GL on one side thereof and a pixel electrode to which a video signal from the drain signal line DL on one side is supplied via the thin film transistor TFT. PX is formed. The pixel electrode PX generates an electric field between the pixel electrode PX and the counter electrode CT connected to the counter voltage signal line CL, and the light transmittance of the liquid crystal is controlled by this electric field.

One end of each of the gate signal lines GL extends beyond the seal material SL, and the extended end constitutes a terminal GLT to which the output terminal of the vertical scanning drive circuit V is connected. There is. Further, a signal from a printed circuit board arranged outside the liquid crystal display panel is inputted to an input terminal of the vertical scanning drive circuit V.

The vertical scanning drive circuit V comprises a plurality of semiconductor devices, a plurality of gate signal lines adjacent to each other are grouped, and one semiconductor device is applied to each of these groups. There is.

Similarly, one end of each of the drain signal lines DL extends beyond the sealing material SL, and the extended end constitutes a terminal DLT to which the output terminal of the video signal drive circuit He is connected. It has become. Further, a signal from a printed circuit board arranged outside the liquid crystal display panel is input to the input terminal of the video signal drive circuit He. The video signal drive circuit He is also composed of a plurality of semiconductor devices, and a plurality of drain signal lines adjacent to each other are grouped, and one semiconductor device is assigned to each of these groups.

Further, the respective counter voltage signal lines CL are commonly connected, for example, at the end portion on the right side in the figure, and the connecting line extends beyond the sealing material SL, and the terminal C is provided at the extending end.
Constitutes the LT. From this terminal CLT, a reference voltage for the video signal is supplied.

One of the gate signal lines GL is sequentially selected by a scanning signal from the vertical scanning driving circuit V.

A video signal is supplied to each of the drain signal lines DL by a video signal drive circuit He at the timing of selecting the gate signal line GL.

In the above-described embodiment, the vertical scanning drive circuit V and the video signal drive circuit He are the transparent substrate SUB1.
1 shows a semiconductor device mounted on the semiconductor device, the semiconductor device may be a so-called tape carrier type semiconductor device which is connected across the transparent substrate SUB1 and the printed circuit board. When the layer is made of polycrystalline silicon (p-Si), the semiconductor element made of polycrystalline silicon may be formed on the surface of the transparent substrate SUB1 together with the wiring layer.

<< Pixel Structure >> FIG. 1 is a plan view showing an embodiment of the structure of each pixel region. 3 is a sectional view taken along line III-III of FIG. 1, and FIG.
The sectional view in the IV line is shown.

First, on the liquid crystal side surface of the transparent substrate SUB1,
A pair of gate signal lines GL extending in the x direction and juxtaposed in the y direction are formed. These gate signal lines GL surround a rectangular area together with a pair of drain signal lines DL described later, and this area is configured as a pixel area.

Further, an opposed voltage signal line CL1 extending between the gate signal lines GL, that is, substantially in the center of the pixel region in the x direction is formed. This counter voltage signal line CL
1 is formed at the same time when the gate signal line GL is formed, for example.

On the surface of the transparent substrate SUB1 on which the gate signal lines GL and the counter voltage signal lines CL1 are formed in this way, an insulating film GI (see FIGS. 3 and 4) made of, for example, SiN is formed on the surfaces of the gate signal lines GL and the like. It is also formed by covering. The insulating film GI functions as an interlayer insulating film for the gate signal line GL and the counter voltage signal line CL1 in the formation region of the drain signal line DL described later, and its gate insulation film in the formation region of the thin film transistor TFT described later. It has a function as.

Here, the insulating film GI has an opening HOL in a part of a formation region of a drain signal line DL described later.
Are formed, and the details of the opening HOL will be described later. Then, a semiconductor layer AS made of, for example, amorphous Si is formed on the surface of the insulating film GI in a region overlapping with part of the gate signal line GL.

This semiconductor layer AS is a thin film transistor T.
By forming the drain electrode SD1 and the source electrode SD2 on the upper surface of the FT, the MIS (met with the inverted stagger structure in which a part of the gate signal line serves as the gate electrode is formed.
al insulator semiconductor) type transistors can be configured.

Here, the drain electrode SD1 and the source electrode SD2 are formed at the same time when the drain signal line DL is formed. That is, the drain signal line DL extending in the y direction and juxtaposed in the x direction is formed, and a part of the drain signal line DL extends to the upper surface of the semiconductor layer AS to form the drain electrode SD1. A source electrode SD2 is formed apart from the electrode SD1 by the channel length of the thin film transistor TFT.

Here, a part of the drain signal line DL is formed so as to run inside the opening HOL formed in the insulating film GI, that is, on the surface of the transparent substrate SUB1 exposed from the opening HOL. It has become so. That is, the drain signal line DL is interlayer-insulated by the insulating film GI and the gate signal line GL and the counter voltage signal line CL at a portion intersecting with the gate signal line GL and the counter voltage signal line CL, and other portions are provided. The part runs in the opening HOL where the insulating film GI is removed. The reason for doing this is that the drain signal line D
This is because a large part of L is formed as close to the transparent substrate SUB1 as possible to reduce a parasitic capacitance generated between the transparent substrate SUB1 and a counter electrode CT described later. This will be described in more detail later.

The source electrode SD2 is formed integrally with the pixel electrode PX formed in the pixel region. That is, the pixel electrode PX is composed of a plurality (two in the figure) of electrode groups which extend in the pixel region in the y direction and are arranged in parallel in the x direction. One of the ends of one pixel electrode PX also serves as the source electrode SD2. further,
The pixel electrodes PX can be electrically connected to each other above the counter voltage signal line CL.

As described above, the thin film transistor TFT, the drain signal line DL, the drain electrode SD1, the source electrode SD
2 and the transparent substrate SUB1 on which the pixel electrode PX is formed
A protective film is formed on the surface of the. This protective film is a film for avoiding direct contact with the liquid crystal of the thin film transistor TFT, and is designed to prevent characteristic deterioration of the thin film transistor TFT. In this case, this protective film
For example, the protective film PAS made of an inorganic material such as SiN and the protective film OPAS made of an organic material such as a resin are sequentially laminated. The reason why at least the organic material layer is used as the protective film is to reduce the dielectric constant of the protective film itself.

A counter electrode CT is formed on the upper surface of the protective film PAS. This counter electrode CT is the above-mentioned pixel electrode PX.
Similarly, a plurality of (three in the figure) electrode groups extending in the y direction and juxtaposed in the x direction are formed, and each of the electrodes has a space between the pixel electrodes PX when viewed in plan. It can be positioned as. That is, the counter electrode CT
And the pixel electrode PX from the drain signal line DL on one side to the drain signal line DL on the other side.
T, pixel electrode PX, counter electrode CT, pixel electrode PX, ...
The counter electrodes CT are arranged at equal intervals in this order.

Here, the counter electrodes CT positioned on both sides of the pixel region are formed so that a part thereof is overlapped with the drain signal line DL, and are formed in common with the corresponding counter electrodes CT of the adjacent pixel regions. Has been done. In other words, the counter electrode CT is overlapped on the drain signal line DL with their central axes substantially aligned with each other, and the width of the counter electrode CT is formed larger than that of the drain signal line DL.
The counter electrode CT on the left side of the drain signal line DL constitutes one of the counter electrodes CT of the left pixel area, and the counter electrode CT of the right side constitutes one of the counter electrodes CT of the right pixel area. It is like this.

By thus forming the counter electrode CT having a width wider than the drain signal line DL above the drain signal line DL, the line of electric force from the drain signal line DL terminates at the counter electrode CT. However, it is possible to avoid the termination of the pixel electrode PX. Drain signal line D
This is because when the electric force line from L terminates in the pixel electrode PX, it becomes noise.

Here, the pixel electrode PX and the counter electrode CT
Each have a V shape having a bent portion on the counter voltage signal line CL1 and employ a so-called multi-domain method.

That is, even when the liquid crystal has the same molecular arrangement, the polarization state of the transmitted light changes depending on the incident direction of the light incident on the liquid crystal display panel, so that the light transmittance varies depending on the incident direction. . The viewing angle dependency of such a liquid crystal display panel causes a phenomenon of brightness inversion when the viewpoint is inclined with respect to the viewing angle direction, and has a display characteristic that an image is colored in the case of color display.

Therefore, the pixel electrode is formed into a pattern in which at least one bent portion is formed in the extending direction thereof, and the counter electrode is formed in a shape obtained by shifting this pattern in parallel, and the bent points of these electrodes are connected. The direction of the electric field acting between the electrodes is made different in one area and the other area with the virtual line as a boundary, thereby compensating the coloring of the image depending on the viewing angle.

The drain signal line DL has the same shape as the shape of each of these electrodes.

Each counter electrode CT composed of an electrode group is formed integrally with the material layer made of the same material so as to cover the gate signal line GL and the counter voltage signal line CL1 sufficiently.

Each counter electrode CT and the material layer formed integrally therewith are, for example, ITO (Indium Tin Oxide), ITZO (In
dium Tin Zinc Oxide), IZO (Indium Zinc Oxide), Sn
It is formed of a light-transmitting conductive layer such as O ₂ (tin oxide) or In ₂ O ₃ (indium oxide). Since these conductive layers themselves are materials having a relatively large electric resistance, the pattern as described above has the effect of reducing the overall electric resistance. Then, the counter voltage signal line CL
1. A part of the upper part of the protective film OPAS
An electrical connection is made to a material layer integrally formed with the counter electrode CT through a through hole TH penetrating through.

Further, the material layer integrally formed with the counter electrode CT and the pixel electrode PX have an overlapping portion, whereby protection is provided between the pixel electrode PX and the counter voltage signal line CL. A capacitive element Cstg having the films OPAS and PAS as dielectric films is formed. This capacitive element Cs
The tg has a function of, for example, accumulating the video signal supplied to the pixel electrode PX for a relatively long time.

An alignment film (not shown) is formed on the upper surface of the transparent substrate SUB1 on which the counter electrode CT is thus formed so as to cover the counter electrode CT. This alignment film is a film that directly contacts the liquid crystal, and the rubbing formed on the surface determines the initial alignment direction of the molecules of the liquid crystal.

In the liquid crystal display device having such a structure, the drain signal line DL is formed by traveling to the removal region of the insulating film GI in most of the region. This makes it possible to secure a larger distance between the drain signal line DL and the counter electrode CT formed so as to be overlapped with the drain signal line DL, and also to increase the thickness of the protective film OPAS made of an organic material layer, thereby increasing the drain signal line DL. This means that the parasitic capacitance between the counter electrode CT and the counter electrode CT can be significantly reduced. Therefore, it is possible to significantly reduce the waveform delay of the video signal supplied to the drain signal line DL.

<< Construction of Terminals of Gate Signal Line >> FIG. 5 shows the gate signal line terminal GLT formed in a portion where the gate signal line GL extends beyond the liquid crystal display portion AR surrounded by the sealing material SL. It is the figure which showed the cross section of. The gate signal line GL near the gate signal line terminal GLT has an insulating film GI,
The protective film PAS and the protective film OPAS are sequentially covered. The insulating film GI, the protective film PAS, and the protective film OPAS are formed so as to extend to these regions when the insulating film GI, the protective film PAS, and the protective film OPAS in the liquid crystal display section AR are formed. is there.

The gate signal line terminal GLT is formed with a relatively large area in that portion of the gate signal line GL, and the opening is formed in that portion of the protective film OPAS, the protective film PAS, and the insulating film GI. It is composed by exposing. Then, on the surface of the gate signal line terminal GLT exposed by the opening, a transparent conductive film E is formed so as to cover even the periphery of the opening.
CO is formed. The translucent conductive film ECO is formed simultaneously with the formation of the counter electrode TC. The translucent conductive film ECO is a so-called electrolytic corrosion prevention film for the gate signal line terminal GLT. That is, the gate signal line terminals G arranged close to each other
When an electrolyte such as water adheres between the LTs, ions are exchanged with the adjacent gate signal line terminal GLT through this electrolyte, and corrosion of the gate signal line terminal GLT is prevented. It is designed to be protected by the electrolytic corrosion preventing film.

<< Construction of Drain Signal Line Terminals >> FIG.
It shows a drain signal line terminal DLT formed in a portion where the drain signal line DL extends beyond the liquid crystal display portion AR surrounded by a sealing material. The drain signal line terminal DLT and the drain signal line DL in the vicinity of the drain signal line terminal DLT are covered with the insulating film G.
Protective film PAS and protective film OPA formed on the upper surface of I
Covered in sequence by S. The insulating film GI, the protective film PAS, and the protective film OPAS are formed to extend to these regions when the insulating film GI, the protective film PAS, and the protective film OPAS are formed in the liquid crystal display section AR.

The drain signal line terminal DL is formed by forming a relatively large area in that portion of the drain signal line DL and exposing that portion through the openings formed in the protective film OPAS and the protective film PAS. Has been done. Then, on the surface of the drain signal line terminal DLT exposed by the opening, a translucent conductive film ECO is formed so as to cover even the periphery of the opening. The translucent conductive film ECO is formed at the same time when the counter electrode CT is formed, and the drain signal line terminal DLT is formed.
It is the same as in the case of the gate signal line terminal GLT that it is an electrolytic corrosion prevention film against.

<< Manufacturing Method >> FIGS. 7A to 7G are process drawings showing an embodiment of the manufacturing method of the above-mentioned liquid crystal display device, and correspond to FIG. In the following description, a method for manufacturing the gate signal line terminal GLT will be described with reference to FIGS. 8A to 8G, and a method for manufacturing the drain signal line terminal DLT will be described with reference to FIGS. 9A to 9G. It will be explained together.

Step 1. (FIG. 7A) The transparent substrate SUB1 is prepared, and the gate signal line GL is formed on the main surface, which is the surface on the liquid crystal side. In this case, although not shown, the counter voltage signal line CL1 is also formed simultaneously with the formation of the gate signal line GL. Further, as shown in FIG. 8A, the gate signal line terminal GLT connected to the gate signal line GL is formed in the formation region of the gate signal line terminal GLT. At this time, as shown in FIG. 9A, the drain signal line terminal DLT is not yet formed in the formation region of the drain signal line terminal DLT.

Step 2. (FIG. 7B) The main surface of the transparent substrate SUB1 is covered with the gate signal line GL (opposing voltage signal line CL1), and an insulating film GI, for example, a semiconductor layer AS made of amorphous silicon, a semiconductor active in which impurities are doped. The layers d0 are sequentially and continuously formed. After that, the semiconductor active layer d0 and the semiconductor layer AS are collectively patterned to form a semiconductor layer of the thin film transistor TFT.
The semiconductor layer AS shown in the same drawing is different from that of the thin film transistor TFT, and is different from the gate signal line GL and the drain signal line DL.
The gate signal line G is also formed at the intersection with
It is provided to strengthen the interlayer insulation between L and the drain signal line DL. As shown in FIG. 8B, the gate signal line terminal GL is formed around the formation region of the gate signal line terminal GLT.
The insulating film GI is formed so as to cover T as well. As shown in FIG. 9B, the insulating film GI is formed around the region where the drain signal line terminal DLT is formed.

Step 3. (FIG. 7C) The insulating film GI is perforated to form an opening HOL. The opening HOL is a formation region of the drain signal line DL, and includes the gate signal line GL and the counter voltage signal line CL.
It is done in the part except the intersection with 1. At this time, at the same time, as shown in FIG. 8C, the opening HO is also formed as an extension of the opening HOL in the formation region of the gate signal line terminal GLT.
L is formed.

Step 4. (FIG. 7D) The drain signal line DL is formed. This drain signal line D
Part of L is a transparent substrate SU in the opening of the insulating film GI.
It will be formed on the B1 surface. Note that the pixel electrode PX is also formed at the same time when the drain signal line DL is formed. Further, as shown in FIG. 9D, the drain signal line DL is formed in a region where the drain signal line terminal DLT is formed.
The drain signal line terminal DLT connected to is formed.

Step 5. (FIG. 7E) A protective film PAS made of, for example, SiN is formed on the main surface of the transparent substrate SUB1 on which the drain signal line DL and the pixel electrode PX are formed. As shown in FIG. 8E, a protective film PAS is also formed around the region where the gate signal line terminal GLT is formed, and the gate signal line terminal GLT is formed on the protective film PAS.
Forming an opening for exposing. As shown in FIG. 9E, the protective film PAS is formed around the region where the drain signal line terminal DLT is formed, and the drain signal line terminal DLT is formed at the same time when the opening exposing the gate signal line terminal GLT is formed. Forming an opening for exposing.

Step 6. (FIG. 7F) On the upper surface of the protective film PAS, a protective film OP made of resin, for example, is used.
The AS is formed by coating. After that, though not shown, a through hole penetrating the protective film OPAS, the protective film PAS, and the insulating film GI is formed in a part of the region overlapped with the counter voltage signal line CL1. As shown in FIG. 8F, the protective film OPAS is also formed around the region where the gate signal line terminal GLT is formed.
Is formed, and simultaneously with the formation of the through hole, an opening for exposing the gate signal line terminal GLT is formed. As shown in FIG. 9F, a protective film OPAS is also formed around the region where the drain signal line terminal DLT is formed, and at the same time when the opening for exposing the gate signal line terminal GLT is formed,
An opening is formed to expose the drain signal line terminal DLT.

Step 7. (FIG. 7G) The counter electrode CT is formed on the surface of the protective film OPAS. Figure 8
As shown in (g), a conductive film ECO that covers the gate signal line terminal GL is formed at the same time when the counter electrode CT is formed.
Further, as shown in FIG. 9G, a conductive film ECO which covers the drain signal line terminal DL at the same time when the counter electrode CT is formed.
To form.

In the above-described embodiment, the opening formed in the insulating film GI is continuous along the running direction of the drain signal line DL (excluding the portion intersecting the gate signal line GL and the counter voltage signal line CL). Although it is formed, it is needless to say that the same effect can be obtained without being limited to this, even if it is formed intermittently.

Further, in the above-mentioned embodiment, the opening formed in the insulating film GI is formed so that the surface of the underlying transparent substrate SUB1 is exposed, but the present invention is not limited to this. Needless to say, it may be a concave portion in which the surface of SUB1 is not exposed. In short,
It suffices if the insulating film GI is provided with a removed portion, and the drain signal line DL and the counter electrode CT are formed depending on the depth of the removed portion.
The parasitic capacitance between the two can be reduced.

Further, in the above-described embodiment, the counter voltage signal line CL1 is formed in the same layer as the gate signal line GL, but the counter voltage signal line CL is not necessarily formed. .

By forming the counter electrode CT integrally with the same material layer formed on the upper layer of the gate signal line, the material layer can have a function as a counter voltage signal line. is there. In this case, by forming the counter electrode CT and the like with a non-translucent metal layer having a small electric resistance, a configuration in which the waveform delay of the reference signal does not occur can be obtained.

Further, in the above-mentioned embodiment, the protective film covering the thin film transistor TFT is formed by sequentially laminating the protective film PAS made of the inorganic material layer and the protective film OPAS made of the organic material layer. Of course, the protective film OPAS made of an organic material layer is not the only option.

[0065]

As is apparent from the above description,
According to the liquid crystal display device of the present invention, it is possible to suppress the waveform delay that occurs in the video signal supplied to the drain signal line.

[Brief description of drawings]

FIG. 1 is a plan view showing an embodiment of a pixel configuration of a liquid crystal display device according to the present invention.

FIG. 2 is a configuration diagram showing an embodiment of a liquid crystal display device according to the present invention.

3 is a sectional view taken along line III-III in FIG.

4 is a sectional view taken along line IV-IV in FIG.

FIG. 5 is a cross-sectional view showing an example of a gate signal line terminal of a liquid crystal display device according to the present invention.

FIG. 6 is a cross-sectional view showing an example of a drain signal line terminal of a liquid crystal display device according to the present invention.

FIG. 7 is a cross-sectional process diagram of a main part showing an embodiment of a method of manufacturing a liquid crystal display device according to the present invention.

FIG. 8 is a sectional process view showing an example of a method of manufacturing a gate signal line terminal of a liquid crystal display device according to the present invention.

FIG. 9 is a cross-sectional process diagram showing an embodiment of a method of manufacturing a drain signal line terminal of a liquid crystal display device according to the present invention.

[Explanation of symbols]

SUB ... Transparent substrate, GL ... Gate signal line, DL ...
Drain signal line, CL1 ... Counter voltage signal line, TFT ...
... Thin film transistor, Cstg ... Capacitive element, PX ...
Pixel electrode, CT ... Counter electrode, GLT ... Gate signal line terminal, DLT ... Drain signal line terminal,

Continued front page    (72) Inventor Takeshi Uchida             Hitachi, Ltd. 3300 Hayano, Mobara-shi, Chiba             Factory Display Group F-term (reference) 2H092 GA14 GA29 HA04 JA26 JA29                       JA38 JA42 JB05 JB13 JB23                       JB32 JB51 JB56 JB63 JB69                       KA05 KA12 KA18 KA22 MA05                       MA08 MA12 MA35 MA37 NA04

Claims (8)

[Claims] 1. A plurality of gate signal lines juxtaposed to each other and a plurality of gate signal lines juxtaposed to these gate signal lines on a liquid crystal side surface of one of the substrates opposed to each other with a liquid crystal interposed therebetween. And a drain signal line of the drain signal line are formed, and a pixel element surrounded by each of these signal lines supplies a switching element that operates by a scanning signal from the gate signal line and a video signal from the drain signal line through the switching element. And a counter electrode to which a reference signal is supplied to the pixel electrode, and the drain signal line is formed in a layer above the gate signal line via a first insulating film. In addition, the counter electrode includes a counter electrode formed by being superposed on the drain signal line via a second insulating film, and the first insulating film is a formation region of the drain signal line and is at least a gate. In the area excluding the intersection with the signal line,
A liquid crystal display device having a removed portion. 2. The liquid crystal display device according to claim 1, wherein the counter electrode is formed integrally with the same material layer formed above the gate signal line. 3. The liquid crystal display device according to claim 2, wherein the counter electrode and the same material layer formed integrally with the counter electrode are formed of a translucent conductive material. 4. A plurality of gate signal lines juxtaposed to each other and a plurality of gate signal lines juxtaposed to these gate signal lines on a liquid crystal side surface of one of the substrates opposed to each other with a liquid crystal interposed therebetween. And a drain signal line of the drain signal line are formed, and a pixel element surrounded by each of these signal lines supplies a switching element that operates by a scanning signal from the gate signal line and a video signal from the drain signal line through the switching element. And a counter electrode that is connected to the counter voltage signal line and generates an electric field between the pixel electrode and the pixel electrode, and the drain signal line includes the gate signal line and the gate via the first insulating film. The counter voltage is formed in a layer above the counter voltage signal line formed in the same layer as the signal line, and the counter electrode is formed by being superposed on the drain signal line via a second insulating film. The liquid crystal display device is characterized in that the first insulating film has a removed portion in a region where the drain signal line is formed, at least in regions other than respective intersections with the gate signal line and the counter voltage signal line. . 5. The counter electrode is integrally formed with the same material layer formed on the upper layer of the gate signal line and the counter voltage signal line, and is formed on the second insulating film and the first insulating film. The liquid crystal display device according to claim 4, wherein the liquid crystal display device is electrically connected to the counter voltage signal line through a through hole. 6. The liquid crystal display device according to claim 5, wherein the counter electrode and the same material layer formed integrally with the counter electrode are formed of a translucent conductive material. 7. The liquid crystal display device according to claim 1, wherein the second insulating film is formed of a protective film made of an organic material. 8. The liquid crystal display according to claim 1, wherein the second insulating film is composed of a sequentially laminated body of a protective film made of an inorganic material and a protective film made of an organic material. apparatus.