JP2003309241A - Lead frame member and manufacturing method thereof, and semiconductor package employing the lead frame member and manufacturing method thereof - Google Patents
Lead frame member and manufacturing method thereof, and semiconductor package employing the lead frame member and manufacturing method thereofInfo
- Publication number
- JP2003309241A JP2003309241A JP2002112642A JP2002112642A JP2003309241A JP 2003309241 A JP2003309241 A JP 2003309241A JP 2002112642 A JP2002112642 A JP 2002112642A JP 2002112642 A JP2002112642 A JP 2002112642A JP 2003309241 A JP2003309241 A JP 2003309241A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- manufacturing
- resin
- plating
- semiconductor package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 118
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 83
- 229920005989 resin Polymers 0.000 claims abstract description 108
- 239000011347 resin Substances 0.000 claims abstract description 108
- 238000007789 sealing Methods 0.000 claims abstract description 57
- 238000000034 method Methods 0.000 claims abstract description 42
- 238000007747 plating Methods 0.000 claims description 72
- 239000000463 material Substances 0.000 claims description 42
- 238000005530 etching Methods 0.000 claims description 24
- 239000000758 substrate Substances 0.000 claims description 24
- 238000005498 polishing Methods 0.000 claims description 13
- 238000005520 cutting process Methods 0.000 claims description 8
- 239000011159 matrix material Substances 0.000 claims description 8
- 238000007788 roughening Methods 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 2
- 238000009413 insulation Methods 0.000 claims description 2
- 238000003825 pressing Methods 0.000 claims description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 17
- 239000010931 gold Substances 0.000 description 13
- 238000000465 moulding Methods 0.000 description 10
- 239000000956 alloy Substances 0.000 description 7
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 229910000881 Cu alloy Inorganic materials 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 3
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 239000000945 filler Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 239000000725 suspension Substances 0.000 description 3
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 239000004809 Teflon Substances 0.000 description 2
- 229920006362 Teflon® Polymers 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 101100316860 Autographa californica nuclear polyhedrosis virus DA18 gene Proteins 0.000 description 1
- 101150000715 DA18 gene Proteins 0.000 description 1
- 229910000640 Fe alloy Inorganic materials 0.000 description 1
- 101100257194 Homo sapiens SMIM8 gene Proteins 0.000 description 1
- 101001038535 Pelodiscus sinensis Lysozyme C Proteins 0.000 description 1
- 102100024789 Small integral membrane protein 8 Human genes 0.000 description 1
- 239000005018 casein Substances 0.000 description 1
- BECPQYXYKAMYBN-UHFFFAOYSA-N casein, tech. Chemical compound NCCCCC(C(O)=O)N=C(O)C(CC(O)=O)N=C(O)C(CCC(O)=N)N=C(O)C(CC(C)C)N=C(O)C(CCC(O)=O)N=C(O)C(CC(O)=O)N=C(O)C(CCC(O)=O)N=C(O)C(C(C)O)N=C(O)C(CCC(O)=N)N=C(O)C(CCC(O)=N)N=C(O)C(CCC(O)=N)N=C(O)C(CCC(O)=O)N=C(O)C(CCC(O)=O)N=C(O)C(COP(O)(O)=O)N=C(O)C(CCC(O)=N)N=C(O)C(N)CC1=CC=CC=C1 BECPQYXYKAMYBN-UHFFFAOYSA-N 0.000 description 1
- 235000021240 caseins Nutrition 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 125000003700 epoxy group Chemical group 0.000 description 1
- 230000009477 glass transition Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000005488 sandblasting Methods 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 238000005496 tempering Methods 0.000 description 1
- 239000013585 weight reducing agent Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01088—Radium [Ra]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置とその
製造方法に関し、特に、片面モールドの半導体装置とそ
の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a single-sided mold and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】近年、携帯機器を中心として、基板実装
の高密度化が進み、これに伴ないパッケージの小型化、
軽量化が急速に進んできている。外部端子がパッケージ
面に格子状に配列されるエリアアレイ型、あるいは、外
部端子がパッケージ面の周辺部に配列されるペリフェラ
ル型が採用されている。エリアアレイ型としては、ＬＧ
Ａ（Ｌａｎｄ Ｇｒｉｄ Ａｒｒａｙ）等があり、ペリ
フェラル型としては、アウターリードがパッケージの外
部にほとんど突出しない構造の、いわゆるノンリードタ
イプのＱＦＮ（Ｑｕａｄ Ｆｌａｔ Ｎｏｎ−Ｌｅａｄ
ｅｄ Ｐａｃｋａｇｅ）、ＳＯＮ（Ｓｍａｌｌ Ｏｕｔ
ｌｉｎｅＮｏｎ−Ｌｅａｄｅｄ Ｐａｃｋａｇｅ）が
ある。これらは、実装基板とのコンタクトをとるため、
リードがパッケージの底面において露出する構造をして
いる。そして、一般に、パッケージを小型化、薄型化す
るために、半導体素子を搭載した側を主に樹脂モールド
しており、例えば、ＱＦＮは、図７（ａ）に示すような
形態を採る。尚、図７（ｂ）は、図７（ａ）に示すＱＦ
Ｎを透視した状態の図である。また、図７に示すＱＦＮ
に用いられているリードフレーム７１０においては、吊
りリード７１３がプレスにより延ばされ、ダイパッド７
１１が、リード７１２より上方に位置するように、アッ
プセットされており、ダイパッド７１１の下側にも封止
樹脂７４０を存在させている。2. Description of the Related Art In recent years, the density of board mounting has been increasing, mainly in portable devices, and the size of packages has been reduced accordingly.
Weight reduction is progressing rapidly. An area array type in which external terminals are arranged in a lattice on the package surface, or a peripheral type in which external terminals are arranged in the peripheral portion of the package surface is adopted. For area array type, LG
There are A (Land Grid Array) and the like, and as a peripheral type, a so-called non-lead type QFN (Quad Flat Non-Lead) having a structure in which outer leads hardly protrude outside the package.
ed Package), SON (Small Out)
lineNon-Leaded Package). These make contact with the mounting board,
The leads are exposed on the bottom surface of the package. In general, in order to reduce the size and thickness of the package, the side on which the semiconductor element is mounted is mainly resin-molded. For example, the QFN has a form as shown in FIG. 7A. Note that FIG. 7B shows the QF shown in FIG.
It is a figure of the state where N was seen through. In addition, the QFN shown in FIG.
In the lead frame 710 used for, the suspension leads 713 are stretched by pressing, and
11 is upset so as to be located above the leads 712, and the sealing resin 740 is also present under the die pad 711.
【０００３】上記ノンリードタイプの薄型のＱＦＮは、
半導体素子のサイズが小型であるため、従来、 1枚の銅
系素材あるいは４２合金（４２％ニッケル−鉄合金）素
材からなる加工用の板材に、リードフレーム複数個を１
単位として、これを１フレームとも言う）として、複数
フレーム分をエッチング形成し、１フレーム単位の状態
で、各リードフレーム毎に個別に、樹脂モールドを行な
い、更に各リードフレーム毎に切断して形成していた。
ここでは、このような個別モールド方式を採り入れた製
造方法を個別モールドタイプの半導体パッケージの製造
方法と言う。しかし、最近では、コストダウンの要求か
ら、後に図５に基づいて説明するような、一括してモー
ルドする方式を採り入れた製造方法である一括モールド
タイプの半導体パッケージの製造方法へ移行しつつあ
る。The non-lead type thin QFN is
Due to the small size of semiconductor devices, it has been common practice to use multiple lead frames on a single plate of copper-based material or 42 alloy (42% nickel-iron alloy) material for processing.
This is also referred to as one frame), and a plurality of frames are etched and formed, and in the state of one frame, resin molding is individually performed for each lead frame, and further, each lead frame is cut and formed. Was.
Here, a manufacturing method incorporating such an individual molding method is referred to as a manufacturing method of an individual molding type semiconductor package. However, recently, due to the demand for cost reduction, there is a shift to a manufacturing method of a collective molding type semiconductor package, which is a manufacturing method adopting a collective molding method as described later with reference to FIG.
【０００４】個別モールドタイプの半導体パッケージの
製造方法は、図６（ａ）に示すように、１枚のフレーム
６１０内に小さなサイズの個々のモールドキャビティ６
２０を別れた状態で設けるようにして、モールド後は金
型により個別に打ち抜いて図６（ｃ）に示す半導体パッ
ケージ６２０Ａを得るものである。尚、図６（ｂ）は図
６（ａ）におけるＥ１側からみた図である。すなわち、
半導体素子６４０を銀ペースト等によりリードフレーム
のダイパッド６３１上に搭載し、ワイヤーボンディング
を実施した後、個々の半導体素子を個別にモールドして
から、金型により個々の半導体パッケージ６２０Ａとし
て打ち抜くのである。一括モールドタイプの半導体パッ
ケージの製造方法は、図５（ａ）に示すように、１枚の
フレーム５１０内に大きいサイズの幾つかのモールドキ
ャビティ５２０Ｌを設けるようにし、その１つ１つのモ
ールドキャビティ５２０Ｌ内には多数の半導体素子をマ
トリックス状に配列し、それらの半導体素子を一括して
モールドした後、各リードフレームのグリッドリード５
２０Ｇのところをダイシングソーで切断して図５（ｃ）
に示す半導体パッケージ５２０Ａを得るものである。
尚、図５（ｂ）は図５（ａ）におけるＤ１側からみた図
である。すなわち、半導体素子を銀ペースト等によりリ
ードフレームのダイパッド上に搭載し、ワイヤーボンデ
ィングを実施した後、複数個配列されている半導体素子
を所定のキャビティサイズで一括モールドしてから、ダ
イシングにより個片化するのである。尚、通常、加工用
素材である金属板をエッチング加工してリードフレーム
を複数個配列した状態で作製するが、エッチング加工後
の、外形加工されたリードフレームを複数個配列させ
た、リードフレームを含む、単位の加工用素材部分を、
フレーム（５１０、６１０に相当）と言う。ここでは、
各リードフレームは互いに分離しておらず一体的に連結
されている。As shown in FIG. 6A, the method of manufacturing an individual mold type semiconductor package is such that a small size of individual mold cavities 6 is formed in one frame 610.
After the molding, the semiconductor package 620A shown in FIG. 6C is obtained by individually punching with a die. Note that FIG. 6B is a view seen from the E1 side in FIG. That is,
The semiconductor element 640 is mounted on the die pad 631 of the lead frame with silver paste or the like, after wire bonding is performed, the individual semiconductor elements are individually molded, and then die-cut into individual semiconductor packages 620A by a die. As shown in FIG. 5A, the method of manufacturing the collective mold type semiconductor package is such that a plurality of large-sized mold cavities 520L are provided in one frame 510, and each of the mold cavities 520L is formed. A large number of semiconductor elements are arranged in a matrix, and the semiconductor elements are collectively molded.
Fig. 5 (c) after cutting 20G with a dicing saw
The semiconductor package 520A shown in FIG.
Note that FIG. 5B is a view seen from the D1 side in FIG. That is, a semiconductor element is mounted on a die pad of a lead frame with silver paste or the like, wire bonding is performed, a plurality of arranged semiconductor elements are collectively molded with a predetermined cavity size, and then diced into individual pieces. To do. Usually, a metal plate, which is a material for processing, is etched to produce a plurality of lead frames arranged. However, after etching, a lead frame having a plurality of externally processed lead frames arranged is arranged. Including the unit processing material part,
It is called a frame (corresponding to 510 and 610). here,
The lead frames are not separated from each other but are integrally connected.
【０００５】更に、図８にもとづいて、従来の、一括モ
ールドタイプによる半導体パッケージ（ＱＦＮ）の工程
を説明しておく。先ず、フォトリソグラフィーを用いた
エッチング加工により、モールドする単位のフレームを
準備する。銅系材あるいは４２合金（４２％ニッケル−
鉄合金）を加工用素材（図８（ａ））として、例えば、
図８（ｂ）に示す断面形状にする。次いで、ワイヤボン
ディング用、ダイボンディング用のめっき処理を施した
後、リードフレームの半導体素子を搭載する側ではない
裏面に固定用テープ８２０を貼り付け（図８（ｃ））、
半導体素子８３０をダイボンデインングしてダイパッド
８１１上に搭載し、更に、ワイヤーボンディングによ
り、半導体素子８３０の端子部とリード８１２を電気的
に結線する。（図８（ｄ））
次いで、半導体素子搭載側から樹脂封止して、隙間を封
止用樹脂８５０で埋める。（図８（ｅ））
ここでは、先に述べた固定用テープ８２０が、樹脂封止
の際の封止用樹脂８５０の流れ防止し、封止領域を決め
る。次いで、ダイシングによる切断を行ない（図８
（ｆ））、個片化された状態で、目的とする半導体パッ
ケージを得る。（図８（ｇ））
ダイシングによる個片化は、リドフレーム間を接続する
固定用バー（タイバーとも言い、図１の１２３に相当）
を切断する。ここでは、点線矢印の位置にて切断する。Further, a conventional process of a collective package type semiconductor package (QFN) will be described with reference to FIG. First, a frame as a unit for molding is prepared by etching using photolithography. Copper-based material or 42 alloy (42% nickel-
(Iron alloy) as a processing material (Fig. 8 (a)), for example,
The cross-sectional shape shown in FIG. Then, after performing a plating treatment for wire bonding and die bonding, a fixing tape 820 is attached to the back surface of the lead frame that is not the side on which the semiconductor element is mounted (FIG. 8C).
The semiconductor element 830 is die-bonded and mounted on the die pad 811, and the terminal portion of the semiconductor element 830 and the lead 812 are electrically connected by wire bonding. (FIG. 8D) Next, resin sealing is performed from the semiconductor element mounting side, and the gap is filled with the sealing resin 850. (FIG. 8E) Here, the fixing tape 820 described above prevents the sealing resin 850 from flowing during resin sealing and determines the sealing region. Then, cutting by dicing is performed (see FIG.
(F)) The target semiconductor package is obtained in the individualized state. (FIG. 8 (g)) Dividing into individual pieces by dicing is a fixing bar that connects between lid frames (also called a tie bar, corresponding to 123 in FIG. 1).
Disconnect. Here, cutting is performed at the position of the dotted arrow.
【０００６】図８（ｇ）に示す、従来の一括モールドタ
イプによる半導体パッケージ（ＱＦＮ）の工程において
は、以下のような、問題点がある。(1) 従来の工程で
は、ワイヤーボンディング時のリード固定、および、樹
脂封止時の樹脂バリ発生防止を目的として、裏面にテー
プを貼る必要があり、これが生産性の低下やコストアッ
プの要因となっている。(2) 裏面のテープとリードとの
界面での接着剤が原因で、ワイヤーボンディング性を阻
害する要因にもなっている。即ち、接着剤のＴｇ（ガラ
ス転移温度）が低いため、ワイヤーボンディング温度で
接着剤がゴム状態となり、ワイヤーボンディングの超音
波振動に対してリードを固定し難くなる。あるいは、ワ
イヤーボンディングの超音波振動が吸収されてしまう。
これにより、不圧着が発生する。[0006] The following problems are encountered in the process of the conventional package package type semiconductor package (QFN) shown in Fig. 8 (g). (1) In the conventional process, it is necessary to attach a tape to the back surface for the purpose of fixing leads during wire bonding and preventing resin burrs during resin encapsulation, which is a cause of reduced productivity and increased costs. Has become. (2) Due to the adhesive at the interface between the tape on the backside and the leads, it is also a factor that hinders wire bonding. That is, since the Tg (glass transition temperature) of the adhesive is low, the adhesive becomes a rubber state at the wire bonding temperature, and it becomes difficult to fix the lead against ultrasonic vibration of the wire bonding. Alternatively, the ultrasonic vibration of wire bonding will be absorbed.
As a result, non-bonding occurs.
【０００７】[0007]
【発明が解決しようとする課題】上記のように、従来
の、一括モールドタイプによる半導体パッケージ（ＱＦ
Ｎ）の作製工程においては、種々問題があり、その対応
が求められていた。本発明は、これらに対応するもの
で、具体的には、一括モールドタイプの半導体パッケー
ジの製造工程で、従来必要とされた固定用、且つ、樹脂
封止の際の封止用樹脂の流れ防止用の裏面テープを不要
とし、従来の問題点を解決できる工程の半導体パッケー
ジの製造方法を提供しようとするものである。さらに
は、このような半導体パッケージの製造に用いられるリ
ードフレーム部材を提供しようとするものである。SUMMARY OF THE INVENTION As described above, the conventional collective package type semiconductor package (QF) is used.
There are various problems in the manufacturing process of N), and it has been required to cope with them. The present invention responds to these problems, and specifically, in the manufacturing process of a collective mold type semiconductor package, it is necessary to prevent the flow of the resin for fixing and the resin for sealing which is conventionally required. It is an object of the present invention to provide a method for manufacturing a semiconductor package, which eliminates the need for a backside tape for use and solves the conventional problems. Further, the present invention aims to provide a lead frame member used for manufacturing such a semiconductor package.
【０００８】[0008]
【課題を解決するための手段】本発明のリードフレーム
部材は、一括モールドタイプの半導体パッケージの製造
方法により、ノンリードタイプの薄型の半導体パッケー
ジを製造するための、一括モールドタイプ用のリードフ
レーム部材であって、リードフレームを複数配列したフ
レームを有し、該フレームの各リードフレームの表裏面
間の隙間部に、リードフレーム固定用、且つ、樹脂封止
の際の封止用樹脂の流れ防止用の絶縁性の樹脂を埋め込
んでいることを特徴とするものである。そして、上記に
おいて、その表裏面側には、実装用配線基板と接続する
ための端子部の面と、ワイヤボンディングするための端
子部の面とを、あるいは、実装用配線基板と接続するた
めの端子部の面と、ワイヤボンディングするための端子
部の面と、ダイパッド面とを、そのまま露出させて、あ
るいはめっき処理を施して露出させていることを特徴と
するものである。そしてまた、上記において、めっき処
理は、順にＮｉめっき、Ａｕめっき、あるいは、順に粗
化Ｎｉめっき、Ｐｄめっき、薄Ａｕめっきを施すもので
あることを特徴とするものであり、粗化は、中心値平均
粗度Ｒａが０. １〜０. ５μｍの範囲であることを特徴
とするものである。The lead frame member of the present invention is a lead frame member for a batch mold type for manufacturing a thin non-lead type semiconductor package by a method for manufacturing a batch mold type semiconductor package. A frame having a plurality of lead frames arranged in the gap between the front and back surfaces of each lead frame for fixing the lead frame and preventing the flow of sealing resin during resin sealing It is characterized in that it is embedded with an insulating resin for use. Then, in the above, on the front and back surfaces thereof, the surface of the terminal portion for connecting to the mounting wiring board and the surface of the terminal portion for wire bonding, or for connecting to the mounting wiring board It is characterized in that the surface of the terminal portion, the surface of the terminal portion for wire bonding, and the die pad surface are exposed as they are or by performing a plating treatment. Further, in the above, the plating treatment is characterized in that Ni plating, Au plating, or roughening Ni plating, Pd plating, and thin Au plating are sequentially performed, and the roughening is mainly performed. The value average roughness Ra is in the range of 0.1 to 0.5 μm.
【０００９】本発明のリードフレーム部材の製造方法
は、一括モールドタイプの半導体パッケージの製造方法
により、ノンリードタイプの薄型の半導体パッケージを
製造するための、一括モールドタイプ用のリードフレー
ム部材で、リードフレームを複数配列したフレームを有
し、該フレームの各リードフレームの表裏面間の隙間部
に、リードフレーム固定用、且つ、樹脂封止の際の封止
用樹脂の流れ防止用の絶縁性の樹脂樹脂を埋め込んでい
るリードフレーム部材を、製造するための、リードフレ
ーム部材の製造方法であって、順に、（ａ）加工用素材
に繋ぎ部を介して保持させた状態で、エッチング加工に
より、リードフレームを多数、二次元的に配列して（マ
トリックス状に配列して）、エッチング加工基板を形成
する、エッチング加工工程と、（ｂ）エッチング加工基
板の表裏面間の隙間部に絶縁性の樹脂を埋め込む、樹脂
埋め込み工程と、（ｃ）表裏面を研磨して、加工用素材
面を露出させる研磨処理工程とを行なうことを特徴とす
るものである。そして、上記おける樹脂埋め込み工程
は、エッチング加工基板の一面側に樹脂シートを配し、
エッチング加工基板と樹脂シートとを、耐熱性、剛性の
ある板材間に挟んだ状態で、真空中で、加熱、加圧し
て、埋め込むものであることを特徴とするものである。
そしてまた、上記において、研磨処理工程後に、露出し
た表裏の加工用素材の露出部に、接続用あるいはダイボ
ンディング用のめっき処理を施すことを特徴とするもの
である。また、上記において、めっき処理が、表裏の加
工用素材の露出部に、順にＮｉめっき、Ａｕめっき、あ
るいは、順に粗化Ｎｉめっき、Ｐｄめっき、薄Ａｕめっ
きを施すめっき処理工程を施すものであることを特徴と
するものであり、粗化は、中心値平均粗度Ｒａが０. １
〜０. ５μｍの範囲であることを特徴とするものであ
る。The lead frame member manufacturing method of the present invention is a batch mold type lead frame member for manufacturing a non-lead type thin semiconductor package by the method of manufacturing a batch mold type semiconductor package. A frame having a plurality of frames arranged therein is provided in the gap between the front and back surfaces of each lead frame of the frame with an insulating property for fixing the lead frame and for preventing the flow of the sealing resin during resin sealing. A method of manufacturing a lead frame member for manufacturing a resin-embedded lead frame member, the method comprising: (a) holding a processing material through a connecting portion, and then performing an etching process. A large number of lead frames are two-dimensionally arranged (arranged in a matrix) to form an etched substrate. And (b) a resin embedding step of embedding an insulating resin in the gap between the front and back surfaces of the etched substrate, and (c) a polishing treatment step of polishing the front and back surfaces to expose the processing material surface. It is characterized by performing. Then, in the resin embedding step in the above, the resin sheet is arranged on one surface side of the etching processed substrate,
It is characterized in that an etching-processed substrate and a resin sheet are sandwiched between plate materials having heat resistance and rigidity, and are heated and pressurized in a vacuum to be embedded.
Further, in the above, after the polishing treatment step, the exposed exposed portions of the processing material on the front and back sides are subjected to a plating treatment for connection or die bonding. Further, in the above, the plating treatment is performed by performing a plating treatment step of sequentially performing Ni plating, Au plating, or roughened Ni plating, Pd plating, and thin Au plating on exposed portions of the front and back processing materials. In the roughening, the center value average roughness Ra is 0.1.
It is characterized by being in the range of up to 0.5 μm.
【００１０】本発明の半導体パッケージは、ノンリード
タイプの薄型の半導体パッケージであって、リードフレ
ームの表裏面間の隙間部に、リードフレーム固定用、且
つ、樹脂封止の際の封止用樹脂の流れ防止用の絶縁性の
樹脂を埋め込んでいることを特徴とするものである。The semiconductor package of the present invention is a non-lead type thin semiconductor package, and is a resin for fixing the lead frame in the gap between the front and back surfaces of the lead frame and for sealing with resin. It is characterized in that an insulating resin for preventing the flow of is embedded.
【００１１】本発明の半導体パッケージの製造方法は、
一括モールドタイプの半導体パッケージの製造方法によ
り、リードフレームの表裏面間の隙間部に、リードフレ
ーム固定用、且つ、樹脂封止の際の封止用樹脂の流れ防
止用の絶縁性の樹脂を埋め込んでいるノンリードタイプ
の薄型の半導体パッケージの製造方法であって、順に、
（Ａ）加工用素材に繋ぎ部を介して保持させた状態で、
エッチング加工により、リードフレームを多数、二次元
的に配列して（マトリックス状に配列して）、エッチン
グ加工基板を形成する、エッチング加工工程と（Ｂ）エ
ッチング加工基板の表裏面間の隙間部に絶縁性の樹脂を
埋め込む、樹脂埋め込み工程と、（Ｃ）表裏面を研磨し
て、加工用素材面を露出させる研磨工程と、（Ｄ）表裏
の加工用素材の露出部に、接続用あるいはダイボンディ
ング用のめっき処理を施すめっき処理工程と、（Ｅ）半
導体素子を搭載する処理、および半導体素子の端子とリ
ードフレームのリード端子とを接続する処理を行なう半
導体素子組み立て工程と、（Ｆ）半導体素子搭載側を樹
脂封止する樹脂封止工程と、（Ｇ）切断により個別の半
導体パッケージに個片化する切断処理とを行なうことを
特徴とするものである。そして、上記における半導体素
子組み立て工程は、半導体素子を搭載する処理がダイボ
ンディング処理で、半導体素子の端子とリードフレーム
のリード端子とを接続する処理がワイヤボンディング処
理であることを特徴とするものである。そしてまた、上
記において、めっき処理が、表裏の加工用素材の露出部
に、順にＮｉめっき、Ａｕめっき、あるいは、順に粗化
Ｎｉめっき、Ｐｄめっき、薄Ａｕめっきを施すめっき処
理工程を施すものであることを特徴とするものであり、
粗化は、中心値平均粗度Ｒａが０. １〜０. ５μｍの範
囲であることを特徴とするものである。The semiconductor package manufacturing method of the present invention is
An insulative resin for fixing the lead frame and preventing the flow of sealing resin during resin sealing is embedded in the gap between the front and back surfaces of the lead frame by the method of manufacturing the one-piece mold type semiconductor package. Is a method of manufacturing a non-lead type thin semiconductor package,
(A) With the material for processing held through the connecting portion,
By etching processing, a large number of lead frames are two-dimensionally arranged (arranged in a matrix) to form an etched substrate. (B) In the gap between the front and back surfaces of the etched substrate. A resin embedding step of embedding an insulative resin, (C) a polishing step of polishing the front and back surfaces to expose the processing material surface, and (D) an exposed portion of the processing material on the front and back surfaces for connection or die A plating treatment step for performing a plating treatment for bonding; (E) a semiconductor element mounting step; and a semiconductor element assembling step for connecting the terminals of the semiconductor element to the lead terminals of the lead frame; The invention is characterized by performing a resin sealing step of resin-sealing the element mounting side and a cutting process of (G) cutting into individual semiconductor packages. That. The semiconductor element assembly process in the above is characterized in that the process of mounting the semiconductor device is a die bonding process, and the process of connecting the terminals of the semiconductor element and the lead terminals of the lead frame is a wire bonding process. is there. Further, in the above, the plating treatment is performed by performing a plating treatment step of sequentially performing Ni plating, Au plating, or roughened Ni plating, Pd plating, and thin Au plating on exposed portions of the front and back processing materials. Is characterized by the fact that
The roughening is characterized in that the center value average roughness Ra is in the range of 0.1 to 0.5 μm.
【００１２】[0012]
【作用】本発明のリードフレーム部材は、このような構
成にすることにより、一括モールドタイプの半導体パッ
ケージの製造工程で、従来必要とされた固定用、且つ、
樹脂封止の際の封止用樹脂の流れ防止用の裏面テープを
不要とし、従来の問題点を解決できる工程の半導体パッ
ケージの製造方法において用いられるリードフレーム部
材の提供を可能としている。具体的には、一括モールド
タイプの半導体パッケージの製造方法により、ノンリー
ドタイプの薄型の半導体パッケージを製造するための、
一括モールドタイプ用のリードフレーム部材であって、
リードフレームを複数配列したフレームを有し、該フレ
ームの各リードフレームの表裏面間の隙間部に、リード
フレーム固定用、且つ、樹脂封止の際の封止用樹脂の流
れ防止用の、絶縁性の樹脂を埋め込んでおり、その表裏
面側には、実装用配線基板と接続するための端子部の面
と、ワイヤボンディングするための端子部の面とを、あ
るいは、実装用配線基板と接続するための端子部の面
と、ワイヤボンディングするための端子部の面と、ダイ
パッド面とを、そのまま露出させて、あるいはめっき処
理して露出させていることにより、これを達成してい
る。The lead frame member of the present invention has the above-described structure, and is used for the fixing which has been conventionally required in the manufacturing process of the collective mold type semiconductor package.
This makes it possible to provide a lead frame member used in a method for manufacturing a semiconductor package in a process that can solve the conventional problems by eliminating the need for a back tape for preventing the flow of a sealing resin during resin sealing. Specifically, in order to manufacture a non-lead type thin semiconductor package by the method of manufacturing a collective mold type semiconductor package,
A lead frame member for a batch mold type,
Having a frame in which a plurality of lead frames are arranged, insulation for fixing the lead frame and for preventing the flow of sealing resin at the time of resin sealing in the gap between the front and back surfaces of each lead frame of the frame Resin is embedded, and on the front and back sides, the surface of the terminal part for connecting to the mounting wiring board and the surface of the terminal part for wire bonding, or connecting to the mounting wiring board This is achieved by exposing the surface of the terminal portion for performing the bonding, the surface of the terminal portion for performing wire bonding, and the die pad surface as they are or by performing a plating treatment.
【００１３】また、本発明のリードフレーム部材の製造
方法は、このような構成にすることにより、一括モール
ドタイプの半導体パッケージの製造工程で、従来必要と
された固定用の裏面テープを不要とし、従来の問題点を
解決できる工程の半導体パッケージの製造方法において
用いられるリードフレーム部材の製造方法の提供を可能
としている。具体的には、（ａ）加工用素材に繋ぎ部を
介して保持させた状態で、エッチング加工により、リー
ドフレームを多数、二次元的に配列して（マトリックス
状に配列して）、エッチング加工基板を形成する、エッ
チング加工程と、（ｂ）エッチング加工基板の表裏面間
の隙間部に絶縁性の樹脂を埋め込む、樹脂埋め込み工程
と、（ｃ）表裏面を研磨して、加工用素材面を露出させ
る研磨処理工程とを行なうことにより、これを達成して
いる。Further, the lead frame member manufacturing method of the present invention, by adopting such a structure, eliminates the need for a fixing back tape which has been conventionally required in the manufacturing process of the collective mold type semiconductor package. It is possible to provide a method of manufacturing a lead frame member used in a method of manufacturing a semiconductor package, which is a process capable of solving the conventional problems. Specifically, (a) a large number of lead frames are two-dimensionally arranged (arranged in a matrix) by etching while being held by the processing material via a connecting portion, and then etching processing is performed. An etching step of forming a substrate, (b) a resin embedding step of embedding an insulating resin in a gap between the front and back surfaces of an etched substrate, and (c) polishing the front and back surfaces to form a processing material surface. This is achieved by performing a polishing process step for exposing the.
【００１４】また、本発明の半導体パッケージは、この
ような構成にすることにより、これを、一括モールドタ
イプの半導体パッケージの製造工程で作製する際、従来
必要とされた固定用、且つ、樹脂封止の際の封止用樹脂
の流れ防止用の裏面テープを不要とし、且つ、従来の製
造工程に起因する問題点を解決できるものとしている。Further, the semiconductor package of the present invention has the above-mentioned structure, and when it is manufactured in the manufacturing process of the collective mold type semiconductor package, the fixing and the resin sealing which are conventionally required. The backside tape for preventing the flow of the sealing resin at the time of stopping is unnecessary, and the problems caused by the conventional manufacturing process can be solved.
【００１５】また、本発明の半導体パッケージの製造方
法は、このような構成にすることにより、一括モールド
タイプの半導体パッケージの製造工程で、従来必要とさ
れた固定用、且つ、樹脂封止の際の封止用樹脂の流れ防
止用の裏面テープを不要とし、且つ、従来の製造工程に
起因する問題点を解決できる、半導体パッケージの製造
方法の提供を可能としている。Further, according to the method of manufacturing a semiconductor package of the present invention, by adopting such a structure, in the manufacturing process of the collective mold type semiconductor package, the fixing and resin sealing which are conventionally required are performed. It is possible to provide a method for manufacturing a semiconductor package that does not require the backside tape for preventing the flow of the sealing resin and can solve the problems caused by the conventional manufacturing process.
【００１６】[0016]
【発明の実施の形態】本発明の実施の形態例を図に基づ
いて説明する。図１（ａ）は本発明のリードフレーム部
材の実施の形態の第１の例の概略平面図で、図１（ｂ）
は図１（ａ）のＡ１−Ａ２における断面の一部を示した
図で、図１（ｃ）は本発明のリードフレーム部材の実施
の形態の第２の例の一部断面図で、図２は図１（ａ）に
示すリードフレーム部材の中の単位のリードフレームを
拡大して示した平面図で、図３は実施の形態の第１の例
のリードフレーム部材の製造方法および第２の例のリー
ドフレーム部材の製造方法を図示した工程断面図で、図
４（ｄ）は本発明の半導体パッケージの実施の形態の１
例の断面図で、図４（ａ）〜図４（ｄ）は実施の形態例
の半導体パッケージの製造工程の一部を示した工程断面
図である。尚、図２中、Ａ３−Ａ４における断面は、図
１中、Ａ１−Ａ２における断面の一部とする。また、点
線四角内が単位の部材１２０の領域であり、単位のリー
ドフレームの領域でもある。図１〜図４中、１００、１
００Ａはリードフレーム部材、１１０はフレーム、１１
０Ｓは加工用素材、１１１はエッチング加工基板、１２
０は単位の部材、１２０ａは単位のリードフレーム、１
２１はダイパッド、１２２はリード、１２３はタイバ
ー、１２４は吊りリード、１２８はリードフレーム、１
３０は（絶縁性の）樹脂、１３０Ａは樹脂シート、１３
５は板材、１５０はめっき層、１６０はレジスト層、１
６１は開口部、１７０は半導体素子、１７１はボンディ
ングワイヤ、１８０は封止用樹脂である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described with reference to the drawings. FIG. 1A is a schematic plan view of a first example of an embodiment of a lead frame member of the present invention, and FIG.
1A is a diagram showing a part of a cross section taken along line A1-A2 of FIG. 1A, and FIG. 1C is a partial cross sectional view of a second example of the embodiment of the lead frame member of the present invention. 2 is an enlarged plan view showing a unit lead frame in the lead frame member shown in FIG. 1A, and FIG. 3 is a method for manufacturing a lead frame member of a first example of the embodiment and a second method. 4D is a process cross-sectional view illustrating the method of manufacturing the lead frame member of the example of FIG.
4A to 4D are cross-sectional views of an example, and are process cross-sectional views showing a part of the manufacturing process of the semiconductor package of the embodiment. The section taken along line A3-A4 in FIG. 2 is a part of the section taken along line A1-A2 in FIG. Further, the area within the dotted line rectangle is the area of the unit member 120, and is also the area of the unit lead frame. 1 to 4, 100, 1
00A is a lead frame member, 110 is a frame, 11
0S is a processing material, 111 is an etching processed substrate, 12
0 is a unit member, 120a is a unit lead frame, 1
21 is a die pad, 122 is a lead, 123 is a tie bar, 124 is a suspension lead, 128 is a lead frame, 1
30 is an (insulating) resin, 130A is a resin sheet, 13
5 is a plate material, 150 is a plating layer, 160 is a resist layer, 1
61 is an opening, 170 is a semiconductor element, 171 is a bonding wire, and 180 is a sealing resin.
【００１７】はじめに、本発明のリードフレーム部材の
実施の形態例を、図に基づいて説明する。先ず、実施の
形態の第１の例のリードフレーム部材を、図１、図２に
基づいて説明する。第１の例のリードフレーム部材は、
一括モールドタイプの半導体パッケージの製造方法でノ
ンリードタイプの薄型の半導体パッケージＱＦＮを製造
するためのリードフレーム部材１００で、図２にその平
面図を示す、単位の部材１２０を、図１（ａ）に示すよ
うに、複数個二次元的に面付けして配置（マトリックス
配列とも言う）したものである。そして、図１（ｂ）に
その断面を示すように、その表裏面間の隙間部に、リー
ドフレーム固定用、且つ、樹脂封止の際の封止用樹脂の
流れ防止用の樹脂１３０を埋め込んでおり、その表裏面
側には、実装用配線基板と接続するためのリードフレー
ムの端子部の面と、ワイヤボンディングするための端子
部の面と、ダイパッド面とを、そのまま露出させてい
る。尚、本例のリードフレーム部材は、この後、露出さ
れている端子部の面、ダイパッド面をめっき処理した
後、半導体素子搭載、ワイヤボンディングされ、一括モ
ールドに供される。First, an embodiment of the lead frame member of the present invention will be described with reference to the drawings. First, the lead frame member of the first example of the embodiment will be described with reference to FIGS. 1 and 2. The lead frame member of the first example is
A lead frame member 100 for manufacturing a non-lead type thin semiconductor package QFN by a method of manufacturing a collective mold type semiconductor package. A unit member 120 of which a plan view is shown in FIG. 2 is shown in FIG. As shown in FIG. 3, a plurality of two-dimensional surfaces are arranged and arranged (also referred to as a matrix arrangement). Then, as shown in the cross section in FIG. 1B, a resin 130 for fixing the lead frame and for preventing the flow of the sealing resin during resin sealing is embedded in the gap between the front and back surfaces. On the front and back surfaces, the surface of the terminal portion of the lead frame for connecting to the mounting wiring board, the surface of the terminal portion for wire bonding, and the die pad surface are exposed as they are. The lead frame member of this example is then subjected to a plating treatment on the exposed surface of the terminal portion and the die pad surface, then mounted with a semiconductor element, wire-bonded, and subjected to batch molding.
【００１８】各リードフレーム１２８の素材としては、
銅材、銅合金材、あるいは、４２合金（４２％ニッケル
−鉄合金）等が適用される。絶縁性の樹脂１３０として
は、配線基板用の樹脂や封止用樹脂が用いられる。具体
的には、シリカフィラー含有のＢステージエポキシが挙
げられるが、これらに限定はされない。リードフレーム
の固定と樹脂封止の際の封止用樹脂の流れ防止の面で優
れ、半導体パッケージの製造方法において、あるいは半
導体パッケージとなった際に、問題とならない材質であ
れば良い。As the material of each lead frame 128,
A copper material, a copper alloy material, or 42 alloy (42% nickel-iron alloy) or the like is applied. As the insulating resin 130, a wiring board resin or a sealing resin is used. Specific examples include, but are not limited to, B-stage epoxies containing silica filler. Any material may be used as long as it is excellent in terms of fixing the lead frame and preventing the flow of the sealing resin during resin sealing, and is not a problem in the method of manufacturing the semiconductor package or when the semiconductor package is formed.
【００１９】第１の例のリードフレーム部材の製造方法
の１例を、図３に基づいて、簡単に、説明する。尚、こ
れを以って、本発明のリードフレーム部材の製造方法の
実施の形態の１例の説明に代える。先ず、エッチング加
工の加工用素材１１０Ｓ（図３（ａ））の両面に、形成
するリードフレーム形状に合せて、耐エッチング性のレ
ジスト層１６０を形成する。（図３（ｂ））
加工用素材１１０Ｓとしては、銅材、銅合金材、あるい
は、４２合金（４２％ニッケル−鉄合金）等が用いられ
る。レジスト層１６０としては、所望の解像性があり、
耐エッチング性があり、処理性の良いものであれば、特
に限定はされない。次いで、レジスト層の開口１６１か
ら露出した、加工用素材１１０Ｓを両面からエッチング
し、貫通させ、所望の形状に加工する。（図３（ｃ））
加工用素材１１０Ｓに、繋ぎ部（通常リード延長部やタ
イバー１２３をこれに当てる）を介して、保持させた状
態で、エッチング加工により、リードフレーム（図２の
１２８）を多数、二次元的に配列して（マトリックス状
に配列して）、エッチング加工基板１１１を形成する。
エッチング液としては、通常、塩化第二鉄液が用いられ
る。An example of the method of manufacturing the lead frame member of the first example will be briefly described with reference to FIG. It should be noted that, instead of this, the description of one example of the embodiment of the method for manufacturing a lead frame member of the present invention will be replaced. First, an etching resistant resist layer 160 is formed on both surfaces of a material 110S for etching processing (FIG. 3A) according to the shape of the lead frame to be formed. (FIG. 3B) As the processing material 110S, a copper material, a copper alloy material, 42 alloy (42% nickel-iron alloy), or the like is used. The resist layer 160 has a desired resolution,
There is no particular limitation as long as it has etching resistance and good processability. Next, the processing material 110S exposed from the opening 161 of the resist layer is etched from both sides, penetrated, and processed into a desired shape. (FIG. 3 (c)) The lead frame (128 in FIG. 2) is formed by etching while holding the material 110S for processing through the connecting portion (usually the lead extension portion or the tie bar 123 is applied thereto). Are arranged in a two-dimensional manner (arranged in a matrix form) to form an etched substrate 111.
A ferric chloride solution is usually used as the etching solution.
【００２０】次いで、エッチング加工基板１１１の一面
側に樹脂シート１３０Ａを配し、エッチング加工基板１
１１と樹脂シート１３０Ａとを、耐熱性、剛性のあるテ
フロン（登録商標）等の板材１３５間に挟んだ状態で、
真空中で、加熱、加圧して図３（ｄ））、絶縁性の樹脂
１３０をエッチング加工基板１１１の両面間の隙間部に
埋め込んだ後、両面を研磨して、端子部の面、ダイパッ
ドの面を露出させる。（図３（ｅ））
真空中で行なうのは、ボイドの発生を防止するためであ
る。樹脂シートの素材としては、配線基板用の樹脂や封
止用樹脂が用いられ、具体的には、シリカフィラー含有
のＢステージエポキシが挙げられるが、これらに限定は
されない。板材１３５としては、耐熱性、剛性があり、
更に、樹脂１３０と易剥離性であるものが好ましい。研
磨はサンドブラストまたはバフ研磨などの方法で行な
う。これにより、第１の例のリードフレーム部材１００
が作製される。Next, the resin sheet 130A is arranged on one surface side of the etching processed substrate 111, and the etching processed substrate 1
11 and the resin sheet 130A are sandwiched between plate members 135 such as Teflon (registered trademark) having heat resistance and rigidity,
After heating and pressurizing in a vacuum (FIG. 3D), the insulating resin 130 is embedded in the gap between the both surfaces of the etching-processed substrate 111, and then both surfaces are polished to remove the surface of the terminal portion and the die pad. Expose the surface. (FIG. 3 (e)) The reason for performing in a vacuum is to prevent generation of voids. As a material for the resin sheet, a resin for wiring boards and a sealing resin are used, and specific examples thereof include silica filler-containing B-stage epoxy, but are not limited thereto. The plate material 135 has heat resistance and rigidity,
Further, a resin that is easily peelable from the resin 130 is preferable. Polishing is performed by a method such as sandblasting or buffing. Accordingly, the lead frame member 100 of the first example
Is created.
【００２１】次ぎに、実施の形態の第２の例のリードフ
レーム部材を、図１（ｃ）に基づき説明する。第２の例
のリードフレーム部材１００Ａは、第１の例のリードフ
レーム部材１１０の露出した端子部の面、ダイパッド面
に、めっき処理を施したものである。めっき処理として
は、順にＮｉめっき、Ａｕめっき、あるいは、順に粗化
Ｎｉめっき、Ｐｄめっき、薄Ａｕめっきを施すめっき処
理工程を施すものが挙げられるが、これに限定はされな
い。粗化Ｎｉめっき層としては、中心値平均粗度Ｒａが
０. １〜０. ５μｍの範囲であるものがモールド樹脂の
密着性の点で好ましい。尚、本例のリードフレーム部材
は、この後、半導体素子搭載、ワイヤボンディングさ
れ、一括モールドに供される。第２の例のリードフレー
ム部材の製造方法は、勿論、先に述べた図３（ａ）〜図
３（ｅ）の工程にて、第１の例のリードフレーム部材１
００を形成し、更に、露出した端子部の面、ダイパッド
面に、めっき処理を施して形成する。（図３（ｆ））Next, the lead frame member of the second example of the embodiment will be described with reference to FIG. The lead frame member 100A of the second example is one in which the surface of the exposed terminal portion and the die pad surface of the lead frame member 110 of the first example are plated. Examples of the plating treatment include, but are not limited to, a plating treatment step in which Ni plating, Au plating, or roughened Ni plating, Pd plating, and thin Au plating are sequentially performed. The roughened Ni plating layer preferably has a center value average roughness Ra in the range of 0.1 to 0.5 μm from the viewpoint of the adhesiveness of the mold resin. The lead frame member of this example is then mounted with a semiconductor element, wire-bonded, and subjected to batch molding. The method of manufacturing the lead frame member of the second example is of course the same as the lead frame member 1 of the first example in the steps of FIGS. 3 (a) to 3 (e) described above.
No. 00 is formed, and the exposed surface of the terminal portion and the die pad surface are plated. (Fig. 3 (f))
【００２２】次に、本発明の半導体パッケージの実施の
形態の１例を、図４（ｄ）に基づいて説明する。本例の
半導体パッケージは、ノンリードタイプの薄型の半導体
パッケージＱＦＮで、リードフレームの表裏面間の隙間
部に、リードフレーム固定用、且つ、樹脂封止の際の封
止用樹脂の流れ防止用の樹脂を埋め込んでおり、半導体
素子１７０搭載側を封止用樹脂１８０で封止しているも
ので、図１（ｃ）に示す第２の例のリードフレーム部材
１００Ａを用いて、ダイパッド１２１上にダイボンデイ
ンングし、ワイヤボンディングした後、一括モールドし
て、更に個片化して得たものである。即ち、本例は、図
１（ｃ）に示す第２の例のリードフレーム部材１００Ａ
を用いて、一括モールドタイプの半導体パッケージの製
造方法で作製したものである。封止用樹脂１８０として
は、通常、エポキシ樹脂が用いられるが、これに限定は
されない。Next, an example of the embodiment of the semiconductor package of the present invention will be described with reference to FIG. The semiconductor package of this example is a non-lead type thin semiconductor package QFN, which is used to fix the lead frame in the gap between the front and back surfaces of the lead frame and to prevent the flow of sealing resin during resin sealing. The semiconductor chip 170 mounting side is sealed with the sealing resin 180, and the lead frame member 100A of the second example shown in FIG. It was obtained by die-bonding, wire-bonding it, molding it all at once, and separating it into individual pieces. That is, this example is the same as the lead frame member 100A of the second example shown in FIG.
Is manufactured by a method of manufacturing a collective mold type semiconductor package. An epoxy resin is usually used as the sealing resin 180, but the sealing resin 180 is not limited to this.
【００２３】次いで、本例の半導体パッケージの製造方
法の１例を、図４に基づいて、簡単に、説明する。尚、
これを以って、本発明の半導体パッケージの製造方法の
実施の形態の１例の説明に代える。先ず、図１（ｃ）に
示すリードフレーム部材１００Ａを、既に述べたように
して、作製した後、リードフレーム部材１００Ａのダイ
パッド１２１上にダイボンディングにより半導体素子１
７０を搭載し、ワイヤボンディングを行なう。（図４
（ａ））
この際、樹脂１３０は、リード１２２およびダイパッド
１２１をしっかり固定し、ワイヤボンディングの時の超
音波が有効に働くようにする。次いで、半導体素子１７
０搭載側を、一括モールドする。（図４（ｂ））
この際、樹脂１３０は封止用樹脂の流れを防止する。次
いで、ダイシングソーによりタイバー１２３部の切断を
行ない、個別の半導体パッケージに個片化する。（図４
（ｄ））
このようにして、個別の半導体パッケージＱＦＮが得ら
れる。Next, one example of the method of manufacturing the semiconductor package of this example will be briefly described with reference to FIG. still,
Therefore, the description of one example of the embodiment of the method for manufacturing a semiconductor package of the present invention will be replaced. First, the lead frame member 100A shown in FIG. 1C is manufactured as described above, and then the semiconductor element 1 is formed on the die pad 121 of the lead frame member 100A by die bonding.
70 is mounted and wire bonding is performed. (Fig. 4
(A)) At this time, the resin 130 firmly fixes the leads 122 and the die pad 121 so that ultrasonic waves at the time of wire bonding work effectively. Then, the semiconductor element 17
Mold the 0 mounting side at once. (FIG. 4B) At this time, the resin 130 prevents the sealing resin from flowing. Next, the tie bar 123 is cut with a dicing saw to be separated into individual semiconductor packages. (Fig. 4
(D)) In this way, individual semiconductor packages QFN are obtained.
【００２４】上記の各実施の形態は、ＱＦＮ用のリード
フレーム部材とその製造方法、及びＱＦＮ型半導体パッ
ケージとその製造方法について記したが、これに限定は
されない。また、本発明は、上記実施の形態例に限定さ
れるものではない。In each of the above-mentioned embodiments, the lead frame member for QFN and its manufacturing method, and the QFN type semiconductor package and its manufacturing method have been described, but the present invention is not limited to this. Further, the present invention is not limited to the above-mentioned embodiments.
【００２５】[0025]
【実施例】（実施例１）実施例１は、図３に示すように
して、実施の形態の第１のリードフレーム部材を作製
し、これにめっき処理を施して、実施の形態の第２のリ
ードフレーム部材を作製し、該第２のリードフレーム部
材を用い、図４のようにして、実施の形態例のＱＦＮを
作製したものである。図３、図４に基づいて、実施例の
製造工程を説明する。先ず、古河電工製の銅合金材ＥＦ
ＴＥＣ−６４Ｔ、１／２Ｈ、０. １５ｍｍ厚材（図３
（ａ））の表面にカゼインレジストを配設し、所定の１
対のパターン版を用いその両面から表裏位置合せして密
着露光し、現像処理を行ない、両面に、所定のパターン
にレジスト層１６０を形成した。（図３（ｂ））
次いで、塩化第二鉄液（４１ボーメ）にて両面からスプ
レーエッチングを行ない、貫通させ、所定形状にエッチ
ング加工された、エッチング加工基板１１１を得た。
（図３（ｃ））
次いで、レジスト層１６０を除去後、エッチング加工基
板１１１の一面側に、シリカフィラー含有のＢステージ
エポキシからなるの樹脂シート１３０Ａをを配し、エッ
チング加工基板１１１と樹脂シート１３０Ａとを、耐熱
性、剛性のあるテフロン（登録商標）からなる板材１３
５間に挟んだ状態で、真空中で、加熱、加圧して（図３
（ｄ））、樹脂１３０をエッチング加工基板１１１の両
面間の隙間部に埋め込んだ後、更に、両面を研磨して、
端子部の面、ダイパッドの面を露出させた。（図３
（ｅ））
この状態が実施の形態の第１のリードフレーム部材１０
０に相当する。EXAMPLES Example 1 In Example 1, as shown in FIG. 3, the first lead frame member of the embodiment was produced, plated with this, and then the second lead frame member of the embodiment was formed. 4 is manufactured, and the second lead frame member is used to manufacture the QFN of the embodiment as shown in FIG. The manufacturing process of the embodiment will be described with reference to FIGS. First, the copper alloy material EF made by Furukawa Electric
TEC-64T, 1 / 2H, 0.15mm thick material (Fig. 3
A casein resist is provided on the surface of (a)), and a predetermined 1
Using a pair of pattern plates, the front surface and the back surface were aligned and contact exposure was performed, and development processing was performed to form a resist layer 160 in a predetermined pattern on both surfaces. (FIG. 3 (b)) Next, spray etching was performed from both sides with a ferric chloride solution (41 Baume) to penetrate, and etching-processed substrate 111 obtained by etching processing into a predetermined shape was obtained.
(FIG. 3C) Next, after removing the resist layer 160, a resin sheet 130A made of B-stage epoxy containing silica filler is arranged on one surface side of the etching processed substrate 111, and the etching processed substrate 111 and the resin sheet are formed. 130A is a plate material 13 made of Teflon (registered trademark) having heat resistance and rigidity.
In the state of being sandwiched between the five, it is heated and pressurized in a vacuum (Fig. 3
(D)), after embedding the resin 130 in the gap between the both surfaces of the etching-processed substrate 111, further polishing both surfaces,
The surface of the terminal portion and the surface of the die pad were exposed. (Fig. 3
(E)) This state is the first lead frame member 10 of the embodiment.
Equivalent to 0.
【００２６】次いで、表裏の露出した端子部の面、ダイ
パッド面に、順にＮｉめっき、Ａｕめっきを施した。順
に、ニッケルめっき層、金めっき層を、それぞれ、２μ
ｍ、０. ５μｍ厚に形成した。ニッケルめっきは、ＷＨ
Ｎめっき液（日本高純度化学社製）を用い、温度５０
℃、電流密度１Ａ／ｄｍ2 で、金めっきは、テンペレジ
ストＫ−９１Ｓ（日本高純度化学社製）を用い、温度６
０℃、電流密度０. ４Ａ／ｄｍ2 で行った。（図３
（ｆ））
この状態が実施の形態の第２のリードフレーム部材１０
０Ａに相当する。次いで、ダイボンディングにより半導
体素子１７０を搭載し、ワイヤボンディングを行った
（図４（ａ））後、半導体素子１７０搭載側をエポキシ
樹脂にて、一括封止した。（図４（ｂ））
更に、ダイシングソーにより切断して（図４（ｃ））、
個片化したＱＦＮを得た。（図４（ｄ））Next, the exposed surface of the terminal portion on the front and back surfaces and the die pad surface were sequentially plated with Ni and Au. 2μ of nickel plating layer and 2μm of gold plating layer respectively.
m and 0.5 μm in thickness. Nickel plating is WH
Using N plating solution (manufactured by Nippon Kojundo Chemical Co., Ltd.), temperature 50
At a temperature of 1 ° C. and a current density of 1 A / dm 2 , the tempering was performed at a temperature of 6 using a temper resist K-91S (manufactured by Nippon Kojundo Chemical Co., Ltd.).
It was carried out at 0 ° C. and a current density of 0.4 A / dm 2 . (Fig. 3
(F)) This state is the second lead frame member 10 of the embodiment.
Equivalent to 0A. Next, the semiconductor element 170 was mounted by die bonding, wire bonding was performed (FIG. 4A), and then the semiconductor element 170 mounting side was collectively sealed with an epoxy resin. (FIG. 4 (b)) Further, cutting with a dicing saw (FIG. 4 (c)),
Individualized QFN was obtained. (Fig. 4 (d))
【００２７】（実施例２）実施例２は、実施例１におい
て、作製した第１のリードフレーム部材１００の表裏の
露出した端子部の面、ダイパッド面に施した、Ｎｉめっ
き、Ａｕめっきに代え、作製した第１のリードフレーム
部材１００の表裏の露出した端子部の面、ダイパッド面
に、順に、粗化Ｎｉめっき、Ｐｄめっき、薄Ａｕめっき
を、それぞれ、３μｍ、０. １μｍ、０. ０１μｍ施し
たもので、それ以外は、同じである。尚、ニッケルめっ
きは、ＷＨＮめっき液（日本高純度化学社製）を用い、
温度５０℃、電流密度２. ５Ａ／ｄｍ2 の条件で針状の
粗化めっきを行ない、パラジウムめっきは、日本高純度
化学社製パラブライトＳＳＴＬ浴を用い、温度４０℃、
電流密度３. ５Ａ／ｄｍ2 で行ない、金めっきは、ＥＥ
ＪＡ製Ａｕめっき浴（テンペレックス４０１）を用い、
温度６０℃、電流密度０. ５Ａ／ｄｍ2 で行った。(Example 2) Example 2 is the same as Example 1 except that the surface of the exposed terminal portion on the front and back of the produced first lead frame member 100 and the die pad surface were replaced with Ni plating and Au plating. Rough Ni plating, Pd plating, and thin Au plating were sequentially applied to the exposed surface of the front and back terminals of the first lead frame member 100 and the die pad surface, respectively, of 3 μm, 0.1 μm, and 0.01 μm. Other than that, it is the same. For nickel plating, a WHN plating solution (manufactured by Nippon Kojundo Chemical Co., Ltd.) is used.
Needle-like roughening plating is performed under conditions of a temperature of 50 ° C. and a current density of 2.5 A / dm 2 , and palladium plating is performed using a Parabright SSTL bath manufactured by Nippon Kojundo Chemical Co., Ltd. at a temperature of 40 ° C.
The current density was 3.5 A / dm 2 , and the gold plating was EE
Using JA Au plating bath (Temperex 401),
It was carried out at a temperature of 60 ° C. and a current density of 0.5 A / dm 2 .
【００２８】[0028]
【発明の効果】本発明は、上記のように、一括モールド
タイプの半導体パッケージの製造工程で、従来必要とさ
れた固定用、且つ、樹脂封止の際の封止用樹脂の流れ防
止用の裏面テープを不要とし、従来の問題点を解決でき
る工程の半導体パッケージの製造方法の提供を可能とし
た。同時に、そのような半導体パッケージの製造方法に
用いられるリードフレーム部材の提供を可能とした。As described above, according to the present invention, in the manufacturing process of the collective mold type semiconductor package, the fixing resin, which is conventionally required, and the flow of the sealing resin at the time of resin sealing are prevented. It is possible to provide a method for manufacturing a semiconductor package that eliminates the need for a backside tape and solves the conventional problems. At the same time, it is possible to provide a lead frame member used in such a semiconductor package manufacturing method.
【図１】図１（ａ）は本発明のリードフレーム部材の実
施の形態の第１の例の概略平面図で、図１（ｂ）は図１
（ａ）のＡ１−Ａ２における断面の一部を示した図で、
図１（ｃ）は、図１（ａ）は本発明のリードフレーム部
材の実施の形態の第２の例の一部断面図である。1 (a) is a schematic plan view of a first example of an embodiment of a lead frame member of the present invention, and FIG. 1 (b) is FIG.
(A) is a view showing a part of a cross section taken along line A1-A2 of FIG.
FIG. 1C is a partial cross-sectional view of the second example of the embodiment of the lead frame member of the present invention.
【図２】図１（ａ）に示すリードフレーム部材の中の単
位のリードフレームを拡大して示した平面図である。FIG. 2 is an enlarged plan view showing a unit lead frame in the lead frame member shown in FIG. 1 (a).
【図３】実施の形態の第１の例のリードフレーム部材の
製造方法および第２の例のリードフレーム部材の製造方
法を図示した工程断面図である。FIG. 3 is a process cross-sectional view illustrating the method of manufacturing the lead frame member of the first example and the method of manufacturing the lead frame member of the second example of the embodiment.
【図４】図４（ｄ）は本発明の半導体パッケージの実施
の形態の１例の断面図で、図４（ａ）〜図４（ｄ）は実
施の形態例の半導体パッケージの製造工程の一部を示し
た工程断面図である。FIG. 4D is a cross-sectional view of an example of an embodiment of a semiconductor package of the present invention, and FIGS. 4A to 4D show a manufacturing process of the semiconductor package of the embodiment. It is a process sectional view showing a part.
【図５】一括モールドタイプの半導体パッケージの製造
方法を説明するための図である。FIG. 5 is a diagram for explaining a manufacturing method of a collective mold type semiconductor package.
【図６】個別モールドタイプの半導体パッケージの製造
方法を説明するための図である。FIG. 6 is a diagram illustrating a method for manufacturing an individual mold type semiconductor package.
【図７】ＱＦＮを説明するための図である。FIG. 7 is a diagram for explaining QFN.
【図８】従来のＱＦＮの製造方法を説明するための工程
断面図である。FIG. 8 is a process sectional view for explaining a conventional method for manufacturing a QFN.
１００、１００Ａ リードフレーム部材
１１０ フレーム
１１０Ｓ 加工用素材
１１１ エッチング加工基板
１２０ 単位の部材
１２０ａ 単位のリードフレーム
１２１ ダイパッド
１２２ リード
１２３ タイバー
１２４ 吊りリード
１２８ リードフレーム
１３０ （絶縁性の）樹脂
１３０Ａ 樹脂シート
１３５ 板材
１５０ めっき層
１６０ レジスト層
１６１ 開口部
１７０ 半導体素子
１７１ ボンディングワイヤ
１８０ 封止用樹脂
５１０ フレーム
５２０ 単位部
５２０Ａ 半導体パッケージ
５２０Ｌ モールドキャビティ
５２０Ｇ グリッドリード
５３１ ダイパッド
５３２ リード
５４０ 半導体素子
５４１ ボンディングワイヤ
５５０ 封止樹脂
６１０ フレーム
６２０ モールドキャビティ（単位
部でもある）
６２０Ａ 半導体パッケージ
６３１ ダイパッド
６３２ リード
６４０ 半導体素子
６４１ ボンディングワイヤ
６５０ 封止樹脂
７１０ リードフレーム
７１１ ダイパッド
７１２ リード
７１３ 吊りリード
７２０ 半導体素子
７３０ ボンディングワイヤ
７４０ 封止用樹脂
８１０ リードフレーム
８１１ ダイパッド
８１２ リード
８２０ た固定用テープ
８３０ 半導体素子
８４０ ボンディングワイヤ
８５０ 封止用樹脂100, 100A Lead frame member 110 Frame 110S Processing material 111 Etching substrate 120 Unit member 120a Unit lead frame 121 Die pad 122 Lead 123 Tie bar 124 Hanging lead 128 Lead frame 130 (Insulating) resin 130A Resin sheet 135 Plate material 150 Plating layer 160 Resist layer 161 Opening 170 Semiconductor element 171 Bonding wire 180 Sealing resin 510 Frame 520 Unit 520A Semiconductor package 520L Mold cavity 520G Grid lead 531 Die pad 532 Lead 540 Semiconductor element 541 Bonding wire 550 Sealing resin 610 Frame 620 Mold cavity (also a unit) 620A Semiconductor package 631 Die pad 632. 640 semiconductor element 641 bonding wire 650 sealing resin 710 lead frame 711 die pad 712 lead 713 suspension lead 720 semiconductor element 730 bonding wire 740 sealing resin 810 lead frame 811 die pad 812 lead 820 fixing tape 830 semiconductor element 840 bonding Wire 850 resin for encapsulation
フロントページの続き Ｆターム(参考） 5F067 AA01 AA09 AB00 BD05 CC07 DA16 DA17 DA18 DC18 DC19 DE14 Continued front page F term (reference) 5F067 AA01 AA09 AB00 BD05 CC07 DA16 DA17 DA18 DC18 DC19 DE14
Claims (14)
の製造方法により、ノンリードタイプの薄型の半導体パ
ッケージを製造するための、一括モールドタイプ用のリ
ードフレーム部材であって、リードフレームを複数配列
したフレームを有し、該フレームの各リードフレームの
表裏面間の隙間部に、リードフレーム固定用、且つ、樹
脂封止の際の封止用樹脂の流れ防止用の絶縁性の樹脂を
埋め込んでいることを特徴とするリードフレーム部材。1. A lead frame member for a batch mold type, for manufacturing a non-lead type thin semiconductor package by a method for manufacturing a batch mold type semiconductor package, comprising a frame in which a plurality of lead frames are arranged. An insulating resin for fixing the lead frame and for preventing the flow of the sealing resin during resin sealing is embedded in the gap between the front and back surfaces of each lead frame of the frame. Characteristic lead frame member.
実装用配線基板と接続するための端子部の面と、ワイヤ
ボンディングするための端子部の面とを、あるいは、実
装用配線基板と接続するための端子部の面と、ワイヤボ
ンディングするための端子部の面と、ダイパッド面と
を、そのまま露出させて、あるいはめっき処理を施して
露出させていることを特徴とするリードフレーム部材。2. The front and back sides according to claim 1,
The surface of the terminal portion for connecting to the mounting wiring board and the surface of the terminal portion for wire bonding, or the surface of the terminal portion for connecting to the mounting wiring board, and the terminal for wire bonding A lead frame member, wherein the surface of the portion and the die pad surface are exposed as they are or by performing a plating treatment.
は、順にＮｉめっき、Ａｕめっき、あるいは、順に粗化
Ｎｉめっき、Ｐｄめっき、薄Ａｕめっきを施すものであ
ることを特徴とするリードフレーム部材。3. The lead frame member according to claim 1, wherein the plating treatment is performed by sequentially performing Ni plating, Au plating, or roughening Ni plating, Pd plating, and thin Au plating. .
粗度Ｒａが０. １〜０. ５μｍの範囲であることを特徴
とするリードフレーム部材。4. The lead frame member according to claim 3, wherein the center value average roughness Ra is in the range of 0.1 to 0.5 μm.
の製造方法により、ノンリードタイプの薄型の半導体パ
ッケージを製造するための、一括モールドタイプ用のリ
ードフレーム部材で、リードフレームを複数配列したフ
レームを有し、該フレームの各リードフレームの表裏面
間の隙間部に、リードフレーム固定用、且つ、樹脂封止
の際の封止用樹脂の流れ防止用の絶縁性の樹脂樹脂を埋
め込んでいるリードフレーム部材を、製造するための、
リードフレーム部材の製造方法であって、順に、（ａ）
加工用素材に繋ぎ部を介して保持させた状態で、エッチ
ング加工により、リードフレームを多数、二次元的に配
列して（マトリックス状に配列して）、エッチング加工
基板を形成する、エッチング加工工程と、（ｂ）エッチ
ング加工基板の表裏面間の隙間部に絶縁性の樹脂を埋め
込む、樹脂埋め込み工程と、（ｃ）表裏面を研磨して、
加工用素材面を露出させる研磨処理工程とを行なうこと
を特徴とするリードフレーム部材の製造方法。5. A lead frame member for a batch mold type for manufacturing a non-lead type thin semiconductor package by a batch mold type semiconductor package manufacturing method, comprising a frame in which a plurality of lead frames are arranged. A lead frame member in which an insulating resin resin for fixing the lead frame and for preventing the flow of the sealing resin at the time of resin sealing is embedded in a gap between the front and back surfaces of each lead frame of the frame. For manufacturing
A method for manufacturing a lead frame member, which comprises:
An etching process in which a large number of lead frames are two-dimensionally arranged (arranged in a matrix) by etching while being held by the processing material via the connecting portion to form an etching-processed substrate. And (b) a resin embedding step of embedding an insulating resin in the gap between the front and back surfaces of the etched substrate, and (c) polishing the front and back surfaces,
A method of manufacturing a lead frame member, which comprises performing a polishing treatment step of exposing a processing material surface.
エッチング加工基板の一面側に樹脂シートを配し、エッ
チング加工基板と樹脂シートとを、耐熱性、剛性のある
板材間に挟んだ状態で、真空中で、加熱、加圧して、埋
め込むものであることを特徴とするリードフレーム部材
の製造方法。6. The resin embedding step according to claim 5,
A resin sheet is arranged on one side of an etched substrate, and the etched substrate and the resin sheet are embedded in a state of being sandwiched between heat-resistant and rigid plate materials by heating and pressing in a vacuum. A method for manufacturing a lead frame member, comprising:
程後に、露出した表裏の加工用素材の露出部に、接続用
あるいはダイボンディング用のめっき処理を施すことを
特徴とするリードフレーム部材の製造方法。7. The lead frame member according to claim 5, wherein after the polishing treatment step, the exposed exposed portions of the processing material on the front and back sides are subjected to a plating treatment for connection or die bonding. Method.
が、表裏の加工用素材の露出部に、順にＮｉめっき、Ａ
ｕめっき、あるいは、順に粗化Ｎｉめっき、Ｐｄめっ
き、薄Ａｕめっきを施すめっき処理工程を施すものであ
ることを特徴とするリードフレーム部材の製造方法。8. The plating treatment according to claim 5, wherein the exposed portions of the processing material on the front and back sides are plated with Ni and A, respectively.
A method of manufacturing a lead frame member, which comprises performing a plating treatment step of performing u plating, or roughening Ni plating, Pd plating, and thin Au plating in this order.
粗度Ｒａが０. １〜０. ５μｍの範囲であることを特徴
とするリードフレーム部材の製造方法。9. The method of manufacturing a lead frame member according to claim 8, wherein the center value average roughness Ra is in the range of 0.1 to 0.5 μm.
ケージであって、リードフレームの表裏面間の隙間部
に、リードフレーム固定用、且つ、樹脂封止の際の封止
用樹脂の流れ防止用の絶縁性の樹脂を埋め込んでいるこ
とを特徴とする半導体パッケージ。10. A non-lead type thin semiconductor package for fixing a lead frame in a gap between front and back surfaces of a lead frame and for preventing a flow of a sealing resin at the time of resin sealing. A semiconductor package having an insulating resin embedded therein.
ジの製造方法により、リードフレームの表裏面間の隙間
部に、リードフレーム固定用、且つ、樹脂封止の際の封
止用樹脂の流れ防止用の絶縁性の樹脂を埋め込んでいる
ノンリードタイプの薄型の半導体パッケージの製造方法
であって、順に、（Ａ）加工用素材に繋ぎ部を介して保
持させた状態で、エッチング加工により、リードフレー
ムを多数、二次元的に配列して（マトリックス状に配列
して）、エッチング加工基板を形成する、エッチング加
工工程と（Ｂ）エッチング加工基板の表裏面間の隙間部
に絶縁性の樹脂を埋め込む、樹脂埋め込み工程と、
（Ｃ）表裏面を研磨して、加工用素材面を露出させる研
磨工程と、（Ｄ）表裏の加工用素材の露出部に、接続用
あるいはダイボンディング用のめっき処理を施すめっき
処理工程と、（Ｅ）半導体素子を搭載する処理、および
半導体素子の端子とリードフレームのリード端子とを接
続する処理を行なう半導体素子組み立て工程と、（Ｆ）
半導体素子搭載側を樹脂封止する樹脂封止工程と、
（Ｇ）切断により個別の半導体パッケージに個片化する
切断処理とを行なうことを特徴とする半導体パッケージ
の製造方法。11. An insulation for fixing the lead frame and for preventing the flow of a sealing resin at the time of resin sealing in a gap between the front and back surfaces of the lead frame by a manufacturing method of a collective mold type semiconductor package. A method for manufacturing a non-lead type thin semiconductor package in which a conductive resin is embedded, in which (A) a plurality of lead frames are etched by etching while being held by a processing material through a connecting portion. , Two-dimensionally arranged (arranged in a matrix form) to form an etched substrate, and (B) an insulating resin embedded in a gap between the front and back surfaces of the etched substrate, a resin Embedding process,
(C) a polishing step of polishing the front and back surfaces to expose the processing material surfaces, and (D) a plating processing step of performing plating processing for connection or die bonding on the exposed portions of the processing materials on the front and back surfaces. (E) a semiconductor element assembling step of performing a step of mounting a semiconductor element and a step of connecting a terminal of the semiconductor element and a lead terminal of a lead frame;
A resin sealing step of sealing the semiconductor element mounting side with resin,
(G) A method of manufacturing a semiconductor package, which is characterized in that a cutting process is performed so that the semiconductor package is separated into individual semiconductor packages by cutting.
て工程は、半導体素子を搭載する処理がダイボンディン
グ処理で、半導体素子の端子とリードフレームのリード
端子とを接続する処理がワイヤボンディング処理である
ことを特徴とする半導体パッケージの製造方法。12. The semiconductor element assembling step according to claim 11, wherein the step of mounting the semiconductor element is a die bonding step, and the step of connecting a terminal of the semiconductor element and a lead terminal of a lead frame is a wire bonding step. A method of manufacturing a characteristic semiconductor package.
き処理が、表裏の加工用素材の露出部に、順にＮｉめっ
き、Ａｕめっき、あるいは、順に粗化Ｎｉめっき、Ｐｄ
めっき、薄Ａｕめっきを施すめっき処理工程を施すもの
であることを特徴とする半導体パッケージの製造方法。13. The plating process according to claim 11, wherein the exposed portions of the processing material on the front and back sides are Ni-plated, Au-plated, or roughened Ni-plated, Pd in order.
A method of manufacturing a semiconductor package, which comprises performing a plating treatment step of performing plating and thin Au plating.
平均粗度Ｒａが０.１〜０. ５μｍの範囲であることを
特徴とする半導体パッケージの製造方法。14. The method for manufacturing a semiconductor package according to claim 13, wherein the center value average roughness Ra is in the range of 0.1 to 0.5 μm.
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|---|---|---|---|
| JP2002112642A JP2003309241A (en) | 2002-04-15 | 2002-04-15 | Lead frame member and manufacturing method thereof, and semiconductor package employing the lead frame member and manufacturing method thereof |
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| WO2010038450A1 (en) * | 2008-09-30 | 2010-04-08 | 凸版印刷株式会社 | Leadframe substrate and method for manufacturing same |
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