JP2003304142A - Oscillation circuit, delay circuit and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an oscillation circuit and electronic equipment capable of shortening a delay time at the time of executing a test. <P>SOLUTION: One external terminal 128 connected to an oscillation circuit is put in an open status, and transistors 109 and 119 are controlled to limit currents flowing in capacitors 106, 107, 116 and 117 so that the normal oscillation frequency of the oscillation circuit can be outputted. Furthermore, a power supply voltage is inputted to the external terminal 128 connected to the oscillation circuit to control the transistors 109 and 119 so that currents flowing in the capacitors 106, 107, 116 and 117 can be increased. Thus, it is possible to output the oscillation frequency for shortening the delay time of a delay circuit. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillation circuit capable of adjusting an oscillation frequency and a delay circuit capable of setting a delay time by dividing the oscillation frequency of an internal oscillation circuit by a frequency dividing circuit. Regarding

[0002]

2. Description of the Related Art Conventionally, it takes a very long time to measure a delay time in an integrated circuit having a built-in delay circuit, especially to measure a delay time of several seconds or more. As a result, the cost increases due to the time-consuming testing of shipping inspection.

Therefore, in order to shorten the test time, an external terminal is provided, and a delay time is shortened by forcibly inputting a waveform with a high oscillation frequency to the external terminal from a separately prepared oscillator to shorten the test time. Was. A method for reducing the test time will be described with reference to FIG. In the configuration of the conventional delay circuit, as shown in FIG. 5, the signal output from the oscillation circuit 501 is input to the frequency dividing circuit 502, and a delay signal is output from 503 after a desired delay time.

In the circuit of this configuration, in order to reduce the delay time, an oscillation frequency higher than the oscillation frequency output from the oscillation circuit 501 is input from the external terminal 504, and the signal is input to the frequency dividing circuit 502. The delay time is shortened. That is, instead of changing the oscillation frequency of the internal oscillation circuit 501 such as by decreasing it, the delay time is shortened and the test time is shortened by using a separately prepared oscillator.

Therefore, a conventional oscillator circuit is shown in FIG. 3 and its operation will be described. First, Nch transistor 304
Consider from the state where is OFF. At this time, in the mirror circuit configured by the Pch transistor 301 and the Pch transistor 303, a current having a magnitude determined by the constant current source 319 and the mirror ratio flows into the capacitor 305 to charge the capacitor 305. When the capacitor 305 is charged and rises to a potential for turning on the Nch transistor 307, the output signal of the inverter circuit 308 changes from Lo to H.
In place of i, the Nch transistor 310 is turned on. When the Nch transistor is turned on, a current having a magnitude determined by the constant current source 319 and the mirror ratio flows into the capacitor 311 in the mirror circuit composed of the Pch transistor 301 and the Pch transistor 309 to discharge the accumulated charge. Then, Pch transistor 314 and N
The output signal of the inverter circuit composed of the ch transistor 315 changes from Hi to Lo. This signal is on terminal 3
16 is sent to the frequency dividing circuit and at the same time the inverter circuit 3
It is input to 04. Since Hi is output when Lo is input to the inverter circuit 304, the Nch transistor 304 is turned on and the electric charge stored in the capacitor 305 is discharged. Then, the Nch transistor 307 is turned off this time, and the output of the inverter circuit 308 becomes Lo,
The capacitor 311 is charged and the Nch transistor 312 is charged.
Rises to the potential to turn on. As a result, the output signal of the inverter circuit composed of the Pch transistor 314 and the Nch transistor 315 is changed from Lo to Hi, the Hi signal is sent from the terminal 316 to the frequency dividing circuit, and at the same time the Hi signal is input to the inverter circuit 304. To be done. By repeating the above operation, the terminal 316 or H
An oscillation signal in which i and Lo are repeated is output.

The oscillation signal output from this oscillation circuit is
It is input to the frequency dividing circuit and produces a delayed signal of the time set by the frequency dividing circuit.

Here, the oscillation period T is generally expressed as T = CV / I (1) where C is a capacitance, V is an inversion voltage for turning on the next stage transistor, and I is a current flowing into the capacitance C. Therefore, from the equation (1), the oscillation cycle T is determined by the values of three variables: the capacitance C, the inversion voltage for turning on the next-stage transistor V, and the current I flowing into the capacitance C. Conventionally, as shown in FIG. 5, in order to shorten the test time, a signal having a short oscillation signal cycle, that is, a high oscillation frequency is forcedly forced from the external terminal 504 of the IC to the oscillation circuit 50.
The delay time is shortened by inputting a signal having an oscillation frequency higher than 1 to the frequency dividing circuit 502 (for example,
See Patent Document 1. ).

[0008]

[Patent Document 1] Japanese Unexamined Patent Publication No. 2002-252930
(Sections 2-4, FIG. 1)

[0009]

Conventionally, in order to shorten the test time, in order to shorten the delay time, an oscillator is prepared from an external terminal and is forcibly output from the oscillation circuit inside the IC. The delay time has been shortened by inputting a frequency higher than the oscillation frequency. As described above, there is a problem that it is necessary to separately provide an oscillator and the configuration of the IC becomes complicated.

[0010]

In order to solve the problems described above, the delay time is shortened at the time of testing when VDD is input to the external terminal. That is, when VDD is input to the external terminal in the oscillation circuit inside the IC, the amount of current charged in the capacitor is increased, and
The delay time is shortened by switching the capacitance value of this capacitor to a value smaller than that during normal oscillation.

The oscillator circuit according to the present invention is connected between the VDD terminal, the GND terminal, the VDD terminal and the GND terminal, and is charged by the current flowing between the VDD terminal and the GND terminal, and the charging is performed. A first capacitor that sets the oscillation frequency according to time. further,
A second capacitor connected in parallel with the first capacitor; a first transistor connected in series with the second capacitor for adjusting a current flowing through the second capacitor; An external terminal to which a signal for controlling the transistor is input, and an output terminal that outputs an oscillation frequency determined by the first and second capacitors.

Further, in the oscillator circuit according to the present invention, the first capacitor is connected in series between the VDD terminal and the GND terminal, and the signal based on the signal of the external terminal is input to the gate terminal. And a second transistor having the above structure.

A delay circuit according to the present invention is characterized by including the oscillation circuit and a frequency dividing circuit for dividing the output of the oscillation circuit.

An electronic device according to the present invention is characterized by including the delay circuit.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION The embodiments of the present invention increase the amount of current charged in a capacitor when VDD is input to an external terminal in an oscillation circuit inside an IC, and
The delay time is shortened by switching the capacitance value of this capacitor to one smaller than that during normal oscillation. Hereinafter, examples will be described in detail.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS As a first embodiment, FIG. 1 shows an oscillator circuit of the present invention. The operation of the oscillator circuit of the present invention will be described with reference to FIG. Here, 130 is a VDD terminal and 129 is GND.
It is a terminal.

First, the Nch transistor 104 is OF
Think from the state of being F. At this time, in the mirror circuit composed of the Pch transistor 101 and the Pch transistor 103, a current of a magnitude determined by the constant current source 131 and the mirror ratio flows into the capacitors 107 and 108, and the capacitors 107 and 108 are charged. When the capacitors 107 and 108 are charged and rise to a potential for turning on the Nch transistor 111, the output signal of the inverter circuit 112 changes from Lo to H.
In place of i, the Nch transistor 114 is turned on. When the Nch transistor is turned on, a current having a magnitude determined by the constant current source 131 and the mirror ratio flows into the capacitors 116 and 117 in the mirror circuit composed of the Pch transistor 101 and the Pch transistor 113 to discharge the accumulated charge. Then, the output signal of the inverter circuit including the Pch transistor 125 and the Nch transistor 126 changes from Hi to Lo. This signal is sent from the terminal 127 to the frequency dividing circuit and simultaneously input to the inverter circuit 102. Since Hi is output when Lo is input to the inverter circuit 102, the Nch transistor 104 is turned on and the capacitor 1
07 and the electric charge stored in the capacitor 108 are discharged.
Then, the Nch transistor 111 is turned off this time,
The output of the inverter circuit 112 becomes Lo, the capacitors 116 and 117 are charged, and the potential rises to the potential at which the Nch transistor 123 is turned on. as a result,
Pch transistor 125 and Nch transistor 126
The output signal of the inverter circuit consisting of Lo to H
The signal i changes to i, the Hi signal is sent from the terminal 127 to the frequency dividing circuit, and at the same time, the Hi signal is input to the inverter circuit 102. By repeating the above operation, the terminal 127
To output an oscillation signal in which Hi and Lo are repeated.

The oscillation signal output from this oscillation circuit is
It is input to the frequency dividing circuit and produces a delayed signal of the time set by the frequency dividing circuit.

Up to this point, the operation is similar to that of the conventional oscillator circuit. Here, in order to increase the oscillation frequency, the external terminal 1
No. 28 is provided, and when this terminal is open, normal oscillation is performed, and when VDD is applied, a higher oscillation frequency than in normal times can be generated.

Since the external terminal 128 is normally open, the input of the inverter 120 is pulled down by the depletion type Nch transistor 122.
Since it becomes Lo, the output becomes Hi. As a result, Pch
The transistor 109 and the Pch transistor 119 are OF
F, Nch transistor 108 and Nch transistor 1
Since 18 is in the ON state, the Pch transistor 10
In the mirror circuit composed of 1 and the Pch transistor 103, a current having a magnitude determined by the constant current source 131 and the mirror ratio flows into the capacitors 107 and 108.
In the mirror circuit composed of the Pch transistor 101 and the Pch transistor 113, a current having a magnitude determined by the constant current source 131 and the mirror ratio is generated by the capacitor 116.
And flows into the capacitor 117.

On the other hand, in order to shorten the delay time, VDD is applied to the external terminal 128 when increasing the oscillation frequency. Then, since the output of the inverter circuit 120 outputs Lo, the Pch transistor 109 and the Pch transistor 119 are turned on, and the Nch transistor 108 and the Nch transistor 118 are turned off. As a result, in the mirror circuit composed of the Pch transistor 101 and the Pch transistor 103, a current of a magnitude determined by the constant current source 131 and the mirror ratio flows only into the capacitor 107,
Further, in the mirror circuit composed of the Pch transistor 101 and the Pch transistor 105, a current having a magnitude determined by the constant current source 131 and the mirror ratio also flows into the capacitor 107. Further, in the mirror circuit composed of the Pch transistor 101 and the Pch transistor 113, a current of a magnitude determined by the constant current source 131 and the mirror ratio flows only into the capacitor 117, and further the mirror circuit composed of the Pch transistor 101 and the Pch transistor 115. Therefore, a current having a magnitude determined by the constant current source 131 and the mirror ratio also flows into the capacitor 117.

Here, the capacitor 106 and the capacitor 1
Regarding the size relationship of 07, the size of the capacitor 107 is 1/10 of the size of the capacitor 106, and similarly, the size of the capacitor 117 is 1/10 of the size of the capacitor 118.
It was. Further, assuming that the charging current flows into these capacitors 10 times as much as in the normal time, T = C × (1/10) V / (I × 10) (3) = CV / (I × 100) And the oscillation cycle is about 1/100, so about 100
A double oscillation frequency will be obtained.

This increased oscillation frequency is input to the frequency dividing circuit as shown in FIG. 4, the delay time is shortened, and the time required for the test is shortened. For example, the oscillation cycle is 2
When the frequency of 50 μs is divided by a 12-stage T-type flip-flop circuit or the like, the delay time is about 1 s. When the oscillation frequency is increased 100 times as described above, the delay time becomes 0.01 s, and the delay time can be reduced to 1/100.

As a second embodiment, the delay time can be shortened even in the circuit shown in FIG. In FIG. 2, the delay time is manipulated by switching the transistors having different threshold values instead of switching the capacitance value during acceleration.

In FIG. 2, the operation will be described below assuming that the threshold voltage of the Nch transistors 235 and 237 is Vtnl, the threshold voltage of the Nch transistors 211 and 223 is Vtnm, and Vtnl is smaller than Vtnm.

In a normal state, the external terminal 228 is in an open state, so that the input of the inverter circuit 220 is pulled down by the depletion type Nch transistor 222 and the resistor 221 and becomes Lo. Therefore, the Nch transistors 232 and 233 are turned off, and further the inverter circuit 220 is
Output becomes Hi, so Pch transistors 209 and 219
Is also turned off. As a result, the Nch transistors 235 and 237 having a low threshold voltage are not used and the Nch transistor 21 is not used.
1 and 223 are used to perform the oscillating operation.

Regarding the oscillating operation, the output terminal 227 is obtained by performing the same operation as described below in the first embodiment.
More oscillation signal is output. Therefore, the cycle of the oscillator circuit can be expressed as follows.

T = C × (Vtnm) / I (4) When the oscillation frequency is increased to accelerate the delay time,
VDD is applied to the external terminal 228. Then, contrary to the normal state, since Hi is input to the input of the inverter circuit 220, the output becomes Lo. As a result, as a result, the Nch transistors 211 and 223 are not used, and the Nch transistors 235 and 237 having a low threshold value are used to perform the oscillation operation. Considering the cycle of the oscillation circuit as in the normal state, it can be expressed by the following equation.

T = C × (Vtnl) / I (5) Therefore, according to equations (4) and (5), the cycle becomes (Vtnl) / (Vtnm) during acceleration as compared with the normal time. That is, it can be seen that the oscillation frequency is (Vtnm) / (Vtnl) times higher during acceleration than in normal times. Further, by applying VDD to the external terminal 228 as in the first embodiment, the Pch transistors 209 and 219 are turned on, the Nch transistor 208,
218 is turned off, the capacitors 206 and 216 are not used, the capacitors 207 and 217 are used, and a circuit capable of increasing the amount of current flowing into the capacitors 207 and 217 is added to further increase the oscillation frequency. .

As in the case of the first embodiment, if the capacitance value is set to 1/10 and the current value flowing into the capacitance is set to 10,
The period T of the oscillation frequency is T = C × (1/10) × (Vtnl) / (Vtnm) / (10 × I) (6), and the oscillation period is (Vtnl) / (100 ×
(Vtnm)). For example Vtnl = 0.3V, V
When tnm = 0.6V, the period of the oscillation frequency can be shortened to 1/200 and the delay time can be reduced to 1/200.

[0031]

According to the present invention configured as described above, the delay time of the delay circuit is shortened at the time of testing without introducing a separate oscillator, and the test time of the electronic device having the delay circuit is shortened. it can.

[Brief description of drawings]

FIG. 1 is a diagram of an oscillator circuit according to a first embodiment of the present invention.

FIG. 2 Embodiment 2 Oscillation circuit of the present invention

FIG. 3 Conventional oscillator circuit

FIG. 4 is a schematic diagram of a delay circuit of the present invention.

FIG. 5 is a schematic diagram of a conventional delay circuit.

[Explanation of symbols]

101 Pch transistor 102 Inverter circuit 103 Pch transistor 104 Nch transistor 105 Pch transistor 106 capacitor 107 capacitor 108 Nch transistor 109 Pch transistor 110 constant current source 111 Nch transistor 112 Inverter circuit 113 Pch transistor 114 Nch transistor 115 Pch transistor 116 capacitor 117 capacitors 118 Nch transistor 119 Pch transistor 120 inverter circuit 121 resistance 122 Depletion type Nch transistor 123 Nch transistor 124 constant current source 125 Pch transistor 126 Nch transistor 127 output terminals 128 external input terminal 129 GND 130 VDD 131 constant current source 201 Pch transistor 202 Inverter circuit 203 Pch transistor 204 Nch transistor 205 Pch transistor 206 capacitor 207 capacitor 208 Nch transistor 209 Pch transistor 210 constant current source 211 Nch transistor 212 inverter circuit 213 Pch transistor 214 Nch transistor 215 Pch transistor 216 capacitors 217 capacitors 218 Nch transistor 219 Pch transistor 220 inverter circuit 221 resistance 222 Depletion type Nch transistor 223 Nch transistor 224 constant current source 225 Pch transistor 226 Nch transistor 227 output terminal 228 External input terminal 229 GND 230 VDD 231 constant current source 232 Nch transistor 233 Nch transistor 234 Nch transistor 235 Nch transistor 236 Nch transistor 237 Nch transistor 301 Pch transistor 302 Inverter circuit 303 Pch transistor 304 Nch transistor 305 capacitor 306 constant current source 307 Nch transistor 308 Inverter circuit 309 Pch transistor 310 Nch transistor 311 capacitors 312 Nch transistor 313 constant current source 314 Pch transistor 315 Nch transistor 316 output terminal 317 VDD 318 GND 319 Constant current source 401 oscillator circuit 402 frequency divider 403 Delayed signal 404 External terminal 501 oscillation circuit 502 frequency divider 503 delayed signal 504 External terminal

Claims (4)

[Claims] 1. A VDD terminal, a GND terminal, a connection between the VDD terminal and the GND terminal, charging by a current flowing between the VDD terminal and the GND terminal, and an oscillation frequency set by the charging time. A first capacitor, a second capacitor connected in parallel with the first capacitor, a first capacitor connected in series with the second capacitor, and adjusting a current flowing through the second capacitor. And an external terminal to which a signal for controlling the first transistor is input, and an output terminal for outputting an oscillation frequency determined by the first and second capacitors. Oscillation circuit. 2. A second transistor, which is connected between the VDD terminal and the GND terminal in series with the first capacitor and has a gate terminal to which a signal based on a signal from the external terminal is input. The oscillator circuit according to claim 1, wherein: 3. A delay circuit, comprising: the oscillator circuit according to claim 2; and a frequency divider circuit for frequency-dividing an output of the oscillator circuit. 4. An electronic device comprising the delay circuit according to claim 3.