JP2003289146A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent step-disconnection of a second layer-wiring, in a thin film transistor. <P>SOLUTION: Almost triangular insulator are formed at a gate electrode coated with a silicon nitride film 108 and on both sides of wires 105, 106 extending from the electrode. As a result, the difference in level in a gate wiring traverse section is relaxed, thereby the step-disconnection is suppressed at a position, where the second layer-wiring 17 traverses the gate wiring. The semiconductor device, having a first wiring formed on the surface of an insulator, the silicon nitride film provided by coating an upper surface and side of the first wiring, the almost triangular insulator formed so as to contact the side of the first wiring through the silicon nitride film, a first interlayer insulator film formed on the silicon nitride film and the almost triangular insulator and a second wiring formed on the first interlayer insulator film, is such that x-100 [nm]≤y, if the thickness of the first wiring is set to x [nm] and that of the second wiring is set to y [nm]. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulating substrate (in the present specification, refers to an entire object having an insulating surface, and is not limited to insulating materials such as glass, but also to materials such as semiconductors and metals unless otherwise specified. It also means that an insulator layer is formed on the
The present invention relates to an integrated circuit having a thin film insulating gate type semiconductor device (also referred to as a thin film transistor or TFT) formed thereon and a method for forming the integrated circuit. In particular, the present invention relates to a gate electrode
The present invention relates to a wiring material using a material containing a metal material such as aluminum, tantalum, or titanium as a main component.
The semiconductor integrated circuit according to the present invention includes an active matrix circuit such as a liquid crystal display and its peripheral drive circuit, a drive circuit such as an image sensor, an SOI integrated circuit, or a conventional semiconductor integrated circuit (microprocessor, microcontroller, microcomputer, semiconductor, or semiconductor). It is used for memory).

[0002]

2. Description of the Related Art Conventionally, when a circuit such as an active matrix type liquid crystal display device or an image sensor is formed on a glass substrate, a thin film transistor (TF) is used.
A configuration in which T) is integrated and used is widely known. In this case, a method of forming a first-layer wiring including a gate electrode first, then forming an interlayer insulator, and then forming a second-layer wiring is generally used. In some cases, the wirings of the third and fourth layers may be formed. In particular, for the purpose of reducing the resistance of the wiring, it has been attempted to use metal materials such as aluminum, tantalum, and titanium as the wiring material including the first layer.

[0003]

The greatest problem in such an integrated circuit of thin film transistors is that there are two problems in the wiring on the extension of the gate electrode (gate wiring) and the crossing portion (override portion) of the wiring of the second layer. It was a disconnection (also called a step break) of the wiring of the layer. This is because it is difficult to form the interlayer insulator on the gate electrode / wiring with good step coverage and further planarize it. FIG. 4 shows a state of disconnection failure often seen in the conventional TFT integrated circuit. A TFT region 401 and a gate wiring 402 are provided on the substrate, and an interlayer insulator 403 is formed so as to cover them. However, if the edge of the gate wiring 402 is steep, the inter-layer insulator 403 cannot sufficiently cover the gate wiring. When the second-layer wirings 404 and 405 are formed in such a state, the second-layer wiring is broken (stepped) as shown in the figure at the crossover portion 406 of the gate wiring.

In order to prevent such disconnection, it was necessary to increase the thickness of the second layer wiring. For example, it has been desired to make the thickness about twice that of the gate wiring. However, this means that the unevenness of the integrated circuit is further increased, and when it is necessary to further stack wiring on it, disconnection due to the thickness of the second layer wiring must be taken into consideration. . Further, when forming a circuit such as a liquid crystal display in which unevenness of the integrated circuit is not preferred, it is practically impossible to deal with it by increasing the thickness of the second layer wiring. In an integrated circuit, if there is even one step break, the whole becomes defective, so how to reduce the step break is an important issue. It is an object of the present invention to provide a method for reducing such step disconnection defects, and thus increasing the yield of integrated circuits.

[0005]

According to the present invention, after the gate electrode / wiring is formed, the gate electrode / wiring is oxidized at least on the upper surface, preferably on the side surface, by an anodic oxidation method to have a thickness of 100 nm or more, Preferably 150
An oxide coating of about 400 nm is formed, and the upper surface and the side surface thereof are formed by a plasma CVD method or a sputtering method.
A silicon nitride film is formed. After that, an insulator film is formed,
It is characterized in that a substantially triangular insulator (sidewall) is formed on the side surfaces of the gate electrode / wiring by anisotropic etching, an interlayer insulator is deposited, and then a second-layer wiring is formed. Silicon nitride has a low etching rate and can be used as an etching stopper under the condition that silicon oxide, which is a material forming a sidewall, is etched by a dry etching method. By the way, a temperature of 200 ° C. or higher is required to form a silicon nitride film or a silicon oxide film, and a temperature of 300 ° C. or higher is required to form a silicon nitride film. When used as an electrode / wiring, unevenness (hillock) occurs on the surface at this temperature.
Caused a short circuit between layers. The generation of hillocks was suppressed by mixing appropriate impurities into these metal materials, but it was not perfect. In order to completely suppress such hillocks, it is preferable to cover the surface with an anodic oxide film having a thickness of 100 nm or more. This is the reason why the gate electrode / wiring is oxidized by the anodizing method to form the oxide film on the surface.

The method for carrying out the present invention is as follows. First, an island-shaped semiconductor layer is formed. Further, a film to be a gate insulating film is formed thereon. Further, a gate electrode / wiring is formed. At this time, the gate electrode / wiring needs to be formed of a material that is anodized. Then, a positive voltage is applied to the gate electrode / wiring in an approximately neutral electrolytic solution to form an anodic oxide film on at least the upper surface of the gate electrode / wiring. This process is
Alternatively, a vapor phase anodic oxidation method (plasma anodic oxidation method or the like) may be used. Further, silicon nitride is deposited by plasma CVD
To 200 nm, preferably 20 to 100 nm. Here, the film may be formed by another CVD method, a sputtering method, or the like. This is the first stage.

After that, an insulating film is formed on the silicon nitride. Coverability is important in forming this coating, and a thickness of 1/3 to 2 times the height of the gate electrode / wiring is suitable. For this purpose, plasma CVD method and low pressure CV
Chemical vapor deposition (CVD) methods such as D method and atmospheric pressure CVD method are preferable. Then, the insulator thus formed is preferentially etched in a direction substantially perpendicular to the substrate by anisotropic etching. The etching is completed on the surface of the silicon nitride, and the gate electrode / gate insulating film thereunder is not etched. As a result, since the insulator film is originally thick at the step portion such as the side surface of the gate electrode / wiring, the insulator (sidewall) of the roughly triangular castle is formed.
Are left behind. The above is the second stage.

Then, after forming an interlayer insulator, TF
A contact hole is formed in one or both of the source / drain of T and a second layer wiring is formed. Up to this point is the third stage. After forming the sidewalls in the second step, the silicon nitride film may be subsequently etched by dry etching. It is more preferable to perform this etching while observing it with an endpoint monitor or the like. In this silicon nitride film etching step, etching is performed with good controllability using a monitor, and the thickness of the silicon nitride film to be etched is 10 to 200.
Since the thickness is nm, even if there is overetching, the depth is much smaller than the thickness of the gate electrode / gate insulating film, and there is virtually no effect on the gate electrode / gate insulating film. Is. Further, since the anodic oxide film exists under the silicon nitride film, the gate electrode is protected.

As described above, in the method of etching the silicon nitride film, the gate insulating film and the interlayer insulating material are the same material,
Moreover, it is effective when it is not silicon nitride. That is, if the interlayer insulator is formed after etching the silicon nitride film, the etching can be performed in one step when the contact hole is formed. In each of the above steps, T
Various variations are conceivable for performing doping to form the source / drain of the FT. For example, when only an N-channel TFT is formed on the substrate, a relatively high concentration of N-type impurities is self-aligned with the semiconductor layer using the gate electrode as a mask between the first step and the second step. Just install it. In this case, when the anodic oxide coating is also present on the side surface of the gate electrode, a so-called offset gate type is formed in which the source / drain and the gate electrode are separated by the thickness of the anodic oxide. However, in the following description, including such a case, the normal TF
Let us call it T.

Similarly, when forming an N-channel type TFT, a TF having a low concentration drain (LDD) is also formed.
When a T (LDD type TFT) is formed, a relatively low concentration of impurities is introduced into the semiconductor layer between the first step and the second step, and then the second step and the third step are performed. High-concentration N-type impurities may be introduced into the semiconductor layer in a self-aligned manner using the gate electrode and the sidewall as a mask. In this case, the LDD width is approximately the same as the sidewall width. The same applies to the case where only the P-channel TFT is formed on the substrate.

In the case of forming an offset type TFT, a high concentration impurity may be introduced into the semiconductor layer in a self-aligned manner between the second step and the third step by using the gate electrode and the sidewall as a mask. In this case, the width of the offset is substantially the same as the width of the sidewall, and in the TFT having such a structure, the width of the substantially intrinsic region which becomes the channel formation region is equal to the width of the gate electrode on both sides thereof. It is approximately equal to the width of the side wall. A so-called complementary circuit (CMOS circuit) in which N-channel TFTs and P-channel TFTs are mixed on a substrate can be formed in the same manner by using the above method. When both N-channel type TFT and P-channel type TFT are composed of normal TFTs, or both are LDD type TFTs
In order to configure the above, the impurities are introduced by performing the introduction of the impurities in the method of forming only one of the N-channel type TFT or the P-channel type TFT on the substrate as described above for the N-type impurity and the P-type impurity, respectively. Good.

For example, when the N-channel type TFT which requires countermeasures against hot carriers is the LDD type and the P-channel type TFT which does not require it is a normal TFT, the step of introducing impurities becomes slightly special. In that case, the first
A relatively low concentration of N-type impurities is introduced into the semiconductor layer between the step and the second step. This is the first impurity introduction. At this time, N-type impurities may be introduced into the semiconductor layer of the P-channel TFT. Further, the semiconductor layer of the N-channel TFT is masked, and a high-concentration P-type impurity is introduced only into the semiconductor layer of the P-channel TFT. This is the second impurity introduction. Even if N-type impurities are present in the semiconductor layer of the P-channel TFT due to the introduction of the N-type impurities as described above, a higher concentration of P-channel impurities is introduced, resulting in the conductivity type of the semiconductor. Is P-type. Of course, compared to the impurity concentration introduced in the first impurity introduction, that of the second impurity introduction is larger, preferably one to three orders of magnitude larger.

Finally, a relatively high concentration of N-type impurities is introduced between the second and third steps to form the source / drain of the N-channel TFT. This is the third impurity introduction. In this case, P-channel TFT
The impurities may be introduced by masking so that the N-type impurities are not introduced into the mask, or the mask may not be particularly masked. However, in the latter case, the concentration of the N-type impurity introduced needs to be lower than the concentration of the P-type impurity introduced in the second impurity introduction, and preferably the second
The concentration is 1/10 to 2/3 of the P-type impurity concentration of the impurity introduction. As a result, N-type impurities are also introduced into the region of the P-channel TFT, but since the impurity concentration is lower than the concentration of P-type impurities introduced before that, the P-type is maintained.

In the present invention, the presence of the sidewall improves the step coverage of the interlayer insulating material in the portion where the gate wiring is crossed over, and can reduce the disconnection of the second wiring. Further, as described above, it is possible to obtain the LDD structure and the offset region by using the sidewall. In the present invention, the presence of the silicon nitride film is important. In the above second step, anisotropic etching is performed to form sidewalls.
However, it is difficult to control the plasma on the insulating surface, and variations in etching within the substrate are unavoidable.

Further, the etching depth is 1/3 to 2 times the height of the gate electrode / wiring, and the influence of variations becomes very large. If the silicon nitride film is not formed on the upper surface of the gate electrode, even in the same substrate, the gate electrode / gate insulating film may be severely etched depending on the location in the sidewall etching process. There is also. If the silicon nitride film is present during the sidewall etching, the etching is stopped there and the gate electrode and the gate insulating film are protected. After that, when the silicon nitride film is removed by the dry etching method, the etching depth is much smaller than the etching depth of the sidewalls, and the gate electrode / gate insulating film may be over-etched. However, it does not have a great impact. Even if overetched, the gate electrode is completely protected by the presence of the anodic oxide film. Hereinafter, the present invention will be described in more detail with reference to examples.

[0016]

[Embodiment 1] FIG. 1 shows the present embodiment. First,
A base oxide film 102 on a substrate (Corning 7059, 300 mm × 400 mm or 100 mm × 100 mm) 101 having a thickness of 100 to 500 nm, for example, 200
nm silicon oxide film was formed. As a method for forming this oxide film, a sputtering method in an oxygen atmosphere was used. However, in order to improve mass productivity, TEOS is used as plasma CV.
It may be formed by decomposing / depositing by the D method. Further, the silicon oxide film thus formed may be annealed at 400 to 650 ° C.

After that, an amorphous silicon film of 30 to 500 n is formed by plasma CVD or LPCVD.
m, preferably 40 to 100 nm, for example 50 nm, is deposited in a reducing atmosphere at 550 to 600 ° C. for 8 to 2
It was left to stand for 4 hours for crystallization. In that case, a small amount of a metal element such as nickel that promotes crystallization may be added to promote crystallization. Further, this step may be performed by laser irradiation. Then, the crystallized silicon film is etched to form the island-shaped regions 10
Formed 3. Furthermore, as a gate insulating film on this,
A silicon oxide film 104 having a thickness of 70 to 150 nm, for example, 120 nm, was formed by the plasma CVD method.

After that, aluminum (0.1 to 0.3 wt%) having a thickness of 100 nm to 3 μm, for example, 500 nm is used.
Film (including Sc (scandium)) was formed by a sputtering method, and this was etched to form a gate electrode 105 and a gate wiring 106. (FIG. 1 (A)) Then, a current is applied to the gate electrode 105 and the gate wiring 106 in an electrolytic solution to carry out anodization to obtain a thickness of 50 to 250 n.
m, for example, 200 nm of anodic oxide 107 was formed. The electrolytic solution used was prepared by diluting L-tartaric acid in ethylene glycol at a concentration of 5% and adjusting the pH to 7.0 ± 0.2 using ammonia. The substrate 101 is dipped in the solution, the + side of the constant current source is connected to the gate wiring on the substrate, the platinum electrode is connected to the − side, and a voltage is applied in a constant current state of 20 mA, reaching 150 V. Oxidation was continued until. Furthermore, at a constant voltage of 150 V, the voltage is added to 0.
Oxidation was continued until it became 1 mA or less. As a result, a 200 nm thick aluminum oxide film was obtained.

After that, the silicon nitride 108 is deposited to 10 by the plasma CVD method using the NH ₃ / SiH ₄ / H ₂ mixed gas.
To 200 nm, preferably 20 to 100 nm, for example, 50 nm. Although the film may be formed by another CVD method here, it is desirable that the step coverage of the gate electrode is good. After that, the island-shaped silicon film 103 is formed by an ion doping method.
Impurities (phosphorus in this case) were implanted in a self-aligning manner using the gate electrode portion as a mask to form low-concentration impurity regions (LDD) 109 as shown in FIG. Dose amount is 1 × 1
0 ^{13 to} 5 × 10 ¹⁴ atoms / cm ² , acceleration voltage is 10 to 90
kV, for example, the dose amount was 5 × 10 ¹³ atoms / cm ² , and the acceleration voltage was 80 kV. (Fig. 1 (B))

Then, a silicon oxide film 110 was deposited by the plasma CVD method. Here, the source gas is TEO
S and oxygen, or monosilane and nitrous oxide were used.
The optimum value of the thickness of the silicon oxide film 110 differs depending on the height of the gate electrode / wiring. For example, as in this embodiment, the height of the gate electrode / wiring is about 500 n including the silicon nitride film.
In the case of m, 1/3 to 2 times that 200 nm to 1.2
μm is preferred. Here, it is set to 600 nm. In this film forming process, along with the uniformity of the film thickness in the flat portion,
Good step coverage is also required. As a result, the thickness of the silicon oxide film on the side surface of the gate electrode / wiring is increased by the amount shown by the dotted line in FIG.
(Fig. 1 (C))

Next, anisotropic dry etching is carried out by the known RIE method to obtain the silicon oxide film 1.
10 etchings were performed. This etching is completed when the etching reaches the silicon nitride film 108.
Since the silicon nitride film is hard to be etched by anisotropic dry etching by the RIE method, the gate insulating film 104 is not etched. By the above process,
The substantially triangular insulators (sidewalls) 111 and 112 remained on the side surfaces of the gate electrode / wiring. (Fig. 1
(D) After that, phosphorus was again introduced by the ion doping method. In this case, the dose amount is preferably 1 to 3 digits larger than the dose amount in the step of FIG. In this embodiment,
40 times the dose of the first phosphorus doping 2 × 10 ¹⁵
Atom / cm ² . The acceleration voltage was 80 kV. As a result, a region (source / drain) 114 into which a high concentration of phosphorus was introduced was formed, and a low concentration region (LDD) 113 was left below the sidewall. (Fig. 1
(E))

Further, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was irradiated to activate the doped impurities. The energy density of the laser was 200 to 400 mJ / cm ² , preferably 250 to 300 mJ / cm ² . In this example, it is difficult to carry out because the gate electrode / wiring is made of aluminum, which has a problem in heat resistance. However, when the gate electrode is formed using a material having good heat resistance, a laser is used. Instead of irradiation, thermal annealing may be performed. Finally, a silicon oxide film having a thickness of 50 is formed on the entire surface as an interlayer insulator 115 by the CVD method.
0 nm was formed. Then, contact holes were formed in the source / drain of the TFT, and the second-layer aluminum wiring / electrodes 116 and 117 were formed. The thickness of the aluminum wiring is almost the same as the gate electrode / wiring, 400 to 600n
m.

Through the above steps, an N-channel LD
The TFT with D was completed. Hydrogen activation may be further performed at 200 to 400 ° C. to activate the impurity regions. Since the step of the second-layer wiring 117 over the gate wiring 106 is gentle due to the presence of the sidewall 112, the thickness of the second-layer wiring is almost the same as that of the gate electrode / wiring. Regardless of
Almost no breaks were observed. (FIG. 1 (F)) Regarding the thickness of the second layer wiring, as a result of examination by the present inventors, the thickness of the gate electrode / wiring is x [nm] and the thickness of the second layer wiring is y [ nm], if y ≧ x−100 [nm], there was no noticeable disconnection. The smaller the value of y is, the more preferable it is. Particularly in the case of a circuit which requires a small unevenness of the substrate surface such as an active matrix circuit of a liquid crystal display, x-100 [nm] ≤y≤x + 100 [nm] Was found to be suitable.

[Second Embodiment] FIG. 2 shows the present embodiment. The present embodiment relates to a so-called monolithic active matrix circuit in which an active matrix circuit and its drive circuit are simultaneously manufactured on the same substrate. In this embodiment, a P-channel type TFT is used as a switching element of the active matrix circuit, and an N-channel type T is used as a drive circuit.
A complementary circuit composed of FT and P-channel TFT was used. The left side of FIG. 2 is a cross-sectional view of a manufacturing process of an N-channel TFT used in a drive circuit, and the right side of FIG. 2 is a cross-sectional view of a manufacturing process of a P-channel TFT used in a drive circuit and an active matrix circuit. Indicates.
The reason why the P-channel TFT is used as the switching element of the active matrix circuit is that the leak current (also referred to as OFF current) is small.

First, the substrate (Corning 7059) 201
Similar to the first embodiment, the base oxide film 202, the island-shaped silicon semiconductor region, and the silicon oxide film 2 functioning as a gate oxide film are formed above.
03, and gate electrodes 204 and 205 made of an aluminum film (thickness: 500 nm) were formed. After that, the anodic oxide 206 having a thickness of 200 nm was formed around the gate electrode (side surface and upper surface) by anodic oxidation in the same manner as in Example 1. Then, the silicon nitride film 207 is formed to a thickness of 10 to 200.
nm, for example, 100 nm. Then, phosphorus is implanted by an ion doping method using the gate electrode portion as a mask, so that the low concentration N-type impurity regions 208, 20 are formed.
9 was formed. The dose amount was 1 × 10 ¹³ atoms / cm ² . Furthermore, a KrF excimer laser (wavelength 248n
m, pulse width 20 nsec) to activate the doped impurities. The energy density of the laser is 200 to 400 mJ / cm ² , preferably 25.
0 to 300 mJ / cm ² was suitable. (Fig. 2
(A))

After that, the region of the N-channel TFT was masked with a photoresist 210, and in this state, high concentration boron doping was performed by an ion doping method. The dose amount was 5 × 10 ¹⁵ atoms / cm ² , and the acceleration voltage was 65 kV. As a result, the weak N type impurity region 208 is inverted to the strong P type by the phosphorus doping, and becomes the P type impurity region 211. Then again
The impurities were activated by laser irradiation.
(FIG. 2B) After removing the photoresist mask 210, a silicon oxide film 212 having a thickness of 400 to 800 nm was deposited by plasma CVD. (Fig. 2 (C))

Then, as in Example 1, anisotropic etching was performed to form sidewalls 213 and 214 of silicon oxide on the side surfaces of the gate electrode. (FIG. 2D) After that, phosphorus was introduced again by the ion doping method. In this case, the dose amount is preferably one to three orders of magnitude larger than the dose amount in the step of FIG. 2A, and 1/10 to 2/3 of the dose amount in the step of FIG. 2B. In this embodiment, the dose of the first phosphorus doping is 200 times 2 × 10 ^15.
Atom / cm ² . This is 40% of the dose amount of boron in the step of FIG. The acceleration voltage was 80 kV. As a result, a region (source /
A drain) 215 was formed, and a low concentration impurity region (LDD) 216 was left below the sidewall.

Further, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was irradiated to activate the doped impurities. The energy density of the laser was 200 to 400 mJ / cm ² , preferably 250 to 300 mJ / cm ² . On the other hand, phosphorus was also doped in the region of the P-channel TFT (on the right side of the figure), but the concentration of the previously doped boron was 2.5 times that of phosphorus, so that it remained P-type. Apparently, there are two types of P-type regions of the P-channel TFT, that is, a region 218 below the sidewall and a region 217 outside thereof (on the side opposite to the channel formation region), but from the viewpoint of electrical characteristics. There was no significant difference between the two. (Fig. 2 (E))

Finally, as shown in FIG. 2F, a silicon oxide film having a thickness of 300 nm is formed as an interlayer insulator 219 on the entire surface by a CVD method, contact holes are formed in the source / drain of the TFT, and aluminum is formed. Wiring / electrode 2
20, 221, 222, and 223 were formed. Through the above steps, a semiconductor integrated circuit in which the N-channel TFT is the LDD type is completed. Although not shown in the figure, at the portion where the second-layer wiring crosses over the gate wiring, almost no disconnection was observed as in Example 1, although the interlayer insulating material was not so thick.

As in this embodiment, the N-channel TFT is set to L
The DD structure is provided to prevent deterioration due to hot carriers. However, since the LDD region is a parasitic resistance inserted in series with the source / drain, there is a problem that the operation speed is reduced. Therefore, it is desirable that the LDD does not exist in the P-channel TFT, which has low mobility and is less deteriorated by hot carriers, as in this embodiment. Although the doping impurities are activated by laser irradiation in each doping step in this embodiment, they may be collectively performed just before forming the interlayer insulator after all the doping steps are completed.

[Embodiment 3] FIG. 3 shows the present embodiment. This example is an example of manufacturing a TFT in which an offset region is formed using a sidewall. First, a 200-nm-thick silicon oxide film was formed as a base oxide film 302 over the substrate 301. After that, an amorphous silicon film is formed by, for example, a plasma CVD method or an LPCVD method, for example, 50
nm deposition, and this was left to stand in a reducing atmosphere at 550 to 600 ° C. for 8 to 24 hours for crystallization. Then, the silicon film was etched to form island regions 303. Further, a thickness of 120 n is formed on the layer by plasma CVD.
m silicon oxide film 304 was formed.

After that, aluminum with a thickness of 500 nm (1 wt% Si, or 0.1-0.3 wt% S
A c (including scandium) film was formed by a sputtering method, and this was etched to form a gate electrode 305 and a gate wiring 306.

Then, by anodic oxidation, a 200 nm-thick anodic oxide film 30 is formed around the gate electrode (side surface and upper surface).
Formed 7. Further, the silicon nitride 308 is deposited to 20 to 20 by plasma CVD method in a mixed gas of NH ₃ , SiH ₄ , and H _2.
The film was formed to a film thickness of 100 nm. (FIG. 3A) Then, a silicon oxide film 309 is formed by a plasma CVD method.
Was deposited. Here, TEOS and oxygen or monosilane and nitrous oxide were used as the source gas. Silicon oxide film 3
The optimum thickness of 09 depends on the height of the gate electrode / wiring. For example, when the height of the gate electrode / wiring including the silicon nitride film is about 600 nm as in the present embodiment, it is preferably 1/3 to 2 times that of 200 nm to 1.2 μm, and here, 600 nm. did. In this film forming process, it is required that the step coverage be good as well as the uniformity of the film thickness in the flat portion. (Fig. 3
(B))

Next, the silicon oxide film 3 is formed by performing anisotropic dry etching by the known RIE method.
09 etching was performed. This etching was completed when the etching reached the silicon nitride film 308.
Since the silicon nitride film is hard to be etched by anisotropic dry etching by the RIE method, the gate insulating film 304 is not etched. By the above process,
The substantially triangular insulators (sidewalls) 310 and 311 remained on the side surfaces of the gate electrodes and wirings. (Fig. 3
(C))

After that, phosphorus was introduced by the ion doping method. The dose amount in this case is 1 × 10 ^{14 to} 5 × 1
The acceleration voltage was 10 ¹⁷ atoms / cm ² , the acceleration voltage was 10 to 90 kV, for example, 2 × 10 ¹⁵ atoms / cm ² , and the acceleration voltage was 80 kV. As a result, a region (source / drain) 312 into which phosphorus was introduced was formed. Further, phosphorus was not introduced into the lower part of the sidewall, and an offset region was formed.
(FIG. 3D) Further, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was irradiated to activate the doped impurities. The energy density of the laser was 200 to 400 mJ / cm ² , preferably 250 to 300 mJ / cm ² .

Finally, an interlayer insulator 313 is formed on the entire surface,
A silicon oxide film was formed to a thickness of 500 nm by the CVD method. Then, a contact hole is formed in the source / drain of the TFT, and the aluminum wiring / electrode 31 of the second layer is formed.
4,315 were formed. The thickness of the aluminum wiring was 400 to 600 nm, which is almost the same as that of the gate electrode / wiring.
Through the above steps, a TFT having an N-channel type offset was completed. In the second-layer wiring 315, the step difference at the portion overcoming the gate wiring 306 is
Because of the presence of 11, the wirings in the second layer were almost the same thickness as the gate electrode / wiring, but almost no disconnection was observed. (Fig. 3
(D))

[Embodiment 4] FIG. 5 shows the present embodiment. In this embodiment, a TFT having an N-channel type offset and a TF having an N-channel type LDD are formed on the same substrate.
This is a product of T. First, a base oxide film 502, an island-shaped silicon semiconductor region, and a gate oxide (silicon oxide) film 503 are formed on a substrate 501 in the same manner as in Example 1, and a gate electrode 504 made of an aluminum film (thickness 500 nm),
505 was formed. After that, as in the first embodiment, a thickness of 2 is formed around the gate electrode (side surface and upper surface) by anodic oxidation.
A 00 nm anodic oxide 506 was formed. Further, the silicon nitride film 507 is formed to a thickness of 10 by plasma CVD.
To 200 nm, for example, 100 nm. (Fig. 5
(A))

After that, the area of the TFT having an offset is masked with a photoresist 508, and in this state, the LD
Phosphorus was implanted by ion doping in the portion where the TFT having D was formed using the gate electrode portion as a mask to form a low concentration N-type impurity region 509. The dose amount was, for example, 1 × 10 ¹³ atoms / cm ² . Furthermore, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was irradiated to activate the doped impurities. The energy density of the laser is 200 to 400 mJ / cm ² , preferably 250 to 30.
0 mJ / cm ² was suitable. (FIG. 5B) After removing the photoresist mask 508, the thickness is 400 to 800 nm, for example, 6 by plasma CVD.
A 00 nm silicon oxide film 510 was deposited. (Fig. 5
(C))

Then, as in the first embodiment, the silicon oxide film 510 is etched by anisotropic etching to form sidewalls 511 and 512 of silicon oxide on the side surfaces of the gate electrode.
Was formed. (FIG. 5D) After that, phosphorus was introduced again by the ion doping method. In this case, the dose amount is preferably one to three orders of magnitude larger than the dose amount in the step of FIG. In this embodiment,
2 × 10 200 times the dose of the first phosphorus doping
^{It was set to 15} atoms / cm ² . The acceleration voltage was 80 kV. As a result, regions (source / drain) 513, 514 having a high concentration of phosphorus introduced were formed. Also, FIG.
In the step (B), the TFT covered with the mask has an offset region below the sidewall, and the TFT doped with low concentration phosphorus has a low concentration impurity region (LDD) below the sidewall. 515 was left.

Further, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was irradiated to activate the doped impurities. The energy density of the laser was 200 to 400 mJ / cm ² , preferably 250 to 300 mJ / cm ² . (FIG. 5 (E)) Finally, as shown in FIG. 5 (F), the interlayer insulator 5 is formed on the entire surface.
16, a silicon oxide film having a thickness of 300 is formed by the CVD method.
nm, a contact hole is formed in the source / drain of the TFT, and aluminum wiring / electrodes 517 and 51 are formed.
8, 519, 520 were formed. By the above process,
TF with N-channel offset on the same substrate
A semiconductor integrated circuit having T and a TFT having an N-channel LDD was manufactured.

Although not shown in the figure, the gate wiring is 2
At the portion where the wiring of the layer overcame, the disconnection was hardly seen as in Example 1, although the interlayer insulator was not so thick. Although the doping impurities are activated by laser irradiation in each doping step in this embodiment, they may be collectively performed just before forming the interlayer insulator after all the doping steps are completed.
Although only the N-channel type TFT is described in FIG. 5, a CMOS circuit may be formed by forming both the N-channel type TFT and the P-channel type TFT on the same substrate as in FIG. For example, in a monolithic active matrix circuit in which a peripheral circuit and an active matrix circuit are formed on the same substrate, the peripheral circuit includes an LDD type N-channel TFT and a normal PMO which are fast in operating speed.
A CMOS circuit using an S-type TFT, or an N-channel or P-channel offset type TFT may be used in an active matrix circuit required to have a low leak current. In particular, the P-channel offset TFT is effective in reducing the leak current. Of course, in the peripheral circuit, N channel type, P type
Both the channel type and the LDD type TFT may be used.

[Embodiment 5] FIG. 6 shows the present embodiment. First, a silicon oxide film 602 having a thickness of 200 nm is formed as a base oxide film on a substrate 601, and a thickness of 50 is formed as in the first embodiment.
nm island silicon regions were formed. Then, a gate insulating film having a thickness of 1 is formed thereon by the plasma CVD method.
A 00 nm silicon oxide film 603 was formed. After that, a gate electrode 60 is formed by using an aluminum film having a thickness of 500 nm.
4 and the gate wiring 605 were formed. Further, similarly to Example 1, the anodic oxide 606 having a thickness of 200 nm was formed around the gate electrode by anodic oxidation. And
10-2 silicon nitride film 607 by plasma CVD method
00 nm, preferably 20-100 nm, eg 5
The film was formed to a film thickness of 0 nm.

After that, an impurity (here, phosphorus) is self-alignedly injected into the island-shaped silicon film by an ion doping method using the gate electrode portion as a mask, and as shown in FIG. LDD) 608 was formed.
Dose is 1 × 10 ¹³ ~5 × 10 ¹⁴ atoms / cm ^2, the acceleration voltage 10～90KV, for example, a dose of 5 × 10 ^{1 3}
The atom / cm ² and the acceleration voltage were 80 kV. (Fig. 6
(A)) Then, a silicon oxide film 609 was deposited by the plasma CVD method. The thickness was 600 nm. In this film forming process, along with the uniformity of the film thickness in the flat portion,
Good step coverage is also required.
(Fig. 6 (B))

Next, anisotropic dry etching is performed using CHF ₃ to obtain the silicon oxide film 609.
Was etched. At this time, the etching may be performed until the silicon nitride film 607 is reached. However, as shown in FIG. 6C, the etching is stopped immediately before the silicon nitride film 607 is reached, and the silicon oxide film 60 is preferably stopped.
It is good to leave 9 slightly left. Through the above steps, substantially triangular insulators (sidewalls) 610 and 611 were formed on the side surfaces of the gate electrode / wiring. (FIG. 6C) Then, dry etching was performed using CH ₄ / O ₂ . In this dry etching, the silicon oxide film slightly left on the silicon nitride film and the silicon nitride film were etched. This etching can be measured by an endpoint monitor (plasma monitor), so
Over-etching can be very small for gate insulating films. (Figure 6 (D))

After that, phosphorus was introduced again by the ion doping method. The dose amount in this case is shown in FIG.
It is preferable that the dose is 1 to 3 orders of magnitude larger than the dose in the step. In this embodiment, the dose is 2 × 10 ¹⁵ atoms / cm ^{2 which} is 40 times the dose of the first phosphorus doping. Acceleration voltage is 80kV
And As a result, a region (source / drain) 612 in which a high concentration of phosphorus was introduced was formed, and a low concentration region (LDD) 613 was left below the sidewall.
(FIG. 6 (E)) Furthermore, a KrF excimer laser (wavelength 248 nm,
Irradiation with a pulse width of 20 nsec) was performed to activate the doped impurities. The energy density of the laser is 200 to 400 mJ / cm ² , preferably 250 to
300 mJ / cm ² was suitable.

Finally, an inter-layer insulator 614 is formed on the entire surface.
A silicon oxide film was formed to a thickness of 500 nm by the CVD method. Then, contact holes are formed in the source / drain of the TFT, and the second-layer aluminum wiring / electrode 61 is formed.
5, 616 was formed. The thickness of the aluminum wiring was 400 to 600 nm, which is almost the same as that of the gate electrode / wiring.
Through the above steps, the T having the N-channel LDD is formed.
The FT has been completed. Hydrogen activation may be further performed at 200 to 400 ° C. to activate the impurity regions. As in the first embodiment, the second layer wiring 616 is the gate wiring 60.
The side wall 611
Since the thickness of the second-layer wiring is almost the same as that of the gate electrode / wiring because of the presence of, the disconnection was hardly observed. (Fig. 6
(F))

In this embodiment, the silicon nitride film 607 is etched to expose the gate insulating film 603. As a result,
When the contact hole is formed by the wet etching method, it can be performed in one step. As is clear from FIG. 6E, as a result of such etching of the silicon nitride film, the silicon nitride film becomes an anodic oxide film 6.
Between 06 and the sidewalls 610, 611, or
It remains only between the sidewalls 610 and 611 and the gate insulating film 603.

Sixth Embodiment FIG. 7 shows this embodiment. This embodiment is an example in which an LDD-type N-channel TFT and a normal P-channel TFT are formed on the same substrate as in the second embodiment. The left side of FIG. 7 is a sectional view of the manufacturing process of the N-channel TFT, and the right side of the figure is the P-channel TFT.
The manufacturing process sectional drawing of is shown. First, the substrate (Corning 70
59) A base oxide film 702, an island-shaped silicon semiconductor region, and a silicon oxide film 703 functioning as a gate oxide film on 701.
And the gate electrodes 704, 70 of an aluminum film (thickness: 500 nm) whose surface is covered with anodic oxide.
5 was formed.

Further, the gate oxide film in the N-channel type TFT portion was selectively removed by using the gate electrode 704 as a mask to expose the semiconductor layer. After that, plasma CV
A silicon nitride film 706 was formed to a thickness of 10 to 200 nm, preferably 20 to 100 nm, for example, 60 nm by the D method. Then, phosphorus is implanted by an ion doping method using the gate electrode portion as a mask to form a low concentration N-type impurity region 707. Dose amount is 1 × 10
^{It was 13} atoms / cm ² and the acceleration voltage was 20 keV. In this doping step, phosphorus was not doped in the island region 708 of the P-channel TFT covered with the gate oxide film 703 because the acceleration voltage was low. (Fig. 7
(A))

After that, the region of the N-channel TFT was masked with a photoresist 709, and in this state, high-concentration boron was doped by an ion doping method. The dose amount was 5 × 10 ¹⁴ atoms / cm ² , and the acceleration voltage was 65 kV. As a result, a P-type impurity region 710 was formed in the island region 708. (FIG. 7 (B)) In the present embodiment, high-concentration boron partial selective doping was carried out after low-concentration phosphorus overall doping, but this step may be reversed. After removing the photoresist mask 709, a silicon oxide film 711 having a thickness of 400 to 800 nm was deposited by a plasma CVD method.
(Fig. 7 (C))

Then, as in Example 2, by anisotropic etching, sidewalls 712 and 713 of silicon oxide were formed on the side surfaces of the gate electrode. (FIG. 7D) After that, phosphorus was introduced again by the ion doping method. In this case, the dose amount is preferably 1 to 3 digits larger than the dose amount in the step of FIG. In this embodiment, the dose of the first phosphorus doping is 200 times 2 ×.
It was set to 10 ¹⁵ atoms / cm ² . The acceleration voltage was 20 kV. As a result, a region (source /
A drain) 714 was formed, and a low concentration impurity region (LDD) 715 was left below the sidewall.

On the other hand, in the P channel type region, since the gate oxide film exists, phosphorus ions were not implanted. In the second embodiment, phosphorus and boron are implanted at a high concentration in the P-channel TFT, so that the dose amount is limited, but in the present embodiment, the dose amount is not limited. However, regarding the accelerating voltage, it is necessary to lower phosphorus and increase boron as described above. (Fig. 7
(E) After the doping step, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was irradiated to activate the doped impurities. The energy density of the laser was 200 to 400 mJ / cm ² , preferably 250 to 300 mJ / cm ² .

Finally, as shown in FIG. 7F, a silicon oxide film having a thickness of 500 nm is formed as an interlayer insulator 716 on the entire surface by a CVD method, contact holes are formed in the source / drain of the TFT, and aluminum is formed. Wiring / electrode 7
17, 718, 719 and 720 were formed. Through the above steps, a semiconductor integrated circuit in which the N-channel TFT is the LDD type is completed. In this embodiment, as compared with the second embodiment, an extra photolithography process and one etching process are required to remove the gate oxide film in the N-channel TFT portion. However, since N-type impurities are not substantially introduced into the P-channel type TFT, there is also an advantage that the dose amounts of N-type and P-type impurities can be relatively arbitrarily changed. In addition, phosphorus injected into the vicinity of the surface of the gate oxide film 703 of the P-channel TFT is effective in forming phosphorus glass and preventing entry of mobile ions such as sodium in the subsequent laser irradiation step.

Seventh Embodiment FIG. 8 shows this embodiment. This embodiment relates to a method for manufacturing an active matrix liquid crystal display, which will be described with reference to FIG. T on the left side of FIG.
The two FTs are LDD-type N-channel TFs, respectively.
T is a normal P-channel TFT, and shows a logic circuit used for peripheral circuits and the like. Further, the TFT on the right side is a switching transistor used in the active matrix array, which is an offset P-channel TFT. First, a base oxide film, an island-shaped silicon semiconductor region (the island-shaped region 8 for a peripheral circuit) on a substrate (Corning 7059).
01, island-shaped region 80 for active matrix circuit
2), a silicon oxide film 803 which functions as a gate oxide film is formed, and further, an aluminum film (thickness 500 nm) gate electrode 80 whose surface is covered with anodic oxide.
4, 805 (for peripheral circuits) and 806 (for active matrix circuits) were formed.

Furthermore, for peripheral circuits and active mats
Gate oxidation of P-channel TFT for lix circuit
Selectively the film using the gate electrodes 804 and 806 as a mask
It was removed to expose the semiconductor layer. After that, plasma C
A silicon nitride film 807 having a thickness of 10 to 200 nm is formed by the VD method.
Preferably, a film having a thickness of 20 to 100 nm, for example 40 nm
It was formed into a thick film. In addition, the active matrix circuit area
Was masked with photoresist 808. And the gate
The ion doping method is used with the electrode section as a mask.
A high concentration P-type impurity region 809 is formed by implanting the element.
Formed. Dose amount is 1 × 10 ¹⁵Atom / cm², Acceleration power
The pressure was 20 keV. In this doping process
Is covered with a gate oxide film 803 because the acceleration voltage is low.
In the region of the N-channel type TFT, which has been
Wasn't done. (Figure 8 (A))

After that, low-concentration phosphorus was doped by the ion doping method. Dose amount is 1 × 10
^{It was 13} atoms / cm ² and the acceleration voltage was 80 kV. As a result, a low concentration N-type impurity region 810 was formed in the N-channel TFT region. (FIG. 8B) Although the photoresist mask 808 is removed in the drawing for doping, the doping may be performed with the photoresist still attached. Since the accelerating voltage of phosphorus is high, if doping is performed with the photoresist left, phosphorus is not injected into the active matrix circuit region, so an ideal offset P-channel TFT can be obtained. The resist may be carbonized and it may take time to remove it.

Even when the photoresist is removed, the phosphorous concentration has a peak below the island-shaped semiconductor region because the phosphorous acceleration voltage is high. However, there is no guarantee that phosphorus is not completely doped, and a small amount of phosphorus is formed in the semiconductor region. However, in this case, even if phosphorus is doped, its concentration is low, and P ⁺ (source) / N− / I (channel) / N− / P ⁺ (drain)
This structure is suitable as a TFT for an active matrix circuit that needs to reduce a leak current. Thereafter, a silicon oxide film having a thickness of 400 to 800 nm is deposited by the plasma CVD method, and by anisotropic etching as in the second embodiment, the side walls 811, 812, 813 of silicon oxide are formed on the side surfaces of the gate electrode.
Was formed. (Fig. 8 (C))

After that, boron was again introduced by the ion doping method. The dose amount in this case is shown in FIG.
It is desirable that the dose amount is approximately the same as the dose amount in the step (A). In this embodiment, the dose amount is 1 × 10 ¹⁵ atoms / c
m ² and the acceleration voltage were 20 keV. Since the accelerating voltage is low, the N-channel type TFT in which the gate oxide film 803 exists
Region is not doped with boron, and is mainly used in the P channel type T of the peripheral circuit and the active matrix circuit.
The FT source / drain was doped. As a result, the source / drain 814 of the TFT of the active matrix circuit was formed. This TFT has an offset structure in which the gate electrode and the source / drain are separated.
(Figure 8 (D))

Next, phosphorus doping was performed. In this case, the first phosphorus doping step, as shown in FIG.
It is preferable that the dose amount is larger than that of (B) by 1 to 3 digits. In this embodiment, the dose is set to 5 × 10 ¹⁴ atoms / cm ^{2, which} is 50 times the dose of the first phosphorus doping. Accelerating voltage is 8
It was set to 0 kV. As a result, a region (source / drain) 815 in which a high concentration of phosphorus is introduced is formed, and a low concentration impurity region (LDD) 816 is formed under the sidewall.
Was left. On the other hand, in the P-channel type TFT region, most of the phosphorus ions were implanted into the base film and did not significantly affect the conductivity type. (Fig. 8 (E))

After the doping step, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was irradiated to activate the doped impurities. Laser energy density is 200 ~ 400mJ /
cm ^2, and a preferably suitably 250~300mJ / cm ^2. Then, a silicon nitride film having a thickness of 500 nm is formed as a first interlayer insulator 817 on the entire surface by a CVD method, contact holes are formed in the source / drain of the TFT, and aluminum wiring / electrodes 818, 819, 82 are formed.
0,821 was formed. The peripheral circuit region is formed by the above steps. (FIG. 8F) Further, as the second interlayer insulator 822, a silicon oxide film having a thickness of 300 nm is formed by a CVD method, and this is etched to form a contact hole, which is transparent to the TFT of the active matrix circuit. By the conductive film, the pixel electrode 8
23 was formed. In this way, an active matrix type liquid crystal display substrate was produced. (Fig. 8 (G))

[0061]

As described above, according to the present invention, it is possible to prevent the disconnection of the second layer wiring in the gate wiring crossover portion. In particular, an integrated circuit is composed of a large number of elements and wirings, but if any one of them is defective, the entire circuit may become unusable. Needless to say, the fact that the number of such defects can be significantly reduced by the present invention has a very great effect in increasing the yield rate of integrated circuits.

Further, according to the present invention, it is possible to make the thickness of the second layer wiring to the same extent as that of the gate electrode / wiring, specifically, the gate electrode / wiring ± 100 [nm]. This has a great effect, and it is suitable for an active matrix circuit of a liquid crystal display, which is required to have less unevenness on the substrate surface. In addition, the merit obtained by using the present invention is “action”.
As described in section. Thus, the present invention is a TFT
It is of great benefit in improving the yield of integrated circuits.

[Brief description of drawings]

FIG. 1 shows a method for manufacturing a TFT circuit according to a first embodiment.

FIG. 2 shows a method of manufacturing a TFT circuit according to a second embodiment.

FIG. 3 shows a method for manufacturing a TFT circuit according to a third embodiment.

FIG. 4 shows a method of manufacturing a TFT circuit by a conventional method.

FIG. 5 shows a method for manufacturing a TFT circuit according to a fourth embodiment.

FIG. 6 shows a method of manufacturing a TFT circuit according to a fifth embodiment.

FIG. 7 shows a method for manufacturing a TFT circuit according to a sixth embodiment.

FIG. 8 shows a method for manufacturing a TFT circuit according to a seventh embodiment.

[Explanation of symbols]

101 ... Glass substrate 102 .. Underlying oxide film (silicon oxide) 103 ... Island-shaped silicon region (active layer) 104 ... Gate insulating film 105, 106 ... Gate electrode (aluminum) 107 ・ ・ ・ ・ Anodic oxide film 108 ... Silicon nitride film 109 ... Weak N-type impurity region 110 ... Insulator coating (silicon oxide) 111, 112 ... Sidewall 113 ・ ・ ・ ・ LDD (low-concentration impurity region) 114 ... Source / drain 115 ... Interlayer insulating film (silicon oxide) 116, 117 ... Metal wiring and electrodes (aluminum)

Continued front page    F-term (reference) 2H090 HA03 HA05 HB03X HB04X                       HC03 HC12 HD03 LA01 LA04                 2H092 JA25 JB58 KB25 MA08 MA19                       MA24 MA27 NA15                 5F033 HH08 HH10 HH38 JJ01 JJ08                       JJ38 KK04 LL04 PP09 PP12                       PP15 QQ08 QQ09 QQ10 QQ11                       QQ13 QQ16 QQ19 QQ25 QQ37                       QQ53 QQ59 QQ65 QQ71 QQ73                       QQ74 QQ89 RR03 RR04 RR06                       SS02 SS04 SS08 SS15 TT02                       TT08 VV15 WW02 XX01 XX02                 5F110 AA18 AA26 BB02 BB04 CC02                       DD02 DD13 EE03 EE06 EE31                       EE32 EE34 EE37 EE44 FF02                       FF30 GG02 GG13 GG24 GG45                       GG47 HJ01 HJ04 HJ12 HJ23                       HL03 HM14 HM15 NN03 NN04                       NN06 NN23 NN24 NN35 NN72                       NN78 PP03 PP10 PP13 PP34                       QQ11 QQ19 QQ24

Claims (7)

[Claims] 1. A first wiring formed on an insulating surface, a silicon nitride film provided to cover an upper surface and a side surface of the first wiring, and the first wiring via the silicon nitride film. An approximately triangular insulator formed so as to contact the side surface of
A semiconductor device comprising: a first interlayer insulating film formed on the silicon nitride film and the substantially triangular insulator; and a second wiring formed on the first interlayer insulating film, When the thickness of the first wiring is x [nm] and the thickness of the second wiring is y [nm], x-100 [nm] ≦ y. 2. A first wiring formed on an insulating surface, a silicon nitride film provided to cover an upper surface and a side surface of the first wiring, and the first wiring via the silicon nitride film. An approximately triangular insulator formed so as to contact the side surface of
A semiconductor device comprising: a first interlayer insulating film formed on the silicon nitride film and the substantially triangular insulator; and a second wiring formed on the first interlayer insulating film, When the thickness of the first wiring is x [nm] and the thickness of the second wiring is y [nm], x-100 [nm] ≦ y ≦ x + 100 [nm] Semiconductor device. 3. A semiconductor layer formed on an insulating surface and provided with a pair of source and drain regions and a channel region, a gate insulating film provided on the semiconductor layer, and a gate insulating film on the gate insulating film. A gate electrode and a gate wiring provided on the gate electrode, a silicon nitride film provided on the upper surface and side surfaces of the gate electrode and the gate wiring, and a side surface of the gate electrode and the gate wiring via the silicon nitride film. What is claimed is: 1. A semiconductor device including a thin film transistor having a substantially triangular insulator formed so as to be in contact with the first nitride film, the first interlayer insulating film formed on the silicon nitride film and the substantially triangular insulator, and A wiring formed on the first interlayer insulating film, the thickness of the gate electrode and the gate wiring is x [nm], and the thickness of the wiring is y.
X-100 [nm] ≦ y when [nm] is satisfied. 4. A semiconductor layer formed on an insulating surface and provided with a pair of source and drain regions and a channel region, a gate insulating film provided on the semiconductor layer, and the gate insulating film. A gate electrode and a gate wiring provided on the gate electrode, a silicon nitride film provided on the upper surface and side surfaces of the gate electrode and the gate wiring, and a side surface of the gate electrode and the gate wiring via the silicon nitride film. What is claimed is: 1. A semiconductor device including a thin film transistor having a substantially triangular insulator formed so as to be in contact with the first nitride film, the first interlayer insulating film formed on the silicon nitride film and the substantially triangular insulator, and A wiring formed on the first interlayer insulating film, and the thickness of the gate electrode and the gate wiring is x [n
m], when the thickness of the wiring is y [nm], x-100 [nm] ≦ y ≦ x + 100 [nm] is satisfied. 5. The semiconductor device according to claim 3, wherein a plurality of the thin film transistors are provided, and the semiconductor layer of the N-channel type thin film transistor among the plurality of thin film transistors includes the pair of source and drain regions and the channel. A low-concentration impurity region is provided between the channel region and the region, and a low-concentration impurity region is provided between the channel region and the pair of source and drain regions in a semiconductor layer of a P-channel thin film transistor among the plurality of thin film transistors. A semiconductor device having no region. 6. The method according to claim 3, further comprising a second interlayer insulating film on the wiring, wherein the first interlayer insulating film is made of silicon nitride, 2. The semiconductor device, wherein the second interlayer insulating film is formed of silicon oxide. 7. The semiconductor device according to claim 1, wherein the semiconductor device is used in an active matrix circuit, a peripheral drive circuit, a microprocessor, a microcontroller, a microcomputer, or a semiconductor memory. Semiconductor device.