JP2003282839A - Method of manufacturing ferroelectric memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a decrease in the thickness of a base interlayer insulating film due to over-etching when etching a constituent part of a ferroelectric capacitor, thereby making it possible to reduce a step of the capacitor, and furthermore, between a pattern and a wafer. Provided is a method for manufacturing a ferroelectric memory that can eliminate unevenness of steps in a plane. SOLUTION: The method for manufacturing a ferroelectric memory according to the present invention includes a step of forming an etching stop layer 20 made of a metal which is easily oxidized or a compound of the metal on a base 10; Forming a layered body for at least a portion of a ferroelectric capacitor, forming a mask layer having a predetermined pattern on the layered body, using the mask layer as a mask, And a step of overetching the layered body with a mixed gas containing at least oxygen and a halogen gas.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a ferroelectric memory, and more particularly, to a method of manufacturing a ferroelectric memory device related to patterning at least a part of a ferroelectric capacitor.

[0002]

2. Description of the Related Art A ferroelectric memory (FeRAM) uses a ferroelectric film in a capacitor portion to hold data by its spontaneous polarization.

Usually, a device such as a transistor for operating a memory is incorporated in the lower layer of the capacitor, and is separated from the capacitor section by an interlayer insulating film. For this reason, the layer forming the capacitor is formed on a surface having irregularities to some extent. Conventionally, the patterning of the component parts (for example, electrodes, ferroelectric film) of this capacitor has been performed by dry etching with a patterned photoresist as a mask to enhance the sputterability with chlorine gas, argon gas, or the like. At this time, in order to completely pattern the capacitor, it is necessary to always perform overetching in consideration of the uniformity of the wafer surface in the dry etching, the density of the pattern, and the unevenness of the wafer. If the amount of over-etching is small, the lower electrode material remains unetched, particularly in the in-plane recesses and in the portions where the pattern is dense, which causes device defects such as short circuits.

At the time of this over-etching, the underlying interlayer insulating film is also etched. In this case, since the dry etching has a strong sputter property, it is difficult to obtain a difference in etching rate depending on the material. Therefore, the underlying interlayer insulating film is also etched at the same etching rate as the capacitor constituent material. Therefore, the underlying interlayer insulating film is largely removed by overetching. As a result, the level difference formed between adjacent capacitors and between the capacitor portion and the peripheral portion is increased by the amount of the underlying interlayer insulating film removed by overetching. That is, the aspect ratio of the space between adjacent capacitors is increased by the etching amount of the underlying interlayer insulating film. For this reason,
For example, when forming a hydrogen barrier film on a capacitor,
The coverage of the hydrogen barrier film becomes poor, and sufficient hydrogen barrier properties cannot be obtained. Therefore, the ferroelectric characteristics deteriorate. In particular, as miniaturization progresses, the distance between adjacent capacitors becomes closer, and the effect becomes remarkable. In addition, since the step between the capacitor part and the peripheral part becomes large, there is a problem that the cost is increased due to the addition of steps such as flattening in the subsequent steps such as the aluminum wiring step and the contact hole forming step.

On the other hand, the unevenness of the step caused by the pattern density and the in-plane distribution of the etching characteristics reduces the process margin in the etching step and the subsequent steps, resulting in a lower yield.

[0006]

SUMMARY OF THE INVENTION It is an object of the present invention to prevent a decrease in film thickness of an underlying interlayer insulating film due to over-etching when etching a constituent part of a ferroelectric capacitor, thereby making it possible to reduce the step of the capacitor. Further, the present invention provides a method for manufacturing a ferroelectric memory, which can eliminate variations in steps between patterns and within a wafer surface.

[0007]

A method of manufacturing a ferroelectric memory device according to the present invention is a method of manufacturing a ferroelectric memory device having a ferroelectric capacitor, wherein the ferroelectric capacitor is at least A method of manufacturing a ferroelectric memory device, comprising a lower electrode, a ferroelectric layer and an upper electrode, and including the following steps (a) to (e). (A) a step of forming an etching stop layer made of a metal that is easily oxidized or a compound of the metal on the substrate,
(B) forming a layered body for at least a part of the ferroelectric capacitor on the etching stop layer, and (c) forming a mask layer having a predetermined pattern on the layered body. And (d) etching the layered body using the mask layer as a mask until a part of the etching stop layer appears, (e)
The method includes overetching the layered body with a mixed gas containing at least oxygen and a halogen gas.

According to the present invention, in the step (a), the etching stop layer made of a metal or a compound of the metal which is easily oxidized is formed on the substrate. Therefore, even if overetching is performed in step (e), oxygen as an etching gas reacts with the metal forming the etching stop layer or a compound of the metal to form a metal oxide film, which hinders etching. Therefore, reduction of the interlayer insulating film due to overetching can be eliminated.

Further, the present invention can take at least one of the following aspects.

(1) A mode in which the etching stop layer is an insulating film. In this case, since the etching stop layer also functions as an interlayer insulating film, it is not necessary to remove the etching stop layer.

(2) The layered body is a conductive layer for the lower electrode, or a laminated film including a conductive layer for the lower electrode and the ferroelectric layer, or a conductive layer for the lower electrode. And a laminated film including the ferroelectric layer and a conductive layer for the upper electrode.

(3) A mode including a step of removing the etching stop layer after the step (e). In the case of this aspect, since the etching stop layer is not provided at the place where the contact hole is formed in the device under the capacitor, the conventional dry etching method can be applied. When the etching stop layer is a conductor layer, the layered body can be completely electrically separated. Further, if patterning is performed again, it can function as a lower electrode.

(4) The mask layer is a resist. In this case, patterning of the mask can be easily performed. Further, since it is removed by oxygen in the over etching, a mask removing step is not necessary.

The mask layer is a metal or a compound of the metal which is easily oxidized. In this case, since the etching rate in steps (d) and (e) is low, the material can be formed thin. As a result, it is possible to reduce the deposits on the side wall of the mask that occur during etching, and it is possible to obtain a good etching shape. Furthermore, when removing the etching stop layer,
At the same time, the mask can be removed by using a gas containing chlorine gas or boron trichloride gas.

Further, the mask layer is a laminated film made of a resist and a metal which is easily oxidized, or a compound of the metal. In this case, since the resist is used, the above-mentioned material serving as a mask can be thinly deposited. Therefore, it is possible to perform precise patterning even with a material that causes a large dimensional conversion difference due to patterning. Further, even if the resist is rapidly etched by oxygen in the step (e), the resist film can be thinned because of the above-mentioned material in the resist lower layer, and the exposure can be performed with good resolution. From the above, patterning of the layered body can be performed accurately.

(5) A mode in which the memory cells composed of the ferroelectric capacitors include a memory cell array arranged in a matrix.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will be described below with reference to the drawings. 1 to 9 are
It is a figure which shows typically the manufacturing method of the ferroelectric memory which concerns on embodiment of this invention. The ferroelectric memory has an upper electrode 5
A plurality of ferroelectric thin film capacitors are provided with a memory including a capacitor portion including 0, the ferroelectric layer 40, and the lower electrode layer 30 as a storage unit. The plurality of memory cells can be regularly arranged in a plurality of rows and a plurality of columns.

In the method of manufacturing a ferroelectric memory according to this embodiment, a memory cell is formed by forming a capacitor portion using the etching stop layer 20 and the ferroelectric layer on the substrate 10. The base 10 may be composed of, for example, a Si substrate and an interlayer insulating film made of SiO 2 formed thereon. Further, the base 10 may have a functional device such as a transistor formed thereon and may be covered with an interlayer insulating film such as SiO 2 or SiN. A known method can be used for forming the transistor.

The method of manufacturing the capacitor portion of the ferroelectric memory will be described below. First, as shown in FIG. 1A, an etching stop layer 20, a lower electrode 30, a ferroelectric layer 40, and an upper electrode 50 are sequentially laminated and formed on a substrate 10.

The etching stop layer 20 is made of a metal such as Ti, which is easily oxidized by oxygen, or its compound, Ti.
It can be formed using Ox, TiN, Al2O3, or the like as a material. In addition to this function, the etching stop layer 20 may have other functions such as an adhesion layer, a barrier layer, and a diffusion prevention layer. Further, it may have conductivity such as Ti and TiN, and may itself function as the lower electrode. Further, it may be an insulating film such as TiOx or Al2O3, and may itself function as an interlayer insulating film. Also,
It may be composed of these laminated films. In the present embodiment, Pt is used for the lower electrode 30, and S is used for the ferroelectric film 40.
Since BT (Strontium Bismuth Tantalates) is used as a material, a diffusion prevention layer of Bi, an adhesion layer of Pt, and TiOx that itself functions as an interlayer insulating film are used. The etching stop layer 20 is formed by forming a Ti film on the substrate 10 to a thickness of, for example, 20 nm by a sputtering method, and oxidizing the Ti film in an oxidizing furnace to form a TiOx film having a thickness of 40 nm.
It can be formed with a film thickness of m.

The lower electrode 30 can be formed of a noble metal such as Pt or Ir or an oxide thereof (for example, IrOx). Further, the lower electrode 20 may be a single layer of these, or may have a multilayer structure in which layers made of a plurality of materials are laminated. In this embodiment, since SBT is used as the material for the ferroelectric layer 40, the lower electrode 2
0 is formed of Pt. In forming the lower electrode 20, a Pt film is formed with a film thickness of, for example, 200 nm by a sputtering method.

The ferroelectric layer 40 is made of SBT, PZT (Lead).
Zircon Titanate), BST (Barium Strontium Titan
ate) and so on. As a film forming method, a solution coating method (including a sol-gel method, a MOD (Metal Organic Deposition) method, etc.), a sputtering method or a CVD (Chemical Vapor) method is used.
Deposition (MOCVD (Metal Organic Chemica
l Deposition) method is included). In this embodiment, the ferroelectric layer 40 is formed on the lower electrode 30 with a film thickness of, for example, 200 nm using SBT as a material.

For the upper electrode 50, the same material and film forming method as those for the lower electrode 30 can be used. In the present embodiment, the upper electrode 50 is made of Pt as a material and is formed on the ferroelectric layer 40 by sputtering with a film thickness of, for example, 200 nm.

Next, as shown in FIG. 1 (b), a mask layer 60 having a predetermined pattern is formed on the upper surface in a state where the etching stop film 20, the lower electrode 30, the ferroelectric layer 40 and the upper electrode 50 are laminated. It is formed on the electrode 50. The mask layer 60 is formed on the plurality of formation regions on the upper electrode 50. This mask layer is a resist or SiO2
Can be formed with a so-called hard mask such as.

The patterning with each mask material will be described below.

(Patterning with Resist Mask) First, a resist mask 61 is formed as shown in FIG. Since the resist mask has a higher etching rate by dry etching than the material forming the ferroelectric capacitor, the lower electrode 30, the ferroelectric film 40, and the upper electrode 50 are etched.
It is necessary to form about 3.0 times or more of the total film thickness. In the present embodiment, since the total thickness of the lower electrode 30, the ferroelectric film 40, and the upper electrode 50 is 600 nm, the resist film thickness is about 2.0 μm.

Next, as shown in FIG. 3, the upper electrode 50, the ferroelectric film 40 and the lower electrode 30 are formed into the etching stop layer 2.
Etch and pattern until at least part of 0 appears. Dry etching can be used for etching, and for example, ICP (Inductively Coupled Pl
High density plasma etching equipment such as asma) can be used. In this etching, an etching gas such as chlorine gas is used for the upper electrode 50 and the lower electrode 30,
Argon gas mixed gas with a gas pressure of 1.0 Pa
Low voltage (0.5 Pa, for example), bias output of 1k
As W, patterning can be performed by etching with high sputterability. In etching the ferroelectric layer 40, for example, a CFC-based gas (CF4 or CHF3 gas, etc.) is used.
And a gas mixture of argon gas, the gas pressure is 1.0
Low pressure below Pa (eg 0.5 Pa), bias output
When patterning is performed by etching with a sputtering property of 1 kW to enhance the sputterability, the etching rate ratio with the resist can be increased. At this time, the secondary product generated by the etching is left on the sidewall of the resist mask 61.
It is attached as 5. In addition, pattern steps and density,
There is a portion where Pt of the lower electrode material is completely removed and a portion where the lower electrode residue 31 is present due to etching uniformity and the like.

Next, as shown in FIG. 4, the lower electrode residue 31 is removed by over-etching. A similar dry etching apparatus can be used for over etching. For this etching, an etching gas, that is, a mixed gas containing at least oxygen gas and halogen gas is used. Further, a rare gas such as argon gas can be mixed. In the present embodiment, it is a mixed gas of oxygen gas and chlorine gas, the flow rate of oxygen gas is 40% of the ratio of the total gas flow rate, and the gas pressure is 1.0 Pa or lower (for example, 0 Pa). 0.5 Pa), the bias output is set to 1 kW, and etching is performed to enhance the sputterability.

At this time, the surface of the etching stop layer 20 is oxidized by oxygen plasma to form a metal oxide film. To prevent this metal oxide film from being etched,
The etching rate of the etching stop layer 20 sharply decreases when the flow rate ratio of oxygen gas and chlorine gas is about 30% or more,
It becomes about 1/10 or less. Although TiOx is used for the etching stop layer 20 in the present embodiment, it is difficult to etch by adding oxygen in the same manner, and the etching rate becomes 20 nm / min or less. However, in metals that are not easily oxidized, such as Pt, the decrease in etching rate due to the addition of oxygen is not remarkable. The etching rate of Pt at this time is 220 nm / min.
It is a degree. Therefore, the etching rate ratio between the material forming the lower electrode 30 and the material forming the etching stop layer 20 is 10 or more. Thus, by adding oxygen, the ratio of the etching rates of the lower electrode 30 and the etching stop layer 20 can be increased.

On the other hand, the residue 65 is simultaneously etched when the resist recedes. Since this process is over-etching, the amount of the lower electrode material that causes the residue does not adhere to the side wall of the mask, or even if it adheres, the amount is small. Therefore, the amount of etching caused by the resist receding becomes larger than the amount of adhesion. As a result, the residue 65 can be completely removed. Further, since the oxygen gas is mixed, the resist etching rate is about 8
Since it is 00 nm / min, the resist is removed during overetching.

From the above, the pattern shown in FIG. 5 is obtained.
For example, it is assumed that the lower electrode remaining portion 31 can be completely etched by performing overetching by 50%.
Since the etching rate of the etching stop layer 20 is 1/10 or less with respect to the lower electrode layer 30, it is 3 at the maximum.
Only about 0 nm is etched. That is, TiOx
If is used as it is as the interlayer insulating film, the non-uniformity of the pattern or the interlayer insulating film in the wafer surface generated by the main etching step can be about 30 nm.
If the etching stop layer 20 is not provided, the non-uniformity of the interlayer insulating film generated by the main etching process becomes about 300 nm at maximum when overetching is performed by 50%.

From the above, the nonuniformity of the interlayer insulating film formed by overetching by the etching stop layer 20 can be reduced to 1/10 or less.

The step difference between the capacitors and the space around the capacitors is the sum of the total film thickness of the lower electrode 30, the ferroelectric film 40, and the upper electrode 50 and the film thickness of the underlying interlayer insulating film to be removed by overetching. When the manufacturing method of the present invention is used, there is almost no scraping of the underlying interlayer insulating film due to overetching, and therefore, in this embodiment, about 600 to 630 nm is used.
It can be a step. If patterning is performed without using the etching stop film 20, the step difference is 600.
nm to 900 nm. Therefore, according to the present invention, the step difference can be minimized. That is, a hydrogen barrier film or the like can be satisfactorily formed thereon. Also,
A post-process such as an aluminum wiring or contact hole forming process can be favorably performed. Further, since the steps can be made substantially the same between the patterns and in the wafer surface, the yield is improved.

After that, the etching stop layer 20 can be removed by performing dry etching using chlorine gas or boron trichloride gas having a reducing action. For example, with boron trichloride gas or a mixed gas of chlorine gas and boron trichloride gas, an ICP etcher is used, the pressure is about 10 Pa, and the plasma output is 1 k.
This can be performed by dry etching with W and bias output set to 50 W to enhance the reactivity.

In this step, the mask 61 may be used as it is, or another mask may be used for patterning. For example, when a conductive material is used as the etching stop layer, this material can be patterned again as the lower electrode 30.

(Patterning with Hard Mask) First, as shown in FIG. 6, a hard mask 62 is formed on the upper electrode 50. As a method of forming the hard mask 62, for example, a hard mask material is formed on the upper electrode 50, a resist is patterned thereon by a known method, and then the hard mask material is patterned by etching. Then, it is formed by removing the resist by ashing or the like.

The mask material is not particularly limited, such as SiO 2 or SiN, but a metal such as Ti, which is easily oxidized by oxygen, or its compound, TiOx, TiN, or A.
When formed of 12O3 or the like as a material, it has the same properties as the etching stop layer, and therefore the ratio of the etching rate to the material forming the ferroelectric capacitor (= etching rate of the material forming the ferroelectric capacitor / mask material The etching rate) can be 10 or more.
Therefore, the film thickness of the mask can be reduced. In the present embodiment, for example, a TiN film is formed on the upper electrode 50 by 20 times.
It is formed by a sputtering method to have a film thickness of 0 nm. After that, the resist is patterned by a known method, and dry etching is performed in an ICP dry etching apparatus using chlorine gas at a pressure of about 1.0 Pa and a bias output of 100 W. Further, the hard mask layer 62 is formed by removing the resist by ashing using oxygen plasma.

Next, as shown in FIG. 7, the upper electrode 50, the ferroelectric film 40, and the lower electrode 30 are formed into the etching stop layer 2.
Etch and pattern until at least a portion of the zeros appear. Dry etching can be used for etching, and for example, ICP (Inductively Coupled
High density plasma etching equipment such as Plasma) can be used. This etching is performed by using, for example, chlorine gas,
It is a mixed gas of oxygen gas, and the ratio of oxygen gas to the total gas flow rate is 40%, the gas pressure is low pressure of 1.0 Pa or less (for example, 0.5 Pa), and the bias output is 1 kW to enhance the sputterability. Etching is performed. In this case, since the hard mask layer 62 is thin, the hard mask layer 62
The residue 65 attached to the side wall is smaller than that when the resist mask 61 is used. Therefore, a better etching shape than the resist mask can be obtained.

Next, over-etching is performed as shown in FIG. For this over-etching, a mixed gas containing at least oxygen gas and halogen gas is used as an etching gas. Further, for example, a rare gas such as argon gas can be mixed. In the etching of the upper electrode 50, the ferroelectric film 40, and the lower electrode 30, when the etching gas is a mixed gas containing at least oxygen gas and halogen gas, the above etching conditions can be used as they are. In this embodiment, patterning is performed by etching similar to the etching of the upper electrode 50, the ferroelectric film 40, and the lower electrode 30. At this time, in the residue 65, the hard mask 62 recedes and the taper angle θ is about 80.
By setting the angle to °, sputter etching is easily performed. Further, the lower electrode material which causes the residue does not adhere to the side wall of the mask, or even if it adheres, it is a small amount. Therefore, the amount of sputter etching is larger than the amount of adhesion. As a result, the residue 65 can be completely removed.

From the above, as shown in FIG. 9, the nonuniformity of the interlayer insulating film formed during overetching by the etching stop layer can be reduced to 1/10 or less.

The hard mask 62 is oxidized by oxygen plasma and becomes TiOx. Therefore, in this embodiment, both the hard mask 62 and the etching stop film 20 are made of TiOx, so that they can be removed at the same time. For example, boron trichloride gas or a mixed gas of chlorine gas and boron trichloride gas having a reducing action
This can be performed by dry etching using a CP etcher with a pressure of about 10 Pa, a plasma output of 1 kW, and a bias output of 50 W to improve the reactivity.

The hard mask 62 may be removed in a later step, or a contact hole may be formed on the upper electrode 50.

(Patterning with a mask having a laminated structure of a resist mask and a hard mask) As a modification of the resist mask and the hard mask, a mask obtained by combining the above two masks can be used.

In particular, in order to use as a hard mask a material that causes a large dimensional conversion difference and is difficult to etch, it is necessary to thin the material to facilitate etching. Therefore, the material is thinned by stacking a resist on the material and increasing the film thickness of the mask. As such a material, a material having a high hydrogen barrier property such as Al2O3 can be used.

In this case, since the hard mask is located in the lower layer as compared with the case where only the resist mask is used, it is not necessary to consider the increase in the resist etching amount due to the oxygen plasma during overetching. Therefore, the resist film thickness is
The film thickness can be about twice the total film thickness of the lower electrode 30, the ferroelectric film 40, and the upper electrode 50. In this embodiment, since the total film thickness is 600 nm, the resist film can be formed to have a film thickness of about 1.2 μm.

The patterning method using this mask can be performed by using the resist mask 61.

[0047]

As described above, according to the method of manufacturing a ferroelectric memory device of the present invention, a metal that is easily oxidized or a compound of the metal is used as an etching stop layer, and at least oxygen and halogen gas are used in overetching. By using the contained mixed gas, the etching rate of the etching stop layer can be reduced to 1/10 of the etching rate of the material forming the ferroelectric memory. That is, the step formed by over-etching can be reduced to 1/10. Therefore,
The step difference of the capacitor formed in the etching can be minimized, and the step difference caused by the pattern density and the in-plane distribution of the etching characteristics can be prevented.

[Brief description of drawings]

FIG. 1A and FIG. 1B are diagrams schematically showing a method of manufacturing a ferroelectric memory according to an embodiment of the present invention.

FIG. 2 is a diagram schematically showing the manufacturing method of the ferroelectric memory according to the embodiment of the present invention.

3A to 3D are diagrams schematically showing a method of manufacturing a ferroelectric memory according to an embodiment of the present invention.

FIG. 4 is a diagram schematically showing a manufacturing method of the ferroelectric memory according to the embodiment of the present invention.

FIG. 5 is a diagram schematically showing the manufacturing method of the ferroelectric memory according to the embodiment of the present invention.

FIG. 6 is a diagram schematically showing a manufacturing method of the ferroelectric memory according to the embodiment of the present invention.

FIG. 7 is a diagram schematically showing the manufacturing method of the ferroelectric memory according to the embodiment of the present invention.

FIG. 8 is a diagram schematically showing the manufacturing method of the ferroelectric memory according to the embodiment of the present invention.

FIG. 9 is a diagram schematically showing the manufacturing method of the ferroelectric memory according to the embodiment of the present invention.

[Explanation of symbols]

10. Substrate 20. Etching stop layer 30. Lower electrode 31. Lower electrode remaining 40. Ferroelectric layer 50. Upper electrode 60. Mask layer 61. Resist mask 62. Hard mask 65. Leftovers

Claims (8)

[Claims] 1. A method of manufacturing a ferroelectric memory device having a ferroelectric capacitor, wherein the ferroelectric capacitor is composed of at least a lower electrode, a ferroelectric layer and an upper electrode, and the steps of: A method of manufacturing a ferroelectric memory device, comprising: (A) a step of forming an etching stop layer made of a metal that is easily oxidized or a compound of the metal on the substrate,
(B) forming a layered body for at least a part of the ferroelectric capacitor on the etching stop layer, and (c) forming a mask layer having a predetermined pattern on the layered body. And (d) etching the layered body using the mask layer as a mask until a part of the etching stop layer appears, (e)
The method includes overetching the layered body with a mixed gas containing at least oxygen and a halogen gas. 2. The method for manufacturing a ferroelectric memory device according to claim 1, wherein the etching stop layer is an insulating film. 3. The layered body according to claim 1, wherein the layered body is a conductive layer for the lower electrode, or a laminated film including a conductive layer for the lower electrode and the ferroelectric layer, or the lower layer. A method of manufacturing a ferroelectric memory device, which is a laminated film including a conductive layer for an electrode, the ferroelectric layer, and a conductive layer for the upper electrode. 4. The method for manufacturing a ferroelectric memory device according to claim 1, further comprising a step of removing the etching stop layer after the step (e). 5. The method for manufacturing a ferroelectric memory device according to claim 1, wherein the mask layer is a resist. 6. The method of manufacturing a ferroelectric memory according to claim 1, wherein the mask layer is made of a metal that is easily oxidized or a compound of the metal. 7. The method of manufacturing a ferroelectric memory device according to claim 1, wherein the mask layer is a laminated film of a resist and a metal that is easily oxidized or a compound of the metal. 8. The method of manufacturing a ferroelectric memory device according to claim 1, further comprising a memory cell array in which memory cells including the ferroelectric capacitors are arranged in a matrix.