JP2003273239A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit in which efficiency in the layout of an element on a device is improved in the semiconductor integrated circuit capable of high-speed operating at a low voltage. <P>SOLUTION: Each of MOS transistors comprising a flip-flop circuit 50 is an MOS transistor making a threshold voltage variable by changing a body voltage for the purpose of low-voltage and high-speed driving, and is driven on the basis of a forward phase clock signal CB or a backward phase clock signal CN. The respective transistors are located together in either an N-well area 701 and a P-well area 704 in which the voltage is controlled by the forward phase clock signal CB, or in a P-well area 702 and an N-well area 703 in which the voltage is controlled by the backward phase clock signal CN on the basis of an input signal and a conductive type thereof. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit which realizes high speed operation with a low voltage.

[0002]

2. Description of the Related Art In order to meet the demand for higher performance of information equipment such as personal computers and personal digital assistants accompanying the progress of IT technology, semiconductor integrated circuits mounted on these information equipment also have higher performance and higher performance. It has been planned. However, on the other hand, the power consumption of the semiconductor integrated circuit is increased due to the improvement of the operating frequency, the increase of the chip area, and the like, and the problems of heat radiation and the voltage drop are becoming more serious.

It is generally known that reducing the power supply voltage is effective for reducing power consumption. On the other hand, if the power supply voltage is reduced to near the threshold voltage of a MOS transistor used in a semiconductor integrated circuit, The drive current of the MOS transistor is reduced and the operating speed is deteriorated. Further, if the threshold voltage is reduced in consideration of the deterioration of the operating speed, a remarkable leak current is generated, which in turn leads to an increase in power consumption. As a transistor that can deal with such problems,
DT-MOS transistor (Dynamic Threshold MOSFE) that operates under low voltage and can prevent deterioration of operating speed
T) is known.

FIG. 12 is a sectional view showing the device structure of an N-channel DT-MOS transistor. Referring to FIG. 12, N-channel DT-MOS transistor 100
Is formed on an SOI (Silicon On Insulator) substrate, and has a SiO buried oxide layer 101 and a SiO buried oxide layer 1.
01, a P-type silicon layer 102 is formed. In the P-type silicon layer 102, N + diffusion regions 1021, 102
2 and a P-type body region 102 formed between them
3 is formed. Above the central portion of the element region, the gate electrode 10 is formed via the gate oxide film 103.
4 is formed.

N-channel DT-MOS transistor 10
0, the P-type body region 1023 is the gate electrode 1
04 is connected. As a result, when a voltage is applied to the gate electrode 104 (H (logical high) as an input signal)
Level signal is input), P-type body region 1
Since a voltage is also applied to 023 and the PN junction in the element region is in a forward bias state, the threshold voltage in the DT-MOS transistor 100 becomes low. On the other hand, when no voltage is applied to the gate electrode 104 (when an L (logical low) level signal is input as an input signal)
No voltage is applied to the P-type body region 1023, and the PN junction in the element region is in a non-biased state, so that the threshold voltage of the DT-MOS transistor 100 does not decrease.

Therefore, in the N-channel DT-MOS transistor 100, when the transistor is turned on, the driving capability is increased due to the reduction of the threshold voltage,
When the transistor is off, the leak current due to the decrease in the threshold voltage can be suppressed to some extent.

However, this N channel DT-MO
Also in the S transistor 100, the transistor is ON
During this period, the PN junction in the element region is in a forward bias state, so that a through current flows from the input node to the node connected to the N + diffusion regions 1021 and 1022.

A CMOS logic circuit which can solve such problems and can operate at a high speed with a low voltage is disclosed in Japanese Patent Laid-Open No. 25101/1996.
No. 2 publication. FIG. 13 shows Japanese Patent Laid-Open No. 8-25.
It is a circuit diagram which shows the structure of the CMOS inverter described in Japanese Patent No. 1012. Referring to FIG. 13, CMOS inverter 200 includes P-channel MOS transistor 201.
, N-channel MOS transistor 202, input node 203, output node 204, and power supply node 205
And a ground node 206.

The gate and body of P-channel MOS transistor 201 are connected to input node 203, the source thereof is connected to power supply node 205, and the drain thereof is connected to output node 204.

N channel MOS transistor 202 has its gate connected to input node 203, its drain connected to output node 204, and its source and body connected to ground node 206.

FIG. 14 is a sectional view showing the device structure of the CMOS inverter 200. Referring to FIG. 14, C
The MOS inverter 200 is formed on the SOI substrate,
P channel MOS transistor 201 and N channel MOS transistor 202 are formed on SiO buried oxide layer 214. The P-channel MOS transistor 201 and the N-channel MOS transistor 202 are isolated from each other and from other element regions (not shown) by the SiO insulating layers 212 to 213.

The element region of P channel MOS transistor 201 includes P + diffusion regions 2011 and 2012 and an N type body region 2013 formed therebetween.
Further, a gate electrode 2015 is formed above the N-type body region 2013 via a gate oxide film 2014.

Further, the N-channel MOS transistor 20
The second element region includes N + diffusion regions 2021 and 2022 and a P-type body region 2023 formed between them. A gate electrode 2025 is formed above the P type body region 2023 with a gate oxide film 2024 interposed therebetween.

Then, as described above, the P channel MO
The gate electrode 2015 and the N-type body region 2013 of the S transistor 201 are connected to the input node 203,
The P + diffusion region 2011 is connected to the power supply node 205,
P + diffusion region 2012 is connected to output node 204.

Further, the N-channel MOS transistor 20
The second gate electrode 2025 is connected to the input node 203, the N + diffusion region 2021 is connected to the output node 204, the N + diffusion region 2022 and the P-type body region 202.
3 is connected to the ground node 206.

In CMOS inverter 200, when an L level signal is input to input node 203, P channel MOS transistor 201 is turned on to pull up output node 204 to the power supply level and N channel MOS transistor.
The transistor 202 is turned off. Therefore, an H level signal is output from output node 204.

On the other hand, when an H level signal is input to input node 203, P channel MOS transistor 201
Turns off and the N-channel MOS transistor 202 turns O
N, the output node 204 is fixed to the ground level. Therefore, an L level signal is output from output node 204.

Here, when an L level signal is input to the input node 203, the body bias is not applied to the N type body region 2013 and the threshold voltage of the P channel MOS transistor 201 is lowered, so that the driving capability is increased. Increase. On the other hand, in N-channel MOS transistor 202, P-type body region 2023 is fixed to the ground level, and a through current generated by the PN junction being in the forward bias state does not flow.

When an H level signal is input to the input node 203, the P channel MOS transistor 2
Since the body bias of 01 rises and the threshold voltage of P channel MOS transistor 201 rises, a through current does not flow in P channel MOS transistor 201. On the other hand, the P-type body region 2023 of the N-channel MOS transistor 202 is fixed to the ground level, and P
No through current flows through the N-junction.

[0020]

As described above, the CM
The OS inverter 200 realizes a low voltage and high speed operation, but in the P channel MOS transistor 201 and the N channel MOS transistor 202, the voltage applied to the well (body region) of each transistor differs depending on the operation of each transistor. It is necessary to separate the well (body region) for each transistor. Therefore, especially when a circuit having the above-described device structure is applied to a large-scale logic circuit, the area demerit becomes a serious problem.

Here, the above-mentioned CMOS inverter is not provided on the SOI substrate without separately forming each transistor.
Consider the case of forming on a mold type silicon substrate.

FIG. 15 is a sectional view showing a device structure when a CMOS inverter corresponding to the CMOS inverter 200 is formed on a P-type silicon substrate.
Referring to FIG. 15, in CMOS inverter 300, P channel MOS transistor 301 is formed in N well region 311 formed on P type silicon substrate (P well region) 310, and N channel is formed in P well region 310. A MOS transistor 302 is formed.

The element region of the P-channel MOS transistor 301 is a channel formation region 3 between the P + diffusion regions 3011 and 3012 and the P + diffusion regions 3011 and 3012.
013 and. Further, above the channel formation region 3013, the gate electrode 30 is provided with a gate oxide film 3014 interposed therebetween.
15 is formed.

Further, the N-channel MOS transistor 30
The element regions of No. 2 are N + diffusion regions 3021 and 3022,
The channel formation region 3023 between the N + diffusion regions 3021 and 3022 is included. In addition, the channel formation region 302
A gate electrode 3025 is formed above the gate electrode 3 via a gate oxide film 3024.

Then, the P-channel MOS transistor 3
01 gate electrode 3015 and N + diffusion region 307 formed in the N well region 311 are input nodes 303.
And the P + diffusion region 3011 is connected to the power supply node 305.
Connected to the output node 304 of the P + diffusion region 3012.
Connected to.

Further, the N-channel MOS transistor 30
The second gate electrode 3025 is connected to the input node 303, the N + diffusion region 3021 is connected to the output node 304, the N + diffusion region 3022 and the P-type silicon substrate 31.
The P + diffusion region 308 formed in 0 is the ground node 30.
6 is connected.

In CMOS inverter 300, when an H level signal is input to input node 303, P channel MOS transistor 301 is turned off and N channel MOS transistor 302 is turned on to output node 20.
Fix 4 to ground level. Therefore, output node 2
From 04, an L level signal is output.

However, when an L level signal is input to the input node 303, no reverse bias is applied between the N well region 311 and the P type silicon substrate 310 (P well region), and wells are separated. Without P channel M
The OS transistor 301 and the N-channel MOS transistor 302 cannot operate at the same time.

Therefore, in such a case, conventionally, each well is separated on the SOI substrate to form a circuit. Therefore, there is a problem that the layout area cannot be increased and the layout efficiency cannot be sufficiently improved, and this problem has been particularly remarkable in a large-scale semiconductor integrated circuit.

Therefore, the present invention has been made to solve the above problems, and an object thereof is to improve the layout efficiency of elements on a device in a semiconductor integrated circuit capable of high-speed operation under a low voltage. It is to provide a semiconductor integrated circuit capable of performing.

[0031]

According to the present invention, a semiconductor integrated circuit is a semiconductor integrated circuit including a MOS transistor capable of changing a threshold voltage by changing a well voltage applied to a well. The well voltage is controlled according to the operation of the MOS transistor, and the same conductivity type MO
The S transistors are formed on the same well.

Preferably, the well voltage is controlled so that the threshold voltage of the MOS transistor becomes small when the MOS transistor is driven.

Preferably, the gate electrode of the MOS transistor is connected to the well in which the MOS transistor is formed.

Preferably, the well includes a first well region of a first conductivity type and a second well region of a second conductivity type, the well voltage of the first well region and the second well region. The well voltages of the regions are controlled to different voltages.

Preferably, the well includes a first well region of the first conductivity type and a second well region of the second conductivity type, and the gate of the MOS transistor formed in the first well region. Electrode and M formed in the second well region
A control signal different from that of the gate electrode of the OS transistor is input.

Preferably, the well further includes a third well region of the first conductivity type and a fourth well region of the second conductivity type, and the well voltages of the first and fourth well regions are , The well voltage of the second and third well regions is controlled based on the second control signal which is complementary to the first control signal. Has a second conductivity type MOS transistor receiving a first control signal at its gate electrode, and a first conductivity type MOS transistor receiving a second control signal at its gate electrode in the second well region. A second conductivity type MOS transistor whose gate electrode receives the second control signal is formed in the third well region, and the first control signal is applied to the gate electrode in the fourth well region. First conductivity type MOS transistor Njisuta is formed.

Preferably, the semiconductor integrated circuit further includes a well drive circuit that controls the well voltage to a predetermined voltage based on the first control signal.

Preferably, the well driving circuit controls the well voltage of the first well region to the power supply voltage and controls the well voltage of the third well region when the first control signal is at the first logic level. The voltage is controlled to be lower than the power supply voltage, and the second
Controlling the well voltage of the well region to the ground voltage, the well voltage of the fourth well region to a voltage higher than the ground voltage, and the first control signal at the second logic level,
The well voltage of the first well region is controlled to a voltage lower than the power supply voltage, the well voltage of the third well region is controlled to a power supply voltage, and the well voltage of the second well region is controlled to a voltage higher than the ground voltage. The well voltage of the fourth well region is controlled to the ground voltage.

As described above, according to the semiconductor integrated circuit of the present invention, the well voltage is the same and the conductivity is the same in the semiconductor integrated circuit using the MOS transistor for controlling the well voltage to realize a low voltage and high speed operation. Type MOS
By integrating the wells of the transistors, the layout area of the semiconductor integrated circuit can be reduced and the layout efficiency can be improved.

Further, by providing the well drive circuit for driving the well voltage, the well voltage can be stably driven and the circuit operation can be stabilized.

[0041]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts will be denoted by the same reference characters and description thereof will not be repeated.

In the following description, a semiconductor integrated circuit using a MOS transistor that realizes high-speed operation under a low voltage by changing the threshold voltage by changing the voltage level of the body according to the gate input An example in which a circuit is configured without separating wells for each element will be described above, but the circuit configuration is not limited to the circuit according to the following embodiments, and a semiconductor integrated circuit using the MOS transistor is described. In, the idea of the invention can be applied.

[First Embodiment] FIG. 1 is a circuit diagram showing the structure of a precharge type three-input NOR circuit using a MOS transistor having a body and a gate connected to each other.

Referring to FIG. 1, NOR circuit 10 includes a P channel MOS transistor 11, N channel MOS transistors 12 to 14, a clock input node 15, and
It includes input nodes 16-18, an output node 19, a power supply node 20, and a ground node 21.

The gate and body of P channel MOS transistor 11 are connected to clock input node 15, the source thereof is connected to power supply node 20, and the drain thereof is connected to output node 19.

N-channel MOS transistors 12-14
Each gate of is connected to the input nodes 16-18 respectively, and each drain is connected to the output node 19,
Each source and body is connected to ground node 21.

In NOR circuit 10, when clock signal CK input to clock input node 15 is at L level (hereinafter, a period when clock signal CK is at L level is referred to as "standby period"), a P channel MOS transistor is provided. 11 is turned on, and the output node 19 is pulled up to the power supply level.

At this time, since no voltage is applied to the body of the P-channel MOS transistor 11, the P-channel M
The OS transistor 2 is in the forward bias state, the threshold voltage is lowered, and the driving capability is increased. Also, N channel M
Since the bodies of the OS transistors 12 to 14 are grounded, no through current flows in the N channel MOS transistors 12 to 14.

Next, when the clock signal CK becomes H level (hereinafter, the period when the clock signal CK is H level is referred to as "active period"), the input signals IN1 to IN3 input to the input nodes 16 to 18, respectively. In response to the,
The output node 19 outputs the NOR logic state for the three input signals IN1 to IN3. That is, the output node 19 becomes L level when at least one of the input signals IN1 to IN3 is at H level, and the output node 19 becomes H level only when all of the input signals IN1 to IN3 are at L level.

FIG. 2 is a sectional view showing the device structure of the NOR circuit 10. Referring to FIG. 2, in NOR circuit 10, P channel MOS transistor 11 is formed in N well region 23 formed on P type silicon substrate (P well region) 22, and N channel is formed in P well region 22. MOS transistors 12-14 are formed.

The element region of the P-channel MOS transistor 11 includes P + diffusion regions 24 and 25 and a P + diffusion region 2.
And a channel forming region 26 between 4 and 25. Also,
A gate electrode 29 is formed above the channel formation region 26 via a gate oxide film 28.

Further, the N-channel MOS transistor 12
The element region of includes the N + diffusion regions 30 and 31 and the channel formation region 32 between the N + diffusion regions 30 and 31. The gate oxide film 3 is formed above the channel forming region 32.
The gate electrode 34 is formed through the line 3.

Further, the N-channel MOS transistor 1
The element region of No. 3 includes N + diffusion regions 31 and 35 and a channel forming region 36 between the N + diffusion regions 31 and 35.
A gate electrode 38 is formed above the channel forming region 36 with a gate oxide film 37 interposed therebetween.

Further, the element region of the N-channel MOS transistor 14 has N + diffusion regions 35, 39 and N + diffusion regions 35, 39.
And a channel forming region 40 between the + diffusion regions 35 and 39. A gate electrode 42 is formed above the channel formation region 40 with a gate oxide film 41 interposed.

Then, the P-channel MOS transistor 1
The gate electrode 29 of 1 and the N + diffusion region 27 included in the N well region 22 are connected to the clock input node 15, the P + diffusion region 24 is connected to the power supply node 20, and the P + diffusion region 24 is connected to the power supply node 20.
The + diffusion region 25 is connected to the output node 19.

Further, the N-channel MOS transistor 12
Gate electrodes 34, 38, 42 of N.about.14 are connected to input nodes 16-18, respectively, and N-channel MOS
The N + diffusion region 30 of the transistor 12 and the N + diffusion region 35 of the N-channel MOS transistors 13 and 14 are
It is connected to the output node 19. In addition, N-channel MOS
The N + diffusion region 31 of the transistors 12 and 13 and the N + diffusion region 39 of the N-channel MOS transistor 14 are
Each of the P + diffusion regions 43 connected to the ground node 21 and included in the P-type silicon substrate 22 is connected to the ground node 21.

In this NOR circuit 10, the input of P-channel MOS transistor 11 and the inputs of N-channel MOS transistors 12-14 are separated, and P-channel MOS transistor 11 and N-channel MOS transistors 12-14 do not operate simultaneously. As described above, the clock signal CK and the input signals IN1 to IN3 are clock-controlled.

By doing so, during the standby period, N
No reverse bias is applied to the PN junction between the well region 23 and the P-type silicon substrate 22, but at this time the N-channel M
During the active period in which the OS transistors 12 to 14 do not operate and the N channel MOS transistors 12 to 14 operate, a voltage is applied to the N well region 23 from the clock input node 15 and the N well region 23 and the P type Since the PN junction with the silicon substrate 22 is reverse-biased, the N-channel MOS transistors 12 to 14 operate normally without being affected by the state of the P-channel MOS transistor 11.

As described above, a circuit which realizes a low voltage and a high speed operation can be constructed only by dividing the well region into two regions (P well region (P type silicon substrate 22) and N well region 23). Therefore, the layout area of the semiconductor integrated circuit can be reduced and the layout efficiency can be improved.

[Second Embodiment] FIG. 3 is a circuit diagram showing a structure of a flip-flop circuit using a MOS transistor having a body and a gate connected to each other.

Referring to FIG. 3, flip-flop circuit 5
0 is the master latch circuit 51 and the master latch circuit 51.
A slave latch circuit 52 connected in series, an input node 53 to which data D is input, and an output node 61 to which data Q is output.

The master latch circuit 51 includes transfer gates 511 and 512, inverters 513 and 514,
Slave latch circuit 52 including nodes 54 to 57
Includes transfer gates 521 and 522, inverters 523 and 524, and nodes 57-60.

The transfer gate 511 has a P-channel MOS transistor 5111 whose gate and body receive the positive-phase clock signal CB and an N-channel MOS transistor whose gate and body receive the negative-phase clock signal CN.
And a transistor 5112.

The anti-phase clock signal CN is the clock signal C.
K is generated by being inverted by the inverter 62, and the positive phase clock signal CB is generated by further inverting the opposite phase clock signal CN by the inverter 63.

The transfer gate 512 has a gate and a body to which the positive-phase clock signal CB is input.
It includes a channel MOS transistor 5121 and a P-channel MOS transistor 5122 to which a reverse phase clock signal CN is input to its gate and body. Further, the transfer gate 521 has a P-channel MOS transistor 5211 having a gate and a body to which a negative-phase clock signal CN is input, and an N-channel MOS transistor 52 having a gate and a body to which the positive-phase clock signal CB is input.
It consists of 12. In addition, the transfer gate 5
Reference numeral 22 denotes an N-channel MOS transistor 5221 to which a reverse phase clock signal CN is input at its gate and body,
A P-channel MOS transistor 5222 to which the positive phase clock signal CB is input to the gate and the body.

The positive-phase clock signal CB and the negative-phase clock signal CN are supplied to the inverters 513, 514, 523, 52.
It is also input to 4.

4 and 5 show inverters 513, 514, and
It is a circuit diagram which shows the detailed structure of 523,524. Since the inverters 513 and 524 have the same configuration and the inverters 514 and 523 have the same configuration, only the inverter 513 will be described in FIG. 4, and the description of the inverter 524 will be omitted because it is repeated. Also in FIG. 5, only the description of the inverter 514 will be given, and the description of the inverter 523 will be omitted.

Referring to FIG. 4, inverter 513 is a P channel M whose positive phase clock signal CB is input to the body.
The OS transistor 5131 and the N-channel MOS transistor 51 to which the negative phase clock signal CN is input to the body
And 32. The drains of the respective transistors are connected, the source of the P channel MOS transistor 5131 is connected to the power supply node 5133, and the source of the N channel MOS transistor 5132 is connected to the ground node 5134. Then, an output signal is output from the node to which the drain of each transistor is connected.

In the inverter 513, the positive phase clock signal CB is at L level (the negative phase clock signal CN is at H level).
, P-channel MOS transistor 5131
Since the N-channel MOS transistor 5132 is in the forward bias state, the drivability is increased. On the other hand, when the positive phase clock signal CB is at the H level (the negative phase clock signal CN is at the L level), the P channel MOS transistor 5131 and the N channel MOS transistor 513.
No. 2 is in a non-biased state, so no through current flows.

Further, referring to FIG. 5, an inverter 514
Is composed of a P-channel MOS transistor 5141 having a body to which a negative-phase clock signal CN is input, and an N-channel MOS transistor 5142 having a body to which a positive-phase clock signal CB is input. The drain of each transistor is connected, the source of the P-channel MOS transistor 5141 is connected to the power supply node 5143, and the N-channel MOS transistor is connected.
The source of transistor 5142 is connected to ground node 5144. Then, an output signal is output from the node to which the drain of each transistor is connected.

In the inverter 514, the negative phase clock signal CN is at the L level (the positive phase clock signal CB is at the H level).
Level), the P-channel MOS transistor 5141 and the N-channel MOS transistor 5142
Is in a forward bias state, so that the driving capability is increased. On the other hand, when the negative-phase clock signal CN is at the H level (the positive-phase clock signal CB is at the L level), the P-channel MOS transistor 5141 and the N-channel MOS transistor 5142 are in the non-biased state, and no through current flows.

Referring again to FIG. 3, in flip-flop circuit 50, when clock signal CK attains L level, positive phase clock signal CB and negative phase clock signal CN attain L level and H level, respectively. , The transfer gates 511 and 512 are in the ON state,
The master latch circuit 51 is turned off, and the master latch circuit 51 is in the through mode for outputting the data D to the output node 57 (the logic state of the signal is inverted by the inverter 513).

At this time, all the transistors used in the transfer gate 511 and the inverter 513 are in the forward bias state, so that they are driven at high speed.

On the other hand, transfer gates 521 and 522
Are in the OFF state and the ON state, respectively, and the slave latch circuit 52 outputs the data latched in the slave latch circuit 52 to the output node 61 regardless of the state of the data D input to the flip-flop circuit 50. To do.

Next, the clock signal CK changes from L level to H level.
When the level changes, the positive-phase clock signal CB and the negative-phase clock signal CN become the H level and the L level, respectively, so that the transfer gates 511 and 512 are in the OFF state and the ON state, respectively, and the master latch circuit 51.
Shifts to the latch mode state, and the state of the data D immediately before is latched by the master latch circuit 51.

On the other hand, transfer gates 521 and 522
Are turned on and off, respectively, and the slave latch circuit 52 enters a through mode in which the data latched by the master latch circuit 51 is output to the output node 61 (the data latched by the master latch circuit 51 is inverted by the inverter 523). Will be output.).

At this time, all the transistors used in the transfer gate 521 and the inverter 523 are in the forward bias state, so that they are driven at high speed.

FIG. 6 is a plan view showing a device layout of the flip-flop circuit 50 formed on the P-type silicon substrate. Referring to FIG. 6, N well regions 701, 703, 7 are formed on a P type silicon substrate (not shown).
11, 712 and P well regions 702, 704, 713
To form a well region. P well region 70
2, 704 are formed on the N well regions 711 and 712, respectively.

The voltage level of N well region 701 is controlled by positive phase clock signal CB. N well region 7
01 is a P-channel MOS transistor 5111, 513 whose positive electrode clock signal CB is input to its gate electrode.
1, 5222, 5241 are formed.

The P well region 702 is the P well region 71.
Formed on the N well region 711 for separating from
The voltage level is controlled by the anti-phase clock signal CN. In the P well region 702, N channel MOS transistors 5112, 5132, 5221, 5242 having the gate electrode to which the reverse phase clock signal CN is input are formed.

The voltage level of N well region 703 is controlled by antiphase clock signal CN. N well region 7
03 is a P-channel MOS transistor 5122, 514 to which the reverse phase clock signal CN is input to the gate electrode.
1, 5211, 5231 are formed.

The P well region 704 corresponds to the P well region 71.
Formed on the N well region 712 for separating from
The voltage level is controlled by the positive phase clock signal CB. In the P well region 704, N channel MOS transistors 5121, 5142, 5212, 5232 having the positive electrode clock signal CB input to the gate electrode are formed.

N well regions 711 and 712 are regions formed to separate P well regions 702 and 704 from P well region 713, respectively.

The P well region 713 is the N well region 70.
1, 703 and P well regions 702, 704 are formed to separate each, and are fixed to the ground level of the P type silicon substrate.

N + diffusion region 721 is connected through a contact hole to node 731 to which positive phase clock signal CB is input. Then, the positive well clock signal CB input to the node 731 drives the N well region 701.

P + diffusion region 722 is connected through a contact hole to node 732 to which antiphase clock signal CN is input. Then, the P-well region 702 is driven by the negative-phase clock signal CN input to the node 732.

N + diffusion region 723 is connected to node 732 via a contact hole. And node 7
The negative well clock signal CN input to 32 drives the N well region 703.

P + diffusion region 724 is connected to a node 734 to which positive phase clock signal CB is input via a contact hole. Then, the P-well region 704 is driven by the positive-phase clock signal CB input to the node 734.

The P-channel MOS transistor 5111 forming the transfer gate 511 has a P + diffusion region 8
11 and 812, the P + diffusion region 811 is connected to the input node 53 through the contact holes 801 and 802, and the P + diffusion region 812 includes the contact hole 80.
It is connected to the node 56 via 3, 804. The gate electrode 821 is formed above a channel formation region (not shown) formed between the P + diffusion regions 811 and 812 via a gate oxide film (not shown) and is connected to the node 54 (see FIG. The positive phase clock signal CB is input (not shown).

The N-channel MOS transistor 5112 forming the transfer gate 511 is composed of the N + diffusion region 8
13 and 814, the N + diffusion region 813 is connected to the input node 53 through the contact holes 805 and 806, and the N + diffusion region 814 includes the contact hole 80.
It is connected to the node 56 via 7,808. The gate electrode 822 is formed above a channel forming region (not shown) formed between the N + diffusion regions 813 and 814 via a gate oxide film (not shown) and is connected to the node 55 (see FIG. A negative phase clock signal CN is input (not shown).

Other P-channel MOS transistor 5
131, 5222, 5241, 5122, 5141, 5
211, 5231 and N-channel MOS transistors 5132, 5221, 5242, 5121, 514
2, 5212, and 5232, the P-channel MOS transistor 5111 or the N-channel M
The configuration is similar to that of the OS transistor 5112, and detailed description of individual transistors is omitted below.

N channel MOS transistor 5121 and P channel M forming transfer gate 512.
OS transistor 5122 is connected via nodes 56 and 841. N-channel MOS transistor 512
The gate electrode 823 of No. 1 is connected to the node 54 (not shown) to receive the positive phase clock signal CB, and the gate electrode 824 of the P-channel MOS transistor 5122 is connected to the node 55 (not shown). Phase clock signal C
N is input.

P channel M forming the inverter 513
OS transistor 5131 and N-channel MOS transistor 5132 are connected to power supply node 5133 and ground node 5134, respectively, and are also connected to node 57. P-channel MOS transistor 51
The common gate electrode 825 of 31 and the N-channel MOS transistor 5132 is connected to the node 56 via the contact hole.

P-channel M forming the inverter 514
OS transistor 5141 and N-channel MOS transistor 5142 are connected to power supply node 5143 and ground node 5144, respectively, and are also connected to node 841. P-channel MOS transistor 5
Common gate electrode 826 of 141 and N channel MOS transistor 5142 is connected to node 57 through a contact hole.

P channel MOS transistor 5211 and N channel M forming transfer gate 521.
OS transistor 5212 is connected via nodes 57 and 60. P-channel MOS transistor 5211
The gate electrode 827 of the N-channel M is connected to the node 58 (not shown) to receive the negative-phase clock signal CN.
The gate electrode 828 of the OS transistor 5212 is connected to the node 59 (not shown) and the positive-phase clock signal CB
Is entered.

N-channel MOS transistor 5221 and P-channel M forming transfer gate 522.
The OS transistor 5222 is connected via the nodes 60 and 842. N-channel MOS transistor 522
The gate electrode 829 of No. 1 is connected to the node 58 (not shown) to receive the negative phase clock signal CN, and the gate electrode 830 of the P-channel MOS transistor 5222 is connected to the node 59 (not shown) to be positive. Phase clock signal C
B is input.

P channel M forming the inverter 523
OS transistor 5231 and N-channel MOS transistor 5232 are connected to power supply node 5233 and ground node 5234, respectively, and are also connected to output node 61. P-channel MOS transistor 5231 and N-channel MOS transistor 5232
Common gate electrode 831 is connected to the node 60 through a contact hole.

P channel M forming the inverter 524
OS transistor 5241 and N-channel MOS transistor 5242 are connected to power supply node 5243 and ground node 5244, respectively, and are both connected to node 842. P-channel MOS transistor 5
Common gate electrode 832 of 241 and N channel MOS transistor 5242 is connected to output node 61 via a contact hole.

All of these transistors are configured as low voltage and high speed transistors in which the gate and body (well) are driven in the same voltage state. In such a case, in the conventional case, as described above, all the transistors had to be separated by the SiO insulating phase, but the well voltage in the N well region 701 was driven by the positive phase clock signal CB. P channel MOS transistor 5111,
5131, 5222, 5141 are collectively arranged, and P
The well voltage is applied to the well region 702 as the negative phase clock signal CN.
N-channel MOS transistor 51 driven by
12, 5132, 5221 and 5142 are collectively arranged, P-channel MOS transistors 5122, 5141, 5211 and 5231 whose well voltages are driven by the anti-phase clock signal CN are collectively arranged in N well region 703, and P well region is arranged. N-channel MOS transistors 5121, 5142, 5212, and 5232 whose well voltages are driven by the positive-phase clock signal CB are collectively arranged at 704.

That is, all the transistors operate in synchronization with the clock signal CK, and the transistors of the same conductivity type that operate in the same phase are collectively arranged on the same well, whereby the efficiency of the layout is greatly improved. ing.

The arrangement of each well region is not limited to the layout shown in FIG. The layout shown in FIG. 6 is an example, and when actually designing a specific circuit, the well regions should be arranged appropriately for the circuit while considering the integration of the well regions as described above. Is.

As described above, in a semiconductor integrated circuit using a MOS transistor which controls a well voltage to realize a low voltage and high speed operation, wells of MOS transistors operating in the same phase and having the same conductivity type are integrated. As a result, the layout area and the layout efficiency of such a semiconductor integrated circuit can be reduced.

[Third Embodiment] The voltage of each well region in the flip-flop circuit 50 according to the second embodiment is
The well voltage was directly driven by the positive-phase clock signal CB and the negative-phase clock signal CN, but when the circuit configuration becomes large-scale, the well region to be combined tends to be large. It is necessary to drive with a driver. In the flip-flop circuit 50A according to the third embodiment, which corresponds to the flip-flop circuit 50 according to the second embodiment, a well driver that drives the voltage of each well region is provided, and the voltage of each well region is driven by the well driver. It

Referring to FIG. 7, flip-flop circuit 5
In 0A, N + diffusion region 723 is not connected to node 732 but is connected to node 733.

Then, the node 73 of the N well region 701 is formed.
The voltage output from the output node for the N well region of the well driver 65 described later is applied to the node 733 of the 1 and N well regions 703, and the node 732 of the P well region 702 and the node 734 of the P well region 704 are applied.
Is applied with the voltage output from the output node of the well driver 65 for the P well region. The other device configuration of flip-flop 50A is the same as that of flip-flop circuit 50, and the description thereof will not be repeated.

FIG. 8 is a circuit diagram showing the circuit configuration of the well driver 65. Referring to FIG. 8, well driver 6
5 is a driver circuit 65A, 65B, and an input node 65
6 and inverters 665 and 666. The driver circuit 65A includes P-channel MOS transistors 651 and 6
52 and N-channel MOS transistors 653, 654
, Inverter 655, and output nodes 657 and 658
, A power supply node 659, a ground node 660, and nodes 661 to 664. The driver circuit 65B has a P
Channel MOS transistors 751 and 752, N channel MOS transistors 753 and 754, inverter 755, output nodes 757 and 758, and power supply node 7
59, a ground node 760, and nodes 761-764.

The clock signal CK is applied to the input node 656.
Is entered. The driver circuit 65A uses the clock signal C
K receives the positive-phase clock signal CB in phase with clock signal CK, which is inverted twice by inverters 665 and 666. The output node 657 of the driver circuit 65A is connected to the node 731 of the N well region 701 shown in FIG. 7, and the output node 658 is the P well region 7 shown in FIG.
02 node 732.

The driver circuit 65B also receives a reverse-phase clock signal CN, which is the reverse phase of the clock signal CK and is obtained by inverting the clock signal CK by the inverter 665. The output node 757 of the driver circuit 65B is connected to the node 733 of the N well region 703 shown in FIG. 7, and the output node 758 is connected to the node 734 of the P well region 704 shown in FIG.

Next, the circuit configuration of the driver circuit 65A will be described. P-channel MOS transistor 651
Receives an output from inverter 655 at its gate through node 663, has its source connected to power supply node 659, and has its drain connected to output node 657.

The P-channel MOS transistor 652 is
The gate receives positive-phase clock signal CB through node 664, the source is connected to node 661, and the drain is connected to output node 657.

The N-channel MOS transistor 653 is
The gate receives the output from the inverter 655, the drain is connected to the output node 658, and the source is the ground node 6.
Connected to 62.

The N-channel MOS transistor 654 is
The positive phase clock signal CB is received at the gate through the node 664, the drain is connected to the output node 658, and the source is connected to the ground node 660.

Inverter 655 inverts positive-phase clock signal CB, which is an input signal, and outputs it to node 663.

Voltage Vref1 lower than the power supply level of power supply node 659 is applied to node 661. Further, voltage Vref2 higher than the ground level of ground node 660 is applied to node 662.

In the driver circuit 65A, when the positive phase clock signal CB is at H level, the P channel MO
Since S transistor 651 is turned on and P channel MOS transistor 652 is turned off, power supply voltage Vcc is output to output node 657. In addition, N channel MO
Since S transistor 653 is turned off and P channel MOS transistor 654 is turned on, ground voltage GND is output to output node 658.

On the other hand, when the positive-phase clock signal CB is at L level, the P-channel MOS transistor 651 is O.
Since the FF is performed and the P-channel MOS transistor 652 is turned on, the voltage Vref1 is output to the output node 657. In addition, the N-channel MOS transistor 653 is O
Then, the P-channel MOS transistor 654 is turned off, and the voltage Vref2 is output to the output node 658.

Next, the driver circuit 65B will be described. The circuit configuration of the driver circuit 65B is the driver circuit 6
The circuit configuration is the same as that of 5A and the operation with respect to the input is the same, and therefore the description thereof will not be repeated.

In the driver circuit 65B, when the anti-phase clock signal CN is at H level, the P channel MO
Since S transistor 751 is turned on and P channel MOS transistor 752 is turned off, power supply voltage Vcc is output to output node 757. In addition, N channel MO
Since S transistor 753 is turned off and P channel MOS transistor 754 is turned on, ground voltage GND is output to output node 758.

On the other hand, when anti-phase clock signal CN is at L level, P-channel MOS transistor 751 is turned on.
Since the FF is performed and the P-channel MOS transistor 752 is turned on, the voltage Vref1 is output to the output node 757. In addition, the N-channel MOS transistor 753 is O
Then, the P-channel MOS transistor 754 is turned off and the voltage Vref2 is output to the output node 758.

FIG. 9 is an MO formed in each well region in the flip-flop circuit 50A in response to the clock signal CK, based on the operation of the well driver 65 described above.
It is the figure which put together the bias state of the S transistor.

When the clock signal CK is at L level,
Voltage Vref1 (<power supply voltage Vcc) is applied from output node 657 of driver circuit 65A to N well region 701, and P channel MOS in N well region 701 is applied.
The transistor becomes forward biased. In the P well region 702, the output node 658 of the driver circuit 65A is also provided.
Voltage Vref2 (> ground voltage GND) is applied from
The N channel MOS transistor in P well region 702 is in a forward bias state. Furthermore, the N well region 7
Power supply voltage Vcc is applied to output circuit 03 from output node 757 of driver circuit 65B, and the P channel MOS transistor in N well region 703 is in a non-biased state. Further, the ground voltage GND is applied to the P well region 704 from the output node 758 of the driver circuit 65B, and the N channel MOS transistor in the P well region 704 is in a non-biased state.

Therefore, when clock signal CK attains the L level, master latch circuit 51 is formed, and each MOS transistor formed in N well region 701 and P well region 702 and included in transfer gate 511 and inverter 513 is The master latch circuit 51 is driven at high speed because of the forward bias state, and the master latch circuit 51 operates at high speed.

Next, when clock signal CK attains the H level, power supply voltage Vcc is applied from output node 657 of driver circuit 65A to N well region 701, and the P channel MOS transistor in N well region 701 is in the non-biased state. Become. Further, the P-well region 702 is connected to the ground voltage G from the output node 658 of the driver circuit 65A.
ND is applied, and the N channel MOS transistor in the P well region 702 becomes non-biased. Further, in the N well region 703, the voltage Vref1 (<power supply voltage Vcc) from the output node 757 of the driver circuit 65B is input.
Is applied to the P channel M in the N well region 703.
The OS transistor is in a forward bias state. Further, in the P well region 704, the voltage Vref2 (> ground voltage GND) from the output node 758 of the driver circuit 65B is applied.
Is applied to the N channel M in the P well region 704.
The OS transistor is in a forward bias state.

Therefore, when the clock signal CK goes high, the slave latch circuit 52 is formed and formed in the N well region 703 and the P well region 704.
Each of the MOS transistors included in the transfer gate 521 and the inverter 523 is in a forward biased state and therefore driven at high speed, and the slave latch circuit 52 operates at high speed.

In this way, the flip-flop circuit 5
0A can transit data from the input node 53 to the output node 61 at high speed.

Instead of the well driver 65 shown in FIG. 8, a well driver 67 shown in FIG. 10 may be used.

FIG. 10 is a circuit diagram showing the circuit configuration of the well driver 67. Referring to FIG. 10, the well driver 67 includes well circuits 65A, 65B instead of the driver circuits 65A, 65B in the well driver 65, respectively.
With 67B. The driver circuit 67A is a P channel M
OS transistors 671 and 672 and N-channel MOS
Transistors 673, 674, an inverter 675,
It includes output nodes 677 and 678, a power supply node 679, a ground node 680, and nodes 681 and 682. The driver circuit 67B includes the P-channel MOS transistor 7
71, 772 and N-channel MOS transistor 77
3,774, an inverter 775, and an output node 77.
7, 778, power supply node 779, and ground node 780
And nodes 781 and 782.

The driver circuit 67A includes an inverter 666.
From the positive phase clock signal CB. The output node 677 of the driver circuit 67A is connected to the node 731 of the N well region 701 shown in FIG. 7, and the output node 678 is the node 7 of the P well region 702 shown in FIG.
Connected to 32.

Further, driver circuit 67B receives anti-phase clock signal CN output from inverter 665.
Output node 777 of driver circuit 65B is connected to node 733 of N well region 703 shown in FIG. 7, and output node 778 is connected to node 734 of P well region 704 shown in FIG.

Next, the circuit configuration of the driver circuit 67A will be described. P-channel MOS transistor 671
Receives an output from inverter 675 at its gate through node 681, has its source connected to power supply node 679, and has its drain connected to output node 677.

The N-channel MOS transistor 673 is
The output from the inverter 675 is received by the gate through the node 681, the drain is connected to the power supply node 679,
The source is connected to the output node 677.

The N-channel MOS transistor 674 is
The positive phase clock signal CB is received by the gate through the node 682, the drain is connected to the output node 678, and the source is connected to the ground node 680.

The P-channel MOS transistor 672 is
The gate receives positive phase clock signal CB through node 682, the source is connected to output node 678, and the drain is connected to ground node 680.

Inverter 675 inverts positive-phase clock signal CB, which is an input signal, and outputs it to node 681.

In the driver circuit 67A, when the positive phase clock signal CB is at H level, the P channel MO
Since S transistor 671 is turned on and N channel MOS transistor 673 is turned off, power supply voltage Vcc is output to output node 677. In addition, N channel MO
Since S transistor 674 is turned on and P channel MOS transistor 672 is turned off, ground voltage GND is output to output node 678.

On the other hand, when the positive-phase clock signal CB is at L level, the P-channel MOS transistor 671 is O.
Then, the N-channel MOS transistor 673 is turned on, but in this case, since the voltage level of the output node 677 makes the N-channel MOS transistor 673 the source follower, the voltage level of the output node 677 changes from the power supply voltage Vcc to the N-channel MOS transistor. The voltage level drops by the threshold voltage of transistor 673. Similarly, the voltage level of output node 678 has a value increased from ground voltage GND by the threshold voltage of P-channel MOS transistor 672.

That is, the driver circuit 65 shown in FIG.
In A, when positive-phase clock signal CB is at L level, voltage Vref1 lower than power supply voltage Vcc and voltage Vr higher than ground voltage are applied to output nodes 657 and 658.
Corresponding to the output of ef2, in driver circuit 67A as well, when positive phase clock signal CB is at L level, output nodes 677 and 678 have a voltage lower than power supply voltage Vcc and a voltage lower than ground voltage GND. High voltage is output respectively.

Next, the driver circuit 67B will be described. The circuit configuration of the driver circuit 67B is the driver circuit 6
Since the circuit configuration of 7A is the same and the operation for the input is the same, the description thereof will not be repeated.

In the driver circuit 67B, when the negative-phase clock signal CN is at H level, the P-channel MO
Since S transistor 771 is turned on and N channel MOS transistor 773 is turned off, power supply voltage Vcc is output to output node 777. In addition, N channel MO
Since S transistor 774 is turned on and P channel MOS transistor 772 is turned off, ground voltage GND is output to output node 778.

On the other hand, when the anti-phase clock signal CN is at L level, the P channel MOS transistor 771 is turned on.
Since the FF is performed and the N-channel MOS transistor 773 is turned on, a voltage lower than the power supply voltage Vcc and a voltage higher than the ground voltage GND are output to the output nodes 777 and 778, respectively, as in the case of the driver circuit 67A. .

As described above, the well driver 67 has the same effect as the well driver 65.

Further, the well driver 65 shown in FIG.
The well driver 67 shown in FIG. 10 may be replaced with the well driver 69 shown in FIG.

FIG. 11 is a circuit diagram showing the circuit configuration of the well driver 69. Referring to FIG. 11, well driver 69 includes well driver 65, instead of driver circuits 65A and 65B.
With 69B. The driver circuit 69A is a P channel M
OS transistors 691, 692 and N-channel MOS
Transistors 693, 694, an inverter 695,
It includes output nodes 697 and 698, a power supply node 699, a ground node 689, and nodes 687 and 688. The driver circuit 69B includes the P-channel MOS transistor 7
91, 792 and N-channel MOS transistor 79
3, 794, the inverter 795, and the output node 79.
7, 798, power supply node 799, and ground node 789
And nodes 787 and 788.

The driver circuit 69A includes an inverter 666.
From the positive phase clock signal CB. The output node 697 of the driver circuit 69A is connected to the node 731 of the N well region 701 shown in FIG. 7, and the output node 698 is the node 7 of the P well region 702 shown in FIG.
Connected to 32.

Driver circuit 69B also receives anti-phase clock signal CN output from inverter 665.
Output node 797 of driver circuit 69B is connected to node 733 in N well region 703 shown in FIG. 7, and output node 798 is connected to node 734 in P well region 704 shown in FIG.

Next, the circuit configuration of the driver circuit 69A will be described. P-channel MOS transistor 691
Receives the output from inverter 695 at its gate via node 688, has its source connected to power supply node 699, and has its drain connected to output node 697.

The N-channel MOS transistor 693 is
The output from the inverter 695 is received by the gate via the node 688, the drain is connected to the output node 697,
The source is connected to ground node 689.

The P channel MOS transistor 692 is
The gate receives positive phase clock signal CB through node 687, the source is connected to power supply node 699, and the drain is connected to output node 698.

The N-channel MOS transistor 694 is
The gate receives positive phase clock signal CB through node 687, the drain is connected to output node 698, and the source is connected to ground node 689.

Inverter 695 inverts positive-phase clock signal CB, which is an input signal, and outputs it to node 688.

In the driver circuit 69A, when the positive phase clock signal CB is at H level, the P channel MO
Since S transistor 691 is turned on and N channel MOS transistor 693 is turned off, power supply voltage Vcc is output to output node 697. In addition, P channel MO
Since S transistor 692 is turned off and N channel MOS transistor 694 is turned on, ground voltage GND is output to output node 698.

On the other hand, when the positive-phase clock signal CB is at L level, the P-channel MOS transistor 691 is turned on.
Since the FF is performed and the N-channel MOS transistor 693 is turned on, the ground voltage GND is output to the output node 697. Further, the P-channel MOS transistor 692 is O
The N-channel MOS transistor 694 is turned off and the power supply voltage Vcc is output to the output node 698.

That is, in the driver circuit 69A, the voltage Vref1 in the driver circuit 65A is the ground voltage GND.
And is equivalent to the case where the voltage Vref2 is the power supply voltage Vcc.

Next, the driver circuit 69B will be described. The circuit configuration of the driver circuit 69B is the driver circuit 6
Since the circuit configuration of 9A is the same and the operation for the input is the same, the description thereof will not be repeated.

In the driver circuit 69B, when the anti-phase clock signal CN is at H level, the P channel MO.
Since S transistor 791 is turned on and N channel MOS transistor 793 is turned off, power supply voltage Vcc is output to output node 797. In addition, P channel MO
Since S transistor 792 is turned off and N channel MOS transistor 794 is turned on, ground voltage GND is output to output node 798.

On the other hand, when anti-phase clock signal CN is at L level, P-channel MOS transistor 791 is O.
Since the FF is performed and the N-channel MOS transistor 793 is turned on, the ground voltage GND is output to the output node 797. Further, the P-channel MOS transistor 792 is O
Since the N-channel MOS transistor 794 is turned off, the power supply voltage Vcc is output to the output node 798.

That is, in the driver circuit 69B, the voltage Vref1 in the driver circuit 65B is the ground voltage GND.
And is equivalent to the case where the voltage Vref2 is the power supply voltage Vcc.

In this way, the well driver 69 also has the same effect as the well driver 65.

As described above, in a semiconductor integrated circuit using a MOS transistor which controls a well voltage to realize a low voltage and a high speed operation, wells of a MOS transistor operating in the same phase and having the same conductivity type are integrated. By driving the integrated well voltage by the well driver, the layout area in such a semiconductor integrated circuit can be reduced, the layout efficiency can be improved, and the well voltage can be stably driven. It is possible to stabilize the circuit operation.

The embodiments disclosed this time must be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the claims, and is intended to include meanings equivalent to the claims and all modifications within the scope.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a precharge type 3-input NOR circuit using a MOS transistor having a body and a gate connected to each other.

FIG. 2 is a cross-sectional view showing a device configuration of the 3-input NOR circuit shown in FIG.

FIG. 3 is a circuit diagram showing a configuration of a flip-flop circuit using a MOS transistor having a body and a gate connected to each other.

4 is a circuit diagram showing a circuit configuration of a first inverter in the flip-flop circuit shown in FIG.

5 is a circuit diagram showing a circuit configuration of a second inverter in the flip-flop circuit shown in FIG.

FIG. 6 is a plan view showing a layout of a flip-flop circuit formed on a P-type silicon substrate.

FIG. 7 is a plan view showing a layout of another flip-flop circuit formed on a P-type silicon substrate.

FIG. 8 is a circuit diagram showing a circuit configuration of a well driver.

9 is a diagram showing a bias state of a MOS transistor formed in each well region in the flip-flop circuit shown in FIG.

FIG. 10 is a circuit diagram showing another circuit configuration of the well driver.

FIG. 11 is a circuit diagram showing still another circuit configuration of the well driver.

FIG. 12 is a cross-sectional view showing a device structure of an N-channel DT-MOS transistor.

FIG. 13 is a circuit diagram showing a configuration of a prior art CMOS inverter.

14 is a cross-sectional view showing the device structure of the CMOS inverter shown in FIG.

FIG. 15 C when formed on a P-type silicon substrate
It is sectional drawing which shows the device structure of a MOS inverter.

[Explanation of symbols]

10 NOR circuits 11,21,301,651,6
52,671,672,691,692,751,75
2,771,772,791,792,5111,51
22, 5131, 5141, 5211, 5222 P-channel MOS transistors, 12-14, 202, 30
2,653,654,673,674,693,69
4,753,754,773,774,793,79
4,5112, 5121, 5132, 5142, 521
2,5221 N-channel MOS transistor, 15
Clock input node, 16-18, 53, 203, 30
3,656 input nodes, 19, 61, 204, 30
4,657,658,677,678,697,69
8,757,758,777,778,797,798
Output node, 20, 205, 305, 659, 67
9,699,759,779,799,5133,51
43 power supply nodes 21, 206, 306, 660, 6
80,689,760,780,789,5134,5
144 ground node, 22,310 P-type silicon substrate, 23,311 N well region, 24,25,43,
308, 722, 724, 811, 812, 2011,
2012, 3011 and 3012 P + diffusion region, 27,
30, 31, 35, 39, 307, 721, 723, 8
13, 814, 1021, 1022, 2021, 202
2, 3021, 3022 N + diffusion region, 26, 32,
36, 40, 3013, 3023 channel formation region,
28, 33, 37, 41, 103, 2014, 202
4,3014,3024 gate oxide film, 29,34,
38, 42, 104, 821-832, 2015, 20
25, 3015, 3025 Gate electrode, 50 Flip-flop circuit, 51 Master latch circuit, 52 Slave latch circuit, 54-60, 661-664, 68
1,682,687,688,731-734,761
~ 764, 781, 782, 787, 788, 841,
842 nodes, 62, 63, 513, 514, 52
3,524,655,665,666,675,69
5,755,775,795 Inverter, 65,6
7,69 well driver, 65A, 65B, 67A,
67B, 69A, 69B driver circuit, 100 N-channel DT-MOS transistor, 101, 214 S
iO buried oxide layer, 102 P-type silicon layer, 200 C
MOS inverter, 211-213 SiO insulating layer, 3
00 CMOS inverter, 511, 512, 521
522 transfer gates, 701, 703, 711
712 N well region, 702, 704, 713 P well region, 801 to 808 contact hole, 102
3,2023 P-type body region, 2013 N-type body region.

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5F048 AA01 AA07 AA09 AB03 AB04                       AB10 AC03 BA01 BA16 BB05                       BB15 BD01 BE03 BE09

Claims (8)

[Claims] 1. A semiconductor integrated circuit including a MOS transistor capable of changing a threshold voltage by changing a well voltage applied to a well, wherein the well voltage is controlled according to an operation of the MOS transistor. A semiconductor integrated circuit in which the MOS transistors of the same conductivity type are formed on the same well. 2. The semiconductor integrated circuit according to claim 1, wherein the well voltage is controlled so that the threshold voltage of the MOS transistor becomes small when the MOS transistor is driven. 3. The semiconductor integrated circuit according to claim 1, wherein a gate electrode of the MOS transistor is connected to a well in which the MOS transistor is formed. 4. The well includes a first well region of a first conductivity type and a second well region of a second conductivity type, and a well voltage of the first well region and the second well region. 3. The semiconductor integrated circuit according to claim 1 or 2, wherein the well voltages of the well regions are controlled to different voltages. 5. The well includes a first well region of a first conductivity type and a second well region of a second conductivity type, and a well of a MOS transistor formed in the first well region. Gate electrode and M formed in the second well region
The semiconductor integrated circuit according to claim 3, wherein a control signal different from the gate electrode of the OS transistor is input. 6. The well further includes a third well region of a first conductivity type and a fourth well region of a second conductivity type, and a well voltage of the first and fourth well regions. Is the first
Is controlled based on the control signal of the first and second well regions,
A second conductivity type MOS transistor is formed on the first well region, the second conductivity type MOS transistor having a gate electrode receiving the first control signal is formed in the first well region. A first conductivity type MOS transistor having a gate electrode receiving the second control signal is formed in the second well region, and the second control signal is applied to the gate electrode in the third well region. A second conductivity type MOS transistor for receiving is formed, and a first conductivity type MOS transistor for receiving the first control signal at its gate electrode is formed in the fourth well region. The semiconductor integrated circuit according to claim 5. 7. The semiconductor integrated circuit according to claim 6, further comprising a well drive circuit that controls the well voltage to a predetermined voltage based on the first control signal. 8. The well driving circuit controls a well voltage of the first well region to a power supply voltage when the first control signal has a first logic level,
The well voltage of the third well region is controlled to a voltage lower than the power supply voltage, the well voltage of the second well region is controlled to a ground voltage, and the well voltage of the fourth well region is controlled to the ground voltage. A voltage higher than the power supply voltage, the well voltage of the first well region is controlled to a voltage lower than the power supply voltage, and the third well is controlled to a voltage lower than the power supply voltage. Controlling the well voltage of the region to the power supply voltage, controlling the well voltage of the second well region to a voltage higher than the ground voltage, and controlling the well voltage of the fourth well region to the ground voltage. The semiconductor integrated circuit according to claim 7.