JP2003271097A - Display panel driving circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce output current variance with a tendency in an IC chip as to a display panel driving circuit which includes a plurality of DAC parts and a single bias part supplying a bias signal to those DAC parts and drives a display panel by supplying a plurality of output currents led out of the plurality of DAC parts to pixels. <P>SOLUTION: Switch groups SW1 to SW4 are controlled to turn on in order and correspondence relations with the plurality of output currents led out of the plurality of DAC parts d1 to d20 are switched on a time-division basis. The switch groups SW1 to SW4 include switches S11 to S44 provided corresponding to the DAC parts d1 to d20 and those switches are switched in order. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display panel driving circuit, and more particularly to a circuit for driving a display panel in which light emitting elements are arranged in a matrix.

[0002]

2. Description of the Related Art A display panel is a device in which light emitting elements such as electroluminescence elements (EL elements) are arranged in a matrix and an image is displayed on the panel screen by passing a current through the elements. The light emitting element used for the display panel is represented by an equivalent circuit as shown in FIG. 7, and emits light with an intensity proportional to the current flowing through the diode section.

A display panel driver is a circuit for supplying a current to the light emitting elements arranged in a matrix, and a driver on the column side (column) causes a current to flow to the + pole (anode terminal) of the light emitting element. The side (low) driver grounds the negative electrode (cathode terminal) of the light emitting element and draws current. When the image data is input to the light emission control circuit, information on the columns and rows of the light emitting elements that emit light is transmitted to the drive circuit. A schematic configuration of a conventional display device is shown in FIG. The display device shown in the figure includes a display panel 10 and the display panel 10.
It is configured to include drive circuits 20 and 30 for driving the light emitting device and a light emission control circuit 1. Each circuit block in the display device will be described with reference to FIG.

Referring to FIG. 1, a display panel 1
0 is a cathode line for carrying the 1st display line to the nth display line (a line connected to the cathode terminal of the diode of the light emitting element)
B ₁ and .about.B _n, these and cathode line B ₁ (line leading to the anode terminal of the light-emitting element diode) .about.B _n arranged to intersect the a m number of anode lines A ₁ to A _m are formed. These cathode lines B ₁ .about.B _n and anode lines A _1-emitting element at the intersection between ~A _m E ₁₁ ~E _nm are formed, their respective light-emitting elements is responsible for one pixel of the display panel 10.

The emission control circuit 1 is shown in FIG.
Image data of one screen (n rows, m columns) input
The light emitting element E₁₁~ E_nmPixel data corresponding to each
Group D ₁₁~ D_nmTo the anode line
The live circuit 20 is sequentially supplied. Where, for example,
Pixel data D₁₁~ D_1mIs the display panel 10
Light-emitting element E belonging to one display line₁₁~ E_1mEach of
M data bit rows that specify whether or not to emit light
Light emission at logic level "1", no light emission at logic level "0"
Becomes Similarly, pixel data D_{twenty one}~ D_2mIs the second display line
Light-emitting element E belonging to_{twenty one}~ E_2m, Pixel data D₃₁~ D_3m
Is a light emitting element E belonging to the third display line₃₁~ E_3m, Pixel
Data D_n1~ D_nmIs a light emitting element E belonging to the nth display line_n1
~ E_nm, M to specify whether to emit each of
It is a data bit line.

Further, the light emission control circuit 1 synchronizes with the supply timing of the pixel data for each row, and the first display line to
A cathode line selection control signal for sequentially scanning the nth display line is supplied to the cathode line drive circuit 30. The anode line drive circuit 20 first extracts a data bit designating light emission from m data bits in the pixel data group sent from the light emission control circuit 1. Then, the anode wire belonging to the column corresponding to each of the extracted data bits is set to the anode wire A.
₁ selected from the to A _m, it connects the constant current source to an anode line selected to supply a predetermined pixel drive current.

The cathode line drive circuit sets the display line selected by the cathode line selection control signal of the light emission control circuit among the cathode lines B _{1 to} B _n to the ground potential and is connected to the anode line of the element to emit light. Apply current from a constant current source. At this time, the diode of the light emitting element is connected in the forward direction. The non-selected cathode lines are then connected to the high potential. At this time, the diode of the light emitting element is reversely connected. A light emission drive current flows between the column connected to the constant current source by the anode line drive circuit 20 and the display line set to the ground potential by the cathode line drive circuit 30,
The light emitting element intersecting this column and the display line emits light with an intensity proportional to the amount of the light emission drive current. On the other hand, since no current flows between the display line connected to the high potential by the cathode ray drive circuit 30 and the column connected to the constant current source, the light emitting element intersecting this column and the display line does not emit light. It remains.

The above operation is performed by the pixel data groups D _{11 to} D _1m ,
When performed for each of D _{21 to} D _2m , ..., D _{n1 to} D _nm , a light emission pattern for one field, that is, an image according to the input image data is sent on the screen of the display panel.

[0009]

By the way, the constant current source of the anode line drive circuit is usually a current DAC (digit).
al analog converter) circuit is used. That is, a multi-channel current DAC circuit corresponding to the number of anode lines is required. The configuration of each current DAC circuit in this case is shown in FIG. The current DAC circuit shown in the figure can be divided into a BIAS section B and a DAC section D. The transistor operating as the BIAS unit B is a reference current source I for the current mirror.
_It is directly connected to _ref . On the other hand, the transistors other than the transistor operating as the BIAS unit B operate as a DAC circuit for generating an output current I _out which is a drive signal to be given to the pixel. With this configuration, the data signal (D0 to Dn) to the DAC unit D
By changing the current mirror ratio, it is possible to generate the output current I _out which becomes analog data.

The structure of the multi-channel current DAC circuit is as follows:
Two types are conceivable: a type having a plurality of BIAS sections and a plurality of DAC sections, and a type having one BIAS section and a plurality of DAC sections. The circuit configuration shown in FIG. 11 is a type having a plurality of BIAS sections and a plurality of DAC sections. That is, a bias signal is applied from one BIAS section to one corresponding DAC section. In this case, B
Since the IAS portion and the DAC portion are close to each other, there is an advantage that the tendency of V _th in the IC chip and the voltage drop due to long wiring are not affected.

However, since the current mirror circuit is present in each channel, a systematic current value shift occurs due to the drain voltage shift of the transistor. This occurs because the drain current becomes I _DS = K (V _GS −V _th ) ² · (1 + λV _DS ) when the drain voltage is different even when the transistor is saturated, and therefore it is slightly shifted due to the effect of λ. . Further, random current value variation ΔI determined by the transistor size and V _on occurs. Therefore, there is a demerit that the output current I _{out of} each channel varies. The variation in this case is the current variation between adjacent channels.

On the other hand, the circuit configuration shown in FIG.
One BIAS unit is provided and only a plurality of DAC units are provided. That is, a bias signal is applied from one BIAS section to a plurality of DAC sections. In this case, since the current mirror circuit is common to all channels, it is possible to suppress a systematic current value deviation due to a transistor drain voltage deviation and a random current value variation ΔI determined by the transistor size and Von. This is because the number of mirrors is reduced. Therefore, there is an advantage that variation in the output current I _out of each channel can be suppressed.

However, the BIAS section and the D
Since there is a difference in distance from the AC portion, there is a demerit that it is affected by the tendency of V _th in the IC chip and voltage drop due to long wiring. The variation in this case is I
This is a variation in the output current having a tendency in the C chip. As described above, there are merits and demerits in each of the circuit configurations of FIG. 11 and FIG. In particular, as shown in FIG. 12, BIAS with less variation between adjacent channels
When a circuit configuration in which there is one section and only a plurality of DAC sections is adopted, output current variations tend to occur in the IC chip, and it has been desired to reduce this variation.

An object of the present invention is to provide a display panel drive circuit capable of reducing the output current variation which tends to occur in the IC chip.

[0015]

A display panel drive circuit according to a first aspect of the present invention includes a plurality of digital-analog conversion units and a single bias unit that applies a bias signal to the digital-analog conversion units. A display panel drive circuit for driving a display panel by applying a plurality of output currents derived from a plurality of digital-analog conversion units to a pixel, wherein the plurality of digital-analog conversion units and the plurality of output currents derived from the plurality of digital-analog conversion units are provided. It is characterized in that it includes a switching means for switching the correspondence to time division. By sequentially switching the correspondence relationship between the plurality of DAC units and the plurality of output currents in a time-division manner, it is possible to reduce the output current variation that tends to occur in the IC chip.

A display panel drive circuit according to a second aspect of the present invention is the display panel drive circuit according to the first aspect, wherein the switching means includes a plurality of switches provided respectively corresponding to the plurality of digital-to-analog converters. It is characterized in that the correspondence relationship between the plurality of digital-analog converters and the plurality of output currents derived is switched in a time division manner by sequentially switching the switches. By providing a plurality of switches corresponding to each of the plurality of digital-analog conversion units and sequentially controlling the switching of the switches, it is possible to reduce the above variation with a simple circuit configuration.

In short, according to the present invention, in the display panel driving circuit having a single BIAS section and a plurality of DAC sections, the output current of the DAC section in each channel is sequentially switched between the channels. That is, by sequentially switching the correspondence relationship between the plurality of DAC units and the plurality of output currents in a time-division manner, it is possible to reduce the output current variation that tends to occur in the IC chip, and also to reduce the randomly generated current variation. You can

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. In each of the drawings referred to in the following description, the same parts as those in the other drawings are designated by the same reference numerals. FIG. 1 is a block diagram showing a configuration of a main part of an embodiment of a display panel drive circuit according to the present invention. The figure shows a display panel drive circuit having a single BIAS section and a plurality of DAC sections. And the D on each channel
The problem of the conventional circuit is solved by sequentially switching the output current of the AC section between the channels.

FIG. 1 shows the circuit configuration when a plurality of DAC sections are divided into two blocks. In the case shown in the figure, the 20 DAC units d1 to d20 are divided into two blocks. That is,
Block B1 from DAC unit d1 to DAC unit d10
And a block B2 from the DAC section d11 to the DAC section d20. Then, the outputs of the ten DAC units d1 to d10 included in the block B1 are derived as the output currents I _out 1 to I _out 10. In addition, the 10 DACs included in the block B2
The outputs of the parts d11 to d20 are output currents I _out 11 to I _out
It is derived as 20.

However, in this circuit, the DAC section d1
To the output side of the DAC section d20 from the switch group SW1 to SW
4 are provided, and these are sequentially controlled to be turned on. However, the two switch groups should not be turned on at the same time. By controlling in this way, the switch group S
Correspondence between the DAC section and the output current that is derived is averaged while being switched and controlled by W1 to SW4, and is derived as output currents I _out 1 to I _out 20.

In this example, as clearly shown in FIG.
4 DAC sections d1, d10, d11 and d20, 4
Output currents I _out 1, I _out 10, I _out 11 and I
The correspondence with the _out 20 is switched and controlled by each switch included in the switch groups SW1 to SW4. The switch group SW1 includes switches S11, S12, S13.
And S14 are included. The switch group SW2 includes switches S21, S22, S23 and S24. The switch group SW3 includes switches S31, S32,
S33 and S34 are included. The switch group SW4 includes switches S41, S42, S43 and S44.

Then, in this example, as indicated by arrows Y1 and Y2 and arrows Y3 and Y4 in the figure, the correspondence is controlled so as to be sequentially switched in both directions. By switching the correspondences in this way, time-division control (averaging over time) can be realized, so that it is possible to reduce output current variations that tend to occur in the IC chip. Similarly, for the DAC section not shown in the figure, four D
The correspondence between the AC section and the four output currents is the switch group S.
Each switch S _ij (i = 1 to 1) included in W1 to SW4
4, j = 1 to 4). That is, four DAC units d2, d9, d12 and d19,
Four output currents I _out 2, I _out 9, I _out 12 and I
The correspondence with _out 19 is controlled to be switched. Also, four DAC sections d3, d8, d13 and d18 and four output currents I _out 3, I _out 8, I _out 13 and I _out 18 are provided.
The correspondence relationship with is switched and controlled. In addition, 4 DAs
The correspondence relationship between the C sections d4, d7, d14 and d17 and the four output currents I _out 4, I _out 7, I _out 14 and I _out 17 is switched and controlled. And four DAC parts d
5, d6, d15 and d16 and four output currents I _out
The correspondence with 5, I _out 6, I _out 15 and I _out 16 is switched and controlled.

FIG. 2 shows an example of the switching timing of the correspondence relationship between the output of each DAC section and the output current. In the figure, the states of the respective switch groups SW1 to SW4 and the output current I
DAC sections d1 to d20 having the contents of _out 1 to I _out 20
And the output of is shown. CLK in the figure is a clock. Referring to the figure, four DAC units d1,
The outputs of d10, d11 and d20 are time-division averaged,
It is synthesized as the output current I _out 1. In addition, DAC
The outputs of the parts d2, d9, d12 and d19 are time-division averaged and output as the output current I _out 2, the DAC parts d3, d8,
The outputs of d13 and d18 are time-division averaged and combined as an output current I _out 3. Similarly, the other output currents are derived by time-averaging the outputs of the four DAC units.

Here, the output currents I _out 1, I _out 10,
Both I _out 11 and I _out 20 are DAC parts d1 and d1.
The outputs of 0, d11, and d20 are combined. However, in the period in which the switches SW1 is turned ON, the output current I _{ou t} 1 is the output of the DAC portion d1, I _out 10 is the output of the DAC portion d10, I _out 11 is the output of the DAC portion d11, I _out 20 is the output of the DAC unit d20. Further, the output current I _out 1 is D while the switch group SW2 is in the ON state.
The output of the AC section d10, I _out 10 is the output of the DAC section d1, I _out 11 is the output of the DAC section d20, and I _out 20 is the output of the DAC section d11. Similarly, while the switch group SW3 is in the ON state, the output current I _out 1 is the output of the DAC unit d11, I _out 10 is the output of the DAC unit d20, and I _out 11 is the output of the DAC unit d1. _out 20 is the output of the DAC unit d10,
While the switch group SW4 is in the ON state, the output current I _out 1 is the output of the DAC unit d20, I _out
10 is the output of the DAC unit d11, and I _out 11 is the DAC unit d11.
The output of 10 and I _out 20 are the outputs of the DAC unit d1. After that, the switching control is similarly repeated.

The other output currents are also those in which the outputs of the respective DAC units are combined in a time division manner by the switching control of the switch group. In this way, by providing a plurality of switches corresponding to each of the plurality of DAC units and sequentially controlling the switching thereof, it is possible to reduce the above variation with a simple circuit configuration. The control signal for switching the correspondence between the DAC section and the output current at the timing shown in FIG. 2 is generated by using a counter circuit or the like. For example, an N-stage ring counter (N = 4 in the above example) is used. The N-stage ring counter can be configured, for example, by connecting the output of the final stage of the shift register connected in series with the N stage to the input of the first stage.

When a 4-stage ring counter is used, FIG.
The waveforms of the control signals r1 to r4 output from the ring counter shown in (a) change so that the high-level period is sequentially shifted as shown in (b) of the figure. Control signals r1 to r4 whose waveforms change in this way
Is supplied to the switches included in each of the switch groups SW1 to SW4. The supply destinations of these control signals r1 to r4 are shown in FIG. As shown in the figure,
The control signal r1 is the switch s11, s12, s in FIG.
13 and s14. Further, the control signal r2 is supplied to the switches s21, s22, s23, s24 in the figure. Similarly, the control signal r3 is output to the switches s31 and s3.
2, s33, s34, and the control signal r4 is supplied to the switches s41, s42, s43, s44. As described above, by supplying the control signals r1 to r4 to the switches included in the switch groups SW1 to SW4, the operation as shown in FIG. 2 described above can be realized.

The switches included in the switch groups SW1 to SW4 are constructed, for example, as shown in FIG. 3 (d). In the figure, the switch s is NM
OS (N-channel Metal oxide)
(Semiconductor) transistor NT and P
MOS (P-channel Metal oxide)
This is a configuration in which the source terminals and drain terminals of the semiconductor transistors PT are connected to each other. The control signal r is directly applied to the gate terminal of the NMOS transistor NT, and the control signal r is applied to the gate terminal of the PMOS transistor PT by the inverter IN.
It is applied after being inverted by V.

Here, in the conventional circuit, that is, in the circuit in which the switching control of the correspondence relationship is not performed as described above, the output current variation having a tendency in the IC chip has the characteristic shown in FIG. think about. In the figure,
The output current of the DAC section for the channel of the column line is shown. Referring to the figure, the output current I
_out 1, ... Output current I _out 10, Output current I _out 11,
... for the output current I _out 20, toward the output current I _out 20 from the output current I _out 1, the position of the black dots ● are moved upward. Therefore, as shown by the solid line J in the figure, DA is applied to the channel of the column line.
The value of the output current of the C section tends to gradually increase.

With respect to such characteristics, when the circuit configuration of the present invention is adopted, it becomes as follows. For example, focusing on the output current I _out 1, the DAC unit d1, the DAC unit d10, the DAC unit d11, and the DAC unit d20 are used for the output current I _out 1. That is, these DACs
Output current I
_out 1 That is, the output current I _out 1 is (output of DAC section d1 + output of DAC section d10 + DAC
A current corresponding to the output of the part d11 + the output of the DAC part d20) / 4 is derived. As a result of the averaging in this way, each output current shown by the solid line J in FIG. 5 shows the output current variation having a tendency in the IC chip as shown by the broken line H in FIG. It can be reduced. Note that other output currents are similarly averaged, and
It is possible to reduce the output current variation that tends to occur in the chip.

Further, in this circuit, it is also possible to reduce random current variations that the DAC section has. Hereinafter, this point will be described. Let ΔI be the random variation of the current that the circuit of the DAC section has. This △
I is the same as the current variation in the conventional DAC section. Then, the current variation of each DAC connected to the switch group SW1 is ΔI ₁ , and each DAC connected to the switch group SW2 is
Current variation of △ I ₂ parts, the current variations of each DAC unit connected to the switch group SW3 △ I _3, the switch group SW
It is assumed that the current variation of each DAC circuit of ₄ is ΔI ₄ . At this time, the average of the variations is as follows. That is, the average of the variations = 1/4 x √ (ΔI ₁ ² + ΔI ₂ ² + Δ
I ₃ ² + ΔI ₄ ² ). Here, if ΔI ₁ , ΔI ₂ , ΔI ₃ , and ΔI ₄ = ΔI, the average of the variations becomes 1 / √4 × ΔI. Therefore, if the configuration of this circuit is adopted, the amount of current variation is smaller than the current variation ΔI in the conventional DAC section.

FIG. 6 shows a timing chart in the case of considering the random current variation in the DAC section. In the same figure, as a representative example, the relationship between the output current I _out 1 and each switch group is shown. As shown in the figure, while the switch group SW1 is in the ON state, the output current I _out 1 has a current value obtained by adding the current variation ΔI ₁ to the output of the DAC unit d1. Further, while the switch group SW2 is in the ON state, the output current I _out 1 has a current value obtained by adding the current variation ΔI ₁₀ to the output of the DAC unit d10. Similarly, the output current I _out 1 with respect to the switch group that is turned on is the same as the current value _obtained by adding the current variation ΔI _k to the output of the DAC unit dk (k = 1, 10, 11, 20, hereinafter the same). Become. Similarly, other output currents have current values obtained by adding current variations to the output of the DAC unit. Even if random current variations occur in this way, the amount of current variations can be reduced by averaging in time division as described above.

Although the plurality of DAC sections are divided into two blocks in the configuration example shown in FIG. 1 described above, the number of blocks is not limited to two. Further, the number of switch groups is required to be twice the number of blocks in the DAC section. Further, the number of bits of the DAC unit is not limited to the case described above. The number of channels of the DAC unit is not limited to the case described above. The circuit configuration of the DAC section is P
A MOS transistor may be used, or an NMOS
A transistor may be used. Further, although the case where the pixel element forming the display panel is the EL element has been described above, it is obvious that the present invention can be applied to the case where the pixel element constituting the display panel is any other element.

[0033]

As described above, according to the present invention, a plurality of D
By sequentially switching the correspondence relationship between the AC unit and the plurality of output currents in a time-division manner, it is possible to reduce the output current variation that tends to occur in the IC chip and also reduce the randomly generated current variation. There is.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a display panel drive circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of each unit of the display panel drive circuit of FIG.

3A is a diagram showing an example of a counter, FIG. 3B is a diagram showing an output waveform of the counter, FIG. 3C is a diagram showing a correspondence relationship between an output of the counter and a switch to which it is supplied, d)
FIG. 3 is a diagram showing a configuration example of each switch.

FIG. 4 is a diagram showing an example of characteristics of output current variation having a tendency in an IC chip.

5 is a diagram showing how the characteristics of FIG. 4 are improved by the circuit of FIG.

FIG. 6 is a timing chart in the case of considering random current variations in the DAC section.

FIG. 7 is a diagram showing an equivalent circuit of a light emitting element used in a display panel.

FIG. 8 is a schematic configuration diagram of a general display panel device.

9 is a timing chart showing an operation of the display device of FIG.

FIG. 10 is a diagram illustrating a configuration example of a DAC unit.

FIG. 11 is a diagram showing a configuration of a display panel drive circuit having a plurality of BIAS units and a plurality of DAC units.

FIG. 12 is a diagram showing a configuration of a display panel driving circuit having one BIAS unit and a plurality of DAC units.

[Explanation of symbols]

1 Light emission control circuit 10 Display panel 20 Anode line drive circuit 30 Cathode line drive circuit d1 to d20 DAC section I _out 1 to I _out 20 Output current r1 to r4 Control signal s11 to s44 Switch SW1 to SW4 switch group

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 G09G 3/20 623V 641 641D 642 642A

Claims (2)

[Claims] 1. A plurality of digital-to-analog converters and a single bias unit for applying a bias signal to the digital-to-analog converters, and a plurality of output currents derived from the plurality of digital-to-analog converters to pixels. A display panel driving circuit for driving a display panel by giving a switching means for time-divisionally switching a correspondence relationship between the plurality of digital-analog converters and the plurality of output currents derived. Panel drive circuit. 2. The switching means includes a plurality of switches respectively provided corresponding to the plurality of digital-analog converters, and the plurality of switches are sequentially switched to switch between the plurality of digital-analog converters. 2. The display panel drive circuit according to claim 1, wherein the correspondence relationship with the derived plurality of output currents is switched in a time division manner.