JP2003264438A - High frequency power amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To advantageously suppress lowering of power efficiency and output power in a high frequency power amplifier. <P>SOLUTION: The resistance loss is reduced by constituting a transmission line 28 provided to an amplifier circuit of two electrode layers 23 and 24 which are placed sandwiching a dielectric ceramic layer 22. Furthermore, occurrence of potential difference between the two electrode layers 23 and 24 is avoided by mutually connecting the two electrode layers 23 and 24 via a plurality of via hole conductors 29 provided at intervals equal to or less than 1/8 the wavelength of a high frequency signal passing through the transmission line 28. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high frequency power amplifier, and more particularly to a structure of a transmission line in a high frequency power amplifier formed by using a multilayer ceramic substrate such as a high frequency power amplifier module for mobile communication. It is a thing.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram of a high frequency power amplifier 1 which is of interest to the present invention. The high frequency power amplifier 1 shown in FIG. 3 is used as a high frequency power amplifier module in the field of mobile communication, and constitutes a three-stage field effect transistor (FET) power amplifier.

Referring to FIG. 3, the high frequency power amplifier 1 is
To form an amplifier circuit, three-stage FETs 2, 3 and 4
, Input matching circuit 5, and two interstage matching circuits 6 and 7
And gate bias circuits 8, 9 and 10 of each of FETs 2, 3 and 4, and drain bias supply choke circuits 11, 12 and 13, and an output matching circuit 14.

In such high frequency power amplifier 1, the largest current flows in the drain bias supply choke circuit 13. For example, GSM (Global
System for Mobile Communi
The operating current of about 2 A flows in the power amplifier for the (stations). Therefore, even if the DC resistance of each of the drain bias supply choke circuits 13 is 0.1Ω, the voltage drop thereof is 0.2V, which is about 6.7% with respect to the power supply voltage of about 3V, for example. This results in loss, which leads to a reduction in output power as well as a reduction in power added efficiency.

The optimum load impedance of the FET used in a high output power amplifier such as GSM is several Ω or less. To improve the power added efficiency and the output power, the resistance component of the transmission line in the output matching circuit 14 is used. It is necessary to make it as close to zero as possible. Therefore, the DC resistance generated in the transmission line in the output matching circuit 14 causes not only the deviation from the optimum load impedance but also resistance loss, which directly causes a reduction in the power addition efficiency and the output power.

On the other hand, when the power amplifier module constituting the high frequency power amplifier 1 as shown in FIG. 3 is formed of a multilayer ceramic substrate, the transmission lines provided in the drain bias supply choke circuits 11 to 13 and the output matching circuit 14. Will be given by the electrode layer provided on the multilayer ceramic substrate, but the thickness of the electrode layer provided on the multilayer ceramic substrate is usually about 3 to 15 μm. In a general resin printed circuit board, the thickness of the electrode layer is 18
Although it is about 40 μm, the thickness of the electrode layer in the multilayer ceramic substrate is less than half of that. Therefore, in the electrode layer in the multilayer ceramic substrate,
The resistance component becomes twice or more as compared with the case of a general resin printed circuit board.

In order to solve this problem, Japanese Patent Laid-Open No. 2001-2001
In Japanese Patent No. 320251, it is proposed to provide a transmission line of a bias circuit for supplying a current to a semiconductor element with two or more electrode layers facing each other in the thickness direction of the dielectric ceramic layer. According to this technique, the resistance component of each electrode layer is connected in parallel, so that the resistance loss of the entire transmission line can be reduced.

[0008]

In a bias circuit such as the drain bias supply choke circuits 11 to 13 shown in FIG. 3, only direct current flows originally. Therefore, it is necessary to prevent an AC signal from flowing in the bias circuit. In other words, even the bias circuit needs to be designed in consideration of the AC signal.

However, the above-mentioned Japanese Patent Laid-Open No. 2001-3
According to the technique described in Japanese Patent No. 20251, a high-frequency AC signal can flow through at least two paths, and thus a potential difference may occur between the two paths. In this way, when a potential difference occurs, current (both direct current and alternating current) flows only in one path, which causes a problem that it becomes meaningless to provide a transmission line with a plurality of electrode layers.

Therefore, an object of the present invention is to provide a high frequency power amplifier which can solve the above problems.

[0011]

According to the present invention, there is provided a multilayer ceramic substrate having a structure in which a plurality of dielectric ceramic layers and a plurality of electrode layers are laminated, and a surface of the multilayer ceramic substrate so as to form an amplifier circuit or A semiconductor device and a passive device mounted inside, and a transmission line provided in an amplifier circuit is provided by at least a part of an electrode layer, which is directed to a high frequency power amplifier,
In order to solve the above-mentioned technical problem, the following features are provided.

That is, the electrode layer for providing the transmission line included in the amplifier circuit is composed of at least two electrode layers positioned with the dielectric ceramic layer sandwiched therebetween, and these at least two electrode layers are provided with a predetermined interval. It is characterized in that they are connected to each other through a plurality of via-hole conductors.

Preferably, the above-mentioned plurality of via-hole conductors are provided at intervals of ⅛ or less of the wavelength of the high frequency signal passing through the transmission line.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment in which the present invention is applied to the drain bias supply choke circuit 13 and the output matching circuit 14 in the high frequency power amplifier 1 shown in FIG. 3 will be described below.

FIG. 1 is a plan view schematically showing a part of the high frequency power amplifier 1 in which the drain bias supply choke circuit 13 and the output matching circuit 14 shown in FIG. 3 are formed, and FIG. It is sectional drawing which shows the part provided with the circuit element shown in FIG. 1 of the power amplifier 1 diagrammatically.

A monolithic microwave integrated circuit (MMIC chip 17 including the final stage FET 4 shown in FIG.
It is shown in FIGS. 1 and 2. Further, the capacitor chips 18, 19, 20 and 21 forming the capacitors C1, C2, C3 and C4 shown in FIG.
2 and, of these, the capacitor chip 21 forming the capacitor C4 is shown in FIG.

As shown in FIG. 2, the high frequency power amplifier 1 is a multi-layer ceramic having a structure in which a plurality of dielectric ceramic layers 22 and a plurality of electrode layers 23, 24, 25, 26, ... Are laminated. A substrate 27 is provided. M mentioned above
MIC chip 17 and capacitor chips 18-21
Are mounted on the surface of the multilayer ceramic substrate 27.
At least a part of the semiconductor element such as the MMIC chip 17 and the passive element such as the capacitor chips 18 to 21 may be mounted inside the multilayer ceramic substrate 27.

1 and 2 show a transmission line 28 provided in the drain bias supply choke circuit 13 and the output matching circuit 14. This transmission line 28 is
As best shown in FIG. 2, the dielectric ceramic layer 2
It is composed of two electrode layers 23 and 24 which are located with the electrode 2 in between. Also, these two electrode layers 23 and 2
4 are connected to each other via a plurality of via-hole conductors 29 provided at a predetermined interval.

These via-hole conductors 29 are used for the transmission line 2
It is preferable that they are provided at intervals of ⅛ or less of the wavelength of the high frequency signal passing through 8. The wavelength of the high frequency signal is mainly determined by the dielectric constant of the dielectric ceramic layer 22. In addition, the distance between the via-hole conductors 29 is actually ⅛ or less of the wavelength of the operating frequency,
Not shorter, but shorter.

By providing the via-hole conductor 29 so as to connect the electrode layers 23 and 24 in this manner, the potential difference between the electrode layers 23 and 24 can be eliminated, and the transmission line 28 can be connected to the two electrode layers. The significance given by 23 and 24 can be made more perfect.

Although not shown, the same configuration may be applied to other drain bias supply choke circuits 11 and 12 and the like.

Since it is not directly related to the gist of the present invention,
Although detailed description is omitted, in FIGS.
A bonding wire 30 that electrically connects the C chip 17 and the electrode layer 23 and a conductor pad 31 that is electrically connected to one terminal of the capacitor chip 21 are shown. Further, in FIG. 1, the capacitor chips 18 and 19 are shown. And 20
Pad 3 electrically connected to one terminal of each
Via hole conductor 3 for grounding 2, 33 and 34 and conductor pads 32, 33 and 34
5, 36 and 37 are shown, and in FIG. 2 via hole conductors 38 for electrically connecting the electrode layers 25 and 26 to each other are shown.

Although the present invention has been described above with reference to specific embodiments, within the scope of the present invention, other
Various modifications are possible.

For example, in the above-described embodiment, the one electrode layer 23 that provides the transmission line 28 is the multilayer ceramic substrate 2
Although the other electrode layer 24 formed on the surface of No. 7 and the other electrode layer 24 is formed inside the multilayer ceramic substrate 27, both of the electrode layers providing the transmission line may be formed inside the multilayer ceramic substrate.

The transmission line 28 has two electrode layers 23.
And 24, but may be provided by more than two electrode layers.

In the above-described embodiment, the transmission line 28 provided by the two electrode layers 23 and 24 is
Although it is applied to both the drain bias supply choke circuit 13 and the output matching circuit 14, it may be applied to only one of them.

The drain bias supply choke circuits 11 to 13 may be meander lines or spiral inductors.

In the above-mentioned embodiment, the three-stage amplifier using the FET has been described as an example. However, as the semiconductor element, that is, the active element, in addition to the FET, HBT, MOSF may be used.
It may be ET or the like, and the number of semiconductor elements such as FET may be 1, 2, or 4 or more.

[0029]

As described above, according to the present invention, although the transmission line provided in the amplifier circuit is provided by the electrode layers of the multilayer ceramic substrate, the electrode layers are located at least with the dielectric ceramic layers interposed therebetween. Since it is composed of two electrode layers, it is possible to reduce the resistance loss of the transmission line, and these at least two electrode layers are connected to each other through a plurality of via-hole conductors provided at a predetermined interval. Therefore, it is possible to prevent a potential difference from being generated between the electrode layers, and thus it is possible to prevent the significance of the transmission line being composed of at least two electrode layers from being diminished.

Therefore, according to the present invention, it is possible to advantageously suppress the reduction of the power added efficiency and the output power in the high frequency power amplifier.

If the via-hole conductors described above are provided at intervals of ⅛ or less of the wavelength of the high-frequency signal passing through the transmission line, the above-mentioned effects can be more reliably exhibited.

[Brief description of drawings]

FIG. 1 is a plan view schematically showing a main part of a high frequency power amplifier 1 according to an embodiment of the present invention.

FIG. 2 is a sectional view schematically showing a portion shown in FIG.

FIG. 3 is a high frequency power amplifier 1 of interest to the present invention.
It is a circuit diagram showing the whole of.

[Explanation of symbols]

1 High Frequency Power Amplifier 2, 3, 4 FET 11, 12, 13 Drain Bias Supply Choke Circuit 14 Output Matching Circuit 17 MMIC Chip 18, 19, 20, 21 Capacitor Chip 22 Dielectric Ceramic Layer 23, 24, 25, 26 Electrode Layer 27 Multilayer ceramic substrate 28 Transmission line 29 Via hole conductor

Continued front page    F term (reference) 5J067 AA01 AA04 AA41 CA36 FA16                       HA09 HA29 HA33 KA12 KA29                       KA66 KA68 KS11 LS11 QA04                       QS04 SA13                 5J092 AA01 AA04 AA41 CA36 FA16                       HA09 HA29 HA33 KA12 KA29                       KA66 KA68 QA04 SA13                 5J500 AA01 AA04 AA41 AC36 AF16                       AH09 AH29 AH33 AK12 AK29                       AK66 AK68 AQ04 AS13

Claims (2)

[Claims] 1. A multilayer ceramic substrate having a structure in which a plurality of dielectric ceramic layers and a plurality of electrode layers are laminated,
A semiconductor element and a passive element mounted on the surface or inside of the multilayer ceramic substrate so as to form an amplifier circuit, and a transmission line included in the amplifier circuit is provided by at least a part of the electrode layer. A high frequency power amplifier, wherein the electrode layer that provides a transmission line included in the amplification circuit,
At least two portions that are located with the dielectric ceramic layer sandwiched therebetween
A high-frequency power amplifier, comprising one electrode layer, wherein the at least two electrode layers are connected to each other via a plurality of via-hole conductors provided at a predetermined interval. 2. The high frequency power amplifier according to claim 1, wherein the plurality of via hole conductors are provided at intervals of ⅛ or less of a wavelength of a high frequency signal passing through the transmission line.