JP2003264249A - Memory device using carbon nanotube and method of manufacturing the same - Google Patents

Abstract

(57) [Problem] CNT having high conductivity and high heat release
And a high-speed, highly-integrated memory element free from malfunctions and a method for manufacturing the same. SOLUTION: A substrate, a source electrode and a drain electrode which are located on the substrate at a predetermined distance from each other and to which a voltage is applied, and a CNT which connects the source electrode and the drain electrode and serves as an electron transfer channel. A memory cell positioned above the CNT and storing the charge flowing from the CNT; and a gate electrode contacting the upper part of the memory cell and controlling the amount of charge flowing from the CNT into the memory cell. Prepare.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device and a method for manufacturing the same, and more particularly to a carbon nanotube (Carbon NanoTube; hereinafter abbreviated as CNT).
And a manufacturing method thereof.

[0002]

2. Description of the Related Art A memory device using a semiconductor has, as a basic component, a capacitor which plays a role of storing stored charges, and a current which is used when data is read from or written in the capacitor. A transistor serving as a switch for securing a passage.

In order to pass a large amount of current through a transistor, the transistor itself must have a high transconductance (gm) characteristic.
MOSFET with high transconductance characteristics
(Metal Oxide Semiconductor Field-Effect Transisto
r) tends to be used as a switching element of a semiconductor memory element.

The MOSFET is a transistor having a gate electrode made of polycrystalline silicon and source and drain electrodes made of doped crystalline silicon as basic constituent elements.

The transconductance of the MOSFET is inversely proportional to the channel length (L), the thickness of the gate oxide film, etc. under the same voltage condition, and is proportional to the surface mobility, the dielectric constant of the gate oxide film and the channel width (W). To do. Of these variables, the surface mobility and the dielectric constant of the oxide film, etc., are not the control target because they are the predetermined values depending on the material, that is, the directional silicon wafer, the silicon oxide film, etc. In order to have it, the ratio of the width and the length of the channel (W / L ratio
o) must be increased or the oxide film must be thinned.

However, in order to manufacture a highly integrated memory device, the physical size of the MOSFET must be reduced. Therefore, the gate, source and drain electrodes have to be made small, which causes various problems.

For example, if the gate electrode becomes smaller, the cross-sectional area of the gate electrode is reduced, which induces a large electric resistance in the transistor. The miniaturization of the source and drain electrodes causes a decrease in the thickness, that is, the junction depths, resulting in a larger electrical resistance, and the distance between the source and the drain is shortened so that the depletion layers of the source and the drain are mutually separated. Inducing a punch through phenomenon that causes abutment makes it impossible to regulate the current. In addition, the reduction of the size of the memory device as described above reduces the width of the channel, which is a current passage, to 70 nm or less, disturbs the smooth flow of the current, and causes the memory device to malfunction.

That is, it is generally difficult to realize a high-density memory in a memory device based on a MOSFET due to problems such as heat loss, power consumption, fluctuations in electrical characteristics, and charge leakage.

[0009]

SUMMARY OF THE INVENTION The technical problem to be solved by the present invention is to solve the above-mentioned problems, in which there is no increase in resistance due to the miniaturization of the memory device and there is no heat loss or power consumption. The present invention provides a high-speed highly integrated memory device with less variation in electrical characteristics and charge leakage, and a manufacturing method thereof.

[0010]

In order to achieve the above-mentioned technical objects, the present invention provides a substrate, a source electrode and a drain electrode which are located on the substrate with a predetermined space therebetween and to which a voltage is applied. Connecting the source electrode and the drain electrode,
The CNT that serves as an electron transfer channel, the memory cell that is located above the CNT and stores the charge flowing from the CNT, and contacts the upper portion of the memory cell.
A CNT memory device comprising: a gate electrode for adjusting the amount of charge flowing from T to the memory cell.

Preferably, the substrate is a silicon substrate, and a silicon oxide film is laminated on the substrate. The memory cell may include the CNT on the CNT.
A first insulating film formed in contact with the first insulating film, and a charge storage film deposited on the first insulating film to store charges.
A second insulating layer formed on the charge storage layer and in contact with the gate electrode. It is preferable that the first insulating film has a thickness substantially the same as that of the charge storage film, and the second insulating film has a thickness about twice that of the charge storage film. The first and second insulating films are made of a silicon oxide film, and the charge storage film is made of a silicon film or a silicon nitride film. The charge storage layer preferably has a thickness of 15 nm or less. The charge storage film is preferably
The porous film has a plurality of nanodots filled with a charge storage material.

The memory cell is formed under the gate electrode and is in contact with the gate electrode, and a third insulating film is formed under the third insulating film and is in contact with the CNT to store a charge. And a porous film on which a plurality of nanodots filled with a substance are arranged. The third insulating film may have a thickness about twice that of the porous film, or may have substantially the same thickness. The third insulating layer is a silicon oxide layer and the charge storage material is silicon or silicon nitride. The porous film is an aluminum oxide film. The nanodots preferably have a diameter of 15 nm or less.

In addition, in order to achieve the above-mentioned technical object, the present invention is characterized in that after growing CNTs on a substrate, the CNTs are
Forming a source electrode and a drain electrode which are used as charge transfer channels so as to contact the CNT, and a first step on the CNT, the source electrode and the drain electrode.
A second step of forming a memory cell in contact with the CNT by patterning an insulating layer, a charge storage layer, and a second insulating layer, and then patterning using a photolithography process, and forming a memory cell on the second insulating layer. After depositing the metal layer, patterning is performed using a photolithography process to form the CN.
And a third step of forming a gate electrode for adjusting the amount of charges flowing into the charge storage layer from T. A method of manufacturing a CNT memory device is provided.

Alternatively, after growing carbon nanotubes on a substrate, a first step of forming a source electrode and a drain electrode using the carbon nanotubes as charge transfer channels so as to contact the carbon nanotubes; A second step of depositing a first insulating layer on the source and drain electrodes, anodic oxidation, and etching to form a porous layer having a plurality of nanodots formed by oxidizing the first insulating layer; A third step of depositing a charge storage material on the porous film and then etching the nanodots to fill the charge storage material, and a photolithography process after depositing a second insulating film on the porous film. A fourth step of patterning the first insulating film, the porous film and the second insulating film to form a memory cell, and forming a memory cell on the second insulating film. A fifth step of depositing a metal layer, and patterning the metal layer using a photolithography process to form a gate electrode controlling an amount of charges flowing into the porous film from the carbon nanotube. A method of manufacturing a memory device is provided.

In the first step, preferably, an insulating layer is formed on the upper surface of the substrate and CN is formed on the upper surface of the insulating layer.
Grow T. The substrate is silicon and the insulating layer is silicon oxide. In the first stage,
The source electrode and the drain electrode are formed by electron beam lithography. In the second step, it is preferable that the first insulating film and the storage film are deposited to have substantially the same thickness, and the second insulating film is deposited to be about twice as thick as the porous film. The first and second insulating layers are made of silicon oxide. The charge storage layer is made of silicon or silicon nitride.

The charge storage film is preferably formed to a thickness of 15 nm or less. In the first step, it is preferable that the first insulating film is entirely oxidized to form a porous film having a plurality of nanodots.

Since the present invention uses CNT as a charge transfer channel, it does not require a doping step of a semiconductor memory device, and uses CNT having a large electric conductivity and a high thermal conductivity. Or the problem of malfunction is solved. In addition, since the memory device including the memory cell having the charge storage film that stores charges or the porous film on which the nanodots are formed is formed, a highly efficient and highly integrated memory device can be realized.

[0018]

DETAILED DESCRIPTION OF THE INVENTION A memory device and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a perspective view showing a memory device according to an embodiment of the present invention. Referring to FIG. 1, a memory device according to an exemplary embodiment of the present invention includes a substrate 11, an insulating layer 13 stacked on the substrate 11, and a predetermined distance on the insulating layer 13. A source electrode 15 and a drain electrode 17 made of a metal are connected to the source electrode 15 and the drain electrode 17 to form an electron transfer channel CNT21.
Is located so as to come into contact with the CNT21, and the CN
A memory cell 23 for storing electrons flowing from T21;
A gate electrode 19 that contacts the memory cell 23 and controls the movement of the electrons.

In the drawing, the source and drain electrodes 1
Although 5 and 17 are located above the substrate 11, the source / drain electrodes 15 and 17 may be located inside the substrate 11. In this case, the CNT 21 is located inside the substrate 11 and in contact with the surface thereof.

The substrate 11 is generally a silicon substrate, and the insulating layer 13 laminated thereon is generally silicon oxide.

The source and drain electrodes 15 and 17 are T
The gate electrode 19 is made of a metal such as i and Au, and the gate electrode 19 is made of a metal such as polysilicon. In addition, the transistor structure is formed by known semiconductor processes such as photolithography, e-beam lithography, etching, oxidation, and thin film deposition.

The CNT21 has a hexagonal honeycomb shape formed by binding each carbon atom to another carbon atom as an allotrope of carbon, which has a graphite surface formed by binding a plurality of carbon atoms. It has a nano-sized diameter and is rolled into a circle. CNT21 exhibits the characteristics of metal or semiconductor depending on the winding angle and structure of the graphite surface.
Research using these characteristics is being actively pursued in advanced industrial fields, especially in the field of nanotechnology.

CNTs are classified into two types of CNTs which differ from each other according to their electrical properties. That is, regardless of the gate voltage, the metallic CN having a linear current-voltage characteristic relationship.
T and CNT having a semiconductor characteristic that is greatly affected by the gate voltage and has a non-linear current-voltage characteristic.

The CNT 21 used in the memory device according to the embodiment of the present invention is a CNT having semiconductor characteristics, and the voltage applied to the gate electrode 19 controls the flow of electrons moving through the CNT 21, that is, the current.

CNT21 is an electric discharge method, a laser deposition method, a plasma enhanced chemical vapor deposition method (Plasma Enhanced Chemica).
Vapor Deposition (PECVD), a thermochemical vapor deposition method, a vapor phase synthesis method, or the like.

A first memory cell, a second memory cell and a third memory cell used in a memory device according to an embodiment of the present invention are shown in FIGS. 2, 3A and 3B, respectively.

FIG. 2 is a sectional view of a first memory cell used in a memory device according to an embodiment of the present invention. Referring to FIG. 2, the first memory cell 23 used in the memory device according to the exemplary embodiment of the present invention includes first and second insulating layers 20 and 24 and a charge storage layer 22. The charge storage film 22 stores charges, that is, electrons and holes, and the first and second insulating films 2
It is formed between 0 and 24. First and second insulating films 20,
24 is made of silicon oxide (SiO ₂ ), and the charge storage film 22 is made of silicon (Si) or silicon nitride (S).
i ₃ N ₄ ). In particular, Si ₃ N ₄ thin films provide low potential trap sites that can store a large number of charges.

The total thickness of the first memory cells 23 is about 6
It is desirable that the thickness is 0 nm and the thickness of the charge storage film 22 is approximately 15 nm or less. It was confirmed that the silicon film or the silicon nitride film used as the charge storage film 22 has a function of storing electrons with a thickness of 100 nm or less. Here, the first insulating film 20 is the CNT 21 shown in FIG.
It is desirable to make it thin so as to facilitate tunneling of charges injected from the inside.

It is desirable that the second insulating film 24 is formed thick enough to suppress charge injection from the gate electrode 19 and hold the charges stored in the charge storage film 22 for a long period of time. For example, the first insulating film 20 may be formed of a 7 nm oxide thin film, the charge storage film 22 may be formed of a 7 nm Si ₃ N ₄ thin film, and the second insulating film 24 may be formed of a 14 nm oxide thin film. That is, the first insulating film 20, the charge storage film 22, and the second insulating film 24 are formed to have a thickness ratio of 1: 1: 2, and the charges transferred from the CNT are stabilized in the charge storage film 22 for a long time. Can be held.

FIG. 3A is a cross-sectional view of a second memory cell used in a memory device according to an exemplary embodiment of the present invention. As shown in the figure, the second used in the memory device according to the embodiment of the present invention.
The memory cell 25 includes a third insulating layer 29 formed in contact with the gate electrode 19 and a plurality of nano dots 27 deposited under the third insulating layer 29 and filled with a charge storage material 28. The porous film 26 is included.

The third insulating layer 29 is made of silicon oxide, and the charge storage material 28 is made of silicon or silicon nitride. Desirably, the third insulating film 29 is replaced with the porous film 26.
The charge storage material 28 of the nanodots 27 can be stably stored by making it thicker.

FIG. 3B is a cross-sectional view showing a third memory cell 35 used in the memory device according to the embodiment of the present invention.
The third memory cell 35 used in the memory device according to the embodiment of the present invention has a structure in which an insulating film is further stacked under the porous film 26 of the second memory cell 25, and the fourth insulating film 3
4, a porous film 36 in which a plurality of nanodots 37 filled with the charge storage material 38 are located, and a fifth insulating film 34 ′. The fourth insulating film 34 is preferably formed thick so as to suppress the charge injection from the gate electrode 19 shown in FIG. 1 and keep the charges held in the charge storage material 38 for a long time. It is preferable that the CNTs 21 are thinly formed so that electrons or holes are easily tunneled from the CNTs 21 and move to the porous film 36.

FIG. 4 shows that in the third memory cell 35 used in the memory device according to the embodiment of the present invention shown in FIG. 3B, the fourth insulating film 34 is made of SiO ₂ , and the porous film 36 and the third insulating film 34 'are formed. Is made of Al ₂ O _{3 and} has a charge storage material of 38
Is an SEM (Scanning E) made of Si (or Si ₃ N ₄ )
lectron Microscopy) A photograph is shown.

5A and 5B are SEM photographs showing the CNT 21 connecting the source electrode 15 and the drain electrode 17 in the memory device according to the embodiment of the present invention. The produced CNT21 was determined to have a diameter of about 3 mm as measured by atomic force microscopy.

6A to 6I show the first memory cell 23.
6A and 6B are process diagrams illustrating a method of manufacturing a memory device according to an exemplary embodiment of the present invention.

First, as shown in FIG. 6A, after insulating layer 13 is vapor-deposited on the upper surface of substrate 11, CNT 21 is grown on the upper surface. The CNT powder generated by the CVD technique is dispersed in a chloroform solution, applied to a plurality of points on the insulating layer 13, and then dried. In the drawing, only a single CNT 21 formed on one region is shown.

Next, as shown in FIG. 6B, a conductive material layer 14 for forming source and drain electrodes, for example, a material layer 14 made of a metal layer such as Au or Ti is deposited on the insulating layer 13. The mask 12a is positioned on the conductive material layer 14 and patterned by electron beam lithography. It is preferable that the source and drain electrodes 15 and 17 formed after patterning be subjected to thermal annealing to reduce contact resistance. For example, it can be rapidly annealed at 600 ° C. for about 30 seconds in a vacuum environment. The source and drain electrodes 15 and 17 formed in this manner are shown in FIG. 6C.

6D to 6F show the first memory cell 2
3 shows the step of depositing 3. Referring to FIG. 6D,
Source and drain electrodes 15 and 17, and C connecting both electrodes 15 and 17 between the source and drain electrodes 15 and 17
The first insulating film 2 is formed on the top of the NT 21 and the surface of the insulating layer 13.
0a, the charge storage film 22a, and the second insulating film 24a are sequentially deposited to form the memory cell 23a. Then, FIG.
As shown in FIG. 6E, the mask 12b is positioned on the upper portion, exposed and developed, and then the first memory cell 23 is formed in contact with the source and drain electrodes 15 and 17 and the upper portion of the CNT 21, as shown in FIG. 6F. The first memory cell 23 includes a first insulating film 20 made of oxide, a charge storage film 22 made of Si or Si ₃ N ₄ , and a second insulating film 2 made of oxide.
Including 4. A CVD method is used to mix SiH ₄ and O ₂ gases to form the oxide film, and SiH ₂ Cl ₂ and NH ₃ gases are used to form the Si ₃ N ₄ film.

6G to 6I show a process of forming a gate electrode. Referring to FIG. 6G, a metal layer 18 for forming a gate electrode is deposited on the surface of the insulating layer 13 to form source and drain electrodes 15 and 17, and a CNT 21.
And the memory cell 23 are applied. As shown in FIG. 6H, when the mask 12c is positioned on the metal layer 18, exposed, developed and etched, the gate electrode 19 is patterned as shown in FIG. 6I.

7A to 7E are process diagrams of the third memory cell 35 used in the memory device according to the embodiment of the present invention. First, as shown in FIG. 7A, the fifth insulating film 3
When the oxide film 4'is oxidized, an oxide film 36 'of the fifth insulating film 34' is formed on the upper part. When the oxide film 36 'is oxidized by applying electricity to the oxide film 36', a plurality of nanodots 37 are formed as shown in FIG. The porous film 36 in which is formed is manufactured. For example,
When aluminum is used as the fifth insulating film 34 ',
When this is placed in a sulfuric acid solution or a phosphoric acid solution and electricity is applied to oxidize it, a plurality of nanodots 37 as shown in the figure are formed. Such oxidation is called anodization. When aluminum is oxidized, it is formed into alumina and its volume becomes slightly larger.

Next, as shown in FIG. 7C, the plurality of nanodots 37 are filled with silicon or silicon nitride used as a material forming the charge storage film 22 by using CVD, sputtering, etc., and as shown in FIG. 7D. If dry etching is performed, a porous film 36 capable of collecting charges is formed. As shown in FIG. 7E, the third memory cell 35 is completed by depositing the fourth insulating film 34 on the upper surface. As shown in FIGS. 6A to 6C, the method of manufacturing the memory device including the third memory cell 35 includes forming the CNT 21 and the source and drain electrodes 15 and 17, and then mounting the third memory cell 35 on the CNT 21. Then, after forming the third memory cell 35, the gate electrode 19 can be formed by using the steps shown in FIGS. 6G to 6I.

The second memory cell 25 can be formed in a similar manner. In the process of forming the third memory cell 35, the fifth insulating film 34 'is completely oxidized to form the porous film 26 having the plurality of nanodots 27, and the nanodots 27 are filled with the charge storage material 28 and etched. By depositing the third insulating film 29 on the upper portion, the second memory cell 25 as shown in FIG. 3A is formed.

In the memory device according to the embodiment of the present invention, if the source electrode 15 is grounded and a positive voltage is applied to the drain electrode 17, electrons move to the CNT 21 and a current flows. At this time, if a predetermined gate voltage higher than the drain voltage applied to the drain electrode 17 is applied to the gate electrode 19, electrons are transferred from the CNT 21 to the memory cell 2.
3, 25 and 35 are tunneled to the first insulating film 20 or the fifth insulating film 34 ′ to move to the charge storage film 22 or the nanodots 27 and 37. By properly adjusting the gate voltage and the drain voltage, electrons can be stored, erased, and flowed out in the charge storage film 22 and the nanodots 27 and 37 to record, remove, and reproduce information.

FIG. 8A shows a single upper gate electrode and a number of source and drain electrodes, CNTs, located therebelow.
FIG. 3 is a plan view of a memory device including 8B shows a photograph in which CNTs are connected between the source electrode S and the drain electrode D of FIG. 8A.

In the memory device according to the embodiment of the present invention, the material and thickness of the storage film forming the memory cell, the diameter and length of the plurality of nanodots arranged in the porous film, and the material filling the nanotube channel. The material may be appropriately adjusted to control the gate voltage and the source-drain voltage to operate the volatile or non-volatile memory.

FIG. 9 is a graph showing the relationship between the voltage between the source and drain electrodes and the current between the source and drain electrodes when the gate voltage changes from 0V to 10V in the memory device according to the embodiment of the present invention. is there.

F ₁ indicates that when the gate voltage is 0 V, the source-drain current I _sd becomes 0 regardless of the change in the source-drain voltage V _sd .

When the gate voltage is 10 V, f ₂ is
It is shown that the source-drain current I _sd increases from 0 A to about 1000 nA when the source and drain voltage V _sd increases with a positive value, and from 0 A to − when the source-drain voltage decreases with a negative value. It shows that it decreases to 1000 nA.

When the gate voltage is 0 at a constant source-drain voltage, information cannot be recorded because there is no electron transfer between the source-drain, and when the gate voltage is higher than 0, the source-drain current starts to flow and the gate Information can be stored by capturing a predetermined number of electrons while increasing the voltage.

FIG. 10 shows a CNT FET (Field Effect Transistor) having a charge storage film made of a 28 nm ONO thin film.
sistor) is a graph showing changes in the current I _sd between the source and drain electrodes with respect to changes in the gate voltage.

The current I _sd between the source and drain electrodes increases together as the negative gate voltage increases, and decreases to several femtoampere (fA) at the positive gate voltage p-type CN.
The current-voltage (IV) characteristic of TFET is shown. The ratio of the on-state current Ion to the off-state current Ioff (Io
When the gate electrode changes from −4V to 4V, n / Ioff) exceeds 10 ⁵ when Vsd = 1V. The off-state current was kept below a few pA during the measurement period. This is considered to be due to the structure in which the gate electrode of the memory element is located and the high breakdown voltage of the ONO thin film. In the flash type memory, the higher the Ion / Ioff ratio, the higher the threshold voltage and the better the performance.

FIG. 11A shows a memory cell (S
FIG. 11B shows current-voltage (IV) characteristics of a P-type CNT memory device including iO ₂ / Si ₃ N ₄ / SiO ₂ ).
0 nm thick memory cell (SiO ₂ / Si ₃ N ₄ / Si
O ₂₎ current of the N-type CNT memory device including a - voltage (I
-V) shows characteristics.

Referring to FIG. 11A, in the P-type CNT memory device, Id has some difference depending on the level of V _sd , but when the gate voltage Vg is about 2.5 V, the drain current Id sharply decreases. Indicates a phenomenon.

Referring to FIG. 11B, in the N-type CNT memory device, when the drain current Id is V _sd = 3V, a clear hysteresis phenomenon occurs when the gate voltage is 4V or more.

FIG. 12 shows a gate voltage Vg of 0V to 1V when different V _sd is applied to the N-type CNT memory device.
7 is a graph showing a change in drain current Id due to a change in.

Referring to the drawings, n1 is V_sdIs 0V
N2 is V_sdIs -5V, n3 has Vsd-
When it is 5.5V, n4 is V_sdIs -6V, n5
Is V _sdOf Id with respect to Vg when is −6.5V
Indicates. Id from n1 to n5 increases with Vg
It can be seen that it increases and is saturated by about 0.6V.

When h is the thickness of the memory cell, that is, the ONO film, and L and r are the length and radius of the CNT, respectively,
The capacitance of CNT per unit length is as shown in Equation 1.

[0059]

[Equation 1]

Effective dielectric constant of ONO film = -3, h = 30
By substituting nm, r = 1.5 nm, L = 1 μm, and a defective gate voltage (V _gd ) = 2 V into Equation 1, the hole density P is 580 μm ⁻¹ . At this time, the hole mobility (μ _h ) is presented as Equation 2.

[0061]

[Equation 2]

This value is SWNT (Single wall nanotub
It is higher than the hole mobility of e) and MWNT (Multi wall nanotube).

FIG. 13 shows the same memory device with Id = 50n.
9 is a graph showing a change in threshold voltage due to a change in Vg when A is constant.

The applied positive gate voltage raises the threshold voltage, which means that holes are injected from the CNT into the ONO thin film and the trap sites are filled with holes. It can be seen that when the gate voltage Vg increases from 0V to 7V, the threshold voltage increases by about 60 mV and the holes are quasi-quantized.

FIG. 14 shows a simplified diagram of the electric field between the CNT and the gate electrode and a graph of the surface charge density σ induced on the gate surface per unit distance between the CNT and the gate electrode.

Referring to FIG. 14, the gate voltage is CNT.
Creates a high electric field around the surface of the. When the gate electrode is regarded as a perfect conductor and the CNT diameter is 3 nm,
Since the ONO thin film between the CNT and the gate electrode can be assumed to be a single layer with an effective dielectric constant of 3, the electric field near the CNT can be calculated. When the gate voltage is 5V, the calculated electric field is 970V / μm, the magnitude of which is sufficient to generate Fowller Nodheim-shaped tunneling. Moreover, if the tunneled charges flow along the electric field line, the charges are trapped in the nitride film in proportion to the intensity of the electric field calculated from the induced charge distribution. In the calculation, 70% of all the tunneled charges are FWHM (Full
Width at Half Maximum), which corresponds to 14 of ONO thin film.
It may be implanted into a nitride thin film having a thickness of nm. It is known that charges are quantized at room temperature when the size of quantum dots is 10 nm or less. Referring to the graph, induced charge density σ
Increases as it approaches CNT.

FIG. 15 shows the drain current Id for 100 seconds.
It is a graph which shows the change of. The localized electric charge distribution can be induced in the nitride film by the high electric field distribution of the localized CNT, and the electric charge trapped in the local area can be diffused to the area where the electric charge is not stored, but the total current is As shown, it remains constant over time. From this, it can be seen that the trap sites that store charges in the ONO thin film of the CNT memory device act as quantum points of the flash memory.

The present invention is a non-volatile memory using a CNT-FET and an ONO thin film, in which charges are stored at trap sites of the ONO thin film. The stored charge is 60 mV
It has a quantized voltage increment of the order. This is ONO
It is shown that the thin film has a quasi-quantized energy state. The quantized state is associated with the localized high electric field associated with the nanoscale CNT channels, indicating that the CNT memory device can be operated as an ultra-dense high-capacity flash memory.

The memory device according to the embodiment of the present invention uses a charge storage film or nanodots that store charges by using CNTs instead of the ion-implanted channel required for electron transfer between the source and the drain in the existing semiconductor device. No additional capacitor is required because the porous film having the above is provided.

Also, by using CNT having high electron conductivity and thermal conductivity as an electron transfer channel, a small transistor can be manufactured, and a highly integrated and highly efficient memory device can be realized.

While many of the foregoing items have been specifically described, they should not be construed as limiting the scope of the invention, but rather should be construed as illustrative of the preferred embodiment.

For example, those skilled in the art to which the present invention pertains can use other materials having excellent characteristics of trapping electrons as the charge storage film or the charge storage material according to the technical idea of the present invention. Therefore, the scope of the present invention should not be determined by the above embodiments, but should be determined only by the technical idea of the claims.

[0073]

As described above, since the memory device according to the present invention includes the small transistor using the high conductivity CNT and the memory cell for storing electrons, a highly efficient and highly integrated memory device can be realized.

[Brief description of drawings]

FIG. 1 is a perspective view of a memory device according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of a first memory cell used in a memory device according to an exemplary embodiment of the present invention.

FIG. 3A is a cross-sectional view showing a second memory cell used in a memory device according to an exemplary embodiment of the present invention.

FIG. 3B is a cross-sectional view showing a third memory cell used in a memory device according to an exemplary embodiment of the present invention.

FIG. 4 is a SEM photograph of a third memory cell used in a memory device according to an exemplary embodiment of the present invention.

FIG. 5A shows a memory device according to an embodiment of the present invention,
5 is an SEM photograph showing carbon nanotubes connecting a source electrode and a drain electrode.

FIG. 5B is a memory device according to an embodiment of the present invention,
5 is an SEM photograph showing carbon nanotubes connecting a source electrode and a drain electrode.

FIG. 6A is a manufacturing process diagram of a memory device according to an embodiment of the present invention which employs a first memory cell, and illustrates a process of growing CNTs on an insulating layer formed on a top surface of a substrate.

FIG. 6B is a manufacturing process diagram of a memory device according to an embodiment of the present invention that employs a first memory cell, showing a process of disposing a mask on the conductive material layer.

FIG. 6C is a manufacturing process diagram of the memory device according to the embodiment of the present invention which employs the first memory cell, and illustrates a state after the formation of the source electrode and the drain electrode.

FIG. 6D is a manufacturing process diagram of a memory device according to an embodiment of the present invention which employs a first memory cell, and shows a process of sequentially forming a first insulating film, a charge storage film, and a second insulating film.

FIG. 6E is a manufacturing process diagram of a memory device according to an embodiment of the present invention which employs a first memory cell, and shows a masking / exposure / developing process.

FIG. 6F is a manufacturing process diagram of a memory device according to an embodiment of the present invention which employs a first memory cell, showing a state after the formation of the first memory cell.

FIG. 6G is a manufacturing process diagram of a memory device according to an embodiment of the present invention employing a first memory cell, showing a process of depositing a metal layer for forming a gate electrode.

FIG. 6H is a manufacturing process diagram of the memory device according to the embodiment of the present invention which employs the first memory cell, and shows a masking / exposure / development process for forming a gate electrode.

FIG. 6I is a manufacturing process diagram of a memory device according to an embodiment of the present invention that employs a first memory cell, showing a state after patterning of a gate electrode.

FIG. 7A is a manufacturing process diagram of a third memory cell employed in the memory device according to the embodiment of the present invention, showing an oxide film forming process.

FIG. 7B is a manufacturing process diagram of a third memory cell employed in the memory device according to the embodiment of the present invention, which shows a porous film forming process.

FIG. 7C is a manufacturing process diagram of a third memory cell used in the memory device according to the embodiment of the present invention, which illustrates a process of filling the nanodots with silicon or silicon nitride.

FIG. 7D is a manufacturing process diagram of a third memory cell employed in a memory device according to an embodiment of the present invention, showing a porous film after dry etching.

FIG. 7E is a manufacturing process diagram of a third memory cell employed in a memory device according to an embodiment of the present invention, which shows a process of forming a fourth insulating film to form a third memory cell.

8A is a plan view showing a structure of a memory device according to an embodiment of the present invention, FIG.

FIG. 8B is a view showing a CNT channel between the source and drain electrodes of FIG. 8A.

FIG. 9 is a graph showing changes in the source-drain current Isd with respect to changes in the source-drain voltage Vsd in the memory device according to the example of the present invention.

FIG. 10 shows a source-drain current I with respect to a change in gate voltage Vg in a memory device according to an embodiment of the present invention.
It is a graph which shows change of sd.

FIG. 11A is a diagram showing a source-drain current I of a P-type memory device according to an embodiment of the present invention with respect to a change in gate voltage Vg.
It is a graph which shows change of sd.

FIG. 11B shows a source-drain current I with respect to a change in the gate voltage Vg of the N-type memory device according to the embodiment of the present invention.
It is a graph which shows change of sd.

FIG. 12 is a graph showing changes in the drain current Id with respect to changes in the gate voltage Vg at a predetermined source-drain voltage in the N-type memory device according to the example of the present invention.

FIG. 13 is a graph showing changes in the threshold voltage Vth with respect to changes in the gate voltage Vg when the drain current Id is 50 nA in the memory device according to the embodiment of the present invention.

FIG. 14 shows C in a memory device according to an embodiment of the present invention.
3 is a graph of an electric field between NT and a gate electrode and a surface charge density σ induced from a gate surface per unit distance between CNT and a gate electrode in a memory device according to an exemplary embodiment of the present invention.

FIG. 15 shows a memory device 1 according to an embodiment of the present invention.
It is a graph which shows change of drain current Id for 00 seconds.

[Explanation of symbols]

11 board 13 Insulation layer 15 Source electrode 17 Drain electrode 19 Gate electrode 21 CNT 23 memory cells

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI Theme Coat (reference) H01L 29/788 29/792 (72) Inventor Tora Yanagi ▲ Respect ▼ Yotsutsu-dong, Daedang-gu, Suwon-si, Gyeonggi-do, Republic of Korea 973-3 Address Doosan Apartment 805 Building No. 505 (72) Inventor Zhou Qin ▲ Standing ▼ South Korea 1 Gwangmyeong-si Gyeonggi-do 1-dong 55 Toyo Apartment 101 Building 1802 F Term (reference) 5F083 EP17 EP42 ER11 JA02 JA04 JA19 JA32 JA38 JA39 PR21 PR34 5F101 BA45 BA47 BC02 BD13 BH02 BH16

Claims (36)

[Claims] 1. A substrate, a source electrode and a drain electrode, which are spaced apart from each other on the substrate by a predetermined distance and to which a voltage is applied, and the source electrode and the drain electrode are connected to each other to form a channel for electron transfer. A nanotube, a memory cell located above the carbon nanotube and storing charges flowing from the carbon nanotube, and contacting an upper portion of the memory cell to adjust a charge amount flowing from the carbon nanotube into the memory cell. A carbon nanotube memory device comprising: a gate electrode. 2. The carbon nanotube memory device of claim 1, wherein the substrate is a silicon substrate. 3. The carbon nanotube memory device of claim 2, further comprising a silicon oxide layer stacked on the substrate. 4. The memory cell comprises a first insulating layer formed on the carbon nanotube so as to contact the carbon nanotube, and a charge storage layer that is deposited on the first insulating layer to store charges. The carbon nanotube memory device of claim 1, further comprising a film and a second insulating film formed on the charge storage film and contacting the gate electrode. 5. The carbon nanotube memory device of claim 4, wherein the first insulating layer has substantially the same thickness as the charge storage layer. 6. The carbon nanotube memory device of claim 4, wherein the second insulating layer has a thickness about twice that of the charge storage layer. 7. The carbon nanotube memory device of claim 4, wherein the first and second insulating layers are silicon oxide layers. 8. The carbon nanotube memory device of claim 4, wherein the charge storage layer is a silicon layer or a silicon nitride layer. 9. The carbon nanotube memory device of claim 4, wherein the charge storage layer has a thickness of 15 nm or less. 10. The carbon nanotube memory device of claim 4, wherein the charge storage layer is a porous layer having a plurality of nanodots filled with a charge storage material. 11. The memory cell is formed under the gate electrode, and has a third insulating film that is in contact with the gate electrode, and the memory cell is under the third insulating film and is in contact with the carbon nanotube. The carbon nanotube memory device of claim 1, further comprising: a porous film having a plurality of nanodots filled with a storage material. 12. The third insulating film is about 2 times thicker than the porous film.
The carbon nanotube memory device of claim 11, wherein the carbon nanotube memory device has a double thickness. 13. The carbon nanotube memory device of claim 11, wherein the third insulating layer has the same thickness as the porous layer. 14. The carbon nanotube memory device of claim 11, wherein the third insulating layer is a silicon oxide layer. 15. The carbon nanotube memory device of claim 10, wherein the charge storage material is silicon or silicon nitride. 16. The carbon nanotube memory device of claim 10, wherein the porous film is an aluminum oxide film. 17. The carbon nanotube memory device of claim 10, wherein the nanodot has a diameter of 15 nm or less. 18. A first step of growing a carbon nanotube on a substrate, and forming a source electrode and a drain electrode using the carbon nanotube as a charge transfer channel so as to contact the carbon nanotube, the carbon nanotube, A first insulating layer, a charge storage layer and a second insulating layer are sequentially deposited on the source electrode and the drain electrode, and then patterned using a photolithography process to form a memory cell contacting the carbon nanotube. Forming a gate electrode for controlling an amount of charges flowing from the carbon nanotubes into the charge storage layer by patterning using a photolithography process after depositing a metal layer on the second insulating layer in two steps. A method of manufacturing a carbon nanotube memory device, comprising: 19. The method of claim 18, wherein in the first step, an insulating layer is formed on the upper surface of the substrate and carbon nanotubes are grown on the upper surface of the insulating layer. Method. 20. The substrate is silicon and the insulating layer is silicon oxide.
9. The method for manufacturing the carbon nanotube memory device according to 9. 21. The method of manufacturing a carbon nanotube memory device according to claim 18, wherein the source electrode and the drain electrode are formed by electron beam lithography in the first step. 22. The method of claim 18, wherein, in the second step, the first insulating film and the storage film are deposited to have substantially the same thickness. 23. The method of claim 18, wherein, in the second step, the second insulating layer is deposited to a thickness about twice that of the storage layer. 24. The method of claim 18, wherein the first and second insulating layers are made of silicon oxide. 25. The method of claim 18, wherein the charge storage layer is made of silicon or silicon nitride. 26. The method of claim 18, wherein the charge storage layer is formed to a thickness of 15 nm or less. 27. A first step of growing a carbon nanotube on a substrate and forming a source electrode and a drain electrode using the carbon nanotube as a charge transfer channel so as to be in contact with the carbon nanotube; A second step of depositing a first insulating layer on the source and drain electrodes, anodic oxidation, and etching to form a porous layer having a plurality of nanodots formed by oxidizing the first insulating layer; After depositing a charge storage material on the porous layer, the nano dots are etched to fill the charge storage material with the third layer.
And a step of depositing a second insulating layer on the porous layer and patterning the first insulating layer, the porous layer and the second insulating layer using a photolithography process to form a memory cell.
And a step of depositing a metal layer on the second insulating layer and patterning the layer using a photolithography process to form a gate electrode for controlling an amount of charges flowing from the carbon nanotube into the porous layer. And a method for manufacturing a carbon nanotube memory device, comprising: 28. The carbon nanotube memory device of claim 27, wherein in the first step, an insulating layer is formed on the upper surface of the substrate and carbon nanotubes are grown on the upper surface of the insulating layer. Method. 29. The method of claim 28, wherein the substrate is made of silicon and the insulating layer is made of silicon oxide. 30. The method of manufacturing a carbon nanotube memory device according to claim 27, wherein in the first step, the source electrode and the drain electrode are formed by electron beam lithography. 31. The method of claim 27, wherein in the second step, the first insulating layer and the porous layer are deposited to have substantially the same thickness. 32. The method of claim 27, wherein in the second step, the second insulating layer is deposited to have a thickness about twice that of the porous layer. 33. The method of claim 27, wherein the first and second insulating layers are made of silicon oxide. 34. The method of claim 27, wherein the charge storage material comprises silicon or silicon nitride. 35. The method of claim 27, wherein the porous film is formed to a thickness of 15 nm or less. 36. The method of claim 27, wherein in the first step, the first insulating film is entirely oxidized to form a porous film having a plurality of nanodots.