JP2003258321A - Sheet type β-FeSi2 element - Google Patents
Sheet type β-FeSi2 elementInfo
- Publication number
- JP2003258321A JP2003258321A JP2002057519A JP2002057519A JP2003258321A JP 2003258321 A JP2003258321 A JP 2003258321A JP 2002057519 A JP2002057519 A JP 2002057519A JP 2002057519 A JP2002057519 A JP 2002057519A JP 2003258321 A JP2003258321 A JP 2003258321A
- Authority
- JP
- Japan
- Prior art keywords
- film
- fesi
- sheet
- type
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910006578 β-FeSi2 Inorganic materials 0.000 title 1
- 238000004519 manufacturing process Methods 0.000 claims abstract description 30
- 239000000843 powder Substances 0.000 claims abstract description 25
- 238000010438 heat treatment Methods 0.000 claims abstract description 23
- 230000001681 protective effect Effects 0.000 claims abstract description 14
- 239000002994 raw material Substances 0.000 claims abstract description 11
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 238000003825 pressing Methods 0.000 claims abstract description 4
- 239000010408 film Substances 0.000 claims description 65
- 238000000034 method Methods 0.000 claims description 49
- 239000004065 semiconductor Substances 0.000 claims description 44
- 229910006585 β-FeSi Inorganic materials 0.000 claims description 39
- 239000010409 thin film Substances 0.000 claims description 35
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000004642 Polyimide Substances 0.000 claims description 6
- 229910052742 iron Inorganic materials 0.000 claims description 6
- 229920001721 polyimide Polymers 0.000 claims description 6
- 239000011812 mixed powder Substances 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 239000000919 ceramic Substances 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 239000002904 solvent Substances 0.000 claims description 4
- 239000007921 spray Substances 0.000 claims description 4
- 238000005507 spraying Methods 0.000 claims description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-M hydroxide Chemical compound [OH-] XLYOFNOQVPJJNP-UHFFFAOYSA-M 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 238000004804 winding Methods 0.000 claims description 3
- 229910000859 α-Fe Inorganic materials 0.000 claims description 3
- 229910002651 NO3 Inorganic materials 0.000 claims description 2
- NHNBFGGVMKEFGY-UHFFFAOYSA-N Nitrate Chemical compound [O-][N+]([O-])=O NHNBFGGVMKEFGY-UHFFFAOYSA-N 0.000 claims description 2
- 238000007865 diluting Methods 0.000 claims description 2
- 238000010304 firing Methods 0.000 claims description 2
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 229910052718 tin Inorganic materials 0.000 claims description 2
- 229910052725 zinc Inorganic materials 0.000 claims description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims 5
- 238000000576 coating method Methods 0.000 claims 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims 2
- 229910045601 alloy Inorganic materials 0.000 claims 2
- 239000000956 alloy Substances 0.000 claims 2
- 239000011248 coating agent Substances 0.000 claims 2
- 238000007639 printing Methods 0.000 claims 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims 1
- 229910052802 copper Inorganic materials 0.000 claims 1
- 239000010949 copper Substances 0.000 claims 1
- 238000001035 drying Methods 0.000 claims 1
- 230000001747 exhibiting effect Effects 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 claims 1
- 238000010298 pulverizing process Methods 0.000 claims 1
- 239000011135 tin Substances 0.000 claims 1
- 239000011701 zinc Substances 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract description 7
- 239000013078 crystal Substances 0.000 abstract description 6
- 230000008021 deposition Effects 0.000 abstract description 5
- 239000011261 inert gas Substances 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 30
- 239000000463 material Substances 0.000 description 20
- 239000010410 layer Substances 0.000 description 18
- 238000006243 chemical reaction Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 238000007606 doctor blade method Methods 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000011888 foil Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 238000005224 laser annealing Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 239000011863 silicon-based powder Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 229910001220 stainless steel Inorganic materials 0.000 description 2
- 239000010935 stainless steel Substances 0.000 description 2
- 238000001771 vacuum deposition Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910005329 FeSi 2 Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 239000011247 coating layer Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 238000007726 management method Methods 0.000 description 1
- 229910052748 manganese Inorganic materials 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000002952 polymeric resin Substances 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Landscapes
- Photovoltaic Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は光センサー、太陽電
池、熱電変換素子などエレクトロニクス分野における半
導体素子デバイスの技術分野のうち、新しい半導体材料
を使用して素子を簡便に作製する方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for easily manufacturing an element using a new semiconductor material in the technical field of semiconductor element devices in the field of electronics such as photosensors, solar cells, thermoelectric conversion elements.
【０００２】[0002]
【従来の技術】従来の半導体デバイスはシリコン（Si）
基板、GaP、GaAs基板やセラミクス平面基板材の上に機
能性の材料薄膜を形成し、その上にフォトリソグラフィ
ー技術や真空プロセスを用いて電気信号の入出力を行う
電極を構成し、また光無反射保護膜を真空プロセスを用
いて製作されている。2. Description of the Related Art Conventional semiconductor devices are silicon (Si)
A functional material thin film is formed on a substrate, GaP, GaAs substrate or ceramics planar substrate material, and electrodes for inputting and outputting electrical signals are formed on it by using photolithography technology or a vacuum process. The reflection protection film is manufactured using a vacuum process.
【０００３】近年、地球資源の豊富で環境に負荷の少な
い材料からなるβ-FeSi2半導体デバイスの使用が提案さ
れ開発が行なわれている。この材料による接合膜作製法
はレーザアブレーション法、イオン注入法、分子線ビー
ムエピタキシャル法、真空蒸着法など真空プロセスによ
るものが多い。一方、電極形成としては従来の金属膜蒸
着法に代えて、β-FeSi2材料特有の高温で金属結晶相に
変換する効果を利用する方法があり、レーザアニール法
（特願２００１−１５７０８７、２００１−２３５６６
４）によって金属電極フォトリソグラフ形成を除去する
方法が提案されている。更に光無反射保護膜作製は従来
の真空中製膜プロセスによるSiO2を用いる手法がなされ
てきた。In recent years, the use of β-FeSi 2 semiconductor devices made of materials that are rich in earth resources and have low environmental impact have been proposed and developed. The bonding film forming method using this material is often a vacuum process such as a laser ablation method, an ion implantation method, a molecular beam epitaxial method, or a vacuum deposition method. On the other hand, as an electrode formation, there is a method of utilizing an effect of converting to a metal crystal phase at a high temperature peculiar to a β-FeSi 2 material instead of the conventional metal film vapor deposition method, and a laser annealing method (Japanese Patent Application No. 2001-157087, 2001). -23566
According to 4), a method of eliminating the metal electrode photolithography formation has been proposed. Furthermore, the method of using SiO 2 by the conventional vacuum film forming process has been used for the production of the light non-reflection protective film.
【０００４】[0004]
【発明の解決しようとする課題】従来の素子作成に関し
ては各種工程について以下のような課題を持っていた。
素子の基板には単結晶Siが使用されるので、価格が
高い。太陽電池のように極低価格で素子を作る必然性の
ある場合には、単結晶Siを使用するのでは材料コストや
製造コストが高い。
多結晶Si基板を使用する場合には、多結晶基板原料
となる不純物濃度の高い、いわゆる低級品Siくずの量が
供給に間に合わないので原料入手難である。
Siや化合物で特性の良い半導体接合層を作るには、
高真空中で高度に成長を制御できる高価な装置を使用す
るので、スループットは低くコストが高くなる。
電極形成に金属膜フォトリソグラフ法やレーザアニ
ール法を使用すると、高価な装置が必要であるし、スル
ープットも大きく出来ない。
光無反射保護膜を形成する場合に、真空工程を使用
すると装置コストがかかってしまうし、スループットが
装置の内容積によって制限を受けてしまう。Regarding the conventional device fabrication, there were the following problems in various steps. Since single crystal Si is used for the substrate of the device, the price is high. When it is necessary to manufacture an element at an extremely low price like a solar cell, using single crystal Si requires high material cost and manufacturing cost. When a polycrystalline Si substrate is used, it is difficult to obtain the raw material because the amount of so-called low-grade Si scrap having a high impurity concentration, which is a raw material for the polycrystalline substrate, cannot be supplied in time. To make a semiconductor junction layer with good characteristics using Si or compounds,
Throughput is low and cost is high due to the use of expensive equipment with highly controllable growth in high vacuum. If a metal film photolithography method or a laser annealing method is used for electrode formation, an expensive apparatus is required and throughput cannot be increased. If a vacuum process is used to form the light non-reflective protective film, the cost of the device increases, and the throughput is limited by the internal volume of the device.
【０００５】[0005]
【課題を解決するための手段】上記課題を占めている多
くの原因は、製作コストが高くなるという点にある。本
発明では、素子製造の工程中に、真空や高出力レーザな
ど大掛かりな装置を使わず、高価な単結晶素材などを使
用しない素子形成を行うことである。すなわち、半導体
薄膜を形成してｎ−ｐの接合を作るときに単結晶基板を
使用せず、粉体堆積膜から熱反応で半導体膜を形成する
手法を採用する。電極形成はβ-FeSi2膜の一部を高温に
曝して金属化する現象を利用してパターン形成する。保
護膜形成のために使用する高価な装置を用いない工程を
取り入れる。素子全体の製造スル−プットを上げるため
に、各工程を連続で処理できる一貫システムを採用する
ことにより、課題を解決した。Many of the causes of the above problems are high manufacturing costs. The present invention is to form an element during the element manufacturing process without using a large-scale device such as a vacuum or a high-power laser and without using an expensive single crystal material or the like. That is, a method of forming a semiconductor film from a powder deposition film by a thermal reaction is adopted without using a single crystal substrate when forming a semiconductor thin film to form an np junction. Electrodes are formed by utilizing the phenomenon that a part of the β-FeSi 2 film is exposed to high temperature and metallized. A process that does not use expensive equipment used for forming a protective film is incorporated. The problem was solved by adopting an integrated system that can process each process continuously in order to increase the manufacturing throughput of the entire device.
【０００６】［請求項１の発明の実施の形態］図１は本
発明に従う可撓性を持つ基板上にβ-FeSi2半導体を用い
たデバイス素子の模式図である。素子を構成する基板１
は、可撓性のあるシート材料を用いている。この基板１
上に、β-FeSi2半導体のｎ型の特性を持つ薄膜２２が積
層している。この半導体膜の基板側には、下地電極とな
る薄膜層１１が存在する。更にｎ型半導体膜２の上に、
β-FeSi2半導体のp型の特性を持つ薄膜３２が積層して
おり、下層にあるｎ型とｐ型の薄膜が接合部分２３を形
成している。このｐ型薄膜３２の上面側には、電極７１
が構成されている。更にこのｐ型薄膜の上から、反射防
止膜となる誘電体薄膜４２が積層されている。この誘電
体薄膜４２の一部は剥ぎ取られた部分８があり、その部
分に露出した電極７１には電流や電圧を取り出す電極リ
ード線８１が接着固定されている。リード線８１は電圧
電流計８２に接続されている。なお、下地の半導体膜を
ｎ型とし上に乗せる膜をｐ型としているが、ｎとｐを反
対に構成しても良い。可撓性シートにポリイミドのよう
な高分子シートを用いた場合は、請求項3の実施形態に相
当する。[Embodiment of the Invention of Claim 1] FIG. 1 is a schematic view of a device element using a β-FeSi 2 semiconductor on a flexible substrate according to the present invention. Substrate 1 that constitutes an element
Uses a flexible sheet material. This board 1
A thin film 22 of a β-FeSi 2 semiconductor having an n-type characteristic is laminated on top. A thin film layer 11 serving as a base electrode is present on the substrate side of this semiconductor film. Furthermore, on the n-type semiconductor film 2,
Thin films 32 of p-FeSi 2 semiconductor having p-type characteristics are stacked, and the underlying n-type and p-type thin films form a joint portion 23. An electrode 71 is provided on the upper surface side of the p-type thin film 32.
Is configured. Further, a dielectric thin film 42 serving as an antireflection film is laminated on the p-type thin film. A part 8 of the dielectric thin film 42 is stripped off, and an electrode lead wire 81 for taking out a current or a voltage is adhesively fixed to the electrode 71 exposed at that part. The lead wire 81 is connected to the voltmeter 82. Although the underlying semiconductor film is n-type and the overlying film is p-type, n and p may be reversed. The case of using a polymer sheet such as polyimide for the flexible sheet corresponds to the embodiment of claim 3.
【０００７】［請求項２の発明の実施の形態］図1に示
した可撓性シート材料として、ステンレススチールのよ
うな金属薄板を用いたのが請求項２の発明の実施形態で
あり、この場合には下地電極１１は必要なく、下地基板
１が下地電極を兼ねる。[Embodiment of the Invention of Claim 2] According to the embodiment of the invention of Claim 2, a thin metal plate such as stainless steel is used as the flexible sheet material shown in FIG. In this case, the base electrode 11 is not necessary, and the base substrate 1 also serves as the base electrode.
【０００８】［請求項３の発明の実施の形態］図1に示
した可撓性シート材料として、ポリイミドまたはフッ素
樹脂のような高分子樹脂フィルムを用いたのが請求項２
の発明の実施形態であり、この場合には下地電極１１に
はAuやAlをフィルムに蒸着した膜を用いる。[Embodiment of the Invention of Claim 3] As the flexible sheet material shown in FIG. 1, a polymer resin film such as polyimide or fluororesin is used.
In this case, the base electrode 11 uses a film obtained by vapor-depositing Au or Al on the film.
【０００９】［請求項４の発明の実施の形態］p型及び
ｎ型β-FeSi2半導体薄膜を作る本発明の請求項４及び請
求項5の実施方法を示すのが図２、図3である。図2は下
地シート材が絶縁体を用いた場合のp-型β-FeSi2薄膜の
製法を示したものである。ポリイミド製シート１にはあ
らかじめ金やアルミニウム等の導電性薄膜１１を蒸着し
てあり、これはデバイスにした時の電極となる。この金
属箔付きシート上に、原料となるFe及びSi粉体２１を堆
積するが、原料粉体中にはp-型性質を作る第3元素とし
てAlやMnを添加したものを用いる。これらの混合粉体２
１を均一にシート1上に堆積して粉体層２にするには、
混合粉体を溶媒で溶いてスプレー塗布で行ったり、ドク
ターブレード法で塗布する。シート1上の粉体層２は、
矢印７の方向に移動するうちに乾燥し、加熱ロール５に
到達する。この加熱ロール5はあらかじめ９３７℃以下
に加熱されている。この温度はβ-FeSi2相を形成するの
に必要な温度で、この温度を超えてはならない。通常９
００〜９２０℃位に保つ。この加熱ロールは矢印５１の
方向に回転してシート１上の粉体層２を押圧しており、
粉体がローラに接して加熱移動される間に固体反応を起
こしp-型のβ-FeSi2相２２が生成する。このようにして
p-β-FeSi2薄膜の付着した可撓性シートが完成する。[Embodiment of the Invention of Claim 4] FIGS. 2 and 3 show a method for implementing p-type and n-type β-FeSi 2 semiconductor thin films according to claims 4 and 5 of the present invention. is there. Figure 2 shows the manufacturing method of the p-type β-FeSi 2 thin film when the underlying sheet material is an insulator. A conductive thin film 11 such as gold or aluminum is vapor-deposited on the polyimide sheet 1 in advance, and this becomes an electrode when it is used as a device. Fe and Si powders 21, which are raw materials, are deposited on the sheet with metal foil, and the raw material powders to which Al or Mn is added as a third element that creates p-type properties are used. These mixed powder 2
1 is uniformly deposited on the sheet 1 to form the powder layer 2,
The mixed powder is dissolved in a solvent and spray coating is performed, or a doctor blade method is used. The powder layer 2 on the sheet 1 is
As it moves in the direction of arrow 7, it dries and reaches the heating roll 5. The heating roll 5 has been heated to 937 ° C. or lower in advance. This temperature is the temperature required to form the β-FeSi 2 phase and must not be exceeded. Usually 9
Keep at around 0 to 920 ° C. This heating roll rotates in the direction of arrow 51 and presses the powder layer 2 on the sheet 1,
While the powder contacts the roller and is heated and moved, a solid reaction occurs to generate a p-type β-FeSi 2 phase 22. In this way
The flexible sheet with the p-β-FeSi 2 thin film attached is completed.
【００１０】β-FeSi2半導体層のｐ／ｎ接合層を作る本
発明の請求項５の実施方法を示すのが図３である。可撓
性下地シート上にp-型β-FeSi2膜２２が形成されている
シートを下地として、この上にβ-FeSi2薄膜の原料とな
るFe及びSi粉体３１を堆積するが、原料粉体中にはn-型
性質を作る第3元素としてCoやNiを添加したものを用い
る。これらの混合粉体３１を均一にp-β-FeSi2膜２上に
堆積して塗布層３にするには、混合粉体を溶媒で溶いて
スプレー塗布で行ったり、ドクターブレード法で塗布す
る。シート1上の粉体層３は、矢印７の方向に移動する
うちに乾燥し、加熱ロール５に流入する。この加熱ロー
ル5はあらかじめ９３７℃以下に加熱されている。この
温度はβ-FeSi2相を形成するのに必要な温度で、この温
度を超えてはならない。通常９００〜９２０℃位に保
つ。この加熱ロールは矢印５１の方向に回転してシート
１上の粉体層３を押圧しており、粉体がローラに接して
加熱移動される間に固体反応を起こしｎ-型のβ-FeSi2
相３２が生成する。このときp型のβ-FeSi2膜２２に接
してｎ型の接合面が構成するわけである。このようにし
てp-β-FeSi2薄膜とｎ-β-FeSi2薄膜による接合面が構
成された可撓性シートが完成する。FIG. 3 shows a method for implementing the fifth aspect of the present invention for forming a p / n junction layer of a β-FeSi 2 semiconductor layer. The sheet having the p-type β-FeSi 2 film 22 formed on the flexible base sheet is used as a base, and Fe and Si powder 31, which is a raw material of the β-FeSi 2 thin film, is deposited on the sheet. The powder contains Co and Ni added as the third element that creates the n-type property. In order to uniformly deposit these mixed powders 31 on the p-β-FeSi 2 film 2 to form the coating layer 3, the mixed powders may be dissolved in a solvent and spray coating may be performed, or a doctor blade method may be used. . The powder layer 3 on the sheet 1 dries while moving in the direction of the arrow 7 and flows into the heating roll 5. The heating roll 5 has been heated to 937 ° C. or lower in advance. This temperature is the temperature required to form the β-FeSi 2 phase and must not be exceeded. Usually, it is maintained at about 900 to 920 ° C. This heating roll rotates in the direction of arrow 51 and presses the powder layer 3 on the sheet 1, and a solid reaction occurs while the powder contacts the roller and is heated and moved, so that n-type β-FeSi is produced. 2
Phase 32 forms. At this time, an n-type bonding surface is formed in contact with the p-type β-FeSi 2 film 22. In this way, a flexible sheet having a joint surface composed of the p-β-FeSi 2 thin film and the n-β-FeSi 2 thin film is completed.
【００１１】［請求項６の発明の実施の形態］β-FeSi2
薄膜上に電極を形成する本発明の請求項６の実施方法を
示すのが図4である。接合面を構成した2種類のβ-FeSi2
薄膜２２，３２が付着した可撓性シート１が、矢印６１
の方向に回転している電極形成用の加熱ローラ６に押圧
され、矢印7の方向に流れて行く。この電極形成用加熱
ローラ６には、後に電極パターン形状となるように彫刻
が施された突起状彫刻７が付いており、この突起は982
度以上になるように加熱されている。通常この温度は９
９０℃〜１１００℃である。突起状彫刻７に接触押圧さ
れ９８２℃以上に過熱されたn-β-FeSi2膜の表面部分は
α-Fe2Si5相に変換し、この相が金属相であるから電気
伝導がよく、半導体膜表面上のデバイス電極７１ができ
る。この電極作製法はパターン電極を真空蒸着したり、
リフトオフなどの真空工程を用いないので工程が簡略化
でき、故障の少ないメリットを生じる。[Embodiment of the Invention of Claim 6] β-FeSi 2
FIG. 4 shows a method for carrying out claim 6 of the present invention in which an electrode is formed on a thin film. Two types of β-FeSi 2 forming the joint surface
The flexible sheet 1 to which the thin films 22 and 32 are attached is indicated by an arrow 61.
It is pressed by the heating roller 6 for electrode formation which is rotating in the direction of and flows in the direction of arrow 7. The heating roller 6 for electrode formation is provided with a protrusion-shaped engraving 7 engraved so as to have an electrode pattern shape later.
It is heated so that it becomes more than a degree. Usually this temperature is 9
The temperature is 90 ° C to 1100 ° C. The surface of the n-β-FeSi 2 film, which was pressed by contact with the protrusion-shaped engraving 7 and overheated to 982 ° C. or higher, was converted into an α-Fe 2 Si 5 phase, and this phase is a metal phase, so that the electric conductivity was good, A device electrode 71 is formed on the surface of the semiconductor film. This electrode manufacturing method, vacuum deposition of pattern electrodes,
Since a vacuum process such as lift-off is not used, the process can be simplified and there is a merit that there are few failures.
【００１２】可撓性シート上に形成されたデバイス上に
光無反射保護膜を形成する本発明の請求項７の実施方法
を示すのが図5である。光無反射膜は、透明誘電体の薄
膜を一般的には屈折率の異なる材質で複数枚重ねて作
る。SiやSn、Zn、Zr、Tiなど無機物の水酸塩や硝酸塩を
溶媒で希釈したインクをスプレーガン４３に装着する。
可撓性シート１上にβ-FeSi2接合膜３２が乗り、その一
部に金属化電極パターン７１が構成されたデバイスシー
トが矢印7の方向に流れている。そこへスプレーガン４
３に装着したインク４１を噴霧してデバイス上に堆積さ
せ、乾燥後連続焼成炉９中を通過する。この間を通過す
る際に堆積層は２００−４００℃に過熱されて反応し、
酸化膜４２が形成される。多層の光無反射膜を構成する
には、この工程を繰り返せばよい。なお、粉体積層膜を
形成する方法としてドクターブレード法を用いても良
い。また、加熱方法としてランプ加熱法や熱ローラ押圧
法でもよい。FIG. 5 shows a method for carrying out claim 7 of the present invention in which a light non-reflective protective film is formed on a device formed on a flexible sheet. The light non-reflective film is generally formed by stacking a plurality of transparent dielectric thin films made of materials having different refractive indexes. An ink obtained by diluting a hydroxide or nitrate of an inorganic substance such as Si, Sn, Zn, Zr, or Ti with a solvent is attached to the spray gun 43.
The β-FeSi 2 bonding film 32 rides on the flexible sheet 1, and the device sheet in which the metallized electrode pattern 71 is formed in a part thereof flows in the direction of arrow 7. Spray gun 4 there
The ink 41 attached to No. 3 is sprayed to be deposited on the device, dried, and then passed through the continuous firing furnace 9. When passing through this period, the deposited layer is heated to 200-400 ° C. and reacts,
The oxide film 42 is formed. This step may be repeated to form a multilayer light non-reflective film. A doctor blade method may be used as a method for forming the powder laminated film. A lamp heating method or a heat roller pressing method may be used as the heating method.
【００１３】可撓性シート上に連続してβ-FeSi2半導体
デバイスを製造する本発明の請求項8の実施方法を示す
のが図6（A）、図６（B）である。送り出しロール１５
に可撓性シート材料が巻き込まれており、デバイスの基
体となるシートフィルムが矢印16の方向に回転して流
れ、各種製造工程を経て巻取りロール１８に矢印１９の
方向に回転して巻き取られる。図６（A）に於いては送
り出しロールから出たフィルム１の上に、第1の工程と
して原料粉２を堆積し加熱ロール4によって第1層のβ-F
eSi2半導体膜２２を形成する。次に第2の工程として半
導体接合面を形成するために、半導体膜22とは極性の異
なる原料粉を堆積し加熱ロール5によって第2層のβ-FeS
i2半導体膜3２を形成する。接合膜のできた半導体膜
は、次の第3工程に入る。すなわち電極形成用加熱ロー
ラ6によって押圧された後には、膜上の一部が金属化し
た電極パターン71が形成されている。更に次の工程は図
６（Ｂ）に繋がる。第4工程に入ると、スプレーによっ
て誘電体水酸化物原料４１が堆積し、加熱炉9を通過す
る間に反応が起こり光無反射保護膜４２が形成され、デ
バイス素子の機能部分本体部が出来上がる。更にこれら
の膜は巻取りロール１８に導かれ、矢印19方向に回転し
ているのでロールに巻き取られて生産工程を終える。FIGS. 6 (A) and 6 (B) show a method for carrying out claim 8 of the present invention for continuously producing β-FeSi 2 semiconductor devices on a flexible sheet. Sending roll 15
The flexible sheet material is wound around the sheet, and the sheet film serving as the base of the device rotates and flows in the direction of arrow 16, and after various manufacturing steps, rotates in the direction of arrow 19 and is wound up by the winding roll 18. To be In FIG. 6 (A), the raw material powder 2 is deposited on the film 1 discharged from the delivery roll as the first step and the β-F of the first layer is heated by the heating roll 4.
The eSi 2 semiconductor film 22 is formed. Next, as a second step, in order to form a semiconductor junction surface, a raw material powder having a polarity different from that of the semiconductor film 22 is deposited and the second layer of β-FeS is heated by the heating roll 5.
The i 2 semiconductor film 32 is formed. The semiconductor film having the bonding film enters the next third step. That is, after being pressed by the electrode forming heating roller 6, the electrode pattern 71 in which a part of the film is metallized is formed. Further, the next step is connected to FIG. In the fourth step, the dielectric hydroxide raw material 41 is deposited by spraying and a reaction occurs while passing through the heating furnace 9 to form the light non-reflection protective film 42, and the functional portion main body of the device element is completed. . Further, these films are guided to the take-up roll 18 and are rotated in the direction of arrow 19, so that the film is taken up by the roll to complete the production process.
【００１４】[0014]
【発明の特徴と従来技術】従来のβ-FeSi2半導体を用い
たデバイス素子は、基板として半導体特性を持った単結
晶や多結晶のシリコン板を用いていた。又は基板として
焼結セラミクスやガラスをもちい、その上にアモスファ
スシリコンやIII―V化合物半導体を積層していた。それ
に対して、本特許の素子に用いる基板材料としては、可
撓性のあるステンレススチールなどの金属板や、廉価で
耐熱性のあるポリイミドシートである。これらの材料は
シリコン基板に較べると、大変廉価である。また十分に
大面積が取れるし、長尺ものが得られるので巻き取った
ロール形態を用いて連続加工することができる。単結晶
や無機物焼結体などのように、大きさの制限を受けるこ
とが無い。また、大面積の素子を構成して取り付け加工
をする場合に、可撓性があるので破損することが無く、
工作しやすい。Features and Prior Art A conventional device element using a β-FeSi 2 semiconductor uses a single crystal or polycrystalline silicon plate having semiconductor characteristics as a substrate. Alternatively, sintered ceramics or glass is used as a substrate, and amosphas silicon or III-V compound semiconductor is laminated thereon. On the other hand, the substrate material used in the device of the present patent is a flexible metal plate such as stainless steel or a cheap and heat-resistant polyimide sheet. These materials are much cheaper than silicon substrates. Moreover, since a sufficiently large area can be obtained and a long product can be obtained, continuous processing can be performed using a rolled roll form. There is no size restriction like single crystals or inorganic sintered bodies. In addition, when a device having a large area is formed and mounting is performed, since it has flexibility, it is not damaged,
Easy to work with.
【００１５】基板材料として金属薄板を用いた場合に
は、可撓性や廉価の特長のほかに、薄板自体が下地基板
側の電極を兼用するという特徴も有する。一方、基板材
料として直接ポリイミドなど有機絶縁材料を用いた場合
には、基板１の上に、あらかじめ表面に金やアルミニウ
ム箔などを蒸着したフィルムを用いたり、β-FeSi2半導
体膜に熱加工を加えて、部分的に金属層変化させた部分
を電極としたものを用いる。この金属膜を敷いたフィル
ムは、蒸着法により装飾フィルムとして多量に安価入手
できる。When a metal thin plate is used as the substrate material, in addition to the advantages of flexibility and low price, the thin plate itself also serves as an electrode on the side of the base substrate. On the other hand, when an organic insulating material such as polyimide is directly used as the substrate material, a film on which gold or aluminum foil has been vapor-deposited on the surface is used on the substrate 1, or the β-FeSi 2 semiconductor film is heat-processed. In addition, an electrode in which a portion where the metal layer is partially changed is used is used. A large amount of the film provided with the metal film can be obtained as a decorative film at a low cost by a vapor deposition method.
【００１６】本特許のもう一方の特徴は、その製造プロ
セスにある。請求項４以降の製膜方法、電極形成方法、
保護膜形成法、一貫生産プロセスラインとも、真空系を
使わず日常工場の環境で連続作業生産ができるのが特徴
である。これはベース基板に可撓性のある材料を用い、
生産加工工程も日常使用されているような容易で使い古
された技術だけで成り立っているからである。従来の半
導体素子生産のように、単結晶板やセラミクス基板を用
いたのでは、フィルムを流すような生産方式は採用が難
しい。ベースフィルムをロールから送り出し、出来上が
る製品をロールに巻き取るプロセスを採用できることに
より、スループットも上がり製造装置の管理コストも低
減できる特徴をもつ。Another feature of this patent lies in its manufacturing process. A film forming method and an electrode forming method according to claim 4,
Both the protective film forming method and the integrated production process line are characterized in that continuous work production can be performed in the environment of a daily factory without using a vacuum system. This uses a flexible material for the base substrate,
This is because the production and processing steps are made up of only easy and worn-out techniques that are used on a daily basis. If a single crystal plate or a ceramic substrate is used as in the conventional semiconductor device production, it is difficult to adopt a production method in which a film is flown. By adopting a process in which the base film is sent out from a roll and the finished product is wound up on a roll, the throughput is increased and the management cost of manufacturing equipment can be reduced.
【００１７】[0017]
【発明の効果】本発明では、デバイスを構成する基板を
可撓性のある材料を用いたので、ロールからの送り出し
巻取りが可能となり、デバイスを構成する部品作成プロ
セスが空気中で連続生産可能な方式になったので、全て
の作製プロセスが一貫して連続生産できるようになり、
結果として製品の製作コストを大幅に低減できるように
なった。According to the present invention, since the substrate forming the device is made of a flexible material, it can be fed out from the roll and wound, and the parts forming process of the device can be continuously produced in air. Since it became a system, all the manufacturing processes can be consistently produced continuously,
As a result, it has become possible to significantly reduce the manufacturing cost of the product.
【図１】本発明に従う可撓性を持つ基板上にβ-FeSi2半
導体を用いたデバイス素子の構成模式図。FIG. 1 is a schematic configuration diagram of a device element using a β-FeSi 2 semiconductor on a flexible substrate according to the present invention.
【図２】本発明の可撓性を持つ基板上に第1層のβ-FeSi
2薄膜を作る工程の模式図。FIG. 2 shows the first layer of β-FeSi on the flexible substrate of the present invention.
2 Schematic diagram of the process of making a thin film.
【図３】本発明の可撓性を持つ基板上に第２層のβ-FeS
i2薄膜を作り、接合面を作る工程の模式図。FIG. 3 is the second layer of β-FeS on the flexible substrate of the present invention.
Schematic diagram of the process of making the i 2 thin film and making the joint surface.
【図４】本発明の可撓性を持つ基板上に作製されたβ-F
eSi2半導体薄膜上に、デバイス電極パターンを作る工程
の模式図。FIG. 4 β-F fabricated on a flexible substrate of the present invention
Schematic diagram of the process of forming a device electrode pattern on an eSi 2 semiconductor thin film.
【図５】本発明の可撓性を持つ基板上に出来上がったデ
バイス上に、光無反射保護膜を作る工程の模式図。FIG. 5 is a schematic view of a process of forming a light non-reflection protective film on a device completed on a flexible substrate of the present invention.
【図６】本発明の可撓性を持つ基板上に、半導体膜製
作、接合面製作、電極製作、光無反射保護膜製作の各プ
ロセスを一貫し、デバイスを連続ラインで作る工程の模
式図。FIG. 6 is a schematic diagram of a process of making a device in a continuous line by integrating each process of semiconductor film production, bonding surface production, electrode production, and light non-reflection protective film production on a flexible substrate of the present invention. .
１・・・・可撓性基板 １１・・・・金属薄膜 １５・・・・送り出しローラ １６・・・・ローラの回転方向 １７・・・・基板シートの流れる方向 １８・・・・巻取りローラ １９・・・・ローラの回転方向 ２・・・・第1の半導体の粉体堆積層 ２１・・・・原料粉末 ２２・・・・第1の半導体薄膜 ２３・・・・ｐ／ｎ接合面 ３・・・・第2の半導体の粉末堆積層 ３１・・・・原料粉末 ３２・・・・第２の半導体薄膜 ４・・・・光無反射保護膜の粉体堆積層 ４１・・・・原料粉末 ４２・・・・光無反射保護膜 ４３・・・・スプレーガン ５・・・・加熱ローラ ５１・・・・加熱ローラの回転方向 ６・・・・電極形成ローラ ６１・・・・電極形成ローラの回転方向 ７・・・・電極突起彫刻 ７１・・・・電極パターン ８・・・・保護膜が剥ぎ取られた部分 ８１・・・・リード線 ８２・・・・出力測定器 ９・・・・連続加熱炉 1 ... Flexible substrate 11 ... Metal thin film 15 ... Delivery roller 16 ... Roller rotation direction 17 .... Flow direction of substrate sheet 18 ... Winding roller 19 ... Roller rotation direction 2 ... Powder deposition layer of the first semiconductor 21 ... Raw powder 22 ... First semiconductor thin film 23 ... P / n junction surface 3 ... Powder deposition layer of second semiconductor 31 ··· Raw powder 32 ... Second semiconductor thin film 4 ... Powder deposition layer of light non-reflective protective film 41 ... Raw powder 42 ... Light-reflective protective film 43 ... Spray gun 5 ... Heating roller 51 ... ・ Rotation direction of heating roller 6 ... Electrode forming roller 61 .... Rotation direction of electrode forming roller 7 .... Engraving of electrode protrusions 71 ... Electrode pattern 8 ... The part where the protective film is stripped off 81 ... Lead wire 82 ... Output measuring instrument 9 ... Continuous heating furnace
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 35/34 Ｈ０１Ｌ 31/04 Ｅ (72)発明者 中山 靖彦 神奈川県川崎市宮前区けやき平１−41− 103 (72)発明者 劉 正新 茨城県つくば市竹園三丁目24番の１ 512 棟406号 Ｆターム(参考） 5F051 AA03 AA07 BA14 CB13 CB24 CB27 DA03 FA06 GA02 GA05─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 7 Identification code FI theme code (reference) H01L 35/34 H01L 31/04 E (72) Inventor Yasuhiko Nakayama 1-41 Keyakidaira, Miyamae-ku, Kawasaki-shi, Kanagawa 103 (72) Inventor, Mr. Liu, Xin Xin, 1 512 Building No. 406, 3-24-3 Takezono, Tsukuba City, Ibaraki Prefecture 406 F term (reference) 5F051 AA03 AA07 BA14 CB13 CB24 CB27 DA03 FA06 GA02 GA05
Claims (8)
つ２種類のβ-FeSi2半導体薄膜からなる接合素子を構成
し、該接合薄膜素子の一部をα-Fe2Si5金属膜化して電
極とし、さらにその表面に表面保護層として透明誘電体
膜を設けてデバイス機能を持ったシート型β-FeSi2素
子。1. A junction element comprising two types of β-FeSi 2 semiconductor thin films having p-type and n-type characteristics on a flexible sheet, and a part of the junction thin-film element is α-Fe 2 Si 5 A sheet-type β-FeSi 2 device with a device function by forming a metal film into an electrode and then providing a transparent dielectric film on the surface as a surface protection layer.
単体またはそれらの合金、またはそれらを主成分として
1種類以上の添加元素を含んだ合金からなる金属薄板を
用いる請求項１記載のシート型β-FeSi2素子。2. A flexible sheet comprising iron, nickel, copper alone or an alloy thereof, or containing them as a main component.
The sheet type β-FeSi 2 device according to claim 1, wherein a thin metal plate made of an alloy containing one or more kinds of additional elements is used.
ッ素樹脂フィルムを用いる請求項１記載のシート型β-F
eSi2素子。3. The sheet type β-F according to claim 1, wherein a polyimide or fluororesin film is used as the flexible sheet.
eSi 2 device.
１：２となるFeとSiに不純物を添加して溶解・固化・粉
砕して微粉にしたものを、スプレー法または印刷塗布法
で塗布乾燥して一様の厚みに堆積し、それを５００〜９
８０℃の温度に加熱反応させてβ-FeSi2半導体薄膜を形
成する。さらにその上に先の半導体膜とは反対の特性を
示す不純物を添加した、原材料原子比率が略１：２とな
るFeとSiを溶解・固化・粉砕して微粉にしたものを、ス
プレー法または印刷塗布法でシート上に一様の厚みで堆
積し、それを５００〜９８０℃に加熱反応させてβ-FeS
i2半導体薄膜を形成し、最終的にｐ−ｎ接合界面を構成
したβ−FeSi2半導体薄膜を形成する方法。4. A spray method or a print coating method, which is obtained by adding impurities to Fe and Si having a raw material atomic ratio of about 1: 2, dissolving, solidifying, and pulverizing them into a fine powder on a flexible sheet. Coating and drying to deposit a uniform thickness,
A β-FeSi 2 semiconductor thin film is formed by heating and reacting at a temperature of 80 ° C. Further, an impurity exhibiting the opposite characteristics to the semiconductor film is added thereto, and Fe and Si having a raw material atomic ratio of about 1: 2 are dissolved, solidified, and pulverized into a fine powder, which is then sprayed or It is deposited with a uniform thickness on the sheet by the printing coating method, and it is heated to 500 to 980 ° C to react with β-FeS.
A method of forming an i 2 semiconductor thin film and finally forming a β-FeSi 2 semiconductor thin film having a pn junction interface.
らなる混合粉を、β-FeSi2相に反応形成する手法とし
て、５００〜９８０℃の高温に過熱した熱ローラをシー
ト上に堆積した粉末層に非酸化雰囲気中で押圧し、この
手法によってｐ−ｎ接合界面を持った半導体薄膜を連続
熱処理製膜する請求項４記載の製膜装置。5. A heat roller heated to a high temperature of 500 to 980 ° C. is formed on a sheet as a method for reacting and forming a mixed powder composed of Fe and Si components deposited on a flexible sheet into a β-FeSi 2 phase. The film forming apparatus according to claim 4, wherein the deposited powder layer is pressed in a non-oxidizing atmosphere, and a semiconductor thin film having a pn junction interface is continuously heat-treated by this method.
された金属又はセラミクスローラが加熱されており、こ
のローラをβ-FeSi2半導体膜が形成されて連続走行する
フィルム上に押圧することによって、ローラに触れた部
分を電極化する請求項１記載の電極製造装置。6. A metal or ceramics roller engraved in a pattern shape to be an electrode later is heated, and the roller is pressed against a film on which a β-FeSi 2 semiconductor film is formed and which runs continuously. 2. The electrode manufacturing apparatus according to claim 1, wherein the portion touching the roller is made into an electrode.
機物の水酸塩や硝酸塩を溶媒で希釈したインクをスプレ
ー法又は塗布印刷法によって、連続走行する可撓性シー
ト上に形成されたβ-FeSi2半導体素子表面に極薄く堆積
し、その後連続焼成炉やフラッシュランプ加熱光下を通
過させたり、または高温に加熱した熱ローラを押圧する
ことによって透明誘電体薄膜を形成し無反射光保護膜と
なす請求項1記載のシート型β-FeSi2素子作成方法。7. A β-FeSi formed on a continuously running flexible sheet by spraying or coating printing an ink prepared by diluting a hydroxide or nitrate of an inorganic substance such as silicon, tin, zinc or zirconia with a solvent. 2 A very thin layer is deposited on the surface of the semiconductor device, and then it is passed through a continuous firing furnace or under the flash lamp heating light, or by pressing a hot roller heated to a high temperature, a transparent dielectric thin film is formed to form an anti-reflection light protective film. A method for producing a sheet-type β-FeSi 2 element according to claim 1.
ート上に、p型又はｎ型特性を持つ粉末を堆積する工程
と、シートの流れる先で堆積した粉末層に加熱ローラを
押圧しながら連続的にβ-FeSi2半導体薄膜を形成する工
程と、更にシートの流れる先にパターンが刻印できる加
熱ローラによって、該半導体薄膜の一部を金属α-Fe2Si
5化して電極とする工程と、更にシートの流れる先にゾ
ルーゲル薄層を敷き熱ローラ又は加熱炉の中を通過させ
ることによって透明誘電体膜を作製する工程を設けて、
これらプロセスを一貫して連続的に流してデバイスを製
造するシート型β-FeSi2素子製造装置。8. A step of depositing powder having p-type or n-type characteristics on a flexible sheet delivered from a winding roll, and pressing a heating roller against the powder layer deposited at the destination of the sheet flow. A step of continuously forming a β-FeSi 2 semiconductor thin film and a heating roller capable of engraving a pattern at the sheet flowing point further cause a part of the semiconductor thin film to be a metal α-Fe 2 Si
A step of the 5 turned into the electrode, a step of preparing a transparent dielectric film by causing further pass through the previously sol-gel thin layer spread heat roller or a heating furnace of flow of the sheet is provided,
Sheet-type β-FeSi 2 device manufacturing equipment that manufactures devices by consistently and continuously flowing these processes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002057519A JP4140247B2 (en) | 2002-03-04 | 2002-03-04 | Sheet type β-FeSi2 element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002057519A JP4140247B2 (en) | 2002-03-04 | 2002-03-04 | Sheet type β-FeSi2 element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003258321A true JP2003258321A (en) | 2003-09-12 |
| JP4140247B2 JP4140247B2 (en) | 2008-08-27 |
Family
ID=28667756
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002057519A Expired - Fee Related JP4140247B2 (en) | 2002-03-04 | 2002-03-04 | Sheet type β-FeSi2 element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4140247B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6943388B1 (en) | 2004-03-18 | 2005-09-13 | National Institute Of Advanced Industrial Science And Technology | Sheet-type β-FeSi2 element, and method and device for manufacturing the same |
| JP5761172B2 (en) * | 2010-02-25 | 2015-08-12 | 産機電業株式会社 | Method for producing solar cell using silicon powder |
-
2002
- 2002-03-04 JP JP2002057519A patent/JP4140247B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6943388B1 (en) | 2004-03-18 | 2005-09-13 | National Institute Of Advanced Industrial Science And Technology | Sheet-type β-FeSi2 element, and method and device for manufacturing the same |
| JP5761172B2 (en) * | 2010-02-25 | 2015-08-12 | 産機電業株式会社 | Method for producing solar cell using silicon powder |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4140247B2 (en) | 2008-08-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6127619A (en) | Process for producing high performance thermoelectric modules | |
| US4135290A (en) | Method for fabricating solar cells having integrated collector grids | |
| US6051778A (en) | Electrode structure, process production thereof and photo-electricity generating device including the electrode | |
| US8759144B2 (en) | Fabrication of contacts for silicon solar cells including printing burn through layers | |
| CN100570903C (en) | Integrated thin-film solar cell, method for manufacturing same, method for processing transparent electrode of integrated thin-film solar cell, structure of integrated thin-film solar cell, and transparent substrate having processed transparent electrode | |
| US20100300525A1 (en) | Integrated thin-film solar cell and manufacturing method thereof | |
| EP0654831A2 (en) | Method of manufacturing solar cell | |
| US7317159B2 (en) | Thermoelectric conversion element and method of manufacturing the same, and thermoelectric conversion device using the element | |
| US20190181323A1 (en) | Flexible thermoelectric module | |
| CN1983568A (en) | Integrated thin film solar cell and manufacturing method thereof | |
| US20190181321A1 (en) | Flexible thermoelectric module | |
| Singh et al. | High performance perovskite solar cell via multi-cycle low temperature processing of lead acetate precursor solutions | |
| JP2010518619A (en) | Electronic semiconductor devices based on copper-nickel and gallium-tin-zinc-copper-titanium p-type and n-type oxides, peripheral devices and manufacturing processes thereof | |
| JP3681870B2 (en) | Method for producing compound semiconductor film and solar cell | |
| Liu et al. | A flexible thermoelectric film based on Bi2Te3 for wearable applications | |
| US20180159015A1 (en) | Flexible encapsulation of a flexible thin-film based thermoelectric device with sputter deposited layer of n-type and p-type thermoelectric legs | |
| US10566515B2 (en) | Extended area of sputter deposited N-type and P-type thermoelectric legs in a flexible thin-film based thermoelectric device | |
| US6943388B1 (en) | Sheet-type β-FeSi2 element, and method and device for manufacturing the same | |
| Werner et al. | From Thermoelectric Powder directly to Thermoelectric generators: flexible Bi2Te3 films on Polymer sheets prepared by the Powder Aerosol Deposition Method at Room temperature | |
| JP2003258321A (en) | Sheet type β-FeSi2 element | |
| TW201330290A (en) | Film deposition from a flat ribbon release material by external induction | |
| KR102296386B1 (en) | The method for preparation of transparent thermoelectric materials and transparent and flexible thermoelectric generators using the same | |
| KR20130116689A (en) | Synthesis of antimony telluride (sb-te) paste and p-type thermoelectric material forming method using paste | |
| JPS63102382A (en) | Manufacture and construction of thin film thermoelectric transducer module | |
| US10367131B2 (en) | Extended area of sputter deposited n-type and p-type thermoelectric legs in a flexible thin-film based thermoelectric device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20050223 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20071002 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20071016 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20071213 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20080115 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20080214 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20080218 |
|
| A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20080418 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20080513 |
|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20080602 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110620 Year of fee payment: 3 |
|
| R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110620 Year of fee payment: 3 |
|
| S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313532 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110620 Year of fee payment: 3 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| LAPS | Cancellation because of no payment of annual fees |