JP2003258103A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

[PROBLEMS] To improve the thickness accuracy of an insulating film on a fuse provided in a semiconductor device. SOLUTION: BPSG on polycrystalline silicon fuse 3 is provided.
On the film 5, an etch stop layer 6 'made of the first Al film 6
Is formed, and when the interlayer insulating film 9, the SOG film 8 and the interlayer insulating film 7 are etched, the etching of the interlayer insulating film 9, the SOG film 8 and the interlayer insulating film 7 is performed by the etch stop layer 6 '.
To stop.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and is particularly suitable for application to a trimming fuse.

[0002]

2. Description of the Related Art Some conventional semiconductor devices have trimming fuses for adjusting the characteristics of the semiconductor device. FIG. 6A is a plan view showing a schematic configuration of a fuse portion of a conventional semiconductor device, and FIG.
It is sectional drawing cut | disconnected by the AA line of (a).

In FIG. 6, a field oxide film 42 is formed on a semiconductor substrate 41, and the field oxide film 42 is formed.
Above the polycrystalline silicon fuse 4 connected to the wiring layer
3 is formed. Then, an oxide film 44, a BPSG film 45, an interlayer insulating film 47, an SOG film 48 and an interlayer insulating film 49 are sequentially formed on the polycrystalline silicon fuse 43, and an opening from the interlayer insulating film 49 to the BPSG film 45 is formed. The part 50 is formed.

FIG. 7 is a sectional view showing a conventional method of manufacturing a fuse portion of a semiconductor device. In FIG. 7A, L
The field oxide film 42 is formed on the semiconductor substrate 41 by the OCOS method or the like. Next, as shown in FIG. 7B, a polycrystalline silicon film is laminated on the semiconductor substrate 41 on which the field oxide film 42 is formed by a CVD method or the like,
By patterning the polycrystalline silicon film using the photolithography technique and the etching technique, the polycrystalline silicon fuse 43 connected to the wiring layer is formed.

Next, as shown in FIG. 7C, after the oxide film 44 and the BPSG film 45 are stacked by the CVD method or the like, the oxide film 44 and the BPSG film are formed by using the photolithography technique and the etching technique. 45
Forming a contact hole. Then, a BP with a contact hole formed by sputtering or vapor deposition
An Al film is laminated on the SG film 45, and the Al film is patterned by using a photolithography technique and an etching technique to form a lower Al wiring layer.

Further, an interlayer insulating film 47 is formed on the BPSG film 45 on which the lower Al wiring layer is formed by a CVD method or the like, and then an SOG film 48 is formed on the interlayer insulating film 47 to form an interlayer insulating film. The film 47 is flattened. Then, after depositing the interlayer insulating film 49 by the CVD method or the like, a via hole is formed in the interlayer insulating film 47, the SOG film 48 and the interlayer insulating film 49 by using the photolithography technique and the etching technique.

Then, by sputtering or vapor deposition,
An Al film is laminated on the interlayer insulating film 49 in which the via hole is formed, and the Al film is patterned by using the photolithography technique and the etching technique.
forming a wiring layer. Next, as shown in FIG.
By patterning the interlayer insulating film 49, the SOG film 48, the interlayer insulating film 47, and the BPSG film 45 by using the photolithography technique and the etching technique, the opening 50 from the interlayer insulating film 49 to the BPSG film 45 is formed.

When the polycrystalline silicon fuse 43 is cut, an electric current is caused to flow through the wiring layer connected to the polycrystalline silicon fuse 43 to rupture the oxide film 44 and the BPSG film 45 on the polycrystalline silicon fuse 43. By doing so, the polycrystalline silicon fuse 43 is blown.

[0009]

However, in the conventional semiconductor device, the wiring layer is also laminated as the semiconductor device is highly integrated, and the oxide film 44, the BPSG film 45, the interlayer insulating film 47, and the SOG film 48 are formed. Insulating films such as the interlayer insulating film 49 are laminated on the polycrystalline silicon fuse 43 in many layers.

As a result, the depth of the opening 50 formed on the polycrystalline silicon fuse 43 becomes deep, and the oxide film 4 is formed.
4, an insulating film left on the polycrystalline silicon fuse 43 due to variations in thickness of each layer such as the BPSG film 45, the interlayer insulating film 47, the SOG film 48, and the interlayer insulating film 49, and variations in etching rate. Variation in thickness becomes large.

Therefore, in the conventional semiconductor device, the polycrystalline silicon fuse 4 is associated with the low voltage operation of the semiconductor device.
If the voltage applied when the fuse 3 is blown becomes low, the polycrystalline silicon fuse 43 cannot be blown. On the other hand, if the film thickness of the insulating film left on the polycrystalline silicon fuse 43 is made too thin in order to facilitate the melting of the polycrystalline silicon fuse 43, the polycrystalline silicon fuse 43 is exposed and the polycrystalline silicon fuse 43 is exposed. There is a problem that 43 is corroded and the reliability of the semiconductor device is deteriorated.

Therefore, an object of the present invention is to provide a semiconductor device capable of improving the accuracy of the remaining thickness of an insulating film on a fuse and a method of manufacturing the same.

[0013]

In order to solve the above problems, according to the semiconductor device of claim 1, a part of the lowermost layer wiring of the multilayer wiring structure is formed in the insulating film on the fuse. It is characterized in that it is used as an etch stop layer for the opening. As a result, the selection ratio between the insulating film on the fuse and the etch stop layer can be improved simply by changing the mask when patterning the lowermost layer wiring, and while suppressing the complexity of the manufacturing process, It is possible to improve the accuracy of the remaining thickness when etching the upper insulating film.

Therefore, even when a plurality of insulating films are laminated on the fuse, the insulating film on the fuse can be accurately etched to a predetermined depth, and the fuse can be applied even when the voltage that can be applied to the fuse is low. It is possible to stably blow out. According to the method of manufacturing a semiconductor device of claim 2, a step of forming a fuse on the first insulating layer, a step of forming a second insulating layer on the fuse, and a step of forming a fuse on the second insulating layer. By forming a first conductive film and patterning the first conductive film, a first wiring layer is formed on the second insulating layer and an etch stop layer corresponding to the position where the fuse is arranged is formed. And a step of forming a third insulating layer on the second insulating layer on which the first wiring layer and the etch stop layer are formed, and an opening corresponding to a position where the fuse is arranged is formed on the third insulating layer. Forming a second conductive film on the third insulating layer, and patterning the second conductive film to form a second wiring layer on the third insulating layer, At the location of the fuse Characterized in that it comprises a step of removing the etch stop layer formed by response.

This makes it possible to form the etch stop layer between the insulating films on the fuse and to etch the third insulating layer on the fuse simply by changing the mask when patterning the lowermost layer wiring. Since it is possible to accurately stop the etching stop layer, it is possible to improve the residual thickness accuracy when etching the insulating film on the fuse even when the insulating film is laminated in multiple layers on the fuse. .

Further, it is possible to collectively form an opening in the insulating film on the fuse and a via hole for making an interlayer connection, and also to form an etch stop layer formed on the fuse. The removal and patterning of the upper wiring layer can be performed at one time, and even when the etch stop layer is formed between the insulating films on the fuse, the complexity of the manufacturing process is suppressed and the throughput is deteriorated. Can be suppressed.

According to the method of manufacturing a semiconductor device of the third aspect, a step of forming a second insulating layer on the fuse, a step of forming a first conductive film on the second insulating layer, Patterning the first conductive film to form a first wiring layer on the second insulating layer and an etch stop layer corresponding to a position where the fuse is arranged; Forming a third insulating layer on the second insulating layer having an etch stop layer formed thereon, forming a second conductive film on the third insulating layer, and patterning the second conductive film. The steps of forming a second wiring layer on the third insulating layer, forming a protective film on the third insulating layer on which the second wiring layer is formed, and corresponding to the positions of the fuses The opening
The method is characterized by including a step of forming the protective film and the third insulating layer, and a step of removing the etch stop layer formed corresponding to the position where the fuse is arranged.

Thus, the etch stop layer can be formed between the insulating films on the fuses only by changing the mask when patterning the lowermost wiring, and the protective film is formed on the upper wiring layer. Even in this case, the accuracy of the remaining thickness when forming the opening in the insulating film on the fuse can be improved. Further, according to the method of manufacturing a semiconductor device of claim 4, the opening is formed inside the etch stop layer.

As a result, even when the arrangement position varies in the opening due to variations in mask alignment, etc.
Since the opening is always arranged on the etch stop layer, the accuracy of the remaining thickness when etching the insulating film on the fuse can be improved. Further, according to the method of manufacturing a semiconductor device of claim 5, a step of forming a field oxide film on a semiconductor substrate, a step of laminating a polycrystalline silicon layer on the field oxide film, and the polycrystalline silicon layer. Forming a fuse on the field oxide film by patterning, a step of stacking a first interlayer insulating film on the field oxide film having the fuse formed thereon, and a step of forming a first interlayer insulating film on the first interlayer insulating film. Forming a 1Al film, and forming a first Al wiring layer on the first interlayer insulating film by patterning the first Al film, and forming an etch stop layer corresponding to the position of the fuse. A step of forming a second interlayer insulating film on the first interlayer insulating film on which the first Al wiring layer and the etch stop layer are formed; A step of forming a planarization film on the edge film, a step of forming a third interlayer insulation film on the planarization film, and an opening corresponding to the position of the fuse, the third interlayer insulation film, On the third interlayer insulating layer, a step of forming a planarizing film and the second interlayer insulating film, a step of forming a second Al film on the third interlayer insulating film, and a step of patterning the second Al film. And forming a second Al wiring layer, and removing the etch stop layer formed corresponding to the position where the fuse is arranged.

As a result, the etch stop layer can be formed on the first interlayer insulating film on the polycrystalline silicon fuse only by changing the mask when patterning the first Al film, and the etch stop layer on the etch stop layer can be formed. The third interlayer insulating film, the planarizing film and the second interlayer insulating film can be removed accurately. Therefore, even when the third interlayer insulating film, the planarizing film, and the second interlayer insulating film are stacked on the polycrystalline silicon fuse, only the first interlayer insulating film can be left on the polycrystalline silicon fuse. Since the thickness of the insulating film on the polycrystalline silicon fuse can be defined only by the first interlayer insulating film, the accuracy of the remaining thickness of the insulating film remaining on the polycrystalline silicon fuse can be improved.

According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a step of stacking a polycrystalline silicon layer on the field oxide film and a step of patterning the polycrystalline silicon layer are used to form the field oxide film. Forming a fuse thereon, stacking a first interlayer insulating film on the field oxide film having the fuse formed thereon, forming a first Al film on the first interlayer insulating film, Forming a first Al wiring layer on the first interlayer insulating film by patterning the 1Al film and forming an etch stop layer corresponding to the position of the fuse; the first Al wiring layer and the etch stop; Forming a second interlayer insulating film on the first interlayer insulating film having a layer formed thereon, and forming a planarizing film on the second interlayer insulating film, The step of forming a third interlayer insulating film on the flattening film, the step of forming a second Al film on the third interlayer insulating film, and the patterning of the second Al film to form the third interlayer insulating layer. Forming a second Al wiring layer thereon, forming a protective film on the third interlayer insulating layer on which the second Al wiring layer is formed, and forming an opening corresponding to the position of the fuse with the protective film. A film, the third interlayer insulating film, the planarizing film, and the second interlayer insulating film, and a step of removing the etch stop layer formed corresponding to the position where the fuse is arranged. Characterize.

This makes it possible to form an etch stop layer on the first interlayer insulating film on the polycrystalline silicon fuse only by changing the mask when patterning the first Al film, and on the second Al wiring layer. Even when the protective film is formed on the substrate, the protective film, the third interlayer insulating film, the planarizing film and the second interlayer insulating film on the etch stop layer can be accurately removed.

Therefore, even when the protective film, the third interlayer insulating film, the planarizing film and the second interlayer insulating film are laminated on the polycrystalline silicon fuse, only the first interlayer insulating film is formed on the polycrystalline silicon fuse. It becomes possible to protect the upper layer wiring while improving the accuracy of the remaining thickness of the insulating film remaining on the polycrystalline silicon fuse.

[0024]

DETAILED DESCRIPTION OF THE INVENTION A semiconductor device and a method of manufacturing the same according to embodiments of the present invention will be described below with reference to the drawings. 1 to 3 are cross-sectional views showing a method for manufacturing a fuse portion of a semiconductor device according to the first embodiment of the present invention.

In FIG. 1A, the field oxide film 2 is formed on the semiconductor substrate 1 by the LOCOS method or the like. Next, as shown in FIG. 1B, a polycrystalline silicon film is laminated on the semiconductor substrate 1 on which the field oxide film 2 is formed by the CVD method or the like, and the polycrystalline silicon film is formed by using the photolithography technique and the etching technique. By patterning the silicon film, the polycrystalline silicon fuse 3 connected to the wiring layer is formed.

Next, as shown in FIG. 1C, after the oxide film 4 and the BPSG film 5 are stacked by the CVD method or the like, the thermal oxide film 4 and the BPSG film are formed by using the photolithography technique and the etching technique. A contact hole is formed in the film 5. Then, BPSG in which a contact hole is formed by sputtering or vapor deposition
A first Al film 6 is laminated on the film 5.

Next, as shown in FIG. 1 (d), the first A
By patterning the I film 6, a first Al wiring layer is formed and an etch stop layer 6'is formed. The etch stop layer 6 ′ is preferably formed so as to extend outside the opening 11, so that even if the position of the opening 11 varies, the position of the opening 11 can be changed. It is possible to prevent the protrusion from above 6'and to stably perform the etch stop.

Next, as shown in FIG. 2A, the first Al wiring layer and the etch stop layer 6 are formed by the CVD method or the like.
After the interlayer insulating film 7 is laminated on the BPSG film 5 having the ′ formed thereon, the SOG film 8 is formed on the interlayer insulating film 7 to flatten the interlayer insulating film 7. Then, after depositing the interlayer insulating film 9 by the CVD method or the like, as shown in FIG. 2B, the recess 10 is formed in the interlayer insulating film 9 on the polycrystalline silicon fuse 3 by using the photolithography technique and the etching technique. Is formed, the step difference of the interlayer insulating film 9 on the polycrystalline silicon fuse 3 is reduced.

Next, as shown in FIG. 2C, the inter-layer insulating film 9, the SOG film 8 and the inter-layer insulating film 7 are patterned by using the photolithography technique and the etching technique, whereby the inter-layer insulating film 9, A via hole is formed in the SOG film 8 and the interlayer insulating film 7, and an opening 11 is formed in the polycrystalline silicon fuse 3. here,
Since the etch stop layer 6 ′ made of the first Al film 6 is formed on the BPSG film 5 on the polycrystalline silicon fuse 3, when the interlayer insulating film 9, the SOG film 8 and the interlayer insulating film 7 are etched, The etching of the interlayer insulating film 9, the SOG film 8 and the interlayer insulating film 7 is performed as an etch stop layer 6 '.
Can be stopped accurately.

Therefore, when the interlayer insulating film 9, the SOG film 8 and the interlayer insulating film 7 are etched, it is possible to prevent the BPSG film 5 on the polycrystalline silicon fuse 3 from being overetched, and the polycrystalline silicon fuse 3 can be prevented. Silicon fuse 3
The remaining thickness of the upper insulating film can be defined by the thicknesses of the oxide film 4 and the BPSG film 5. As a result, even when the interlayer insulating film 7, the SOG film 8 and the interlayer insulating film 9 are stacked on the polycrystalline silicon fuse 3, the accuracy of the remaining thickness of the insulating film on the polycrystalline silicon fuse 3 can be improved. Even if the voltage that can be applied to the polycrystalline silicon fuse 3 is low, the polycrystalline silicon fuse 3 can be stably blown.

By forming the opening 11 on the polycrystalline silicon fuse 3 together with the via hole, it is necessary to add an additional step for forming the opening 11 on the polycrystalline silicon fuse 3. Can be prevented, and an increase in the number of manufacturing steps can be prevented. Next, as shown in FIG. 3A, a second layer is formed on the interlayer insulating film 9 in which the via hole and the opening 11 are formed by sputtering or vapor deposition.
The Al film 12 is laminated.

Next, as shown in FIG. 3B, the photoresist film 13 corresponding to the second Al wiring layer 12 'is formed by using the photolithography technique.
Form on 2. Next, as shown in FIG. 3C, anisotropic etching such as RIE is performed using the photoresist film 13 as a mask to form the second Al wiring layer 12 ′ and to etch the inside of the opening 11. Stop layer 6
Remove ´.

By removing the etch stop layer 6'in the opening 11 together with the formation of the second Al wiring layer 12 ', the etch stop layer 6'in the opening 11 is removed. It is not necessary to add additional steps, and it is possible to prevent an increase in manufacturing steps. When the polycrystalline silicon fuse 3 is cut, a current is passed through the wiring layer connected to the polycrystalline silicon fuse 3,
Oxide film 4 and BPSG on polycrystalline silicon fuse 3
The polycrystalline silicon fuse 3 is blown by rupturing the film 5.

In the example of FIG. 3C, since the etch stop layer 6'is formed so as to protrude outside the opening 11, the protruding portion of the etch stop layer 6'is not etched. , Remain on the BPSG film 5.
4 and 5 are cross-sectional views showing the method of manufacturing the fuse portion of the semiconductor device according to the second embodiment of the present invention.

In FIG. 4A, a polycrystalline silicon fuse 23 is formed on the semiconductor substrate 21 on which the field oxide film 22 is formed by performing the same steps as those in FIGS. Furthermore, the polycrystalline silicon fuse 23
An oxide film 24 and a BPSG film 25 are sequentially laminated on the field oxide film 22 on which is formed. Then, after forming the etch stop layer 26 on the BPSG film 25 on the polycrystalline silicon fuse 23, the interlayer insulating film 27, the SOG film 28, and the interlayer insulating film 29 are formed on the BPSG film 25 on which the etch stop layer 26 is formed. Are sequentially laminated.

Then, the interlayer insulating film 29 and the SOG film 2 are formed by using the photolithography technique and the etching technique.
8 and the interlayer insulating film 27 are patterned to form the interlayer insulating film 29, the SOG film 28, and the interlayer insulating film 2.
After forming a via hole in 7, a second Al film 30 is laminated on the interlayer insulating film 29 in which the via hole is formed by sputtering or vapor deposition.

Next, as shown in FIG. 4B, a second photolithography technique and an etching technique are used.
By patterning the Al film 30, a second Al wiring layer 30 ′ is formed on the interlayer insulating film 29. Next, FIG.
As shown in (c), a protective film 31 such as a silicon nitride film is formed on the interlayer insulating film 29 on which the second Al wiring layer 30 'is formed by the CVD method or the like.

Next, as shown in FIG. 5A, the protective film 31, the interlayer insulating film 29, the SOG film 28, and the interlayer insulating film 27 are patterned by using the photolithography technique and the etching technique, and thereby, An opening 32 is formed on the crystalline silicon fuse 23. Here, since the etch stop layer 26 made of the first Al film is formed on the BPSG film 25 on the polycrystalline silicon fuse 23, the protective film 31, the interlayer insulating film 29, the SOG film 28, and the interlayer insulating film 27. Protective film 3 when etching
1, interlayer insulating film 29, SOG film 28 and interlayer insulating film 2
The etching of No. 7 can be stopped by the etch stop layer 26.

Therefore, the protective film 31, the interlayer insulating film 29,
When the SOG film 28 and the interlayer insulating film 27 are etched, the BPSG film 25 on the polycrystalline silicon fuse 23 can be prevented from being over-etched, and the remaining thickness of the insulating film on the polycrystalline silicon fuse 23 can be reduced. , The thickness of the oxide film 24 and the thickness of the BPSG film 25.

As a result, on the polycrystalline silicon fuse 23, the interlayer insulating film 27, the SOG film 28 and the interlayer insulating film 2 are formed.
In addition to 9, the protective film 31 may be further laminated to improve the accuracy of the remaining thickness of the insulating film on the polycrystalline silicon fuse 23.
Even if the voltage that can be applied to the low voltage is low, the polycrystalline silicon fuse 23 can be stably blown, and the second Al wiring layer 30 ′ can be protected by the protective film 31.

Next, as shown in FIG. 5B, the protective film 3
By using 1 as a mask, anisotropic etching such as RIE is performed to remove the etch stop layer 26 in the opening 32. When the polycrystalline silicon fuse 23 is cut, a current is passed through the wiring layer connected to the polycrystalline silicon fuse 23 to rupture the oxide film 24 and the BPSG film 25 on the polycrystalline silicon fuse 23. , The polycrystalline silicon fuse 23 is blown.

According to the above-described embodiment, the case where the wiring layer has a two-layer structure has been described as an example, but the wiring layer has three layers.
Also in the case of more layers, the first wiring layer may be used as an etch stop layer.

[0043]

As described above, according to the present invention,
By using a part of the lowermost layer wiring of the multilayer wiring structure as an etch stop layer when etching the insulating film on the fuse, it is possible to suppress the complication of the manufacturing process while etching the insulating film on the fuse. Since the accuracy of the remaining thickness can be improved, the fuse can be stably blown even when the voltage that can be applied to the fuse is low.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a method of manufacturing a fuse part of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the method of manufacturing the fuse portion of the semiconductor device according to the first embodiment of the invention.

FIG. 3 is a cross-sectional view showing the method of manufacturing the fuse part of the semiconductor device according to the first embodiment of the invention.

FIG. 4 is a cross-sectional view showing the method of manufacturing the fuse portion of the semiconductor device according to the second embodiment of the invention.

FIG. 5 is a cross-sectional view showing the method of manufacturing the fuse portion of the semiconductor device according to the second embodiment of the invention.

6A is a plan view showing a schematic configuration of a fuse portion of a conventional semiconductor device, and FIG. 6B is a sectional view taken along line AA of FIG. 6A. .

FIG. 7 is a cross-sectional view showing a method of manufacturing a fuse portion of a conventional semiconductor device.

[Explanation of symbols]

1, 21 Semiconductor substrate 2.22 field oxide film 3,23 Polycrystalline silicon fuse 4, 24 Oxide film 5,25 BPSG film 6 First Al film 6 ', 26 Etch stop layer 7, 27, 9, 29 Interlayer insulation film 8, 28 SOG film 10 recess 11,32 opening 12, 30 Second Al film 12 ', 30' Second Al wiring layer 31 Protective film

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5F004 AA02 DB00 EA23 EB03 EB08                 5F033 HH04 HH08 JJ01 JJ08 KK08                       PP06 PP15 PP19 QQ08 QQ10                       QQ24 QQ37 RR04 RR09 RR15                       SS11 VV11                 5F038 AV15 EZ11 EZ14 EZ15 EZ20                 5F064 EE22 EE33 FF26 FF27 FF30                       GG03

Claims (6)

[Claims] 1. A semiconductor device, wherein a part of a lowermost layer wiring of a multilayer wiring structure is used as an etch stop layer of an opening formed in an insulating film on a fuse. 2. A step of forming a fuse on the first insulating layer, a step of forming a second insulating layer on the fuse, a step of forming a first conductive film on the second insulating layer, Forming a first wiring layer on the second insulating layer by patterning the first conductive film, and forming an etch stop layer corresponding to the position where the fuse is arranged; and the first wiring layer and the etching. Forming a third insulating layer on the second insulating layer having a stop layer formed thereon; forming an opening in the third insulating layer, the opening corresponding to a position where the fuse is arranged; and the third insulating layer. A step of forming a second conductive film thereon, and patterning the second conductive film to form a second wiring layer on the third insulating layer and to form a second wiring layer corresponding to a position where the fuse is arranged. Etch stop The method of manufacturing a semiconductor device, characterized in that it comprises a step of removing the. 3. A step of forming a fuse on the first insulating layer, a step of forming a second insulating layer on the fuse, a step of forming a first conductive film on the second insulating layer, Forming a first wiring layer on the second insulating layer by patterning the first conductive film, and forming an etch stop layer corresponding to the position where the fuse is arranged; and the first wiring layer and the etching. By forming a third insulating layer on the second insulating layer having a stop layer formed thereon, forming a second conductive film on the third insulating layer, and patterning the second conductive film. A step of forming a second wiring layer on the third insulating layer, a step of forming a protective film on the third insulating layer on which the second wiring layer is formed, and an opening corresponding to an arrangement position of the fuse A part of the protective film and the third The method of manufacturing a semiconductor device characterized in that it comprises a step of forming the edge layer, and removing the etch stop layer which is formed corresponding to the positions of the fuse. 4. The semiconductor device according to claim 2, wherein the opening is formed inside the etch stop layer. 5. A step of forming a field oxide film on a semiconductor substrate, a step of laminating a polycrystalline silicon layer on the field oxide film, and a step of patterning the polycrystalline silicon layer,
Forming a fuse on the field oxide film; stacking a first interlayer insulating film on the field oxide film on which the fuse is formed; forming a first Al film on the first interlayer insulating film; And patterning the first Al film to form a first Al wiring layer on the first interlayer insulating film, and
Forming an etch stop layer corresponding to the location of the fuse; forming a second interlayer insulating film on the first interlayer insulating film having the first Al wiring layer and the etch stop layer formed thereon; A step of forming a planarization film on the second interlayer insulation film; a step of forming a third interlayer insulation film on the flattening film;
Forming an interlayer insulating film, the planarizing film, and the second interlayer insulating film; forming a second Al film on the third interlayer insulating film; and patterning the second Al film to form the second Al film. A second Al wiring layer is formed on the third interlayer insulating layer, and
And a step of removing the etch stop layer formed corresponding to the position where the fuse is arranged. 6. A step of forming a field oxide film on a semiconductor substrate, a step of laminating a polycrystalline silicon layer on the field oxide film, and a step of patterning the polycrystalline silicon layer,
Forming a fuse on the field oxide film; stacking a first interlayer insulating film on the field oxide film on which the fuse is formed; forming a first Al film on the first interlayer insulating film; And patterning the first Al film to form a first Al wiring layer on the first interlayer insulating film, and
Forming an etch stop layer corresponding to the location of the fuse; forming a second interlayer insulating film on the first interlayer insulating film having the first Al wiring layer and the etch stop layer formed thereon; Forming a flattening film on the second interlayer insulating film; forming a third interlayer insulating film on the flattening film; forming a second Al film on the third interlayer insulating film; Patterning the second Al film to form a second Al wiring layer on the third interlayer insulating layer; and forming a protective film on the third interlayer insulating layer having the second Al wiring layer formed thereon. An opening corresponding to the position where the fuse is arranged, the protective film, the third interlayer insulating film, the planarizing film, and the second film.
A method of manufacturing a semiconductor device, comprising: a step of forming an interlayer insulating film; and a step of removing an etch stop layer formed corresponding to a position where the fuse is arranged.