JP2003257981A - Silicon wafer manufacturing method - Google Patents

Abstract

[PROBLEMS] To enlarge a COP-free region, improve flatness, have no scratches, have no haze on the wafer surface, no foreign matter remains on the wafer surface, improve the appearance yield, and Provided is a method for manufacturing a silicon wafer having a constant substrate resistance value by suppressing a decrease in the B concentration in a P-type wafer to which P is added. A wafer cutting step of cutting a wafer having a predetermined thickness from a silicon single crystal grown by the Czochralski method, a lapping step of mechanically processing the surface of the cut wafer, and a mechanical lapping step. An etching process for surface-treating the surface of the wafer by a chemical corrosion method;
This is a method for producing a silicon wafer having a heat treatment step of heating at a temperature of 300 ° C. for 1 to 24 hours and a polishing step of mirror-polishing one or both surfaces of the wafer after the heat treatment by a chemical mechanical polishing method.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a silicon wafer, and more particularly to a method for manufacturing a silicon wafer having a step of mirror-polishing a heat-treated silicon wafer by a chemical mechanical polishing method.

[0002]

2. Description of the Prior Art A silicon single crystal manufactured by the Czochralski method (CZ method) has COP (Crystal Or
It is known that there is a void-type defect having a size of about 100 to 200 nm, which is called “ignited Particle 1e”. If this COP exists on the surface of the wafer and in the surface layer portion corresponding to the device active layer, it may cause deterioration of breakdown voltage of the gate oxide film, defective element isolation, and increase of leakage current. Since the yield will be greatly affected, COP suppression measures are required.

As a means for solving such a problem of COP, an Epi wafer is used or a silicon wafer is
_2. A method of performing high temperature annealing (heat treatment) in an atmosphere of Ar, Ar or the like is known.

However, the Epi wafer has a merit that a region free of COP and oxygen precipitates can be formed on the order of μm, but has a problem of high cost.

On the other hand, H ₂ anneal and Ar anneal are low in cost, and the wafer surface can be completely COP-free, but there is a problem that the COP in the surface layer portion has a profile that increases in the depth direction.

The inventors of the present invention performed heat treatment at 1200 ° C. for 1 hour.
COP can be eliminated by several hundreds at most in the wafer depth direction.
It is about nm, and it is necessary to extinguish the COP deeper.
It has been confirmed that this COP-free area is expanded.
A large temperature (disappearance of COP in the deep region) requires high processing temperature.
Warming or longer processing time and silicon single crystal
Finding that it is necessary to reduce the size of the COP at the growing stage
Is getting Also, H _TwoC for annealing and Ar annealing
Due to the difference in removal efficiency of the OP inner wall oxide film, H_TwoAnnealed
It has been confirmed that the COP reduction effect is higher.

However, the high-temperature annealed wafer has the following further improvements.

In the P-type wafer to which B is added, when H ₂ annealing is performed, the depth from the surface layer portion is 5 μm (1
In the case of annealing at 200 ° C. × 1 hr), the B concentration decreases and the substrate resistance value changes, and this B concentration decrease becomes more severe as the H ₂ anneal is performed at higher temperatures.

As the degree of integration of devices is improved, the flatness generally required for silicon wafers is becoming stricter. As a measure for improving the flatness, it is considered that both sides of the silicon wafer are mirror-finished and some of them are put into practical use. , Diameter 30
Double-side polishing is essential for a 0 mm wafer, but if high-temperature annealing is performed after polishing such a double-side polished wafer, contact marks between the silicon wafer and the jig remain on the back surface of the wafer, which is not desirable in appearance.

The high temperature annealing is performed on the mirror surface wafer, but when the high temperature annealing is performed on the mirror surface wafer, the silicon atoms on the wafer surface are rearranged to form minute steps such as steps and terraces. The haze on the wafer surface may be worse than that on the mirror-finished wafer, and contact marks with the support may occur.

The foreign matter adhered to the silicon wafer before the heat treatment is burned onto the surface of the wafer during the heat treatment and cannot be removed by the subsequent cleaning, which may deteriorate the yield in appearance.

Although the object of the present invention is different from that of the present invention for the purpose of solving the problems described in (1) and (2) above, a conventional technique for achieving some of the objects is disclosed in JP-A-61-154134.
There is a method of manufacturing a semiconductor device described in the publication. The manufacturing method described in this publication has manufacturing steps as shown in FIG. 9, and heat treatment is performed in a wet oxygen at 750 to 1250 ° C. before a polishing step to form an oxide film on the surface of the wafer. This is a method of effectively transferring crystal defects and impurities to the (surface oxide film), and further polishing this oxide film.
Although it is useful for solving the problem of, the polishing method has not been improved, and therefore the solution is insufficient, and no improvement has been made to and. Further, in the method described in this publication, since the heat treatment is performed in an atmosphere containing wet oxygen, an oxide film is formed on the wafer surface, and it is necessary to remove the oxide film before polishing. ,
In an atmosphere containing oxygen, outward diffusion of oxygen in the silicon wafer is suppressed, so that there is a problem that oxygen precipitates deposited during the high temperature heat treatment remain on the surface layer of the wafer.

Further, a method of manufacturing a semiconductor silicon substrate is also described in JP-A-3-19687. The manufacturing method described in this publication is 1100 to 1280 ° C before the polishing step.
Is a method of lowering the oxygen concentration on the surface of the wafer and further polishing this surface, which is useful for solving the problems 1 to 3 as in the manufacturing method described in JP-A-61-154134. Since the polishing method has not been improved, the solution thereof is insufficient, and no improvement has been made to and.

Further, Japanese Unexamined Patent Publication No. 6-21033 also describes a method for processing a silicon single crystal wafer in which a heat treatment is performed in an oxygen atmosphere and an oxide film formed on the surface is removed by polishing. Similar to the manufacturing method described in JP-A-61-154134, the method described in this publication is also useful for solving the problems (1) to (3), but since the polishing method has not been improved, the solution is insufficient. No improvements have been made to, and. Furthermore, in the method described in this publication, it is necessary to remove the oxide film before polishing, the number of steps is increased, and in an atmosphere containing oxygen, outward diffusion of oxygen in the silicon wafer is suppressed, There is a problem that oxygen precipitates deposited during the high temperature heat treatment remain on the surface layer of the wafer.

Similarly, as a method for treating a silicon wafer in which polishing is performed after heat treatment, Japanese Patent Laid-Open No. 10-74771
There is a processing method described in Japanese Patent Publication. The treatment method described in this publication is a method of laminating at least two silicon wafers, performing a heat treatment at 1250 ° C. or higher in oxygen, an oxygen-containing atmosphere or an inert or reducing gas atmosphere, and then performing mirror polishing. . However, in the method described in this publication, since the wafers are laminated, the outward diffusion of oxygen is also suppressed, and if the treatment is not performed at a very high temperature of 1250 to 1380 ° C. for a long time, the DZ (Denuded Z) is performed.
One) layer is not formed. In such high temperature processing, oxygen precipitates in the wafer bulk also disappear due to solubilization, and IG (Intrinsic G
Itering) wafer no longer functioning,
In order to add the G capability, it is necessary to perform a heat treatment in a later step.

[0016]

As described above, the conventional method for manufacturing a silicon wafer, in which the silicon wafer is heat-treated and then polished, cannot solve the problems of the conventional high-temperature annealed wafer.

Therefore, the COP free region is expanded, the flatness is improved, there is no scratch, the haze on the wafer surface is small, foreign matter does not remain on the wafer surface, and the external appearance yield is improved. Further, P containing B is added. In the type wafer, there has been a demand for a method for manufacturing a silicon wafer in which the decrease in B concentration is suppressed and the substrate resistance value is constant in the wafer depth direction.

The present invention has been made in consideration of the above-mentioned circumstances, and has a large COP-free area, an improved flatness, no scratches, a small haze on the wafer surface, and no foreign matter remains on the wafer surface. An object of the present invention is to provide a method for producing a silicon wafer in which the yield is improved, and in a P-type wafer to which B is added, a decrease in B concentration is suppressed and the substrate resistance value is constant in the wafer depth direction.

[0019]

The invention according to claim 1 made in order to achieve the above object comprises a wafer cutting step of cutting a wafer of a predetermined thickness from a silicon single crystal grown by the Czochralski method. A lapping step of mechanically processing the surface of the cut wafer, an etching step of surface-treating the surface of the mechanically processed wafer by a chemical corrosion method, and a wafer after the etching step of 1200 to 1300 ° C. 1-2 at the temperature of
It is a gist of the present invention to provide a silicon wafer manufacturing method characterized by comprising a heat treatment step of heating for 4 hours and a polishing step of mirror-polishing one or both surfaces of the wafer after the heat treatment by a chemical mechanical polishing method.

According to the second aspect of the present invention, the wafer cutting
The silicon wafer in the release process is a silicon single crystal
Nitrogen concentration of 1 × 10^Thirteen~ 5 x 10¹⁵atoms /
cm ^ThreeAnd oxygen concentration is 5 to 18 × 10¹⁷atoms
/ Cm^ThreeControl both to become (Old-ASTM)
It is characterized by cutting out from the silicon single crystal grown by
It is a silicon wafer manufacturing method that
ing. The above-mentioned silicon wafer is made of P containing boron.
Type wafers have a great effect.

In the invention of claim 3 of the present application, the heat treatment step is carried out in an atmosphere of H ₂ or Ar or a mixed atmosphere thereof, and the temperature zone passing speed during heating is set to 5 ° C./sec or less. The gist is that it is a method of manufacturing a silicon wafer.

In the invention of claim 4, the polishing amount of the silicon wafer in the polishing step is 5 to 15 μm on one side.
The gist is that it is a method for manufacturing a silicon wafer.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a silicon manufacturing method according to the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a flow chart of steps for carrying out the method for manufacturing a silicon wafer according to the present invention, which will be described with reference to this flow chart.

As shown in FIG. 1, the method of manufacturing a silicon wafer according to the present invention includes a wafer cutting step P5 for cutting a wafer having a predetermined thickness from a silicon single crystal grown by the Czochralski method, and this cutting step. Lapping step P6 for mechanically processing the surface of the wafer, etching step P7 for surface-treating the surface of the mechanically processed wafer by a chemical corrosion method, and the wafer after the etching step is 1200 to 1300 ° C. At a temperature of 1 to 24 hours, and a chemical mechanical polishing method (CMP: Chemical Mechanical) for one or both surfaces of the wafer after the heat treatment.
Polishing process P9 of mirror polishing by polishing)
And have.

As a pre-process of the wafer cutting process P5, a pulling process P1 for pulling up a silicon single crystal by the Czochralski method and a cylindrical shape for eliminating the unevenness generated by grinding the outer periphery of the pulled single crystal The outer peripheral grinding step P2, the orientation flat / notch step P3 for forming the orientation flats and notches necessary to show a specific crystal orientation, and the metal cutting step P4 for facilitating attachment to a cutting device such as a multi-wire saw are set. is doing.

It is preferable to add nitrogen to the silicon single crystal pulled in the pulling step P1 in the crystal growing stage. This is because the inventors have confirmed that the COP size in as grown can be reduced by adding nitrogen to the crystal growth stage. Further, it has been found that such a nitrogen-added wafer can extinguish COP to a much deeper area than a non-added wafer by high-temperature heat treatment at the same temperature and the same time. Furthermore, since the method for producing a silicon wafer according to the present invention is optimally used for producing a P-type silicon wafer to which boron is added, this embodiment will be described by taking the method for producing a P-type silicon wafer as an example. Take and explain.

Therefore, in the pulling step P1, the nitrogen concentration in the silicon single crystal is 1 × 10 ^{13 to} 5 × 10 ¹⁵ atom.
s / cm ³ and oxygen concentration of 5 to 18 × 10 ¹⁷ ato
The pulling conditions are controlled so as to be ms / cm ^3, and the boron concentration of the silicon wafer in the silicon melt is a predetermined concentration,
For example, boron is added so as to have a concentration of about 1 × 10 ¹⁶ atoms / cm ³ .

The pulled silicon single crystal is cut out as a silicon wafer through an outer peripheral grinding step P2, an orientation flat / notch step P3, a metal cutting step P4 and a wafer cutting step P5.

In the next lapping step P6, the surface of the cut wafer is processed by interposing free abrasive grains suspended in a liquid between the silicon wafer and the polishing platen, and the cut silicon wafer is processed to a predetermined thickness. Alignment, parallelism, flatness and other required shape accuracy are achieved.

In the etching process P7, HF and HN are used.
Etching is performed using a mixed acid of O ₃ and CH ₃ COOH to remove the work strained layer and impurities.

The etched (chemically polished) silicon wafer is heated in a heat treatment step P8. The heating condition of this heat treatment step P8 is 1200 for silicon wafers.
The heating is performed at a temperature of ˜1300 ° C., preferably 1250 ° C. or higher for 1 to 24 hours. The processing atmosphere at this time is H
Any one of ₂ and Ar or a mixed atmosphere thereof, preferably a H ₂ atmosphere. The heating temperature is set to the processing temperature of 12
The reason for defining 50 ° C and heating time as 1 to 24 hours is C
This is to form a region free of OP and oxygen precipitates in the surface layer of 20 μm or more. CO at temperatures or times below this
The area free of P and oxygen precipitates becomes 20 μm or less, and if mirror polishing is performed in the subsequent chemical mechanical polishing step, the free area of the silicon wafer may become 5 μm or less, which hinders device formation. Heating time 24hr
It is not economical to exceed.

Further, the heat treatment step P8 is performed during the temperature rising of 6
The speed of passage from the temperature zone of 0 to 1000 ° C is set to 5 ° C / sec or less.

Since oxygen precipitates generally have the property of capturing metal contamination, it is preferable that there be precipitates in the wafer bulk (IG wafer). However, if oxygen precipitates are present in the surface layer of about 10 μm where the device is formed, element separation failure may occur, so it is better not to exist in the surface layer portion. It is known that nuclei are formed in the oxygen precipitates in a temperature range of about 800 ° C and grow at about 1000 ° C. Oxygen diffuses outward due to the oxygen partial pressure in the temperature range of 1000 ° C. or higher, and the oxygen precipitates in the surface layer portion shrink. Under the above heating conditions, the reason why the temperature band passage speed of 600 to 1000 ° C. is 5 ° C./sec or less is that oxygen precipitates are formed in the wafer bulk. When the temperature is raised at a rate higher than this, oxygen precipitates are not generated, resulting in a silicon wafer having no gettering ability (IG effect).

Further, the boron concentration of the silicon wafer before the heat treatment in the heat treatment step P8 was about 1 × 10 ¹⁶ atoms / cm ³ as shown in FIGS. 2 and ³ , but in an atmosphere containing H _2. In the case of heat treatment, boron is blown (missing) in the vicinity of the surface layer of the silicon wafer, and the phenomenon of boron loss occurs in which the concentration of boron decreases toward the surface.

The heat-treated silicon wafer is polished on one side or both sides by a chemical mechanical polishing method (CMP).

In this polishing step P9 by CMP, a polishing cloth made of non-woven fabric is attached to a surface plate, a silicon wafer is detachably fixed to a mount plate with wax, and the polishing cloth is rotated while being pressed against the silicon wafer to form a polishing cloth. The surface of the silicon wafer is polished while constantly supplying an abrasive. CMP can highly flatten the irregularities on the surface of the silicon wafer. The polishing removal amount (polishing amount) in this polishing step P9 is preferably 5 to 15 μm on one side. By this CMP, the DZ layer, which is a region free from COP and oxygen precipitates, can be formed to a predetermined thickness, and further, one side is polished by 5 to 15 μm. Therefore, as shown in FIG. It is possible to manufacture a silicon wafer having a constant boron concentration in the vicinity of a new surface layer after polishing, by removing the vicinity of the surface layer in which boron has been lost and has a low boron concentration.

Further, by performing CMP, it is possible to remove the haze on the wafer surface due to the step formed by the rearrangement of silicon atoms on the wafer surface generated in the preheat treatment step P8 and the minute step such as the terrace. it can. Further, in the case of a double-sided polished wafer, the trace of contact with the support can be completely removed. Furthermore, the foreign matter that has adhered to the silicon wafer before the heat treatment step P8 can be removed even if it adheres to the wafer surface during the heat treatment.

When the polishing allowance exceeds 15 μm,
The COP formed by the high temperature annealing in the heat treatment step P8 and the DZ layer, which is an oxygen precipitate-free region, have a size of 5 μm or less, and crystal defects are present on the wafer surface, resulting in deterioration of the device yield. . If the removal allowance is less than 5 μm, the steps and terraces formed by the high temperature annealing of the heat treatment step P8 cannot be completely removed, and the layer with a low boron concentration cannot be removed, resulting in a high flatness and a constant boron concentration. It is not possible to manufacture silicon wafers.

As described above, CO is formed on the surface layer of the silicon wafer by the method for producing a silicon wafer according to the present invention.
It is possible to manufacture an IG wafer in which the P and oxygen precipitate free regions (DZ layer) are formed to a thickness of 5 μm or more and the wafer bulk contains oxygen precipitates.

[0041]

EXAMPLES [Test 1] Adjacent wafers sliced from a silicon single crystal ingot produced by the CZ method as shown in FIG. 4 were subjected to chemical polishing. The oxygen concentration is 1.6 × 10 ¹⁸ atoms / cm ³ (Old-A
STM) was used. After that, two adjacent sheets were halved and one was designated as A lot and the other was designated as B lot. The A lot (Example 1) was annealed at 1300 ° C. for 1 hr and H ₂ and then double-side polished by CMP (single-sided machining allowance: 15 μ).
m) was carried out, and the B lot (conventional example 1) was subjected to double-side polishing by CMP and then H ₂ annealing at 1300 ° C. × 1 hr. The B concentration in the depth direction of both was measured by SIMS.

Results: FIG. 5 shows the B concentration profile in the depth direction by SIMS. It was found that the conventional example 1 showed a decrease in the B concentration up to a depth of about 6 μm, whereas the example 1 had a uniform concentration distribution in the depth direction.

[Test 2] Using the wafers of A lot and B lot of test 1, heat treatment (78
(0 ° C. × 3 hr + 1000 ° C. × 16 hr two-stage heating) and CMP are performed to produce wafers of Example 2 and Conventional Example 2. Cleavage of Example 2 and Conventional Example 2 is carried out, and oxygen precipitation of the cross-section is performed by IR tomography. The objects were observed.

Results: FIG. 6 shows the results of observation of oxygen precipitates.
In the conventional example 2, no oxygen precipitate was observed and the DZ layer was formed to a deep portion, whereas in the example 2, the surface layer 10 was formed.
It was found that an oxygen precipitate-free region was formed at about μm, and oxygen precipitates were deposited at a high density in a region deeper than that.

[Test 3] Diameter: φ8 ", plane orientation: <10
0>, type: P, specific resistance: 1.0 Ω · cm, oxygen temperature: 1 × 10 ¹⁸ atoms / cm ³ , sample wafers were cut out from three types of silicon single crystals having different nitrogen concentrations. The nitrogen concentration in each wafer is shown below.

Comparative Example 1: 0 atoms / cm^Three, Comparative example
2: 1 x 10¹²atoms / cm ^Three, Example 3: 5x
10¹⁴atoms / cm^ThreeExample 4: 5x10¹⁵
atoms / cm^Three

Each sample wafer was mirror-polished and then heat-treated in a hydrogen atmosphere at 1250 ° C. for 2 hours. Further, polishing was performed by changing the polishing amount to 0 to 25 μm by CMP, and the number of COPs existing on the wafer surface was measured.

Results: Shown in FIG.

In Comparative Example 1 in which nitrogen was not added, COPs disappeared only on the surface, and almost the same number of COPs existed at a depth of 5 μm or more. Also in Comparative Example 2 having a low nitrogen concentration, the result was almost the same as that of Comparative Example 1. Example 3
Then, COP disappeared in the region from the surface to a depth of about 20 μm. In Example 4, C even at the stage of polishing by 25 μm
No OP was detected. Therefore, in Comparative Example 1 and Comparative Example 2, after the high temperature annealing, 5 μm
The above polishing removes the surface defect-free layer, so that C
It was found that OP was exposed on the wafer surface. In Example 3, even if the polishing is 5 to 10 μm, the COP
It was found that a free area up to a depth of about 5 to 10 μm can be secured. In Example 4, it was found that the COP-free region was deeper than Example 4.

[Test 4] Three mirror-finished wafers having the same characteristics as in Example 3 of Test 3 were subjected to a high temperature heat treatment in a hydrogen atmosphere under the following conditions. Then, the number of COPs in the wafer depth direction was measured by the same method as in Test 3.

Condition 1 (Comparative Example 3): 1150 ° C. × 4 h
r, condition 2 (Example 5): 1200 ° C. × 4 hr, condition 3
(Example 6): 1250 ° C x 4 hours

Results: Shown in FIG.

In Comparative Example 3, 10 at the stage of polishing to 5 μm
COP of 0 or more / wf was detected. In Example 5,
The COP disappeared up to the depth of 13 μm, and several COPs were observed at the depth of 15 μm. In Example 6, the COP disappeared completely up to the depth of 25 μm.

In addition, Example 3 of FIG. 7 showing the results of Test 3
And Example 5 in FIG. 8 are compared, 1200 ° C. × 4 hr
The COP reduction rate by the heat treatment of (Example 5) is 1250.
Since it is slightly inferior to the case of ℃ × 2hr (Example 3), it was found that increasing the temperature is more effective than extending the heat treatment time in order to eliminate the COP to a deeper region. It was

[0055]

According to the method of manufacturing a silicon wafer according to the present invention, the COP free region is expanded, the flatness is improved,
There are no scratches, no haze on the wafer surface, no foreign matter remains on the wafer surface, and the yield in appearance is improved. Also, in the P-type wafer to which B is added, the decrease in B concentration is suppressed and the substrate resistance value is reduced. It is possible to provide a method for producing silicon having a constant value.

That is, the wafer after the etching step for treating the surface of the wafer by the chemical corrosion method
Since it is a method for manufacturing a recon wafer in which one side or both sides of the wafer are mirror-polished by a chemical mechanical polishing method after heating at a temperature of 00 to 1300 ° C. for 1 to 24 hours, it is possible to highly flatten the unevenness of the silicon wafer surface. In addition, it is possible to remove the haze on the wafer surface caused by the step formed by rearrangement of silicon atoms on the wafer surface generated in the heat treatment step, a minute step such as a terrace, and the contact trace with the support tool is Further, it is possible to remove the foreign matter adhered to the silicon wafer before the heat treatment step and the adhered matter burned on the wafer surface during the heat treatment.

The silicon wafer in the wafer cutting step has a nitrogen concentration in the silicon single crystal of 1 × 10 5.
^It is cut out from a silicon single crystal grown by controlling both of them so that the oxygen concentration is ^{13 to} 5 × 10 ¹⁵ atoms / cm ³ and the oxygen concentration is 5 to 18 × 10 ¹⁷ atoms / cm ^3. As a COP-free area, a depth of about 5 to 10 μm can be secured.

Further, the heat treatment step is performed in an atmosphere of H ₂ or Ar or a mixed atmosphere thereof, and the temperature is raised to 600 ° C.
Since the temperature band passage speed of up to 1000 ° C. is set to 5 ° C./sec or less, oxygen precipitates are formed in the wafer bulk, and a silicon wafer having a gettering ability (IG effect) can be manufactured.

Further, a P-type wafer to which boron is added is used as a silicon wafer and is heated in an atmosphere containing H ₂ to remove the boron near the surface layer where the boron concentration is low and the boron concentration is low in the heating step, and the polishing is performed. It is possible to manufacture a silicon wafer having a constant boron concentration in the vicinity of a new surface layer later.

In the heat treatment step, the heat treatment temperature and time are adjusted so as to form a surface defect-free layer free of oxygen precipitates at a depth of at least 20 μm or more from the surface of the silicon wafer. Even if the polishing is performed to some extent, it is possible to secure a depth of 5 to 10 μm as a COP free region.

In addition, since the polishing amount of the silicon wafer in the polishing step is 5 to 15 μm on one side, C after the polishing
It is possible to secure a depth of 5 to 10 μm as an OP-free region.

[Brief description of drawings]

FIG. 1 is a process flow chart of a method for manufacturing a silicon wafer according to the present invention.

FIG. 2 is a boron concentration depth direction profile diagram in the heating step of the method for manufacturing a silicon wafer according to the present invention.

3 (a) and 3 (b) are schematic views of the boron concentration during the steps of the method for manufacturing a silicon wafer according to the present invention.

FIG. 4 is a manufacturing flow chart of an embodiment of the method for manufacturing a silicon wafer according to the present invention.

FIG. 5 is a boron concentration profile diagram of an example in a method for manufacturing a silicon wafer according to the present invention.

FIG. 6 is a wafer cross-sectional view of an example of a method for manufacturing a silicon wafer according to the present invention.

FIG. 7 is a measurement result diagram of the COP number of an example in the method for manufacturing a silicon wafer according to the present invention.

FIG. 8 is a measurement result diagram of the number of COPs in an example in the method for manufacturing a silicon wafer according to the present invention.

FIG. 9 is a process flow chart of a conventional silicon wafer manufacturing method.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hiroshi Kiyomoto             86-1 Higashi Port, Seiro-cho, Kitakanbara-gun, Niigata Prefecture             5 Within Toshiba Ceramics Co., Ltd.

Claims (4)

[Claims] 1. A wafer cutting step of cutting a wafer having a predetermined thickness from a silicon single crystal grown by the Czochralski method, a lapping step of mechanically processing the surface of the cut wafer, and a mechanical processing An etching step of surface-treating the surface of the formed wafer by a chemical corrosion method, and the wafer after this etching step
A method for producing a silicon wafer, comprising: a heat treatment step of heating at a temperature of 1300 ° C. for 1 to 24 hours; and a polishing step of mirror-polishing one or both surfaces of the wafer after the heat treatment by a chemical mechanical polishing method. 2. The silicon wafer in the wafer cutting step has a nitrogen concentration in the silicon single crystal of 1 × 10.
^{13 ~5 × 10 15 atoms / cm} 3 a and the oxygen concentration of ^{5~18 × 10 17 atoms / cm 3} (Old-A
The method for producing a silicon wafer according to claim 1, wherein the silicon single crystal grown by controlling both of them to obtain STM) is cut out. 3. The heat treatment step is performed in an atmosphere of H ₂ or Ar or a mixed atmosphere thereof, and the temperature is increased to 600 ° C. during heating.
The method for producing a silicon wafer according to claim 1 or 2, wherein the temperature band passing speed at a temperature of 1000C to 1000C is set to 5C / sec or less. 4. The method for producing a silicon wafer according to claim 1, wherein the polishing amount of the silicon wafer in the polishing step is 5 to 15 μm on one side.