JP2003256353A - DMA control device and DMA control method - Google Patents

Abstract

(57) [Summary] For a DMA process that does not hinder even a slight delay in execution, the process of the CPU is executed with some priority. A memory, a CPU for executing processing using the memory, a plurality of DMA controllers for directly executing processing using the memory without passing through the CPU; An arbiter 25 for arbitrating access to the memory 13 with the plurality of DMA controllers 21 to 24;
Suppression circuits 33 and 34 are provided for the DMA controllers 23 and 24 inside, and temporarily suppress the DMA request signal output to the arbiter 25.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA transfer control device and a DMA control method for directly transmitting / receiving data to / from a memory without going through a CPU.

[0002]

2. Description of the Related Art DMA (Direct Memory) that has been conventionally used in general computer systems.
FIG. 10 shows an example of the configuration of the access control circuit.
Shown in.

In FIG. 1, a DMA controller 11 and
CPU (MPU) that controls the operation of the entire system
12 and a memory 13, which is a work memory of the CPU 12, include an address (ADRS) bus and a data (DAT).
A) Interconnected by a bus and a control (CONTROL) bus.

The DMA controller 11 includes first to fourth DMA controllers (DMAC1 to 4) 21 to 2
4 and an arbiter 25.

First to fourth DMA controllers 21 to 21
Reference numerals 24 are each connected to the address bus, the data bus, and the control bus to carry out the DMA with the memory 13. At the time of carrying out the DMA, the request signal REQn (n = 1) is sent to the arbiter 25 in advance. ~ 4)
, And when the arbiter 25 receives an acknowledgment signal ACKn, DMA is started.

The arbiter 25 is the first to fourth DMs.
A first to fourth DMA controller 2 is a hardware circuit that performs an arbitration operation for the A controllers 21 to 24.
When the request signal REQn is input from at least one of 1 to 24, a signal BUSR for requesting the bus right accompanying the DMA to the CPU 12 in consideration of the priority order thereof.
When the EQ is sent and the CPU 12 sends a positive response signal BUSACK to the request, the positive response signal ACKn is output to the corresponding nth DMA controller 2n.

In the circuit configuration as described above, its operation will be described next. FIG. 11 mainly shows the processing contents of the DMA transfer control by the arbiter 25 of the DMA general controller 11.

Here, the request signals REQ1 to REQ4 output from the first to fourth DMA controllers 21 to 24, for example.
With respect to, the priority order of REQ1>REQ2>REQ3> REQ4 is set.

At the beginning of the processing, the arbiter 25 receives the request signal RE from the first to fourth DMA controllers 21 to 24.
It waits for at least one of Q1 to Q4 to be input (step A01), and when it is determined that there is an input, a signal BUSREQ for requesting the bus right to the CPU 12 next.
Is set to "1 (H)" (step A02), and in response thereto, an affirmative response signal B sent from the CPU 12
It waits until the USACK level becomes "1" (step A03).

Then, a signal BUSAC from the CPU 12
When it is determined that the K level has become "1", whether the level of the request signal REQ1 from the first DMA controller 21 is "1" according to the above-described priority order (step A04), the second DMA controller 22
Whether the level of the request signal REQ2 from the third DMA controller 23 is "1" (step A07) or the level of the request signal REQ3 from the third DMA controller 23 is "1" (step A10). Judge sequentially.

The first highest priority in step A04
If it is determined that the level of the request signal REQ1 from the first DMA controller 21 is “1”, the positive acknowledgment signal ACK1 to the first DMA controller 21.
Is set to "1" (step A05), the DMA operation for the memory 13 using the address bus, the data bus, and the control bus is started, and when the operation is completed, the first DMA controller 21 It waits until the level of the request signal REQ1 becomes "0 (L)" (step A06).

When it is determined that the level of the request signal REQ1 from the first DMA controller 21 has become "0", it is determined that the DMA operation to the memory 13 by the first DMA controller 21 is completed and the CPU1
The level of the signal BUSREQ for requesting the bus right for 2 is set to "0" (step A15), and C
Acknowledgment signal BUSACK sent from PU12
Waits for the level to become "0" (step A1)
6).

When the level of the signal BUSACK from the CPU 12 becomes "0", the first to fourth DMs are newly set.
Acknowledgment signal ACK to the A controllers 21 to 24
Levels 1 to 4 are collectively set to "0" (step A1
7) Then, the series of processing is ended, and the processing is returned from step A01 to prepare for the next DMA request again.

In step A04, the request signal REQ from the first DMA controller 21 having the highest priority is sent.
When the level of 1 is not "1" and it is determined in step A07 that the level of the request signal REQ2 from the second DMA controller 22 having the second highest priority is "1" , The level to the acknowledge signal ACK2 for the second DMA controller 22 is set to "1" (step A08), and the DMA operation for the memory 13 using the address bus, the data bus and the control bus is started, and Second after the operation is completed
It waits until the level of the request signal REQ2 from the DMA controller 22 becomes 0 (step A09).

When it is determined that the level of the request signal REQ2 from the second DMA controller 22 has become "0", it is assumed that the DMA operation to the memory 13 by the second DMA controller 22 is completed. The processing from step A15 is executed.

Furthermore, in steps A04 and A07, the first and second DMA controllers 21 and 22 having a high priority order.
The level of the request signals REQ1 and REQ2 from the third DMA controller 23 having the third highest priority in step A10 is "1". If it is determined that the level of the acknowledgment signal ACK3 to the third DMA controller 23 is "1" (step A1).
1), the DMA operation for the memory 13 using the address bus, the data bus, and the control bus is started, and the operation is completed, and the third DMA controller 23
It waits until the level of the request signal REQ3 from the signal becomes "0" (step A12).

Then, when it is determined that the level of the request signal REQ3 from the third DMA controller 23 becomes "0", it is assumed that the DMA operation to the memory 13 by the third DMA controller 23 is completed. The processing from step A15 is executed.

Further, in steps A04, A07, and A10, the first to third DMA controllers 21 having a high priority are assigned.
If it is determined that none of the levels of the request signals REQ1 to REQ3 sent from the first DMA controller 24 to the first request signal REQ3 are "1", the request signal REQ4 from the fourth DMA controller 24 having the lowest priority is needless to say. Is "1", the level to the acknowledgment signal ACK4 for the fourth DMA controller 24 is set to "1".
(Step A13), address bus, data bus,
And the DMA operation for the memory 13 using the control bus is started, and the operation is completed, and the fourth DM
It waits until the level of the request signal REQ4 from the A controller 24 becomes "0" (step A14).

Then, when it is determined that the level of the request signal REQ4 from the fourth DMA controller 24 has become "0", it is assumed that the DMA operation to the memory 13 by the fourth DMA controller 24 is completed. The processing from step A15 is executed.

FIG. 12 shows the first DMA controller 21.
And the third DMA controller 23 exemplify the operation timing of each signal when the request signals REQ1 and REQ3 are sent to the arbiter 25.

The request signal REQ1 from the first DMA controller 21 shown in FIG. 12 (1) and the request signal REQ3 from the third DMA controller 23 shown in FIG. 12 (3).
And are at the "1" level at different timings.

The arbiter 25 requests the request signal REQ from the first DMA controller 21 which has become "1" level earlier.
Corresponding to the input of 1, CPU as shown in FIG. 12 (5)
The level of the signal BUSREQ for requesting the bus right to 12 is set to "1".

Thereafter, the timing t shown in FIG.
1, the CPU 12 temporarily releases the bus right, and FIG.
Signal BUS of the positive response to the arbiter 25 shown in 2 (6)
The ACK level is set to "1".

At this time, the arbiter 25 requests the request signal REQ from the first DMA controller 21 according to the priority.
1 is "1", the level of the acknowledge signal ACK1 to the first DMA controller 21 is set to "1" as shown in FIG.
DMA requesting to the DMA controller 21 of
Let the process run.

Thereafter, the DMA processing by the first DMA controller 21 is completed, and the first D shown in FIG.
When the level of the request signal REQ1 from the MA controller 21 becomes "0", the arbiter 25 sets the level of the signal BUSREQ to the CPU 12 shown in FIG. 12 (5) to "0".

On the other hand, the CPU 1 shown in FIG. 12 (6)
The level of the signal BUSACK of the positive response from 2 is also “0”
Then, as shown in FIG.
The levels of the acknowledgment signals ACK1 to ACK4 to the fourth DMA controllers 21 to 24 are collectively set to "0".

After that, the third DMA shown in FIG.
Since the request signal REQ3 from the controller 23 is at "1" level, the level of the signal BUSREQ for requesting the bus right to the CPU 12 is set to "1" again, and then the level of the signal BUSACK of the affirmative response from the CPU 12 is set. Waits for "1".

Then, at the timing t2, the CPU1
2 temporarily releases the bus right and sets the level of the signal BUSACK of the positive response to the arbiter 25 shown in FIG. 12 (6) to "1", the arbiter 25 thereby receives the third DM signal.
Since the request signal REQ3 from the A controller 23 is "1", the acknowledgment signal ACK3 to the third DMA controller 23 as shown in FIG.
Is set to "1", the bus right is given to the third DMA controller 23, and the requested DMA processing is executed.

Thereafter, the DMA processing by the third DMA controller 23 is completed, and the third D shown in FIG.
When the level of the request signal REQ3 from the MA controller 23 becomes "0", the arbiter 25 sets the level of the signal BUSREQ to the CPU 12 shown in FIG. 12 (5) to "0".

On the other hand, the CPU 1 shown in FIG.
The level of the signal BUSACK of the positive response from 2 is also “0”
Then, as shown in FIG.
The levels of the acknowledgment signals ACK1 to ACK4 to the fourth DMA controllers 21 to 24 are collectively set to "0".

As described above, the arbiter 25 includes the first to fourth parts.
When at least one of the DMA controllers 21 to 24 makes a request to the CPU 12, and when a response from the CPU 12 is obtained, a response is sent to the one that has sent the request according to the priority order. Return, D
The MA process is executed.

[0032]

In the above-mentioned control contents of the DMA general controller 11, the arbiter 25 responds to a request asynchronously output from at least one of the first to fourth DMA controllers 21 to 24. The request is unconditionally delivered to the CPU 12 regardless of the priority.

Therefore, when there is a high frequency of requests from the first to fourth DMA controllers 21 to 24,
The CPU 12 temporarily entrusts the bus right to the DMA general controller 11 side each time the minimum processing is performed.
Since the CPU 12 cannot hold the bus right for a long continuous time, it may take a lot of time to perform one processing.

The present invention has been made in view of the above situation, and an object of the present invention is to give priority to the CPU processing to some extent to execute the DMA processing which does not cause any trouble even if the execution is delayed. It is to provide a DMA control device and a DMA control method capable of performing the same.

[0035]

The invention according to claim 1 is
A memory, a main controller that executes processing using the memory, a DMA controller that directly executes processing using the memory without going through the main controller, and a DMA controller provided for the DMA controller.
And a suppressing means for temporarily suppressing a DMA request signal output from the controller to the main controller and requesting an access right to the memory.

With such a configuration, the DMA request signal from the corresponding DMA controller is temporarily suppressed by the DMA request signal from the corresponding DMA controller, because the priority is low and there is no problem even if the execution is delayed. While performing, the processing of the main controller can be preferentially and continuously executed.

According to a second aspect of the present invention, in the first aspect of the present invention, a plurality of DMA controllers are provided, and the suppressing means is provided for at least one of the plurality of DMA controllers. And

With such a configuration, in addition to the operation of the invention described in claim 1, it is possible to efficiently execute the DMA control by setting the priority order depending on the presence or absence of the suppression in each of the plurality of DMA controllers. .

The invention according to claim 3 is the same as the invention according to claim 2, wherein the main controller and a plurality of DMs are provided.
An arbiter circuit that arbitrates the access right to the memory with the A controller is provided, and the suppressing means outputs the DM output from the DMA controller to the arbiter circuit.
It is characterized in that the A request signal is temporarily suppressed.

With such a configuration, in addition to the operation of the present invention described in claim 2, since the DMA request signal is centrally managed by the arbiter circuit before the main controller, the main controller is not burdened. DMA
Can exercise control.

According to a fourth aspect of the present invention, in the above-mentioned first aspect, the suppressing means delays the DMA request signal from the DMA controller by a predetermined time and outputs the delayed signal to the main controller.

With such a structure, in addition to the operation of the invention described in claim 1, it can be realized by adding a simple timer circuit.

According to a fifth aspect of the present invention, in the above-mentioned third aspect, the suppressing means outputs a DMA request signal from a DMA controller directly connected to the arbiter circuit without passing through the suppressing means. The present invention is characterized by counting the number of non-existing states and delaying the output of the DMA request signal until the count value reaches a predetermined value.

According to this structure, in addition to the function of the invention described in claim 3, another DM having a higher priority is added.
Since the A controller counts the time when all DMA processing is not requested or executed and delays the DMA request signal from the DMA controller for a predetermined time, the priority order is low and the DMA processing that causes a slight delay in the execution of the DMA processing can be performed. By distributing, the processing time can be appropriately given to the main controller.

According to a sixth aspect of the present invention, in the first aspect of the invention, the suppressing means temporarily outputs the DMA request signal output from the DMA controller to the main controller in accordance with the signal from the main controller. It is characterized by shutting off.

With such a configuration, in addition to the operation of the invention described in claim 1, it is possible to control the presence / absence of immediate execution of the low priority DMA processing in accordance with the load state of the main controller. Can be efficiently and smoothly processed.

According to a seventh aspect of the present invention, in the above-mentioned sixth aspect of the invention, when the suppressing means outputs the DMA request signal from the DMA controller at the time when the signal is output from the main controller, the DMA request signal is DMA. It is characterized in that the interruption of the request signal is delayed.

With such a configuration, in addition to the operation of the invention described in claim 6, the main controller unnecessarily receives a request for DMA processing from the DMA controller in a situation where continuous processing is required. Can be blocked and the DMA processing can be permitted when the processing is completed.

The invention described in claim 8 is the invention according to claim 3 characterized in that the suppressing means and the arbiter circuit are integrated into a hardware circuit.

With this structure, in addition to the effect of the invention described in claim 3, the circuit structure can be simplified.

According to a ninth aspect of the present invention, there is provided a memory, a main controller that executes processing using the memory, and a DMA controller that directly executes processing using the memory without going through the main controller. DMA
A DMA control method in a control device, comprising:
It is characterized in that the output of a DMA request signal for requesting an access right to the memory output from the controller to the main controller is temporarily suppressed.

According to such a method, the DMA request signal from the corresponding DMA controller is temporarily suppressed by the DMA request signal from the corresponding DMA controller, because the priority is low and there is no problem even if the execution is slightly delayed. While performing, the processing of the main controller can be preferentially and continuously executed.

[0053]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment in which the present invention is applied to a DMA control circuit will be described below with reference to the drawings.

FIG. 1 shows the circuit configuration, and since the basic configuration is almost the same as that shown in FIG. 10, the same parts are designated by the same reference numerals and the description thereof will be omitted.

However, also here, the request signal RE output from the first to fourth DMA controllers 21 to 24, for example.
Regarding Q1, Q2 and REQ_ORG3, 4, REQ1>REQ2>REQ_ORG3> REQ_OR
It is assumed that the priority order of G4 is set, and that there is no problem even if the execution is delayed a little especially in the third and fourth DMA controllers 23 and 24 in the DMA general controller 11 '.
Suppressing circuits 33 and 34 are provided between the third and fourth DMA controllers 23 and 24 and the arbiter 25, respectively, for processing.

That is, the suppression circuit 33 (34) is similar to that shown in FIG.
, The request signal REQ_ORG3 (4) from the DMA controller 23 (24) and the request signals REQ from the first and second DMA controllers 21 and 22.
1, 2 are input, and the request signal REQ3 (4) is output to the arbiter 25 according to the state and the value of the internal counter.

On the other hand, the acknowledgment signal ACK3 (4) sent from the arbiter 25 is directly passed through as shown to form the acknowledgment signal ACK_ORG3 (4).
It is given to the DMA controller 23 (24).

Next, the operation of the above embodiment will be described. Note that the content of the processing operation of the arbiter 25 itself is the same as the content described in FIG. 11 above, and therefore the description thereof will be omitted here.

FIG. 3 shows the processing contents relating to the output of the request signal REQ3 (4) to the arbiter 25, which is executed in the suppression circuit 33 (34).

At the beginning of the processing, the value of the counter for counting the delay time is cleared to "0" (step B0
1), and also request signal REQ3 to arbiter 25
After setting the level of (4) to "0" (step B0
2), the third (fourth) DMA controller 23 (24)
It is judged whether or not the request signal REQ_ORG3 (4) from (1) has become "1" (step B03), and if not, the process returns to the step B01 again, and the suppression circuit 33 (34) is repeatedly executed. ) From the request signal REQ_ORG3 (4) becomes "1".

Then, the request signal REQ_ORG3 (4) from the third (fourth) DMA controller 23 (24).
Becomes "1", this is judged in step B03, and then the request signal RE output from the first DMA controller 21.
It waits for both Q1 and the request signal REQ2 output from the second DMA controller 22 to become "0" (step B
04), the value of the above counter is updated and set to "+1" only when both are determined to be "0" (step B05), and whether or not the updated set count value has reached a preset limit value. Or not (step B0
6) If the limit value is not reached, the process returns to step B04, and the process is repeated,
The first and second DMA controllers 21 and 22 stand by until a predetermined time elapses when neither of the request signals REQ1 and REQ2 is output.

When it is determined in step B06 that the counter value has reached the limiter value, it is assumed that the first and second DMA controllers 21 and 22 are not outputting the request signals REQ1 and REQ for a predetermined time. Again, the level of the request signal REQ3 (4) to the arbiter 25 is set to "1" (step B07), and thereafter, the level of the acknowledgment signal ACK3 (4) from the arbiter 25 becomes "1", and the third (fourth) ), The DMA processing requested by the DMA controller 23 (24) of FIG.
It waits until the request signal REQ_ORG3 (4) from the (fourth) DMA controller 23 (24) becomes "0" (step B08).

When it is determined in step B08 that the request signal REQ_ORG3 (4) from the third (fourth) DMA controller 23 (24) has become "0", the series of processing relating to the DMA request is ended. Then, the process returns from step B01 to prepare for the next DMA request again.

FIG. 4 exemplifies the operation timing of each signal when the first DMA controller 21 and the third DMA controller 23 send the request signals REQ1 and REQ_ORG3 to the arbiter 25.

The request signal REQ1 from the first DMA controller 21 shown in FIG. 4 (1) and the third signal shown in FIG. 4 (3).
Request signal REQ_OR from the DMA controller 23 of
Both become "1" level at different timings from G3.

At this time, in the suppression circuit 33, the third DMA
It is determined in step B03 that the request signal REQ_ORG3 from the controller 23 has become “1”, and in the following step B04, the request signal REQ1 output from the first DMA controller 21 and the request signal output from the second DMA controller 22. It waits until both REQ2 become "0".

The arbiter 25 requests the request signal REQ from the first DMA controller 21 which has been set to "1" level.
Corresponding to the input of 1, the CPU 1 as shown in FIG.
The level of the signal BUSREQ for requesting the bus right to 2 is set to "1".

Then, at timing t11, the CPU
12 temporarily releases the bus right and sets the level of the signal BUSACK of the positive response to the arbiter 25 shown in FIG. 4 (8) to "1".

At this time, the arbiter 25 determines that the request signal REQ1 from the first DMA controller 21 is "1", and as shown in FIG.
The level of the acknowledge signal ACK1 for the controller 21 is set to "1", and the bus right is given to the first DMA controller 21 to execute the requested DMA processing.

Thereafter, the DMA processing by the first DMA controller 21 is completed, and the first DM shown in FIG.
When the level of the request signal REQ1 from the A controller 21 becomes “0”, the arbiter 25 causes the CP shown in FIG.
The level of the signal BUSREQ to U12 is set to "0".

On the other hand, the CPU 12 shown in FIG.
When the level of the signal BUSACK of the acknowledgment from is also "0", the arbiter 25 causes the first and second DMA controllers 21 and 22, as shown in FIG.
Acknowledgment signals ACK1 to ACK4 to the suppression circuits 33 and 34
The levels of are collectively set to "0".

At this time, in the suppression circuit 33, step B0
In step 4, it is determined that both the request signal REQ1 output by the first DMA controller 21 and the request signal REQ2 output by the second DMA controller 22 are "0".
Thereafter, while repeatedly executing the processing of steps B04 to B06, the value of the counter is sequentially incremented by “+1” as shown in FIG.
Continue to update and set.

However, the first DMA shown in FIG.
The request signal REQ1 from the controller 21 is "1" again
At this point, the suppression circuit 33 suspends the counting operation of the counter based on the determination in step B04.

When the request signal REQ1 from the first DMA controller 21 becomes "1" level, the arbiter 25 sends the signal BUSREQ for requesting the bus right to the CPU 12 again as shown in FIG. 4 (7). Set the level to "1".

Thereafter, at timing t12, the CPU
12 temporarily releases the bus right and sets the level of the signal BUSACK of the positive response to the arbiter 25 shown in FIG. 4 (8) to "1".

At this time, the arbiter 25 determines that the request signal REQ1 from the first DMA controller 21 is "1", and as shown in FIG. 4B, the first DMA.
The level of the acknowledge signal ACK1 for the controller 21 is set to "1", and the bus right is given to the first DMA controller 21 to execute the requested DMA processing.

Thereafter, the DMA processing by the first DMA controller 21 is completed, and the first DM shown in FIG.
When the level of the request signal REQ1 from the A controller 21 becomes “0”, the arbiter 25 causes the CP shown in FIG.
The level of the signal BUSREQ to U12 is set to "0".

At this time, in the suppression circuit 33, step B0
In step 4, it is judged that both the request signal REQ1 output from the first DMA controller 21 and the request signal REQ2 output from the second DMA controller 22 have become "0" again, and thereafter, the processing of steps B04 to B06 is performed. While repeatedly executing, as shown in FIG. 4 (5), the operation suspended until then is restarted and the value of the counter is continuously updated and set to "+1".

When the counter value of the suppression circuit 33 reaches the limit value, this is judged in step B06, and
As shown in (4), the request signal REQ3 from the suppression circuit 33 to the arbiter 25 is set to "1" level.

After that, since the request signal REQ3 from the suppressing circuit 33 shown in FIG. 4 (4) is at the "1" level, the arbiter 25 returns to the CPU as shown in FIG. 4 (7).
After the level of the signal BUSREQ for requesting the bus right to the bus 12 is set to "1", the CPU 12 waits until the level of the signal BUSACK of the affirmative response from the CPU 12 becomes "1".

Then, at the timing t13, the CPU
12 temporarily releases the bus right, and when the level of the signal BUSACK of the positive response to the arbiter 25 shown in FIG. 4 (8) is set to "1", the arbiter 25 thereby causes the suppression circuit 3 to operate.
Since the request signal REQ3 from the signal No. 3 is "1", the level of the acknowledge signal ACK3 for the suppression circuit 33 is set to "1" as shown in FIG. To the third DMA controller 23 to execute the requested DMA processing.

Thereafter, the DMA processing by the third DMA controller 23 is completed, and the third DM shown in FIG.
When the level of the request signal REQ_ORG3 from the A controller 23 becomes "0", the suppression circuit 33 judges this at step B08 and returns to the processing from step B01, and at step B01 the counter value is cleared to "0". "
After that, the request signal REQ3 to the arbiter 25 is set to "0" in step B02.

On the other hand, the arbiter 25 is shown in FIG.
When the level of the signal BUSREQ to the CPU 12 shown in FIG. 4 is set to “0” and the level of the signal BUSACK of the positive response from the CPU 12 shown in FIG. Parts as shown in the first and second
DMA controllers 21 and 22, suppression circuits 33 and 34
The levels of the positive acknowledgment signals ACK1 to ACK4 are collectively set to "0".

As described above, the suppression circuit 33 uses the third DMA.
When the request signal REQ_ORG3 from the controller 23 is input, the request signals REQ1 and REQ2 from the first and second DMA controllers 21 and 22, which are set to have higher priority, are not input. By waiting for the predetermined time to elapse, the request signal REQ3 to the arbiter 25 is newly output to the arbiter 25 after the predetermined time elapses.

Therefore, the DMA processing, which has a low priority and has no problem even if the execution is slightly delayed, is distributed to the CPU 12 as shown in FIG. 4 (9) by distributing it by the internal processing in the suppressing circuit 33. Time T1 can be given.

(Second Embodiment) In the following, the present invention is DMA
A second embodiment applied to the control circuit will be described with reference to the drawings.

FIG. 5 shows the circuit configuration, and since the basic configuration is almost the same as that shown in FIG. 10, the same parts are designated by the same reference numerals and the description thereof will be omitted.

However, also here, the request signal RE output from the first to fourth DMA controllers 21 to 24, for example.
Regarding Q1, 2, REQ_ORG3, 4, REQ1>
It is assumed that a priority order of REQ2>REQ_ORG3> REQ_ORG4 is set, and particularly the third and fourth DMA controllers 2 in the DMA integrated controller 11 ″ are set.
It is assumed that the third and fourth DMA controllers 23 and 24 and the arbiter 25 are provided with the suppression circuits 43 and 44, respectively, in order to perform the DMA processing without any problem even if the execution is delayed.

That is, the suppression circuit 43 (44) is similar to that shown in FIG.
As also shown in FIG. 3, the request signal REQ_ORG3 (4) from the DMA controller 23 (24) and the stop flag from the CPU 12 'are input, and the request signal REQ3 is sent to the arbiter 25 according to the states and the mask signal generated internally.
Output (4).

FIG. 7 shows a request signal REQ3 (4) provided in the suppression circuit 43 (44) and output to the arbiter 25 by the request signal REQ_ORG3 (4) from the DMA controller 23 (24) and the mask signal described above. 2) shows the configuration of a logic circuit for generating

As shown, the request signal REQ_ORG3
(4) is directly input to the AND circuit 51, while the mask signal is inverted by the inverter 52 and then the AND circuit 51
Is input to the request signal RE.
It is sent to the arbiter 25 as Q3 (4).

On the other hand, the acknowledgment signal ACK3 (4) sent from the arbiter 25 is passed through as it is as an acknowledgment signal ACK_ORG3 (4),
It is given to the DMA controller 23 (24).

Next, the operation of the above embodiment will be described. Note that the content of the processing operation of the arbiter 25 itself is the same as the content described in FIG. 11 above, and therefore the description thereof will be omitted here.

FIG. 8 shows the processing contents when the mask signal to be processed inside the suppression circuit 33 (34) is generated.

At the beginning of the processing, the level of the mask signal is set to "0" (step C01), and it is judged whether or not the level of the stop flag from the CPU 12 'is "1" (step C02). If not, repeat step C above.
By repeating the process of returning to 01, the CP
It waits until the level of the stop flag from U12 'becomes "1".

Then, when the level of the stop flag from the CPU 12 'becomes "1", this is judged in the step C02, and then the third (fourth) DMA controller 23 (2
It is determined whether the level of the request signal REQ_ORG3 (4) from 4) is "0" (step C03).

Here, the level of the request signal REQ_ORG3 (4) from the third DMA controller 23 is "0".
Not "1", that is, the third (fourth) D
In the state where the MA controller 23 (24) is requesting the DMA processing, the processing is returned to step C01 again.

In step C03, the third (fourth) D
Request signal REQ_ from MA controller 23 (24)
When it is determined that the level of ORG3 (4) is "0", the level of the mask signal is set to "1", and the third (fourth) DMA controller 23 (24) is set as shown in FIG.
The request signal REQ_ORG3 (4) from the arbiter 25
It is blocked from being output to (step C04).

After that, the CPU 12 'waits until the level of the stop flag sent from the CPU 12' becomes "0" (step C05), and when it becomes "0", the process returns from the step C01.

As described above, when the level of the stop flag from the CPU 12 'becomes "1", the third (fourth) DMA is executed.
Request signal REQ_OR from controller 23 (24)
If G3 (4) is at "1" level, the DMA processing is executed to the end in response to the request, and then the third processing is performed.
When the request signal REQ_ORG3 (4) from the (fourth) DMA controller 23 (24) becomes the "0" level, the mask signal is set to the "1" level and the execution of the DMA processing is waited.

The CPU 12 'unnecessarily requests the DMA processing from the third (fourth) DMA controller 23 (24) by setting the level of the stop flag to "1" when continuous processing is required. Block the input,
The DMA processing can be permitted by releasing the level of the stop flag to "0" when the processing is completed.

FIG. 9 exemplifies the operation timing of each signal when the first DMA controller 21 and the third DMA controller 23 send the request signals REQ1 and REQ_ORG3 to the arbiter 25.

The request signal REQ1 from the first DMA controller 21 shown in FIG. 9 (1) and the third signal shown in FIG. 9 (3).
Request signal REQ_OR from the DMA controller 23 of
Both become "1" level at different timings from G3.

At this time, in the suppression circuit 43, since the stop flag from the CPU 12 'shown in FIG. 9 (5) is "0", the processing of steps C01 and C02 is repeated to set the mask signal to "0", The request signal REQ_ORG3 from the third DMA controller 23 is directly output to the arbiter 25 as the request signal REQ3 as shown in FIG. 9 (4).

The arbiter 25 requests the request signal REQ from the first DMA controller 21, which has become the "1" level earlier.
Corresponding to the input of 1, the CPU 1 as shown in FIG.
The level of the signal BUSREQ for requesting the bus right to 2'is set to "1".

Thereafter, at timing t21, the CPU
12 'temporarily releases the bus right, and sets the level of the signal BUSACK of the positive response to the arbiter 25 shown in FIG. 9 (9) to "1".

At this time, the arbiter 25 determines that the request signal REQ1 from the first DMA controller 21 is "1", and as shown in FIG.
The level of the acknowledge signal ACK1 for the controller 21 is set to "1", and the bus right is given to the first DMA controller 21 to execute the requested DMA processing.

During this time, if the level of the stop flag from the CPU 12 'shown in FIG. 9 (5) becomes "1", the suppression circuit 4
3 repeats the processing of steps C01 to C03 to set the mask signal to "0", and outputs the request signal REQ_ORG3 from the third DMA controller 23 as it is to the arbiter 25 as the request signal REQ3 as shown in FIG. 9 (4). On the other hand, it waits for the request signal REQ_ORG3 to become "0" level.

Thereafter, the DMA processing by the first DMA controller 21 is completed, and the first DM shown in FIG.
When the level of the request signal REQ1 from the A controller 21 becomes "0", the arbiter 25 causes the CP shown in FIG.
The level of the signal BUSREQ to U12 'is temporarily set to "0".

On the other hand, the CPU 1 shown in FIG. 9 (9)
When the level of the signal BUSACK of the positive response from 2'becomes also "0", the arbiter 25 causes the first and second DMA controllers 2 to operate as shown in FIG.
1, 22 and the acknowledge signal A to the suppression circuits 43 and 44
The levels of CK1 to CK4 are collectively set to "0".

At this time, the suppression circuit 43 is still in the third state.
Request signal REQ_OR from the DMA controller 23 of
G3 is output as it is to the arbiter 25 as the request signal REQ3.

The arbiter 25 sets the level of the signal BUSREQ to the CPU 12 'to "1" again by the request signal REQ3, and the signal BUS of the affirmative response from the CPU 12'.
It waits until the ACK level becomes “1”.

When the processing in the CPU 12 'is once finished and the level of the signal BUSACK of the affirmative response becomes "1", the arbiter 25 determines that the request signal REQ from the suppression circuit 43 is reached.
Since 3 is "1", the level of the acknowledgment signal ACK3 to the suppression circuit 43 is set to "1" as shown in FIG. DM given to DMA controller 23 and requested
A process is executed.

Thereafter, the DMA processing by the third DMA controller 23 is completed, and the third DM shown in FIG. 9C is generated.
When the level of the request signal REQ_ORG3 from the A controller 23 becomes "0", the suppression circuit 43 judges this in step C03 and sets the level of the mask signal shown in FIG. 9 (6) to "1".

Therefore, the request signal REQ3 to the arbiter 25, which is the output of the AND circuit 51, becomes "0", and the arbiter 25 outputs the signal B to the CPU 12 'shown in FIG. 9 (8).
When the level of USREQ is set to "0" and then the level of the signal BUSACK of the positive response from the CPU 12 'shown in FIG. 9 (9) also becomes "0", a part thereof is also shown in FIG. 9 (7). First and second DMA controllers 21,2
2. Acknowledgment signal ACK1 to the suppression circuits 43 and 44
The levels of 4 to 4 are collectively set to "0".

At this time, the suppression circuit 43 waits for the level of the stop flag from the CPU 12 'to become "0" while temporarily stopping the execution of the DMA processing by setting the mask signal to "1" level. .

After that, the request signal REQ_ORG3 from the third DMA controller 23 becomes "1" again,
In the suppression circuit 43, the mask signal is "1", and the request signal REQ3 to the arbiter 25 is still "0".

When the stop flag from the CPU 12 'shown in FIG. 9 (5) becomes "0", the suppressing circuit 43 judges this at step C05 and proceeds to step C01.
The mask signal is set to "0" again.

As a result, the third DMA controller 23
The request signal REQ_ORG3 from the request signal R
It is delivered to the arbiter 25 as EQ3, and the arbiter 25 sets the level of the signal BUSREQ to the CPU 12 'to "1".

Thereafter, at timing t22, the CPU
12 'temporarily releases the bus right, and sets the level of the signal BUSACK of the positive response to the arbiter 25 shown in FIG. 9 (9) to "1".

At this time, the arbiter 25 determines that the request signal REQ3 from the suppressing circuit 43 is "1".
As shown in FIG. 9 (7), the level of the acknowledgment signal ACK3 to the suppression circuit 43 is set to "1", the bus right is given to the third DMA controller 23 via the suppression circuit 43, and the requested DMA processing is performed. To execute.

Thereafter, the DMA processing by the third DMA controller 23 is completed, and the third DM shown in FIG. 9C is generated.
When the level of the request signal REQ_ORG3 from the A controller 23 becomes “0”, the request signal R to the arbiter 25
EQ3 also becomes "0", and the arbiter 25 sets the level of the signal BUSREQ to the CPU 12 'shown in FIG. 9 (8) to "0".
Then, when the level of the signal BUSACK of the affirmative response from the CPU 12 'shown in FIG. 9 (9) also becomes "0", the first and second DMs are also partially shown in FIG. 9 (7).
The levels of the positive acknowledgment signals ACK1 to ACK4 to the A controllers 21 and 22 and the suppression circuits 43 and 44 are collectively "0".
And

As described above, before the stop flag from the CPU 12 'becomes "1" for the third DMA controller 23 which executes the DMA processing having the low priority and having no trouble even if the execution is slightly delayed. When the request signal REQ_ORG3 is output, the DMA processing is permitted as shown at timing T2 in FIG.
Request signal R after the stop flag from 2'becomes "1"
When EQ_ORG3 is output, the DMA process is not permitted as indicated by timing T3 in FIG. 9 (10), and C
The suppression circuit 43 controls so that the PU 12 ′ preferentially executes the processing using the memory 13.

Therefore, it is possible to control so that the request from the third (fourth) DMA controller 23 (24) having a lower priority order is temporarily cut off according to the load state of the CPU 12 '. The software can be processed efficiently and smoothly.

In the first and second embodiments, the suppression circuits 33, 34, 43 and 44 are arranged between the arbiter 25 and the third and fourth DMA controllers 23 and 24. .

As a result, the arbiter 25 itself is the same as that shown in FIG.
Although it is possible to use a general configuration as shown in 0, the suppression circuit 33,
The functions of 34, 43, and 44 may be integrally provided in the arbiter 25, and by doing so, the entire circuit configuration regarding the DMA control can be further simplified.

In each of the above embodiments, the first
To fourth DMA controllers 2121 to 24 and CPU
Although the arbiter 25 is provided between the CPU 12 (12 ') and the 12 (12'), a signal may be directly transmitted and received between each of the DMA controllers 21 to 24 and the CPU 12 (12 ') without providing the arbiter 25. Good.

Further, instead of providing a plurality of DMA controllers, only one may be provided and the suppressing circuit may be provided for this DMA controller.

Further, a plurality of DMA controllers are provided,
If all DMA controllers have no problem even if the execution is delayed to some extent, suppression circuits may be provided for all the DMA controllers.

In addition, the present invention is not limited to the above-described embodiment, and various modifications can be carried out without departing from the scope of the invention.

Furthermore, the above-described embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent elements are deleted from all the constituent elements shown in the embodiments, at least one of the problems described in the section of the problem to be solved by the invention can be solved, and it is described in the section of the effect of the invention. When at least one of the effects described above is obtained, a configuration in which this constituent element is deleted can be extracted as an invention.

[0132]

According to the first aspect of the present invention, the DMA request signal from the corresponding DMA controller is temporarily suppressed for the DMA processing which has a low priority and has no problem even if the execution is slightly delayed. Thus, while the suppression is being performed, the processing of the main controller can be prioritized and continuously executed.

According to the invention described in claim 2, in addition to the effect of the invention described in claim 1, the priority order is set depending on the presence / absence of suppression in each of the plurality of DMA controllers to efficiently perform the DMA control. I can do it.

According to the invention described in claim 3, in addition to the effect of the invention described in claim 2, since the DMA request signal is centrally managed by the arbiter circuit before the main controller, a load is imposed on the main controller. Without D
MA control can be performed.

According to the invention described in claim 4, in addition to the effect of the invention described in claim 1, it can be realized by adding a simple timer circuit.

According to the invention described in claim 5, in addition to the effect of the invention described in claim 3, the time during which no other DMA controller having a higher priority requests or executes DMA processing is counted. Since the DMA request signal from the DMA controller is delayed by a predetermined time, the DMA processing having a low priority and having no problem even if the execution is slightly delayed is dispersed, thereby giving the main controller an appropriate processing time. be able to.

According to the invention described in claim 6, in addition to the effect of the invention described in claim 1, it is possible to control the presence / absence of immediate execution of the DMA processing having a low priority in accordance with the load state of the main controller. Therefore, the software can be processed efficiently and smoothly.

According to the invention of claim 7, in addition to the effect of the invention of claim 6, the main controller is
In a situation where continuous processing is required, unnecessary DMA processing requests from the DMA controller are blocked, and DMA processing can be permitted when the processing is completed.

According to the invention described in claim 8, in addition to the effect of the invention described in claim 3, the circuit configuration can be simplified.

According to the ninth aspect of the present invention, for the DMA processing having a low priority and having no problem even if the execution is delayed, the DMA request signal from the corresponding DMA controller is temporarily suppressed. While the suppression is being performed, the processing of the main controller can be prioritized and continuously executed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a DMA control circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing each signal input to and output from the suppression circuit of FIG. 1 and a part of a transmission path.

FIG. 3 is a flowchart showing processing contents in the suppression circuit according to the same embodiment.

FIG. 4 is a timing chart illustrating an operation content of each signal according to the same embodiment.

FIG. 5 is a block diagram showing a configuration of a DMA control circuit according to a second embodiment of the present invention.

FIG. 6 is a diagram showing each signal input to and output from the suppression circuit of FIG. 5 and a part of a transmission path.

7 is a diagram showing the configuration of a logic circuit provided in the suppression circuit of FIG.

FIG. 8 is a flowchart showing processing contents in the suppression circuit according to the same embodiment.

FIG. 9 is a timing chart illustrating the operation content of each signal according to the same embodiment.

FIG. 10 is a block diagram illustrating the configuration of a general DMA control circuit.

11 is a flowchart showing the processing contents of DMA control executed by the arbiter of FIG.

12 is a timing chart illustrating the operation content of each signal transmitted and received by the circuit of FIG.

[Explanation of symbols]

11, 11 ', 11 "... DMA integrated controller 12, 12 '... CPU 13 ... Memory 21-24 ... DMA controller 25 ... Arbiter 33, 34 ... Suppression circuit 43, 44 ... Suppression circuit 51 ... AND circuit 52 ... Inverter

Claims (9)

[Claims] 1. A memory, a main controller that executes processing using the memory, a DMA controller that directly executes processing using the memory without going through the main controller, and a DMA controller provided for the DMA controller. , Suppressing means for temporarily suppressing a DMA request signal output from the DMA controller to the main controller and requesting an access right to the memory.
MA controller. 2. The DMA controller according to claim 1, further comprising a plurality of DMA controllers, wherein the suppressing means is provided for at least one of the plurality of DMA controllers. 3. An arbiter circuit for arbitrating access rights to the memory between the main controller and a plurality of DMA controllers, wherein the suppressing means outputs the DMA request signal output from the DMA controller to the arbiter circuit. 3. The DMA control device according to claim 2, wherein the DMA controller is temporarily suppressed. 4. The DM according to claim 1, wherein the suppressing means delays the DMA request signal from the DMA controller by a predetermined time and outputs it to the main controller.
A control device. 5. The suppressing means counts a state in which a DMA request signal is not output from a DMA controller directly connected to the arbiter circuit without passing through the suppressing means, until the count value reaches a predetermined value. 4. The DMA control device according to claim 3, wherein the output of the DMA request signal is delayed. 6. The DMA control according to claim 1, wherein the suppressing means temporarily blocks a DMA request signal output from the DMA controller to the main controller in response to a signal from the main controller. apparatus. 7. The suppressing means outputs D from the DMA controller when a signal is output from the main controller.
7. The DM according to claim 6, wherein the interruption of the DMA request signal is delayed when the MA request signal is output.
A control device. 8. The DMA controller according to claim 3, wherein the suppressing means and the arbiter circuit are integrated into a hardware circuit. 9. A memory, a main controller that executes a process using the memory, and a DMA that directly executes the process using the memory without going through the main controller.
DMA in DMA controller with controller
A control method, wherein a DMA requesting an access right to the memory output from the DMA controller to the main controller
D characterized by temporarily suppressing the output of the request signal
MA control method.