JP2003255884A - Display device, its image signal processor and driving controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device which displays video with better picture quality than a conventional case and to provide its image signal processor and a driving controller. <P>SOLUTION: The display device is provided with a display panel 301 which is provided with display elements arranged in a matrix manner and driven through a plurality of row and column wiring, a scanning circuit 302 which scans the row wiring and a modulation circuit 303 which supplies modulation signals to the column wiring based on image data. The device is also provided with a correcting circuit 304 which conducts correction processes for the image data to compensate for the fluctuation in display luminance caused by voltage drop generated by the resistivity of the row wiring and luminance control circuits 306A, 306B and 306C which control the display luminance of the panel based on the luminance information of the image data. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device such as a television receiver or a display device of a computer for receiving a video signal of a television signal or a computer and displaying an image, an image signal processing device and drive control therefor. Regarding the device.

More specifically, the decrease in the drive voltage effectively applied to the display element due to the electric resistance of the matrix wiring of the display panel is corrected, and the display element is driven with an appropriate drive voltage. The present invention relates to a display device, an image signal processing device and a drive control device therefor.

[0003]

2. Description of the Related Art A cold cathode device is one of the display devices.
An example of a display device provided with a cold cathode element is disclosed in Patent Document 1 (Patent Document 2). The display device described in this publication calculates the correction data by a statistical calculation in order to correct the decrease in luminance due to the voltage drop due to the wiring resistance of the electrical connection wiring to the cold cathode element, and calculates the required electron beam value. And a correction value are combined.

The structure of the display device described in this publication is shown in FIG. The structure relating to the correction of data in this device is roughly as follows.

First, the adder 1206 adds the luminance data for one line of the digital image signal and outputs the added value to the memory 1207, whereby the correction data corresponding to the added value is read from the memory 1207. On the other hand, the digital image signal is serial / parallel converted in the shift register 1204, held in the latch circuit 1205 for a predetermined time, and then input to a multiplier 1208 provided for each column wiring at a predetermined timing. Multiplier 12
08, the luminance data and the correction data read from the memory 1207 are multiplied for each column wiring to generate corrected data, and the corrected data is transferred to the modulation signal generator 1209. The modulation signal generator 1209 generates a modulation signal corresponding to the corrected data. An image is displayed on the display panel based on this modulation signal. Here, adder 1
Like the summing process of the luminance data of one line of the digital image signal in 206, statistical calculation processing such as calculating a sum or average is performed on the digital image signal, and correction is performed based on this value. ing.

[0006]

[Patent Document 1] JP-A-8-248920

[Patent Document 2] US Pat. No. 5,734,361

[0007]

However, in the conventional voltage drop correction, ABL (Automatic Bright) is generally used.
It did not support the processing for power limitation called ness limiter).

Further, when the voltage drop correction is performed, the signal processing for accurately calculating the current (anode current) of the high voltage power supply is not performed.

An object of the present invention is to realize ABL even when voltage drop correction is performed, and further to realize voltage drop correction with high accuracy.

Another object of the present invention is to provide a display device capable of calculating a current (anode current) of a high voltage power source and performing accurate ABL, and an image signal processing device and a drive control device therefor. It is in.

[0011]

SUMMARY OF THE INVENTION The gist of the present invention is to scan a row panel and a display panel provided with display elements arranged in a matrix and driven through a plurality of row wirings and column wirings. In a display device including a scanning unit and a modulation unit that supplies a modulation signal to the column wiring based on image data, a fluctuation in display luminance due to an influence of a voltage drop caused by at least a resistance of the row wiring is compensated. And a brightness control unit for controlling the display brightness of the display panel based on the brightness information of the image data.

In the present invention, the brightness control means is
The drive voltage applied to the display panel may be changed according to the brightness information.

It is preferable that the brightness control means changes the drive voltage applied to the display panel according to the brightness information and changes the correction processing parameter in the correction means.

The brightness control means may change the brightness level of the image data before or after the correction processing according to the brightness information.

Further, there is further provided a coefficient calculation means for determining a coefficient for keeping the width of the image data after the correction processing within a predetermined range, and the brightness control means has the coefficient and the brightness. The display brightness of the display panel may be changed based on the information.

Further, the image processing apparatus further comprises coefficient calculating means for determining a coefficient for keeping the width of the image data after the correction processing within a predetermined range, and the brightness control means has the coefficient and the brightness. A value obtained from the information may be compared with a predetermined luminance limit reference value, and the luminance level of the image data after the correction processing may be changed based on the comparison result.

Further, the display panel is a display panel having a common anode electrode, and further has coefficient calculating means for determining a coefficient for keeping the width of the image data after the correction processing within a predetermined range. From the integrated value of the image data and the coefficient, a value corresponding to the current value flowing in the anode electrode is calculated, and the calculated value is compared with a predetermined brightness limit reference value, and the comparison result is obtained. Based on, the display brightness of the display panel may be changed.

Further, the brightness control means changes the display brightness of the display panel according to the brightness information and the set brightness limit reference value, and the brightness limit reference value of the display device is changed. It can be changed by at least one of power consumption, user interface means, or external environment detection means.

Another gist of the present invention is to provide a display panel having display elements arranged in a matrix and driven through a plurality of row wirings and column wirings, a scanning means for scanning the row wirings, and In an image signal processing device for processing image data to be input to a display device, which has a modulation means for supplying a modulation signal to the column wiring based on incoming image data, at least generated by a resistance component of the row wiring. A correction means for compensating for a change in display brightness due to the influence of a voltage drop, and a correction means for applying the image data, and the image data for controlling the display brightness of the display panel based on the brightness information of the image data. And a brightness control means for changing the brightness level of.

Still another skeleton of the present invention is a display panel having display elements which are arranged in a matrix and driven through a plurality of row wirings and column wirings, and scanning means for scanning the row wirings. In a drive control device for controlling the drive of a display device having a modulation means for supplying a modulation signal to the column wiring based on incoming image data, at least a voltage drop caused by a resistance component of the row wiring The correction process to compensate the fluctuation of the display brightness due to the influence,
And a brightness control unit for changing the drive voltage of the display panel to control the display brightness of the display panel based on the brightness information of the image data. .

In the present invention, the parameter of the correction process may be changed according to the change of the drive voltage.

Another skeleton of the present invention is a display panel having display elements arranged in a matrix and driven through a plurality of row wirings and column wirings, and a scanning means for scanning the row wirings. In the image signal processing method for processing the image data to be input to the display device, the modulating means supplying a modulation signal to the column wiring based on the incoming image data, at least by the resistance of the row wiring. A correction process for compensating for a change in display brightness due to the influence of a voltage drop that occurs is applied to the image data, and the display brightness of the display panel is controlled based on the brightness information of the image data. A brightness control step of changing the brightness level of the image data.

Still another skeleton of the present invention is a display panel having display elements which are arranged in a matrix and driven through a plurality of row wirings and column wirings, and scanning means for scanning the row wirings. In a drive control method for controlling the drive of a display device having a modulation means for supplying a modulation signal to the column wirings based on incoming image data, a voltage drop caused by at least the resistance of the row wirings The correction process to compensate the fluctuation of the display brightness due to the influence,
And a brightness control step of changing a drive voltage of the display panel to control display brightness of the display panel based on brightness information of the image data. .

Here again, according to the change of the driving voltage,
The parameters of the correction processing may be changed.

[0025]

FIG. 1 is a block diagram for explaining a display device according to some preferred embodiments of the present invention.

In FIG. 1A, 301 is a display panel, 302 is a scanning circuit, 303 is a modulation circuit, 304 is a correction circuit as a correction means for correcting a voltage drop, and 305 is brightness information of input image data. Detection circuit, 306
A is a control circuit for performing drive control according to the detected brightness information.

Incoming image data is subjected to a voltage drop correction process, which will be described later, by a correction circuit 304, and is supplied to a modulation circuit 303 which is a driving means of the display panel 301.

On the other hand, the detection circuit 305 detects, for example, the brightness information of the image of one frame from the input image data.
The detected brightness information is input to the control circuit 306A, and the control circuit 306A performs a process of changing the driving voltage applied to the display panel 301 by the driving unit.

According to this embodiment, ABL (automatic
It is possible to favorably perform the voltage drop correction while controlling the display brightness of the display panel such as the brightness limiter).

The display device shown in FIG. 1B is a modification of the details of the display device shown in FIG.
06B not only performs the same process of changing the drive voltage as the control circuit 306A, but also changes the parameter for the voltage drop correction process according to the changed drive voltage, and substantially corrects the correction amount by the voltage drop correction process. Drive control and signal processing control such as adjusting.

According to the present embodiment, the voltage drop correction can be performed more accurately and satisfactorily while controlling the display brightness of the display panel such as ABL.

The display device shown in FIG. 1C is a modification of the details of the display device shown in FIG.
06C performs signal processing control such as changing a parameter for voltage drop correction processing or substantially adjusting a correction amount by the voltage drop correction processing according to the detected luminance information. The control circuit 306C is a circuit that determines a coefficient (gain) for changing and adjusting the brightness level of image data, for example. The determined gain may be used for gain adjustment of the image data before the voltage drop correction process,
It may be used for gain adjustment of the image data after the voltage drop correction processing.

According to this embodiment, the voltage drop correction can be performed more accurately and favorably while the display brightness control of the display panel such as the ABL is performed, and the brightness control can be performed only by processing the image data. The voltage drop can be corrected. Therefore, it is a more preferable form when the detection circuit 305, the correction circuit 304, and the control circuit are realized by a one-chip semiconductor integrated circuit, or when those functions are executed by software.

As described above, the control circuits 306A, 306
B and 306C function as a brightness control unit that controls the display brightness of the display panel 301.

The change of the driving voltage can be easily realized by selecting the reference voltage applied to the display element by the switch of the driving means, for example. The reference voltage is a multi-level voltage that determines a selection potential and a non-selection potential of a scanning signal, a display potential and a non-display potential of a modulation signal, and the like. Alternatively, the reference voltage may be an anode voltage that determines the potential of the anode electrode in the display panel using the electron-emitting device as the display device. Here, adjustment is performed to change at least one of these potentials.

The brightness information is the APL (average pi) in a broad sense.
cture level), that is, the average brightness level of all the pixels in one frame, the integrated value of the image data of all the pixels in one frame, or the average brightness level of a large number of pixels appropriately selected from all the pixels in one frame Alternatively, it is an integrated value of pixel data of many pixels. Luminance information such as APL is A
It is suitable for performing BL control.

In particular, when the integrated value is used as the brightness information, the current value corresponding to the actual display brightness of one frame of the display panel is obtained from the coefficient and the integrated value used for changing the brightness level of the image data. Since it was found that good control can be performed based on this coefficient and the integrated value. The details will be described later.

In the above description, the detection circuit 305 has been described as detecting the brightness information from the input image data. However, other information such as the display mode and the input source of the image data is used as the detected brightness information. It may be one that does. By doing so, it is possible to perform the brightness control in which the voltage drop correction is effective according to the display mode and the input source.

Further, a gain calculating means for determining a gain for keeping the width of the image data after the correction processing within a predetermined range is provided, and a limiter for limiting the maximum width of the image data is provided as necessary. It is also preferable.

Then, the value obtained from the gain and the luminance information is compared with a predetermined luminance limit reference value, and the display luminance level of the display panel may be changed based on the comparison result.

The voltage drop correction is mainly the drive voltage that should be originally applied to the display element due to the voltage drop due to the electric resistance of the wiring connected to the selected display element and the current flowing therethrough. This is a process for compensating for a difference generated between the applied voltage applied to the. As the processing, a method of correcting the image data itself before being modulated by the modulation circuit is preferably used. For example,
For the drive voltage "+5" for displaying image data of a certain brightness level (for example, "+5"), the voltage "+" for displaying the brightness level "+4" is the actual applied voltage due to the voltage drop.
If it becomes 4 ”, the brightness level is“ + ”.
Correction is performed to change the image data of "5" to the image data of brightness level "+6". By doing this, the actual applied voltage becomes "+5" instead of "+6" due to the voltage drop.
The brightness level "+5" that is originally desired to be displayed is displayed. In reality,
Even if the brightness level does not necessarily match "+5", it is sufficient that the brightness level can be compensated for as close as possible. In the case of line-sequential driving of a matrix display panel, the voltage drop due to the resistance of the scanning wiring (row wiring) is the largest, but the amount of current flowing in another display element on the same selection line or ,
The amount of voltage drop also varies depending on the spatial distribution. Furthermore, in the case where pulse width modulation is performed in one horizontal scanning period, the amount of voltage drop varies depending on the temporal distribution of the current within one horizontal scanning period for the same reason.

When performing such a voltage drop correction, A
If brightness adjustment such as BL is also used, the accuracy of voltage drop correction may fluctuate and decrease.

The display device of the present embodiment and the image signal processing device and drive control device thereof suppress such variations.
It is possible to perform more accurate voltage drop correction.

In the case of the configuration shown in FIG. 1B, the control circuit 306B controls the selection potential when the scanning circuit 302 sequentially selects the row wiring and the modulation potential when the modulation circuit 303 modulates. It is preferable to include a correction image data calculation unit having a function of updating a calculation parameter for calculating correction image data according to a drive voltage represented as a difference voltage of (display potential). Alternatively, the calculation parameter such as the gain by which the output of the correction circuit 304 is multiplied may be changed.

As the detection circuit 305, an average brightness detection circuit for detecting the average brightness level of the input image data is provided, and the control circuit 306B has a drive voltage adjusting function for setting a drive voltage based on the average brightness level. Is preferred.

Alternatively, the control circuit 306B has a plurality of display modes including at least a mode giving priority to brightness and a mode giving priority to power consumption, and a drive voltage adjusting function for setting a drive voltage based on the selected display mode. It is preferable to have

Further, the control circuit 306B includes a video signal input terminal for a television and a video input terminal for a computer, and which terminal (video source) is supplying the video to be displayed. Based on this, it is preferable to have a drive voltage adjusting function for setting the drive voltage.

The drive voltage adjusting function may be a function of varying the selection potential when the scanning circuit 302 sequentially selects the row wirings, and / or a function of varying the modulation potential output from the modulation circuit 303. It is suitable.

The corrected image data calculation means is a voltage drop amount calculation means for predicting a voltage drop in the row wiring with respect to the input image data, and a brightness reduction amount for predicting a decrease in brightness due to the voltage drop from the voltage drop amount. It is preferable to include a calculation unit and a correction amount calculation unit that calculates a correction amount to be applied to the input image data from the brightness reduction amount.

It is preferable that the voltage drop amount calculating means updates the element current, which is a calculation parameter used when calculating the voltage drop amount in the row wiring, corresponding to the drive voltage.

The voltage drop amount calculating means sets a plurality of reference times during one horizontal scanning period in accordance with the input image data, and further sets a plurality of reference points along the selected row wiring, It is preferable to predictively calculate the voltage drop amount at the reference point that should occur at a plurality of reference times.

It is preferable that the brightness decrease amount calculating means predictively calculates the horizontal position where the voltage drop amount calculating means calculates the voltage drop amount and the brightness decrease amount corresponding to a plurality of reference times.

The correction amount calculation means presets a plurality of reference points calculated by the brightness reduction amount calculation means at a plurality of discrete horizontal display positions called reference points from the brightness reduction amounts occurring at a plurality of reference times. It is preferable to calculate the corrected image data for the plurality of image data values thus obtained.

The correction image data calculating means interpolates the discrete correction image data calculated by the correction amount calculating means to calculate the correction image data corresponding to the size of the input image data and its horizontal display position. It is preferable to further include an interpolation circuit.

The display element is an electron emitting element capable of emitting electrons according to an applied drive voltage, an organic EL (electrol).
(uminescence) and an EL element having a light-emitting body typified by an inorganic EL, or an LED element is preferable.

The electron-emitting device is preferably a cold cathode device.

The cold cathode device is preferably a surface conduction type emission device, a field emission type device, or the like, and the CNT (Ca
Rbon Nano-Tube) and GNF (Graphite Nano Fiber) typified by using a carbon-based nanostructure as an electron-emitting material are preferably used.

It is preferable to provide a fluorescent member that emits fluorescence when electrons emitted from the electron-emitting device collide with each other.

The display panels are arranged in a matrix,
It is preferable to include a display element driven via a row wiring (scanning wiring) and a column wiring (modulation wiring).

Preferred embodiments of the present invention will be illustratively described in detail below with reference to the drawings. However, the dimensions, materials, shapes, relative arrangements, and the like of the components described in this embodiment are not intended to limit the scope of the present invention to them unless otherwise specified. Absent.

(First Embodiment) In the present embodiment, in a display device in which cold cathode elements as display elements are arranged in a simple matrix, a voltage drop occurs due to the current flowing into the scanning wiring and the wiring resistance of the scanning wiring. In view of the phenomenon that the generated image is deteriorated and the display image is deteriorated, the present invention relates to a display device including a processing circuit that corrects the influence of the voltage drop in the scanning wiring on the display image, and particularly, it is realized with a relatively small circuit scale. To do.

Correction circuit (voltage drop correction circuit) for compensating for the amount of decrease in the applied voltage due to the voltage drop described here.
Is a method for calculating deterioration of a display image caused by a voltage drop according to input image data, obtaining correction data for correcting the deterioration, and correcting the image data.

In the present embodiment, from another viewpoint of reducing the power consumption during display, the drive voltage (scanning potential and modulation potential at the time of selection) applied to the cold cathode element in accordance with the average luminance level of the input video signal. The voltage drop can be properly corrected even when the brightness is limited by controlling the difference voltage).

An embodiment in which the surface conduction electron-emitting device is used as a display device will be described below.

(Overview of Display Device) FIG. 2 is a perspective view of a display panel used in the display device according to the present embodiment, in which a part of the panel is cut away to show the internal structure. In the figure, 1005 is a rear plate, 1006 is a side wall,
1007 is a face plate. Rear plate 10
05, the side wall 1006, and the face plate 1007 form an airtight container for maintaining a vacuum inside the display panel.

The rear plate 1005 has a substrate 1001.
Is fixed. A cold cathode device 1002 is provided on this substrate.
Are formed by N × M. Row wiring (scan wiring) 100
3, the column wiring (modulation wiring) 1004 and the cold cathode element (display element) are connected as shown in FIG. Such a connection structure is called a simple matrix.

A fluorescent film (fluorescent member) 1008 is formed on the lower surface of the face plate 1007. Since the display device according to the present embodiment is a color display device,
The fluorescent film 1008 is separately coated with phosphors of three primary colors of red, green and blue used in the field of CRT. The phosphor is formed in a matrix corresponding to each pixel (picture element) of the rear plate 1005, and forms a pixel at a position irradiated with an electron (emission current) emitted from the cold cathode element. Is configured.

A metal back 1 is formed on the lower surface of the fluorescent film 1008.
009 is formed.

Hv is a high voltage terminal and is a metal back 100.
9 is electrically connected. By applying a high voltage (anode potential) to the Hv terminal, the rear plate 1005
And a high voltage is applied between the face plate 1007 and the face plate 1007.

In this embodiment, a surface conduction electron-emitting device was manufactured as a cold cathode device in the above display panel. A field emission type element can also be used as the cold cathode element. Further, as the display element, an element other than the cold cathode element, for example, an element such as an EL element which emits light by itself can be preferably used.

(Characteristics of Surface Conduction Type Emitting Element) The surface conduction type emitting element has the characteristics of (emission current Ie) vs. (element applied voltage Vf) and (element current If) vs. (element applied voltage Vf) as shown in FIG. ) Has characteristics. Since the emission current Ie is significantly smaller than the device current If and it is difficult to draw the same current scale, the two graphs are shown on different scales.

The surface conduction electron-emitting device has the following three characteristics regarding the emission current Ie.

First, a certain voltage (this is the threshold voltage Vth
When the above voltage is applied to the element, the emission current Ie rapidly increases, while the emission current Ie is hardly detected at a voltage lower than the threshold voltage Vth. That is, it is a non-linear element having a clear threshold voltage Vth with respect to the emission current Ie.

Second, since the emission current Ie changes depending on the voltage Vf applied to the element, the magnitude of the emission current Ie can be controlled by changing the voltage Vf.

Thirdly, since the cold cathode device has a high-speed response, the emission time of the emission current Ie can be controlled by the application time of the voltage Vf.

By utilizing the above characteristics,
The surface conduction electron-emitting device can be preferably used in a display device.

For example, in the display device using the display panel shown in FIG. 2, if the first characteristic is utilized, it is possible to sequentially scan the display screen and display. That is, a voltage equal to or higher than the threshold voltage Vth is appropriately applied to the driven element according to the desired light emission luminance, and a voltage lower than the threshold voltage Vth is applied to the non-selected element. By sequentially switching the elements to be driven, it is possible to sequentially scan the display screen for display.

By utilizing the second characteristic,
By the voltage Vf applied to the element, the emission brightness of the phosphor can be controlled and an image can be displayed.

By utilizing the third characteristic,
The light emission time of the phosphor can be controlled by the time for which the voltage Vf is applied to the element, and an image can be displayed.

In the display device of this embodiment, the amount of the electron beam of the display panel is controlled by utilizing the third characteristic to modulate the modulation signal applied to the element.

(Driving Method of Display Panel) A driving method of the display panel will be specifically described with reference to FIG.

FIG. 5 shows an example of the voltage applied to the voltage supply terminals of the scanning wiring and the modulation wiring when driving the display panel.

In the figure, the horizontal scanning period I indicates a period in which the pixels in the i-th row are caused to emit light.

In order to make the pixel on the i-th row emit light,
The scanning wiring of the i-th row is selected and its voltage supply terminal D
The selection potential Vs is applied to xi. Further, the voltage supply terminals Dxk (k = 1, 2, ... N, where k ≠ i) of the other scanning wirings are set in the non-selected state and the non-selection potential Vns is applied.

In this embodiment, the selection potential Vs is set to the voltage V
-5V which is about 30% to 50% of _SEL (see FIG. 4)
Then, the non-selection potential Vns is set to the ground potential (GND). The voltage V _SEL is a rated voltage for driving the surface conduction electron-emitting device of this embodiment.

The voltage amplitude V is applied to the voltage supply terminal of the modulation wiring.
A pulse width modulated signal of pwm is provided.

Conventionally, the pulse width of the pulse width modulation signal supplied to the j-th modulation wiring is determined according to the size of the image data of the pixel at the i-th row and the j-th column of the image to be displayed,
A pulse width modulation signal according to the size of image data of each pixel is supplied to all the modulation wirings.

On the other hand, in this embodiment, the pulse width of the pulse width modulation signal supplied to the j-th modulation wiring is set to the size of the image data of the pixel at the i-th row and the j-th column of the image to be displayed,
By determining according to the correction amount, the decrease in brightness due to the influence of the voltage drop is corrected.

In this embodiment, the voltage of the voltage Vpwm is +
Set to 0.5V _SEL .

The surface conduction electron-emitting device emits electrons when a voltage V _SEL is applied across the device as shown in FIG. 4, but does not emit electrons at a voltage lower than the voltage Vth. Further, as shown in FIG. 4, the voltage Vth is characterized by being larger than 0.5V _SEL .

Therefore, no electrons are emitted from the surface conduction electron-emitting device connected to the scanning wiring to which the non-selection potential Vns is applied. Similarly, during the period when the output of the pulse width modulator is at the ground potential (hereinafter, the output is "L").
(Referred to as a period of time)), electrons are not emitted because the voltage applied to both ends of the surface conduction electron-emitting device on the selected scanning wiring is Vs.

That is, from the surface conduction electron-emitting device on the scanning wiring to which the selection potential Vs is applied, the output of the pulse width modulation means is changed to Vpwm (hereinafter, referred to as “H” period). Electrons are emitted. When the electrons are emitted, the above-mentioned phosphor emits light in accordance with the amount of the emitted electron beam, so that it is possible to obtain the brightness according to the emission time.

(Regarding Voltage Drop in Scan Wiring) As described above, the fundamental problem to be solved is, in particular, that the potential on the scan wiring rises due to the voltage drop in the scan wiring, resulting in surface conduction type emission. This means that the voltage applied to the device is reduced and the emission current from the surface conduction electron-emitting device is reduced.

The device current for one device of the surface conduction electron-emitting device is about several hundred μA when the voltage V _SEL is applied, although it depends on the design specifications and manufacturing method of the surface conduction electron-emitting device.

When only one pixel on the selected scanning wiring is made to emit light and the other pixels are not made to emit light in a certain horizontal scanning period, the element current flowing from the modulation wiring to the selected scanning wiring is one pixel. Current (i.e., several 100 μA above). In this case, the voltage drop hardly occurs and the emission brightness does not decrease.

However, in the case where all the pixels in the selected row are made to emit light in a certain horizontal scanning period, the current for all the pixels flows from all the modulation wirings to the selected scanning wiring. The sum of this current is several hundred
The current drops from mA to several A, and the voltage drop on the scanning wiring caused by the wiring resistance of the scanning wiring cannot be ignored.

If a voltage drop occurs on the scanning wiring, the driving voltage applied to both ends of the surface conduction electron-emitting device will decrease. For this reason, the emission current emitted from the surface conduction electron-emitting device is reduced, and as a result, the emission brightness is reduced.

Specifically, consider the case where a white cross pattern is displayed on a black background as shown in FIG. 6A as a display image.

When the row L in the figure is driven, since the number of lit pixels is small, almost no voltage drop occurs on the scanning wiring of that row. As a result, a desired amount of emission current is emitted from the surface conduction electron-emitting device of each pixel, and light can be emitted with a desired brightness.

On the other hand, when the row L'in the figure is driven, all the pixels are turned on at the same time, so that a voltage drop occurs on the scanning wiring and the emission current from the surface conduction type emission element of each pixel is generated. Decrease. As a result, the luminance of the line in row L'is reduced.

As described above, the influence of the voltage drop changes due to the difference in the image data for each horizontal line. Therefore, when the cross pattern as shown in FIG. 6A is displayed, the pattern shown in FIG. The image like was displayed.

This phenomenon is not limited to the cross pattern, but occurs even when a window pattern or a natural image is displayed.

Further, more complicatedly, the magnitude of the voltage drop has the property of changing within one horizontal scanning period by performing modulation by pulse width modulation.

For example, as shown in FIG. 5, when the rising edges of the pulse width modulation signals supplied to the respective columns are synchronized, it generally depends on the input image data, but in general, one horizontal scanning period The number of pixels that were lit at the beginning was large,
After that, the light is turned off in order from a place having a low brightness, and thus the number of lighted pixels decreases with time in one horizontal scanning period. Therefore, the magnitude of the voltage drop generated on the scan wiring also tends to decrease gradually toward the beginning of one horizontal scanning period. The pulse width modulation signal is the modulation 1
Since the output changes every time corresponding to the gradation, the temporal change of the voltage drop also changes every time corresponding to one gradation of the pulse width modulation signal.

(Calculation Method of Voltage Drop) In order to obtain the correction amount for reducing the influence of the voltage drop, the first step is the hardware for predicting the magnitude of the voltage drop and its time change in real time. Good.

However, as the display panel of the display device,
It is common to have thousands of modulation wirings, and it is very difficult to calculate the voltage drop at the intersection of all the modulation wirings and the scanning wiring, and the hardware to calculate it in real time is created. To do is not realistic.

On the other hand, as a result of the examination of the voltage drop by the inventors, it has been found that the following features are provided.

I) At a certain point in one horizontal scanning period, the voltage drop generated on the scanning wiring is a spatially continuous amount on the scanning wiring, which is a very smooth curve.

Ii) The magnitude of the voltage drop varies depending on the display image and changes at each time corresponding to one gradation of pulse width modulation. Generally, the larger the rising portion of the pulse, the longer the time. Will it get smaller over time,
Or, the size is maintained.
That is, the driving method as shown in FIG. 5 does not increase the magnitude of the voltage drop in one horizontal scanning period.

Therefore, the following approximate model is used to simplify the calculation.

First, from the characteristic of i), when calculating the magnitude of the voltage drop at a certain point of time, it is approximated by a degenerate model in which thousands of modulation wirings are concentrated in several to several tens of modulation wirings. The calculation is simplified as follows (this will be described in detail in the calculation of the voltage drop by the degenerate model below).

From the characteristic of ii), a plurality of times are set in one horizontal scanning period, and the voltage drop is calculated for each time to roughly predict the time change of the voltage drop.

Specifically, the time change of the voltage drop was roughly predicted by calculating the voltage drop by the degenerate model described below for a plurality of times.

(Calculation of voltage drop by degenerate model) FIG. 7
(A) is a figure for demonstrating the concept of the block and node for approximating a degeneration model. In the same figure, for simplification of the drawing, only the selected scanning wiring, each modulation wiring, and the surface conduction electron-emitting device connected to the intersection thereof are shown.

At a certain time in one horizontal scanning period, the lighting state of each pixel on the selected scanning wiring (that is, whether the output of the modulating means is "H" or "L"). Is known. In this lighting state, the device current flowing from each modulation wiring to the selected scanning wiring is expressed by Ifi (i = 1, 2, ... N; i is a column number).
It is defined as

Further, as shown in the figure, n modulation wirings, a portion of the selected scanning wirings which intersects with the n modulation wirings, and n surface conduction emission devices arranged at the intersections thereof. A block is defined as a group of elements.
In this embodiment, the blocks are divided into four blocks.

A position called a node is set at the boundary position of each block. A node is a horizontal position (reference point) for discretely calculating the amount of voltage drop that occurs on the scan wiring in the degenerate model. That is, each block includes n surface conduction electron-emitting devices connected to the area of the scanning wiring divided by the node (reference point).

In this embodiment, five nodes, node 0 to node 4, are set at the boundary positions of blocks.

FIG. 7B is a diagram for explaining the degenerate model.

In the degenerate model, n modulation wirings included in one block in FIG. 10A were degenerated to one, and they were connected so as to be located at the center of the scanning wiring block.

Further, a current source is connected to the centralized modulation wiring of each block, and the total sum (statistical amount) IF0 to IF3 of the current in each block flows from each current source.

That is, IFj (j = 0, 1, ... 3) is
It is a current represented by (Equation 1).

[Equation 1]

Further, the potentials at both ends of the scanning wiring are shown in FIG.
In the example of (1), Vs is set to Vs, whereas in the same figure (b), the GND potential is set for the following reason. In the degenerate model,
By modeling the current flowing from the modulation wiring to the selected scanning wiring with the current source, the voltage drop amount of each part on the scanning wiring is calculated by calculating the voltage (potential difference) of each part with the feeding part as the reference potential. Because you can.

Further, the surface conduction electron-emitting device is omitted regardless of the presence or absence of the surface conduction electron-emitting device as long as an equivalent current flows from the modulation wiring when viewed from the selected scanning wiring. This is because the generated voltage drop itself does not change. Therefore, here, the current value flowing from the current source of each block is the current value IF of the sum of the element currents in each block.
The surface conduction electron-emitting device was omitted by setting j.

Further, the wiring resistance of the scanning wiring of each block is set to n times the wiring resistance r of the scanning wiring in one section (here, one section is defined as a portion of the scanning wiring from the intersection with a certain modulation wiring. It refers to the portion up to the intersection with the adjacent modulation wiring, and the wiring resistance of the scanning wiring in each section is assumed to be uniform here.).

In such a degenerate model, the voltage drop amounts DV0 to DV generated at each node on the scanning wiring.
4 can be easily calculated by the following product-sum formula.

[Equation 2]

That is, the voltage drop amount DVi (i = 0,
1, 2, 3, 4) are represented by (Formula 2).

[Equation 3]

However, aij is a voltage generated at the i-th node when a unit current is injected into only the j-th block in the degenerate model (hereinafter, this is defined as aij).

Aij can be easily derived as follows by Kirchhoff's law.

That is, in FIG. 7B, the wiring resistance from the current source of the block i to the supply terminal on the left side of the scanning wiring is rli (i = 0, 1, 2, 3, 4), and the supply terminal on the right side. Wiring resistance up to rri (i = 0, 1, 2, 3,
4) If the wiring resistance between the block 0 and the left supply terminal and the wiring resistance between the block 4 and the right supply terminal are both defined as rt, then it is as follows.

[Equation 4]

Further, by setting a, b, c and d as follows,

[Equation 5] aij can be easily derived as in (Equation 3). However, in (Equation 3), A // B is a symbol representing the resistance value of the resistance A and the resistance B in parallel, and A // B = A × B /
(A + B).

[Equation 6]

Even when the number of blocks is not 4, the expression (2) can be easily calculated according to Kirchhoff's law by considering the definition of aij. Further, even when the power supply terminals are not provided on both sides of the scanning wiring as in the present embodiment and only one side is provided, the calculation can be easily performed by performing the calculation according to the definition of aij.

The parameter aij defined by (Equation 3) does not need to be recalculated each time the calculation is performed.
It should be calculated once and stored as a table.

Further, the summation currents IF0 to IF3 of each block defined by (Equation 1) are approximated by the following (Equation 4). However, in (Equation 4), Count
i takes 1 when the i-th pixel on the selected scanning wiring is in a lighting state, and 0 when it is in a non-lighting state.
Is a variable that takes

[Equation 7]

IFS is an amount obtained by multiplying a device current IF flowing when a drive voltage is applied across one device of the surface conduction electron-emitting device by a coefficient α having a value between 0 and 1. That is, it is defined as in (Equation 5).

[Equation 8]

According to (Equation 4), the element current proportional to the number of lighting in the block flows from the modulation wiring of each block into the selected scanning wiring. At this time, the element current IF of one element is multiplied by the coefficient α to obtain the element current I of one element.
The FS is taken into consideration that the amount of the device current decreases due to the increase in the voltage of the scanning wiring due to the voltage drop.

If the drive voltage applied across the surface conduction electron-emitting device is V _DRV , the drive voltage V _DRV
When is changed, the value of the device current IF used in (Equation 5) may be updated according to the actual value of the voltage V _DRV and the calculation may be performed.

FIG. 7C shows an example of the result of calculation of the voltage drop amounts DV0 to DV4 of each node by the degeneration model in a certain lighting state.

Since the voltage drop has a very smooth curve, it is assumed that the voltage drop between the nodes approximately takes the value shown by the dotted line in the figure.

By using the degenerate model as described above, it is possible to calculate the voltage drop for each node at a desired time point with respect to arbitrary image data.

As described above, the amount of voltage drop in a certain lighting state was simply calculated using the degeneration model.

The voltage drop generated on the selected scanning wiring changes with time within one horizontal scanning period, but as described above, this may occur at some time (reference time) during one horizontal scanning period. On the other hand, the lighting state at that time was obtained, and it was predicted by calculating the voltage drop using the degeneration model for the lighting state. Note that the number of lights in each block at a certain point in one horizontal scanning period can be easily obtained by referring to the image data of each block.

As an example, consider a case where the number of bits of input data to the pulse width modulation circuit is 8 bits and the pulse width modulation circuit outputs a linear pulse width with respect to the size of the input data. That is, when the input data is 0, "L" is output for one horizontal scanning period, and the input data is 255.
When the input data is 128, "H" is output during one horizontal scanning period, and when the input data is 128, "H" is output during the first half period, and "L" is output during the second half period. Output.

In such a case, the number of lights at the rise time (start time) of the pulse width modulation signal can be easily detected by counting the number of input data to the pulse width modulation circuit which is larger than zero. Similarly, the number of lights at the center time of one horizontal scanning period can be easily detected by counting the number of input data to the pulse width modulation circuit which is larger than 128. In this way, by comparing the image data with respect to a certain threshold value and counting the number of true outputs of the comparator, the number of lightings at any time can be easily calculated.

Here, in order to simplify the following description, a time amount called a time slot is defined.

The time slot represents the time from the rise of the pulse width modulation signal in one horizontal scanning period, and the time slot = 0 is the time immediately after the start time (rise in this case) of the pulse width modulation signal. Is defined as. Time slot = 64 is defined to represent the time when 64 gradations have elapsed from the start time of the pulse width modulation signal. Similarly, time slot = 128 is defined to represent the time when 128 gradations have elapsed from the start time of the pulse width modulation signal.

In the present embodiment, the example in which the pulse width from the rising time of the pulse is used as the reference is shown as an example. However, even when the pulse width is modulated using the falling time of the pulse as the reference, the time axis , But the direction of the time slot is opposite, but it can be considered in the same manner as above.

(Calculation of Correction Data from Voltage Drop Amount) As described above, the time change of the voltage drop during one horizontal scanning period is approximately and discretely calculated by repeatedly performing the degeneracy model. You can

FIG. 8 shows an example in which the voltage drop is repeatedly calculated for certain image data, and the time change of the voltage drop in the scanning wiring is calculated. The voltage drop shown here and its change with time are examples for one image data, and it is natural that the voltage drop for another image data has another change.

In the figure, time slots = 0, 64, 12
The degeneracy model was applied to each of the four time points of 8 and 192, and the voltage drop amount at each time was calculated discretely.

In FIG. 8, the voltage drop amount at each node is connected by a dotted line, but the dotted line is shown to make the diagram easy to see, and the voltage drop amount calculated by this degenerate model is □, ○, Discrete calculations were performed at the positions of each node indicated by ● and △.

FIG. 9 is a graph in which the emission current emitted from the surface conduction electron-emitting device in the lighting state is estimated when the voltage drop shown in FIG. 8 occurs on the selected scan wiring.

The ordinate represents the amount of the emission current at each time and each position as a percentage, with the magnitude of the emission current emitted when there is no voltage drop being 100%, and the abscissa represents the horizontal position. ing.

As shown in FIG. 9, at the horizontal position (reference point) of node 2, the emission current at time slot = 0 is Ie0, the emission current at time slot = 64 is Ie1, and time slot = 128. The emission current at time is Ie2, and the emission current at time slot 192 is Ie3.

The emission current was calculated from the voltage drop amount in FIG. 8 and the graph of “driving voltage vs. emission current” in FIG. That is, the graph of FIG. 9 is merely a mechanical plot of the value of the emission current when the voltage obtained by subtracting the voltage drop amount from the voltage V _DRV is applied.

Therefore, this figure only means the current emitted from the surface-conduction type emitting device in the lighting state, and the surface-conduction type emitting device in the extinguished state does not emit the current.

FIGS. 10A, 10B, and 10C are diagrams for explaining a method of calculating the correction data of the voltage drop amount from the time change of the emission current of FIG. The figure is 6
4 is an example in which correction data for image data of No. 4 is calculated.

Luminance is nothing but the amount of emitted charge obtained by temporally integrating the emission current by the emission current pulse. Therefore, in the following, in consideration of the change in luminance due to the voltage drop, description will be given based on the amount of emitted charges.

Now, the emission current when there is no influence of the voltage drop is IE, and the time corresponding to one gradation of the pulse width modulation is Δt.
Then, when the image data is 64, the emission charge amount Q0 to be emitted by the emission current pulse is obtained by multiplying the amplitude IE of the emission current pulse by the pulse width (64 × Δt) of (Equation 6). Can be expressed as

[Equation 9]

However, in reality, a phenomenon occurs in which the emission current decreases due to the voltage drop on the scanning wiring.

The amount of charge emitted by the emission current pulse considering the influence of the voltage drop can be calculated approximately as follows. The emission currents of the time slots = 0 and 64 of the node 2 are set to Ie0 and Ie1, respectively, and the time slots 0 to 64 are set.
If it is approximated that the emission current during the period changes linearly between Ie0 and Ie1, the emission charge amount Q1 during this period is shown in FIG.
The area of the trapezoid in (b), that is, it can be calculated as in (Equation 7).

[Equation 10]

Next, as shown in FIG. 10C, it is assumed that the influence of the voltage drop can be eliminated when the pulse width is extended by DC1 in order to correct the decrease in the emission current due to the voltage drop. Further, when the voltage drop is corrected and the pulse width is extended, the amount of emission current in each time slot is considered to change, but here, for simplification, as shown in FIG. = 0, the emission current is Ie0, and the emission current in the time slot = (64 + DC1) is Ie1. Further, the emission current between the time slot 0 and the time slot (64 + DC1) is approximated to take a value on a line connecting the emission currents at two points with a straight line.

Then, the emission charge amount Q2 due to the emission current pulse after correction can be calculated as in (Equation 8).

[Equation 11]

If this is equal to Q0, the following equation holds.

[Equation 12]

If this is solved for DC1, (Equation 9) is obtained.

[Equation 13]

In this way, the correction data when the image data was 64 was calculated.

That is, the size of the position of node 2 is 6
For the image data of 4, as shown in (Equation 9), D
The correction data CData may be added only for C1.

FIG. 11 is an example in which correction data for image data of size 128 is calculated from the calculated voltage drop amount.

When there is no influence of the voltage drop, the amount of emission charge Q3 emitted by the emission current pulse when the image data is 128 is (Equation 10).

[Equation 14]

On the other hand, the input charge amount due to the actual emission current pulse, which is affected by the voltage drop, can be approximately calculated as follows. Node 2 time slot =
The emission current amounts of 0, 64, and 128 are Ie0 and Ie, respectively.
1 and Ie2. Further, the emission current during the time slots 0 to 64 changes linearly between Ie0 and Ie1, and approximates to change on the line connecting Ie1 and Ie2 between the time slots 64 and 128. Then, the emitted charge amount Q4 during the time slots 0 to 128 is as shown in FIG.
The sum of the areas of the two trapezoids in (b), that is, (Equation 11)
Can be calculated as

[0171]

[Equation 15]

On the other hand, the correction amount of the voltage drop was calculated as follows. A period corresponding to the time slots 0 to 64 is defined as a period 1, and a period corresponding to the time slots 64 to 128 is defined as a period 2.
When the correction is applied, the portion of the period 1 extends by DC1 and is extended to the period 1 ', and the portion of period 2 extends by DC2,
We think that it will be extended to period 2 '. At this time, it is assumed that the amount of emitted charge becomes the same as Q0 described above by performing the correction during each period.

It is needless to say that the emission currents at the beginning and the end of each period change due to the correction, but here it is assumed that they do not change in order to simplify the calculation. That is, the emission current at the beginning of the period 1'is Ie.
0, the emission current at the end of the period 1'is Ie1, the emission current at the beginning of the period 2'is Ie1, and the emission current at the end of the period 2'is Ie2.

Then, DC1 can be calculated in the same manner as (Equation 9).

DC2 uses the same concept as above.
It can be calculated as in (Equation 12).

[Equation 16]

As a result, the size of the position of node 2 is 12
The correction data CData represented by (Equation 13) may be added to the image data of No. 8.

[Equation 17]

FIG. 12 is an example in which correction data for image data of size 192 is calculated from the calculated voltage drop amount.

The emission charge amount Q5 due to the emission current pulse expected when the image data is 192 is expressed by the following equation.

[Equation 18]

On the other hand, the amount of electric charge emitted by the actual emission current pulse, which is affected by the voltage drop, can be approximately calculated as follows. Node 2 time slot =
The emission current when 0 is Ie0, the emission current when time slot = 64 is Ie1, the emission current when time slot = 128 is Ie2, the emission current when time slot = 192 is Ie3, and the time slots 0 to 0 The emission current between 64 changes linearly between Ie0 and Ie1, changes on a straight line between Ie1 and Ie2 during time slots 64 to 128, and changes during time slots 128 to 192. If it is approximated to change on a line connecting Ie2 and Ie3 with a straight line, the input charge amount Q6 during the time slots 0 to 192 is the area of the three trapezoids of FIG. It can be calculated as Equation 14).

[Formula 19]

The period corresponding to the time slots 0 to 64 is the period 1, and the period corresponding to the time slots 64 to 128 is the period 2,128.
The period corresponding to 192 is defined as period 3. Similarly to the above, after the correction, the portion of period 1 is extended by DC1 to be extended to period 1 ', the portion of period 2 is extended by DC2 to be extended to period 2', and the portion of period 3 is DC3. It is assumed that it will be extended for a period of 3 '. On this occasion,
It is assumed that the amount of emitted charges becomes the same as Q0 described above by performing the correction in each period.

Further, it is assumed that the emission currents at the beginning and the end of each period do not change before and after the correction. That is, the emission current at the beginning of the period 1'is Ie0, the emission current at the end of the period 1'is Ie1, the emission current at the beginning of the period 2'is Ie1, the emission current at the end of the period 2'is Ie2, and the period 3 '. The emission current at the beginning is Ie2, and the emission current at the end of the period 3'is Ie3.

Then, DC1 and DC2 can be calculated similarly to (Equation 9) and (Equation 12), respectively.

DC3 can be calculated as in (Equation 15).

[Equation 20]

As a result, the size of the position of node 2 is 19
The correction data CData represented by (Equation 16) may be added to the image data of 2.

[Equation 21]

As described above, the correction data CDat of the image data 64, 128, 192 for the position of the node 2 is obtained.
a was calculated.

When the pulse width is 0, of course, there is no effect of the voltage drop on the emission current, so the correction data is set to 0 and the correction data CData is added to the image data.
Is also 0.

As described above, the correction data is calculated for the discrete image data such as 0, 64, 128, 192 in order to reduce the calculation amount. That is, if the same calculation is performed for all arbitrary image data, the amount of calculation becomes very large, and the amount of hardware for performing the calculation becomes very large. On the other hand, at a certain node position, the larger the image data, the larger the correction data tends to be. As a result, when calculating correction data for arbitrary image data, if the points near the image data for which correction data has already been calculated and the points are interpolated by linear approximation, the amount of calculation will be greatly reduced. This is because you can Note that this interpolation will be described in detail when the discrete correction data interpolation means is described.

If the same idea is applied to the positions of all the nodes, the correction data of image data = 0, 64, 128, 192 at the positions of all the nodes can be calculated.

In this embodiment, time slots 0, 64,
Applying the degenerate model to the four points 128 and 192,
By calculating the amount of voltage drop at each time, 0, 64,
The correction data for the four image data reference values of 128 and 192 could be obtained.

However, preferably, the time interval for calculating the voltage drop is made fine by the degenerate model and the reference value of the image data is set to be more large, whereby the time change of the voltage drop can be handled more accurately, and the approximate calculation can be performed. The error of can be reduced.

For example, in the present embodiment, calculation is performed only at four points of time slots 0, 64, 128, and 192, but calculation is performed every 16 time slots of time slots 0 to 255 (that is, image data). The reference value of was set every 16 by the size of the image data), and more preferable results were obtained.

At that time, based on the same way of thinking,
Calculations may be performed by modifying (Equation 6) to (Equation 16).

An example of discrete correction data for certain input image data obtained by this method is shown in FIG. In the figure, the horizontal axis corresponds to the horizontal display position, and the position of each node is described. The vertical axis represents the size of the correction data.

The discrete correction data are calculated for the positions of the nodes indicated by □, ○, ●, and △ in the figure and the size of the image data Data (image data reference value = 0, 64, 128, 192). There is something.

(Interpolation Method of Discrete Correction Data) The correction data calculated discretely is discrete with respect to the position of each node, and does not give the correction data at any horizontal position (column wiring number). Absent. At the same time, it is correction data for image data having a certain reference image data size at each node position and does not give correction data according to the actual image data size. Absent.

Therefore, the correction data suitable for the size of the input image data in each column wiring is calculated by interpolating the correction data calculated discretely.

FIG. 13B shows the image data Dat at the position x located between the node n and the node n + 1.
It is the figure which showed the method of calculating the correction data equivalent to a.

As a premise, it is assumed that the correction data has already been discretely calculated at the positions Xn and Xn + 1 of the nodes n and n + 1. Further, it is assumed that the input image data Data has a value between two image data reference values Dk and Dk + 1 for which correction data has already been calculated discretely.

Reference value D of the kth image data of node n
If the correction data for k is written as CData [k] [n], the correction data CA for the image data Dk at the position x is CData [k] [n] and CData.
By using the values of [k] [n + 1], it is possible to perform calculation as shown in (Expression 17) by linear approximation.

[Equation 22]

Further, the correction data CB of the image data Dk + 1 at the position x can be calculated as in (Equation 18).

[Equation 23]

By linearly approximating the correction data of CA and CB, the correction data CD for the image data Data at the position x can be calculated as in (Equation 19).

[Equation 24]

As described above, in order to calculate the correction data suitable for the actual position and the size of the image data from the discrete correction data, the calculation is simply performed by the method described in (Equation 17) to (Equation 19). it can.

If the correction data thus calculated is added to the image data to correct the image data and pulse width modulation is performed according to the corrected image data, the deterioration of the image quality due to the voltage drop can be reduced. Therefore, the image quality can be improved.

As for the hardware for correction, the amount of calculation can be reduced by introducing an approximation such as degeneracy, so that the hardware can be constructed with a very small scale.

(Explanation of the Function of the Entire System and Each Part) Next, the hardware of the display device incorporating the correction data calculating means will be explained.

FIG. 14 is a block diagram showing an outline of the circuit configuration. In the figure, 1 is the display panel of FIG. 2, Dx
1 to DxM and Dx1 'to DxM' are voltage supply terminals of the scan wiring of the display panel, Dy1 to DyN are voltage supply terminals of the modulation wiring of the display panel, and Hv is to apply an acceleration voltage between the face plate and the rear plate. High-voltage power supply terminal, Va is a high-voltage power supply, 2 is a scanning circuit (scanning means), 3 is a synchronization signal separation circuit, 4 is a timing generation circuit, and 7 is RGB for converting the YPbPr signal into RGB by the synchronization signal separation circuit 3. The conversion unit 17, the inverse γ processing unit, 5 the shift register for one line of image data, 6 the latch circuit for one line of image data, 8 the pulse width modulation means for outputting the modulation signal to the modulation wiring of the display panel ( Modulation means), 12 is an adder (arithmetic processing means, addition processing means), 14 is correction data calculation means, 221 is average brightness level calculation means (average brightness detection circuit), 2 2 is a driving voltage calculation unit.

In the figure, R, G, and B are RGB parallel input video data, Ra, Ga, and Ba are RGB parallel video data subjected to an inverse γ conversion process, which will be described later, and D.
ata is the image data parallel / serial converted by the data array conversion unit 9, and CD is the correction data calculation means 14.
The correction data and Dout calculated by are the image data (corrected image data) corrected by adding the correction data to the image data by the adder 12.

(Synchronous Signal Separation Circuit, Timing Generation Circuit) The display device of this embodiment is NTSC, PAL, SE.
Television signals such as CAM and HDTV, and an input video signal such as VGA output from a computer can be displayed together.

In FIG. 14, HDTV is used to simplify the drawing.
The method is described as an example.

The video signal of the HDTV system is first separated into the synchronizing signals Vsync and Hsync by the synchronizing signal separating circuit 3 and supplied to the timing generating circuit 4. The video signals that have been synchronously separated are supplied to the RGB converter 7. RG
Inside the B conversion unit 7, a low-pass filter, an A / D converter, and the like are provided in addition to the YPbPr to RGB conversion circuit. The RGB conversion unit 7 passes YPbPr through a low-pass filter and then digital R by an A / D converter.
It is converted into a GB signal and supplied to the inverse γ processing unit 17.

(Timing Generation Circuit) The timing generation circuit 4 of FIG. 14 has a built-in PLL circuit, generates a timing signal synchronized with the synchronization signals of various video sources, and generates an operation timing signal for each part. Is.

The timing signal generated by the timing generation circuit 4 is Tsft for controlling the operation timing of the shift register 5, the shift register 5 through the latch circuit 6
Control signal DataLoa for latching data to
d, pulse width modulation start signal Pwmstar of the modulation means 8
t, a clock Pwmclk for pulse width modulation, Tscan for controlling the operation of the scanning circuit 2, and the like.

(Scanning Circuit) The scanning circuits 2 and 2'of FIG.
Is a circuit that outputs the selection potential Vs or the non-selection potential Vns to the connection terminals Dx1 to DxM in order to sequentially scan the display panel 1 row by row in one horizontal scanning period.

As shown in FIG. 15, the scanning circuits 2 and 2'include a variable power source for setting the selection potential Vs on the basis of the selection potential instruction value SVs supplied from the drive voltage calculation section described later. In the present embodiment, by changing the selection potential Vs, the drive voltage of the cold cathode device arranged on the display panel 1 can be changed.

The scanning circuits 2 and 2 ′ are circuits for performing scanning by sequentially switching the selected scanning wirings every horizontal period in synchronization with the timing signal Tscan from the timing generation circuit 4.

Note that Tscan is a timing signal group made up of vertical synchronizing signals and horizontal synchronizing signals.

The scanning circuits 2 and 2'are each composed of M switches and shift registers as shown in FIG. These switches are preferably composed of transistors or FETs.

In order to reduce the voltage drop in the scanning wiring, it is effective to connect scanning circuits to both ends of the scanning wiring of the display panel 1 and drive from both ends as shown in FIG. However, the method of the present embodiment can be applied even when the scanning circuit is not connected to both ends of the scanning wiring. In that case, the above-mentioned parameter of (Equation 3) may be changed.

In FIG. 15, the selection potential Vs and the non-selection potential Vs
Although a panel driving power source for giving ns is arranged in the scanning circuit, it is also preferable to configure such a panel driving power source as an independent power source circuit separate from the scanning circuit.

(Inverse γ Processing Section) The CRT has a light emission characteristic of approximately 2.2 to the input (hereinafter referred to as an inverse γ characteristic). Such characteristics of the CRT are taken into consideration in the input video signal, and the input video signal is generally converted according to the .gamma. Characteristic of 0.45 power so as to have a linear light emission characteristic when displayed on the CRT.

On the other hand, when the display panel 1 of the display device of this embodiment is modulated by the application time of the drive voltage, it has a substantially linear light emission characteristic with respect to the length of the application time. Therefore, it is preferable to convert the input video signal based on the inverse γ characteristic (hereinafter referred to as inverse γ conversion).

FIG. 16 shows the details of the inverse γ processing section 17. The inverse γ processing unit 17 is a block for performing inverse γ conversion on the input video signal.

The inverse γ processing unit 17 of this embodiment implements the inverse γ conversion processing by a memory. The number of bits of the video signals R, G, B is set to 8 bits, and the number of bits of the video signals Ra, Ga, Ba output from the inverse γ processing unit 17 is also set to 8 bits. The inverse γ processing unit 17 is configured by using each color.

(Data Array Converting Section) The data array converting section 9 in FIG. 14 is an RGB parallel video signal of Ra and G.
It is a circuit for performing parallel / serial conversion of a and Ba in accordance with the pixel array of the display panel 1. As shown in FIG. 17, the data array conversion unit 9 has a FIFO for each RGB color.
(First In First Out) Memory 2021R, 2021
G, 2021B and selector 2022.

Although not shown in the figure, the FIFO memory includes two horizontal pixel memory words for odd lines and even lines. When the video data of the odd line is input, the data is written in the FIFO for the odd line, while the image data accumulated in the previous horizontal scanning period is read from the FIFO memory for the even line. When the video data of the even-numbered lines is input, the data is written in the FIFO for the even-numbered lines, while the image data accumulated in the previous horizontal period is read from the FIFO memory for the odd-numbered lines.

The data read from the FIFO memory is parallel / serial converted by the selector 2022 according to the pixel array of the display panel 1 and output as RGB serial image data SData. Although not described in detail, the data array conversion section 9 operates based on the timing control signal from the timing generation circuit 4.

(Adder) The adder 12 shown in FIG. 14 uses the correction data CD and the image data Da from the correction data calculating means 14.
It is a means for adding ta. The image data Data is corrected by the addition, and is transferred to the shift register 5 as the image data Dout.

It should be noted that the image data Data and the correction data C
An overflow may occur in the adder 12 when adding D. On the other hand, in the present embodiment, the image data Da
Depending on the maximum value when ta and the correction data CD are added,
The bit width of the adder 12 and the bit width of the modulator 8 after that were determined.

More specifically, in the case of the display device of the present embodiment, the maximum correction data is 120 when the image data is all 255 screens, so the maximum value of the output of the adder 12 is 255 + 120 = 375. Become. Therefore, adder 1
The number of output bits of 2 is 9 bits, and the number of bits of the modulation means is also 9
The number of bits in each part was determined as bits.

As another configuration for preventing overflow, the maximum value of the correction data to be added is estimated in advance and image data is set so that overflow does not occur when the maximum value is added. The range of values that can be taken may be reduced in advance.

In order to reduce the size of the image data, for example, the input image data may be limited when A / D-converted, or a multiplier may be provided so that the input image data has 0. The magnitude may be limited by multiplying the gain by 1 or more and less than 1.

(Delay Circuit) The image data SData rearranged by the data array converter 9 are input to the correction data calculation means 14 and the delay circuit (delay means) 19 of FIG. The correction data interpolating unit of the correction data calculating unit 14 refers to the horizontal position information x and the value of the image data SData from the timing control circuit, and calculates the correction data CD suitable for them.

The delay circuit 19 is provided to absorb the time required to calculate the correction data. When the adder 12 adds the correction data to the image data, the correction data corresponding to the correction data is correctly added to the image data. It is a means for delaying the addition. The delay circuit 19 can be configured by using a flip-flop.

(Shift register, latch circuit) Adder 1
The image data Dout, which is the output of No. 2, is serial / parallel converted from serial data format to parallel image data ID1 to IDN for each modulation wiring by the shift register 5 and output to the latch circuit 6. The latch circuit 6 latches the data from the shift register 5 by the timing signal Dataload immediately before the start of one horizontal period. The output of the latch circuit 6 is supplied to the modulation means 8 as parallel image data D1 to DN.

In this embodiment, the image data ID1 to I
Each of DN and D1 to DN is 8-bit image data. These operation timings are the timing control signals TSFT and Dataload from the timing generation circuit 4.
It is decided based on.

(Details of Modulating Means) The parallel image data D1 to DN output from the latch circuit 6 are supplied to the modulating means 8.

As shown in FIG. 18A, the modulation means 8 is a pulse width modulation circuit (PWM circuit) including a PWM counter, a comparator and a switch (FET in the figure) for each modulation wiring. .

The relationship between the image data D1 to DN and the output pulse width of the modulator 8 has a linear relationship as shown in FIG. 18 (b).

FIG. 18C shows three examples of output waveforms of the modulation means 8. In FIG. 18C, the upper waveform is the waveform when the input data to the modulating means 8 is 0, the central waveform is the waveform when the input data to the modulating means 8 is 256, and the lower waveform is the modulating waveform. This is a waveform when the input data to the means 8 is 511.

In this embodiment, the number of bits of the input data D1 to DN to the modulating means 8 is set to 9 bits in consideration of the fact that it does not overflow as described above (in the above description, the modulating means 8 is used). 18 is described as outputting a modulation signal having a pulse width corresponding to one horizontal scanning period when the input data is 511.
Although it is a very short time as shown in (c), there is a timing margin before the pulse rises and during the period when the pulse does not drive after the fall. ).

FIG. 19 is a timing chart showing the operation of the modulation means 8 of this embodiment. In the figure, Hs
sync is a horizontal synchronization signal, Dataload is a load signal to the latch circuit 6, and D1 to DN are columns 1 to N of the modulation means 8.
To the PWM counter, Pwmstart is a PWM counter synchronization clear signal, and Pwmclk is a PWM counter clock. Further, XD1 to XDN are the first to the first of the modulation means 8.
The output of the Nth column is shown.

When one horizontal scanning period starts as shown in the figure, the latch circuit 6 latches the image data and transfers the data to the modulating means 8.

The PWM counter has Pwmstart, P
Counting is started based on wmclk, and when the count value reaches 511, the counter is stopped and the count value 511
Hold.

The comparator provided for each column is
The count value of the PWM counter is compared with the image data of each column, and when the value of the PWM counter is greater than or equal to the image data, High
h is output, and Low is output during the other periods.

The output of the comparator is connected to the gates of the switches in each column, and the output of the comparator is Low.
18A, the switch on the upper side (VPwm side) of FIG. 18A is ON, and the switch on the lower side (GND side) is OFF,
The modulation wiring is connected to the voltage VPwm. Conversely, while the output of the comparator is High, the upper switch in FIG. 18A is OFF and the lower switch is ON, and
The voltage of the modulation wiring is connected to the GND potential.

The pulse width modulated signal output from the modulating means 8 is D1,
A waveform in which the rising edges of the pulses are synchronized, as shown by D2, ... DN.

(Average Brightness Level Detecting Means) The average brightness level detecting means 221 for detecting the brightness information detects the average brightness for each frame by referring to the image data Ra, Ga, Ba after the inverse γ conversion. Is a means of. The same means adds the image data of Ra, Ga, and Ba for each frame to calculate the total sum of the image data of the frame unit, and also divides the total sum of the image data of the frame unit by the number of pixels of the screen to obtain the average brightness level. To detect.

The detection of the brightness information used in the present invention is not limited to this method, and other means as described above may be used as long as the value corresponding to the average brightness level can be detected. .

The value corresponding to the average brightness level may be calculated by dividing the total sum of the image data by an appropriate fixed value instead of the number of pixels on the screen. In this case, if a power of 2 is used as the fixed value, the division can be performed by the bit shift operation, and the hardware can be simplified.

The average brightness level has the same meaning as APL (Average Picture Level) which is generally said.

(Drive Voltage Calculation Unit) Drive voltage calculation unit 222
Is a drive voltage calculation means for calculating a drive voltage instruction value based on the average brightness calculated by the average brightness level detection means 221. Calculated drive voltage instruction value SV
_As shown in FIG. 14, the _DRV is supplied to the correction data calculating means 14 which will be described later, while the _DRV is supplied to the scanning circuits 2 and 2 as a selection potential instruction value SVs obtained by subtracting the modulation potential from the driving voltage. Supplied with.

In this embodiment, the drive voltage V is calculated from the average brightness.
_A table ROM was used to calculate the indicated value SV _DRV for _DRV (FIG. 20 (a)). That is, when the average brightness is input as the input (address terminal) of the table ROM, the output value (data terminal) of the ROM outputs the instruction value SV _{DRV of the} drive voltage to be set.

The table ROM in this embodiment.
The contents stored in FIG. 20 are shown in FIG. In the figure, the horizontal axis is the average luminance, but the average luminance when the input video signal of one frame is an all-white screen is standardized as 1 for the sake of easy understanding of the figure. Further, the vertical axis of the figure shows the actual drive voltage V _DRV instead of the drive voltage instruction value SV _DRV . V _SEL is the rated drive voltage of the surface conduction electron-emitting device of this embodiment.

That is, in the case of a dark image, that is, in the case of an image having a low average luminance level, the drive voltage V _DRV is high, and in the case of a high image, the drive voltage V _DRV is low.

(Correction Data Calculation Means) The correction data calculation means 14 is a circuit for calculating the correction data of the voltage drop corresponding to the drive voltage of the display panel 1 by the above-mentioned correction data calculation method. The correction data calculation means 14 is composed of two blocks, a discrete correction data calculation unit and a correction data interpolation unit, as shown in FIG.

The discrete correction data calculation unit refers to the drive voltage instruction value SV _DRV output from the drive voltage calculation unit 222, calculates a voltage drop amount corresponding to the input video signal, and calculates the correction data from the voltage drop amount. Is calculated discretely.

In order to reduce the amount of calculation and the amount of hardware, the means introduces the above-mentioned concept of the degenerate model and calculates correction data discretely. At this time, the drive voltage V _DRV
In accordance with the drive voltage instruction value SV _DRV which is a value corresponding to, the element current amount used for the calculation is updated to calculate the voltage drop amount.

The correction data calculated discretely is interpolated by the correction data interpolating section (correction data interpolating means), and the correction data CD suitable for the size of the image data and its horizontal display position x is calculated.

(Discrete Correction Data Calculation Unit) FIG. 22 shows a discrete correction data calculation unit for calculating correction data discretely.

As will be described below, the discrete correction data calculation unit divides the image data into blocks, calculates a statistic amount (number of lights) for each block, and calculates the voltage drop amount at each node position from the statistic amount. A function as a voltage drop amount calculation unit that calculates a time change, a function that converts the voltage drop amount for each time into a light emission luminance amount, a function that integrates the light emission luminance amount in the time direction, and calculates a total light emission luminance amount, and , A means for realizing a function of calculating correction data for a reference value of image data at discrete reference points.

In FIG. 22, 100a to 100d are lighting number counting means, 101a to 101d are groups of registers for storing the number of lighting at each time for each block, and 102.
Is a CPU, 103 is a table memory (voltage drop amount storage means) for storing the parameters aij described in (Equation 2) and (Equation 3), 113 is a drive voltage instruction value SV _DRV supplied from the drive voltage calculation unit. , 112 is a table memory for calculating the element current amount for calculating the voltage drop amount from the drive voltage instruction value SV _DRV , 104 is a temporary register for temporarily storing the calculation result, and 105 is A program memory in which a CPU program is stored, 111 is a table memory in which conversion data for converting a voltage drop amount into an emission current amount is described, and 106 is a register group for storing the calculation result of the discrete correction data described above. is there.

Lighting number counting means 100a to 100d
Is composed of a comparator, an adder and the like as shown in FIG. Video signals Ra, Ga, B
a is input to each of the comparators 107a to 107c and sequentially compared with the value of Cval. Note that Cval corresponds to the reference value set for the image data described above.

The comparators 107a to 107c are Cva
The image data is compared with l and High is output if the image data is larger, and Low is output if the image data is smaller.

The outputs of the comparators 107a to 107c are added to each other by the adders 108 and 109, and the adder 110 performs addition for each block.
The addition result for each block is stored in the register groups 101a to 101d as the number of lights for each block.

0, 64, 128 and 192 are input to the number-of-lights counting means 100a to 100d as the comparison values Cval of the comparators 107a to 107c, respectively. That is, the lighting number counting means 100a counts the number of image data larger than 0 among the image data,
The total for each block is stored in the register 101a. The lighting number counting means 100b counts the number of image data larger than 64 among the image data, and stores the total for each block in the register 101b. The lighting number counting means 100c counts the number of image data larger than 128 among the image data, and stores the total for each block in the register 101c. The lighting number counting means 100d counts the number of image data larger than 192 among the image data, and stores the total for each block in the register 101d.

When the number of lightings for each block and for each time is counted, the CPU reads the parameter table aij stored in the table memory 103 at any time to obtain (Equation 2).
According to (Equation 5), the voltage drop amount is calculated, and the calculation result is stored in the temporary register 104.

At this time, the CPU 102 first sets the register 11
The value of the drive voltage instruction value SV _DRV instructed by the drive voltage calculation unit 222 is stored with reference to the content of _{No. 3} .

Further, from the drive voltage instruction value SV _DRV ,
The content of the table memory 3 (112) is referred to in order to obtain the element current amount used for the voltage drop. Table memory 3
The relationship between the drive voltage and the element current IF is stored in
When the drive voltage instruction value SV _DRV is input to the table memory 3, the element current amount IF corresponding to it is output. The element current amount IF thus obtained is substituted into (Equation 5), and the voltage drop amount is calculated.

In this embodiment, the CPU 102 is provided with a product-sum calculation function for smoothly performing the calculation of (Equation 2).

As a means for realizing the operation described in (Equation 2), the product sum operation may not be performed by the CPU 102, and for example, the calculation result may be stored in the memory. That is, the number of lighting of each block may be used as an input and the voltage drop amount at each node position may be stored in the memory for all possible input patterns.

When the calculation of the voltage drop amount is completed, C
The PU 102 reads from the temporary register 104 each time,
The amount of voltage drop for each block is read, the amount of voltage drop is converted to the amount of emission current by referring to the table memory 2 (111), and the discrete correction data is calculated according to (Equation 6) to (Equation 16). . The calculated discrete correction data is stored in the register group 106.

(Correction Data Interpolation Unit) The correction data interpolation unit is a means for calculating correction data suitable for the position (horizontal position) where the image data is displayed and the size of the image data. This means interpolates the correction data calculated discretely to display the image data (horizontal position).
Also, correction data corresponding to the size of the image data is calculated.

FIG. 23 is a diagram for explaining the correction data interpolation unit. In FIG. 23, 123 is a decoder a for determining the node numbers n and n + 1 of the discrete correction data used for interpolation from the display position (horizontal position) x of the image data, and 124 is Formula 17) ~
It is a decoder b for determining k and k + 1 in (Equation 19). Further, the selectors 125 to 128 are selectors for selecting the discrete correction data and supplying it to the linear approximation means. Further, 120 to 122 are respectively (Equation 17)
Is a linear approximation means for performing linear approximation of (Equation 19).

FIG. 24 shows a configuration example of the linear approximation means 120. Generally, the linear approximation means is represented by the operators of (Equation 17) to (Equation 19), as shown in the subtractor, integrator, adder
It can be configured by a divider or the like.

However, it is desirable that the number of modulation wiring lines between the nodes for calculating the discrete correction data and the interval of the image data reference value for calculating the discrete correction data (that is, the time interval for calculating the voltage drop) be a power of 2. The above configuration has the advantage that the hardware can be configured very easily. If you set them to a power of 2,
In the divider shown in FIG. 4, since Xn + 1-Xn is a power of 2, division can be realized by bit shift.

If the value of Xn + 1-Xn is always a constant value and a value represented by a power of 2, it is sufficient to shift the addition result of the adder by the multiplier of the power and output it. There is no need to make a divider.

Further, at other points as well, by setting the intervals of the nodes for calculating the discrete correction data and the intervals of the image data to the power of 2, for example, the decoders 123 to 124 can be used.
Can be easily manufactured, and the calculation performed by the subtractor in FIG. 24 can be replaced with a simple bit calculation, which is very advantageous.

(Operation Timing of Each Part) FIG. 25 shows a timing chart of the operation timing of each part. In the figure, Hsync is a horizontal synchronizing signal, DotCLK is a clock generated from the horizontal synchronizing signal Hsync by the PLL circuit in the timing generating circuit 4, R, G and B are digital image data from the input switching circuit, Data.
Is image data after data array conversion, Dout is image data subjected to voltage drop correction, TSFT is a shift clock for transferring image data Dout to the shift register 5, and Dataload is for latching data in the latch circuit 6. The load pulse, Pwmstart is an example of the above-mentioned pulse width modulation start signal, and the modulation signal XD1 is an example of the pulse width modulation signal supplied to the modulation wiring 1.

With the start of one horizontal period, the digital image data RGB is transferred from the input switching circuit. In the figure, in the horizontal scanning period I, the input image data is represented by R_I, G_I, and B_I. They are stored in the data array conversion unit 9 for one horizontal period, and are output as digital image data Data_I according to the pixel arrangement of the display panel in the horizontal scanning period I + 1.

R_I, G_I and B_I are input to the correction data calculating means 14 in the horizontal scanning period I. With this means, the number of times of lighting described above is counted, and at the end of counting, the voltage drop amount is calculated. Following the calculation of the voltage drop amount, the discrete correction data is calculated, and the calculation result is stored in the register.

In the scanning period I + 1, in synchronization with the output of the image data Data_I one horizontal scanning period before from the data array conversion unit 9, the correction data interpolating unit interpolates the discrete correction data and outputs the correction data. It is calculated. The interpolated correction data is immediately subjected to gradation number conversion by a gradation number conversion unit (not shown) and supplied to the adder 12.

The adder 12 sequentially adds the image data Data and the correction data CD and transfers the corrected correction image data Dout to the shift register 5. The shift register 5 stores the corrected image data Dout for one horizontal period according to Tsft, performs serial / parallel conversion, and outputs parallel image data ID1 to IDN to the latch circuit 6. The latch circuit 6 is Dataaloa
The parallel image data ID1 to IDN from the shift register 5 are latched according to the rising edge of d, and the latched image data D1 to DN are transferred to the pulse width modulation means 8.

The modulation means 8 outputs a pulse width modulation signal having a pulse width corresponding to the latched image data. In the display device of the present embodiment, as a result, the pulse width output by the modulator 8 is displayed with a delay of two horizontal scanning periods with respect to the input image data.

When an image is displayed by such a display device, when the driving voltage is changed to be low, the correction data CD becomes small, or conversely, the driving voltage becomes high. When such a change is made, since the voltage drop correction processing by addition is performed so that the correction data CD becomes large, the voltage drop amount in the scanning wiring can be corrected, and the display image is deteriorated due to the correction. It was possible to improve, and it was possible to display a very good image.

Further, even when the drive voltage is controlled to reduce the power consumption, the voltage drop correction circuit can appropriately perform the correction in response to the change in the drive voltage, which is very preferable. .

In the above-described embodiment, the voltage drop correction circuit corresponding to the change in the drive voltage has been described in order to reduce the power consumption, but it is naturally good even when the drive voltage is changed for another purpose. The voltage drop can be corrected.

As another application example, a mode in which the display device dynamically displays the peak brightness by relatively increasing the peak brightness (dynamic mode), or a mode in which the peak brightness is relatively lowered and displayed with importance on power consumption ( In some cases, a power consumption-oriented mode) is prepared in advance and can be selected according to the taste of the user. Even when such multiple display modes are provided, the display image can be easily adjusted by selecting the mode according to the setting of the user and controlling the drive voltage, while the adjusted drive voltage can be adjusted. Correspondingly, the voltage drop correction amount can be adjusted to perform good correction.

As another application example, when the display device is used not only as a television but also as a monitor of a computer, the user looks directly at the monitor and uses it more than when using it as a television. Also, it is preferable to use it while suppressing the brightness. Even when such an input video signal source is a computer,
Brightness can be suppressed and displayed by adjusting the drive voltage, while favorable voltage drop correction can be performed corresponding to the adjusted drive voltage.

It is to be noted that whether the image currently being displayed is a computer image or a television image can be discriminated by the image supply terminal for the television or the image supply terminal for the computer. It is only necessary to detect whether it has been done. Further, the identification may be performed based on the input setting of the user interface means such as a remote controller that can set the video supply terminal, the detection result of the automatic detection means, the detection result of the external environment detection means such as the optical sensor, or the like. .

Further, in the present embodiment, the selection potential of the scanning circuit is changed as an actual control target when adjusting the drive voltage, but as described above, the present invention is not limited to this.

In the above-described embodiment, the reference value of the discrete image data is set for the input image data, the reference point is set on the scanning wiring, and the size of the image data reference value at the reference point is set. The correction data for the image data was calculated discretely. Further, by interpolating the correction data calculated discretely, the correction data corresponding to the horizontal display position of the input image data and its size is calculated, and the correction data is added to the image data to realize the correction. Was there.

On the other hand, the same correction can be performed by the following configuration in addition to the above configuration. The correction result of the image data with respect to the discrete horizontal position and the image data reference value, that is, the sum of the discrete correction data and the image data reference value is calculated, and the correction result calculated discretely is interpolated and input. It is also possible to calculate a horizontal display position of the image data and a correction result corresponding to the size of the horizontal display position and perform modulation according to the correction result. In this configuration, since the image data and the correction data are added when the correction result is calculated discretely, it is not necessary to add the image data and the correction data after the interpolation.

As described above, according to the first embodiment of the present invention, the deterioration of the display image due to the voltage drop can be improved.

By introducing some approximations, the correction amount of the image data for correcting the voltage drop can be easily calculated, and it can be realized by very simple hardware. did it.

Then, for example, even when the drive voltage is adjusted to reduce the power consumption, the voltage drop can be properly corrected according to the change in the adjusted drive voltage.

Further, in the first embodiment, the parameter for changing the drive voltage instruction value is changed, but the coefficient for multiplying the output image data Dout is changed to change the average luminance level of the image data of one frame. It is also possible to change. Such a form will be described later.

(Second Embodiment) A display device according to a second embodiment of the present invention described below is provided with an emission charge amount correction means for correcting a variation in the emission charge amount due to the influence of a voltage drop, and the emission charge amount is corrected. The correction means calculates corrected image data in which the input image data is corrected so as to correspond to the amount of emitted charge to be emitted, and the modulation means outputs a pulse waveform to be applied to the column wiring corresponding to the calculated corrected image data. The image display device is characterized by further comprising current value calculation means for calculating an average current value corresponding to the light emission brightness of the image display device based on the integrated value of the input image data which is the brightness required value.

Alternatively, a correction image data calculating means for calculating the correction image data which is the image data in which the influence of the voltage drop is corrected, and the column wiring are connected, and the correction image data is inputted and the modulation signal is outputted to the column wiring. And a current value calculation means for calculating an average current value corresponding to the light emission brightness of the image display device based on the integrated value of the input image data.

The current value calculating means preferably has an integrating means for integrating the input image data, and the output of the integrating means is preferably the average current value corresponding to the emission brightness of the image display device.

Further, it is preferable to provide an amplitude adjusting means for multiplying a coefficient for adjusting the amplitude of the corrected image data so that the amplitude of the corrected image data corresponds to the input range of the modulation circuit.

It is preferable that the current value calculating means has an integrating means for integrating the input image data, and the result of multiplying the output of the integrating means by the coefficient is an average current value corresponding to the light emission brightness of the image display device. Is.

The average current value calculated by the current value calculating means is compared with a predetermined reference current value, and when the average current value is larger than the reference current value, the power relating to the light emission brightness of the image display device is limited. It is preferable to provide a power limiting means for controlling.

The power limiting means has a function of calculating a coefficient for limiting the power from the reference current value and the average current value and multiplying the coefficient for limiting the power to adjust the amplitude of the corrected image data. Is preferred.

When the overflow process is not performed, the power limiting means sets the integrated value of the input image data as APL, the reference current value as Iamax, the average current value as Ia, and the coefficient for power limiting as G '. , Ia = APL, and when Ia <Iamax, G ′ = 1 When Ia ≧ Iamax, it is preferable to have a function of multiplying the corrected image data by a coefficient G ′ obtained as G ′ = Iamax / APL.

It is preferable that the power limiting means multiplies the correction image data by the coefficient G'to calculate the amplitude-adjusted correction image data.

It is preferable that the power limiting means multiplies the image data before correction by the coefficient G '.

The power limiting means uses the integrated value of the input image data as APL, the reference current value as Iamax, and the average current value as Iamax.
a, when the coefficient for adjusting the amplitude of the corrected image data so that the amplitude of the corrected image data corresponds to the input range of the modulator is G, and the coefficient G is changed to G for power limitation And Ia = APL × G, and G ″ = G when Ia <Iamax, G ″ = Iamax / APL when Ia ≧ Iamax, and a coefficient G ″ calculated as G ″ = Iamax / APL is newly added to adjust the amplitude of the corrected image data. It is preferable that the amplitude adjustment means has a function of adjusting the amplitude of the corrected image data by multiplying it by a coefficient G ″.

It is preferable that the amplitude adjusting means multiplies the corrected image data by the coefficient G ″ to calculate the corrected image data whose amplitude has been adjusted.

It is preferable that the amplitude adjusting means multiplies the image data before correction by the coefficient G ″.

The integrating means preferably calculates the integrated amount of the input image data in frame units.

It is preferable that the reference current value is a value that is predetermined in accordance with the power consumption of the image display device.

It is preferable that the reference current value can be changed by at least one of the user interface means and the external environment detecting means.

It is preferable that the corrected image data calculating unit obtains the corrected image data by expanding the size of the image data input to the corrected image data calculating unit in consideration of the influence of the voltage drop.

The amplitude adjusting means detects the maximum value of the output of the corrected image data calculating means for each frame, and adjusts the amplitude of the corrected image data so that the maximum value falls within the upper limit of the input range of the modulation circuit. It is preferable to adaptively calculate the coefficient of.

The amplitude adjusting means refers to the outputs of the corrected image data calculating means for a plurality of frames before the current frame, and corrects the corrected image data so that those values correspond to the input range of the modulating means. It is preferable to adaptively calculate the coefficient for adjusting the amplitude of.

The coefficient for adjusting the amplitude of the corrected image data is preferably a predetermined coefficient which always has a constant value.

The coefficient for adjusting the amplitude of the corrected image data is preferably a coefficient determined so that the output of the corrected image data calculating means does not overflow the input range of the modulating means when the input image data is maximum. is there.

The corrected image data calculating means is a means for predicting and calculating the spatial distribution and the temporal change of the voltage drop amount that should occur on the row wiring during one horizontal scanning period, corresponding to the input image data. It is preferable to include means for calculating corrected image data obtained by correcting the input image data from the amount of voltage drop.

The corrected image data calculating means discretely predicts and calculates the spatial distribution and the temporal change of the voltage drop amount that should occur on the row wiring during one horizontal scanning period, corresponding to the input image data. It is preferable to include a means for calculating corrected image data obtained by correcting the input image data from the calculated voltage drop amount.

The corrected image data calculating means discretely predicts and calculates the spatial distribution and the temporal change of the voltage drop amount that should occur on the row wiring during one horizontal scanning period, corresponding to the input image data. Discrete correction image data calculation means for discretely calculating correction image data for the image data corresponding to the time at which the voltage drop amount was calculated at the spatial position where the voltage drop amount was calculated, from the calculated voltage drop amount; It is preferable to include a corrected image data interpolation unit that interpolates the output of the image data calculation unit and calculates corrected image data corresponding to the size of the input image data and the horizontal display position.

The correction image data calculated by the correction image data calculating means is such that the emission charge amount of the correction image data becomes the emission charge amount of the input image data when there is no voltage drop amount that should occur on the row wiring. It is preferably adjusted.

In the embodiments described below, the corrected image data calculating means for calculating the corrected image data, which is the image data in which the influence of the voltage drop is corrected, and the corrected image data calculated by the corrected image data calculating means An amplitude adjusting means having a function of adjusting the amplitude of the corrected image data so that the amplitude corresponds to the input range of the modulating means, and the modulating means receives the corrected image data whose amplitude is adjusted by the amplitude adjusting means as an input, A display device that outputs a modulation signal to a column wiring, and when non-zero, uniform image data is input, the pulse width of the pulse output from the modulation means near the output terminal of the scanning means is the output of the scanning means. In an image display device in which the pulse width of the pulse output from the modulator far from the terminal is shorter, the emission brightness of the display device is based on the integrated value of the input image data. Characterized by comprising a power value calculating means for calculating an average current value corresponding to.

(Overall Outline) The voltage drop correction circuit of this embodiment predicts and calculates the deterioration of the display image caused by the voltage drop according to the input image data, obtains the correction data for correcting the deterioration, and inputs the correction data. The image data is corrected.

(Explanation of Function of Entire System and Each Part) Next, the hardware of the image display device having the built-in correction data calculating means will be explained.

FIG. 26 is a block diagram showing an outline of the circuit configuration. The same code | symbol is attached | subjected to the same part as the functional block used by the structure shown in FIG. 14, and the description is abbreviate | omitted here. Reference numeral 23 is a selector for switching between a television video signal and a computer video signal, 20 is a maximum value detection circuit (maximum value detection means), and 21 is a gain calculation means.

(Synchronous signal separation circuit, selector) HDTV
The video signal of the system is first separated into the sync signals Vsync and Hsync by the sync signal separation circuit 3 and supplied to the timing generation circuit 4. The video signal separated by synchronization is R
It is supplied to the GB conversion unit 7. Inside the RGB conversion unit 7, in addition to a conversion circuit for converting YPbPr to RGB, a low-pass filter and an A / D converter (not shown) are provided. The RGB conversion unit 7 converts YPbPr into digital RGB.
It is converted into a signal and supplied to the selector 23.

A video signal output from a computer such as VGA is A / D converted by an A / D converter (not shown),
It is supplied to the selector 23.

The selector 23 appropriately switches between the television signal and the computer signal and outputs the television signal and the computer signal based on which of the video signals the user wants to display.

(Scanning Circuit) As shown in FIG. 27, the scanning circuits 2 and 2 ′ sequentially scan the display panel row by row in one horizontal scanning period, so that the selection potential Vs is applied to the connection terminals Dx 1 to DxM. Alternatively, it is a circuit which outputs the non-selection potential Vns. The difference from the scanning circuits 2 and 2'shown in FIG. 15 is that the power supply Vs is a fixed power supply and the selection potential Vs itself has a preset fixed value.

(Adder) The basic configuration of the adder 12 is
This is the same as in the first embodiment. The image data Data is corrected and transferred to the maximum value detection circuit 20 and the multiplier 22 as corrected image data Dout.

The number of bits of the corrected image data Dout output from the adder 12 is preferably determined so that overflow does not occur when the correction data CD is added to the image data Data.

(Overflow Processing) The correction is realized by the corrected image data obtained by adding the calculated correction data to the image data, as described above.

Now, the number of bits of the modulation means 8 is 8 bits, and the corrected image data Dou which is the output of the adder 12
It is assumed that the number of bits of t is 10 bits. Then,
If the corrected image data is directly connected to the input of the modulation means 8, an overflow will occur. Therefore, it is necessary to adjust the amplitude of the corrected image data before being input to the modulation means 8.

As a method of preventing overflow, an all-white pattern in which the input image data is maximum (where the number of bits of image data is 8 bits, (R, G, B) = (FF
h, FFh, FFh)) is input, the maximum value of the corrected image data is estimated in advance, and the corrected image data is multiplied by a gain such that the maximum value falls within the input range of the modulator 8. Hereinafter, this method is called a fixed gain method.

In the fixed gain method, overflow does not occur, but an image with a low average brightness is multiplied by a small gain even though it can be displayed with a larger gain, so the brightness of the displayed image is dark. May be.

On the other hand, the maximum value of the corrected image data for each frame is detected, a gain is calculated such that this maximum value falls within the input range of the modulator 8, and the gain is multiplied by the corrected image data to cause an overflow. You may prevent it. Hereinafter, this method is called an adaptive gain method.

In the adaptive gain method, the corrected image data Do
Maximum value detection circuit 20 for detecting the maximum value MAX of each frame of ut, gain calculation means 21 for calculating the gain G1 for multiplying the corrected image data by the maximum value, and the corrected image data Dout and the gain. A multiplier or the like for multiplying G1 is required.

In the adaptive gain method, it is preferable to calculate the gain for preventing overflow in units of frames. For example, a gain can be calculated for each horizontal line to prevent overflow, but in that case, due to the difference in gain for each horizontal line,
It is not preferable because the displayed image causes a feeling of strangeness.

It has been confirmed that the amplitude of the corrected image data can be adjusted appropriately even if the gain is calculated by any of the fixed gain method and the adaptive gain method.

Hereinafter, in the present embodiment, a circuit configuration for performing amplitude adjustment (data width adjustment) of corrected image data by the adaptive gain method will be described in detail.

(Maximum value detection circuit) Maximum value detection circuit 20
Is the corrected image data Dout for one frame,
It is a means for detecting the maximum value. The means is a circuit that can be easily configured by a comparator and a register. The means compares the value stored in the register with the size of the correction image data Dout sequentially transferred, and if the correction image data Dout is larger than the value of the register, the value of the register is set to that data. It is a circuit that updates with a value. If the register value is cleared to 0 at the beginning of the frame, the maximum value of the corrected image data in the frame is stored in the register at the end of the frame.

The maximum value of the corrected image data thus detected is transferred to the gain calculating means 21.

(Gain calculation means) Gain calculation means 21
Is the corrected image data Dout based on the adaptive gain method.
Is a means for calculating a gain for adjusting the amplitude so as to be within the input range of the modulating means 8.

When the maximum value detected by the maximum value detection circuit 20 is MAX and the maximum value of the input range of the modulation means 8 is INMAX, the gain G1 may be determined as in (Equation 20) (first). the method of).

[Equation 25]

The gain calculating means 21 updates the gain during the vertical blanking period and changes the gain value for each frame.

In the structure of this embodiment, the maximum value of the corrected image data of the previous frame is used to calculate the gain by which the corrected image data of the current frame is multiplied. That is, the correlation of corrected image data (image data) between frames is used to prevent overflow.

Therefore, strictly speaking, overflow may occur due to the difference in the corrected image data for each frame.

In such a case, a limiter means may be provided for the output of the multiplier that multiplies the corrected image data and the gain, and the circuit may be designed so that the output of the multiplier falls within the input range of the modulating means.

Maximum value detection circuit 20 and multiplier 22
If a frame memory is provided between the two, it is possible to prevent overflow with a configuration with no time delay.

The gain may be calculated by the following method. For example, the maximum value of the corrected image data detected in the frame before the current frame is averaged, and the average value AMAX is used to calculate the gain G1 to be applied to the corrected image data of the current frame in (Equation 21). May be determined (second method).

[Equation 26]

As the third method, the current gain may be calculated by calculating the gain G1 for each frame by (Equation 20) and averaging it.

The second and third methods are more preferable than the first method because they have another effect of greatly reducing flicker in the display image.

When the number of frames to be averaged was examined in the second method and the third method,
For example, when averaging 16 to 64 frames, a preferable image with less flicker was obtained.

In the case of the second and third methods as well, since the corrected image data has a correlation between frames as in the first method, the probability of overflow can be reduced. It is not possible to prevent overflow completely.

As a countermeasure for this, it is preferable to prevent overflow roughly by the above-mentioned method and to completely prevent overflow by providing a limiter on the output of the multiplier 22.

FIG. 28 is a diagram for explaining the flicker by taking the first method and the second method as an example.
FIG. 28 is an example of a moving image in which a white bar rotates counterclockwise in a gray background. When such an image is displayed, the size of the correction data CD changes for each frame as the rod rotates.

FIG. 29 is a diagram for explaining corrected image data when such a moving image is corrected. In FIG. 29, the maximum of each corrected image data in each frame is extracted and graphed. The white part in the figure corresponds to the original image data, and the hatched part corresponds to the part expanded by the correction.

When an image as shown in FIG. 28 is displayed, the maximum value of the corrected image data of consecutive frames fluctuates as shown in FIG. Therefore, when the gain is set for each frame as shown in (Equation 20), the gain varies greatly for each frame as shown in FIG. 30 (a). As a result, the brightness of the displayed image fluctuates significantly, and a flicker feeling occurs.

On the other hand, when the gain is determined by (Equation 21), the gain is averaged.
As shown in (b), the gain variation is small and the luminance variation is small. Therefore, there is an excellent effect that the flicker feeling is reduced. In FIG. 30B, the white circle graph is the gain according to (Equation 20), and the black circle graph is the averaged gain according to (Equation 21).

Also in the third method, as in the second method, the flicker is reduced because the gain variation is small.

The gain calculating means 21 reduces the flicker in images of continuous scenes as described above by averaging the gains. On the other hand, when the scene of the image changes, it is also preferable to change the gain after the scene changes. Therefore, a preset threshold that is the scene switching threshold Gth is provided, the gain of the previous frame calculated by (Equation 20) is GB, and the correction detected by the maximum value detection circuit 20 of the previous frame is corrected. The gain calculated by (Equation 20) from the maximum value of the image data is GN, and the absolute value of the difference between GN and GB is ΔG.
As

[Equation 27] When the gain of the next frame was smoothed and calculated as described above, favorable results were obtained.

Especially, as the values of A and B, A = 1, B = 1/16 to 1/64 When I set it to a degree, I liked it.

(Multiplier) Gain G1 calculated by the gain calculating means 21 and corrected image data Do which is the output of the adder
ut is multiplied by the multiplier 22 and transferred to the limiter circuit as the corrected image data Dmulti having the adjusted amplitude.

(Limiter Means) There is no problem if the gain can be determined so that overflow does not occur as described above, but according to some of the above gain determining methods,
Since it is difficult to determine the gain so that overflow does not occur, it is preferable to provide the limiter 24.

The limiter 24 has a preset limit value, and the output data Dmulti input to the limiter.
If the limit value is smaller than the output data, the limit value is output. If the limit value is larger than the output data, the output data is output as it is.

In this way, the corrected image data Dlim completely limited to the input range of the modulation means 8 is output from the limiter 24 and input to the modulation means 8 via the shift register 5 and the latch 6.

(Brightness Control Means) The brightness control means composed of the high voltage power supply current value calculation circuit and the ABL circuit will be described below.

(High-voltage power supply current value calculation circuit) A method of calculating the current value of the high-voltage power supply (that is, the power value of the high-voltage power supply) by calculating the image data for realizing ABL or the like will be described.

In FIG. 26 described above, reference numeral 200 denotes an integrating unit (integrating means) for integrating the image data, which is the required brightness value, for one frame, and 201 is a multiplier. This accumulator 20
0 and the multiplier 201 are a high-voltage power supply current value calculation circuit as means for calculating the current value (Ia) of the high-voltage power supply from the image data. In the figure, the high-voltage power supply current value calculation circuit is shown surrounded by a broken line.

The means for calculating the current value of the high-voltage power supply calculates the current value (Ia) of the high-voltage power supply according to the following principle.

The correction of the influence of the voltage drop of the scanning wiring in the present embodiment is a correction method of "adjusting the image data to obtain the corrected image data so as to obtain the amount of electric charge emitted when there is no voltage drop in the scanning wiring". . When the pulse width (correction image data) exceeds the horizontal scanning time, the maximum value of the pulse width (correction image data) falls within a predetermined time (horizontal scanning time), for example, in the correction image data in frame units. Adjust by multiplying the gain.

Multiplying the corrected image data by the gain on a frame-by-frame basis means, that is, "corrected image data adjusted to have the amount of emitted charges when there is no voltage drop in the scanning wiring".
Is multiplied by the gain, it means that the amount of charge emitted by each electron-emitting device of the display panel is multiplied by the gain and driven.

Therefore, when the influence of the voltage drop is corrected, the “value obtained by multiplying the integrated value of the image data by the gain” in units of frames directly corresponds to the “emission charge amount of each electron-emitting device in one frame”. To do.

Since the amount of charge per unit time is a current, the value obtained by multiplying the integrated value of image data by the gain is 1
The frame corresponds to an average current within the time, that is, a "current value of the high-voltage power supply" with the unit time. Further, it can be said that the “current value of the high-voltage power supply” is an average current value corresponding to the emission brightness of the display device.

In FIG. 26, the means for calculating the current value of the high voltage power supply (current value calculating means) causes the integrating section 200 to integrate the image data for each frame based on the principle described above. Specifically, the integrating unit 200 includes a register and an adder for each color of RGB. The integrating unit 200 is
The register is reset on a frame-by-frame basis, the input image data and the output of the register are added by an adder, and the addition result is reloaded into the register at each input timing of the image data. As a result, the integrated value for each color is obtained at the end of one frame. Then, the integrated value for each color is added to obtain the integrated value (equivalent to the APL value).

The multiplier 201 is an integrated value (APL value) of the image data output from the integrating section 200 in units of one frame.
And a gain G1 for preventing overflow are multiplied and output. The output of the multiplier 201 becomes a value corresponding to the current value (Ia) of the high voltage power supply.

For example, if the APL values when the image data are all 255 (all white) are normalized to be 255, the output of multiplier 201 (the value corresponding to the current value of the high-voltage power supply) is 255. At the time (gain G1 is 1), the current value of the electron-emitting device when there is no voltage drop in the scanning wiring is equal to the value obtained by multiplying the number of wirings in one row by the driving duty.

In the CRT, as a current detecting means of the high voltage power source, a method of adding a current detecting resistor to the high voltage power source and obtaining the current value of the high voltage power source from the voltage is known.
According to the configuration of the present embodiment, the current value of the high voltage power supply can be accurately calculated only by calculating the data. In particular, in realizing ABL by signal processing, which will be described later, an analog-digital converter and a wiring for outputting a voltage corresponding to a current value from a high-voltage power supply, which are conventionally required, are not required, and the hardware cost can be reduced. .

(ABL Circuit) Next, a method of performing signal processing for realizing ABL will be described.

In FIG. 26, 202 is a register in which the high voltage limit value (Iamax) is stored, 203 is a comparator, 204 is a divider, and 205 is a switch. As described above, the output of the multiplier 201 corresponds to the current value (Ia) of the high voltage power supply. In FIG. 26, the high voltage power supply current value calculating circuit (current value calculating means) and the ABL circuit (power limiting means) are surrounded by broken lines.

The comparator 203 outputs the output (I
a: Corresponding to the current value of the high-voltage power supply) and the register 202 in advance.
Current limit value (Iamax;
(Reference current value). If the output of the multiplier 201 (corresponding to the current value of the high-voltage power supply) is larger than the preset current limit value (Iamax), the gain G1 for preventing the overflow is set in order to limit the power of the display device. On the other hand, a new gain G1 'is calculated. That is, the value obtained by multiplying the new gain G1 'by the APL value (the new current value of the high-voltage power supply) is the current limit value (Iama).
x).

The above signal processing is mathematically expressed as follows.

[Equation 28]

By the control described above, the average current of the high voltage power source for one frame (that is, the power of the high voltage power source) could be limited.

The actual configuration is, as shown in FIG. 26, the output of the multiplier 201 in the comparator 203 (Ia: corresponding to the current value of the high voltage power source) and the current of the high voltage power source preset in the register 202. The limit value (Iamax) is compared. A
When PL × G1 <Iamax, the output of the comparator 203 connects the input of the switch 205 with the output of the gain calculating means 21 to realize (Equation 22).

On the other hand, when APL × G1 ≧ Iamax, the output of the comparator 203 is the input of the switch 205 divided by the divider 20.
4 output. The divider 204 outputs a value obtained by dividing the limit value (Iamax) of the high voltage current by the output of the multiplier 201. Therefore, when APL × G1 ≧ Iamax, (Equation 2
3) can be realized.

As described above, the ABL function can be realized by changing the gain G1 for preventing the overflow to the new gain G1 '.

In the above embodiment, the ABL operation is realized by changing the gain G1 for preventing the overflow to a new gain G1 '. Naturally, after the gain G1 for preventing the overflow is multiplied, APL ×
1 when G1 <Iamax, APL × G1 ≧ Iama
When x is set, Iamax / (APL × G1) may be further multiplied.

If the effect of the voltage drop of the scanning wiring is not corrected, the amount of electric charge actually discharged is
The image data and the amount of discharged electric charges do not match because they change depending on the voltage drop of the scanning wiring. Therefore, according to the signal processing of the present embodiment, it is possible to accurately calculate the current value of the high-voltage power supply and accurately perform the ABL operation.

The current value calculation method of the high voltage power supply and the ABL in the case of performing the overflow processing have been described above. Next, a case where the amount of voltage drop is small or the scanning time is long and overflow processing is not necessary will be described.

When there is no overflow processing, the gain G1 is 1, so that (Equation 22) and (Equation 23) become (Equation 24) and (Equation 25).

[Equation 29]

Since the actual configuration has the gain G1 = 1, the maximum value detection circuit 20, the gain calculation means 21, and the multiplier 201 in FIG. 26 are unnecessary. The current value (Ia) of the high voltage power supply corresponds to the APL itself.

FIG. 31 shows the structure of the brightness control means when there is no overflow processing. When there is overflow processing, the multiplier 22 multiplies the coefficient for preventing overflow. On the other hand, when there is no overflow processing in FIG. 31, the multiplier 22 is used to multiply the corrected image data by the coefficient for limiting the power.
In FIG. 31, the high-voltage power supply current value calculation circuit and the ABL circuit are surrounded by a broken line. 206 is a register, AP
A coefficient G1 'of "1" when L <Iamax is stored. The other operations are the same as those in the case where the overflow processing is performed, and thus the description thereof will be omitted.

By the control described above, the average current of the high-voltage power supply for one frame (that is, the power of the high-voltage power supply) can be calculated from the APL value and the ABL operation can be performed even when there is no overflow processing. .

When the overflow process is not performed, the integrated value (APL value) of the image data is the current value (I
Although it corresponds to a) as it is, this indicates that the current value (Ia) of the high-voltage power supply can be accurately obtained by correcting the influence of the voltage drop of the scanning wiring. That is, if the effect of the voltage drop is not corrected, it goes without saying that even if the integrated value of the image data is simply obtained, the current value of the high-voltage power supply will not be accurately corresponded.

(Shift Register, Latch Circuit) The corrected image data Dlim output from the limiter 24 is transferred from the serial data format by the shift register 5 to
The parallel image data ID1 to IDN for each modulation wiring are serial / parallel converted and output to the latch circuit 6. The latch circuit 6 latches the data from the shift register 5 by the timing signal Dataload immediately before the start of one horizontal period. The output of the latch circuit 6 is
The parallel image data D1 to DN are input to the modulation means 8.

In this embodiment, image data ID1 to ID
Each of N and D1 to DN is 8-bit image data. These operation timings are the timing generation circuit 4
It operates based on the timing control signals TSFT and Dataload from (FIGS. 26 and 31).

(Details of Modulating Means) The parallel image data D1 to DN output from the latch circuit 6 are supplied to the modulating means 8. The structure of the modulator 8 is the same as that of the first embodiment described above.

FIG. 32 is a timing chart showing the operation of the modulation means 8 of this embodiment. In the figure, Hs
sync is a horizontal synchronization signal, Dataload is a load signal to the latch circuit 6, and D1 to DN are columns 1 to N of the modulation means 8.
To the PWM counter, Pwmstart is a PWM counter synchronization clear signal, and Pwmclk is a PWM counter clock. Further, XD1 to XDN are the first to the first of the modulation means 8.
The output of the Nth column is shown.

When one horizontal scanning period starts as shown in the figure, the latch circuit 6 latches the image data and transfers the data to the modulating means 8.

The PWM counter has Pwmstart, P
Counting is started based on wmclk, and when the count value reaches 255, the counter is stopped and the count value 255
Hold.

The comparator provided for each column is
The count value of the PWM counter is compared with the image data of each column, and when the value of the PWM counter is greater than or equal to the image data, High
h is output, and Low is output during the other periods.

The output of the comparator is connected to the gates of the switches in each column, and the output of the comparator is Low.
18A, the switch on the upper side (VPwm side) of FIG. 18A is ON, and the switch on the lower side (GND side) is OFF,
The modulation wiring is connected to the voltage VPwm. Conversely, while the output of the comparator is High, the upper switch in FIG. 18A is OFF and the lower switch is ON, and
The voltage of the modulation wiring is connected to the GND potential.

The pulse width modulation signal output from the modulation means 8 is XD in FIG. 32 as a result of the operation of each section as described above.
1, XD2, ... XDN have a waveform in which the rising edges of the pulses are synchronized.

(Correction Data Calculation Means) The correction data calculation means 14 is a circuit for calculating the voltage drop correction data by the above-mentioned correction data calculation method. The correction data calculation means 14 is composed of two blocks, a discrete correction data calculation unit and a correction data interpolation unit, as shown in FIG.

(Discrete Correction Data Calculation Unit) FIG. 34 shows a discrete correction data calculation unit for calculating correction data discretely.

The discrete correction data calculation unit has the configuration shown in FIG. 22, and the register 113 and the table memory 3 (112).
This is a configuration that omits. Then, it divides the image data into blocks, calculates a statistic amount (number of lights) for each block, and functions as a voltage drop amount calculation unit that calculates the time change of the voltage drop amount at the position of each node from the statistic amount. Function, a function of converting the voltage drop amount for each time into a light emission brightness amount, a function of integrating the light emission brightness amount in the time direction to calculate a total light emission brightness amount, and image data at discrete reference points therefrom. It is a means for realizing the function of calculating the correction data for the reference value.

The operation of each block is almost the same as the configuration of FIG.

(Correction Data Interpolation Unit) The correction data interpolation unit has the same structure as that of the first embodiment shown in FIG. The straight line approximation means a120 is also the same as in the first embodiment.

(Operation Timing of Each Part) The timing chart of the operation timing of each part is almost the same as that shown in FIG. The difference is that the output Dou in FIG.
The point t has been replaced with the output Dlim of the limiter 24.

In the adder 12, the image data Data and the correction data CD are sequentially added, and the corrected correction image data Dlim is transferred to the shift register 5. The shift register 5 stores the corrected image data Dlim for one horizontal period according to Tsft, and also performs serial / parallel conversion to perform parallel image data ID1 to IDN.
Is output to the latch circuit 6. The latch circuit 6 is Data
The parallel image data ID1 to IDN from the shift register 5 are latched according to the rise of oad, and the latched image data D1 to DN are transferred to the pulse width modulation means 8.

(Third Embodiment) In order to prevent overflow, in the second embodiment, the maximum value of the corrected image data is detected, and the maximum value corresponds to the maximum value of the input range of the modulation means. Thus, the gain was calculated, and the gain was multiplied by the corrected image data to prevent overflow.

On the other hand, in the third embodiment, the maximum value of the corrected image data is detected in the same manner, but the correction is performed so that the maximum value corresponds to the maximum value of the input range of the modulation means. It was decided to limit the size of the previous image data. That is, in order to prevent overflow, the image data input in advance is multiplied by a gain to reduce its amplitude range, and overflow is prevented.

The overflow process of this embodiment will be described below with reference to FIG.

In FIG. 35, 22R, 22G and 22B are multipliers, 9 is a data array converter, 5 is a shift register for one line of image data, 6 is a latch circuit for one line of image data, and 8 is a modulation of the display panel. Pulse width modulation means for outputting a modulation signal to the wiring, 12 is an adder, 14 is correction data calculation means, and 20 is correction image data Dou in the frame.
A maximum value detection circuit (maximum value detection means) for detecting the maximum value of t, 21 is a gain calculation means.

Further, R, G, B are RGB parallel input video data, Ra, Ga, Ba are RGB parallel video data subjected to inverse γ conversion processing, and Rx, Gx, Bx are multipliers, and gain G2 is The image data multiplied by the gain G2 is the gain calculated by the gain calculating means 21, Data
Is image data parallel / serial converted by the data array converter 9, CD is correction data calculated by the correction data calculating unit 14, and Dout is corrected by adding the correction data to the image data by the adder 12. Image data (corrected image data) Dlim is image data in which Dout is limited by the limiter 24 to be equal to or lower than the upper limit of the input range of the modulator 8.

(Multiplier) Multipliers 22R, 22G, 22B
Is a means for multiplying the image data Ra, Ga, Ba after the inverse γ conversion by a gain G2.

More specifically, the multipliers 22R, 22G, 2
2B multiplies the image data Ra, Ga, Ba by the gain G2 according to the gain determined by the gain calculating means 21, and outputs the image data Rx, Gx, Bx after the multiplication.

The gain G2 is a value calculated by the gain calculating means 21, and is the image data D in the adder 12 to be described later.
Corrected image data D which is the addition result of ata and correction data
out is a value that is determined so that it falls within the input range of the modulation means 8.

(Maximum Value Detection Circuit) The maximum value detection circuit 20 is connected to each section as shown in FIG.

The maximum value detection circuit 20 is means for detecting the maximum value in the corrected image data Dout for one frame. The means is a circuit that can be easily configured by a comparator and a register. The means compares the value stored in the register with the size of the correction image data Dout that is sequentially transferred, and corrects the correction image data Dout.
If out is larger than the register value, the circuit updates the register value with the data value. If the register value is cleared to 0 at the beginning of the frame, at the end of the frame, the maximum value M of the corrected image data in the frame will be reached.
AX is stored in the register.

The maximum value MAX of the corrected image data detected in this way is transferred to the gain calculating means 21.

(Gain calculation means) Gain calculation means 21
Is a unit that refers to the detected value MAX of the maximum value detection circuit 20 and calculates a gain so that the corrected image data Dout falls within the input range of the modulation unit 8. Also in this embodiment, the gain calculation means 21 calculates the gain for adjusting the amplitude of the corrected image data based on the adaptive gain method. In the configuration of this embodiment, the gain may be calculated by the fixed gain method.

The gain G2 is MAX for the maximum value detected by the maximum value detection circuit 20, INMAX for the maximum value of the input range of the modulation means 8, and gain calculation means 21 for the previous frame.
When the gain calculated by is set to GB, it may be determined as in (Expression 26).

[Equation 30]

The gain calculating means 21 updates the gain in the vertical blanking period and changes the gain value for each frame.

Here, the maximum value of the corrected image data of the preceding frame is used to calculate the gain by which the corrected image data of the current frame is multiplied. That is, the correlation of corrected image data (image data) between frames is used to prevent overflow.

Therefore, strictly speaking, an overflow may occur due to the difference in the corrected image data for each frame.

In such a case, a limiter means is provided for the output of the multiplier that multiplies the corrected image data and the gain, and the circuit may be designed so that the output of the multiplier always falls within the input range of the modulating means. .

Further, the present inventors have confirmed that, in addition to the above-described gain determination method, the gain may be calculated by the following other method.

For example, the maximum values of the corrected image data detected in the frames before the current frame are averaged,
Using the average value AMAX, the gain G2 to be applied to the corrected image data of the current frame may be determined as in (Equation 27). However, GB is the gain G2 calculated by the gain calculating means 21 for the previous frame.

[Equation 31]

As another method, the current gain may be calculated by calculating the gain G2 for each frame by (Equation 26) and averaging it.

Of these three methods, any method is preferable in the sense of preventing overflow, but considering the occurrence of flicker, it is preferable to calculate by the method of (Equation 27).

In the gain calculation method of (Equation 27), the number of frames for averaging the maximum value of the corrected image data was examined.
When the maximum values of the corrected image data up to 64 frames before were averaged, a preferable image with little flicker was obtained.

Needless to say, it is preferable that the present method also includes a limiter 24 for limiting the output of the adder 12 to completely prevent the overflow, as shown in FIG.

Further, the method of calculating the gain may be changed by detecting a scene change as in the second embodiment.

Next, the brightness control means will be described.
The basic configuration is the same as that shown in FIG.

The means for calculating the current value of the high voltage power source is the second means.
Similar to the embodiment of FIG.
Composed of. In the present embodiment, the current value of the high-voltage power supply is obtained by multiplying the integrated value of the image data integrated by the integration unit 200 and the gain G2 that prevents overflow (see FIG. 35).

The principle and configuration of the high voltage power supply current value calculation circuit are the same as those in the second embodiment, and the description thereof will be omitted.

According to the configuration of this embodiment, the current value of the high voltage power source can be calculated only by calculating the data, and the hardware cost can be reduced.

(ABL Circuit) Next, in FIG.
A method of performing signal processing for realizing BL will be described.

In FIG. 35, reference numeral 200 is an integrating unit (integrating means) for integrating image data, which is a required brightness value, by one frame, 201 is a multiplier, and 202 is a high-voltage current limit value (I
amax) is stored in the register, 203 is a comparator, 204 is a divider, and 205 is a switch. As described above, the output of the multiplier 201 is the current value (I
It corresponds to a). In FIG. 35, the high voltage power supply current value calculation circuit (current value calculation means) and the ABL circuit (power limitation means)
Are surrounded by a broken line.

The comparator 203 outputs the output (I
a: Corresponding to the current value of the high-voltage power supply) and the register 202 in advance.
Current limit value (Iamax;
(Reference current value). If the output of the multiplier 201 (corresponding to the current value of the high-voltage power supply) is larger than the preset current limit value (Iamax), the gain G2 that prevents overflow is set in order to limit the power of the display device. On the other hand, a new gain G2 'is calculated. That is, the value obtained by multiplying the new gain G2 ′ by the APL value (the new current value of the high voltage power supply) is the current limit value (Iama).
x).

The above signal processing is mathematically expressed as follows.

[Equation 32]

By the control described above, it was possible to limit the average current of the high voltage power source for one frame (that is, the power of the high voltage power source).

As shown in FIG. 35, the actual configuration is such that in the comparator 203, the output of the multiplier 201 (Ia: corresponding to the current value of the high voltage power source) and the current of the high voltage power source preset in the register 202. The limit value (Iamax) is compared. A
When PL × G2 <Iamax, the output of the comparator 203 connects the input of the switch 205 with the output of the gain calculating means 21 to realize (Equation 28).

On the other hand, when APL × G2 ≧ Iamax, the output of the comparator 203 is the input of the switch 205 divided by the divider 20.
4 output. The divider 204 outputs a value obtained by dividing the limit value (Iamax) of the high voltage current by the output of the multiplier 201. Therefore, when APL × G2 ≧ Iamax, (Equation 2
9) can be realized.

As described above, the ABL function can be realized by changing the gain G2 for preventing the overflow to the new gain G2 '.

The current value calculation method and ABL of the high voltage power supply when the overflow processing is performed have been described above. Next, a case where the amount of voltage drop is small or the scanning time is long and overflow processing is not necessary will be described.

When there is no overflow processing, the gain G2 is 1, so that (Equation 28) and (Equation 29) become (Equation 30) and (Equation 31).

[Expression 33]

Since the actual configuration has the gain G2 = 1, the maximum value detection circuit 20, the gain calculation means 21, and the multiplier 201 in FIG. 35 are unnecessary. The current value (Ia) of the high voltage power supply corresponds to the APL itself.

FIG. 36 shows the structure of the brightness control means when there is no overflow processing. When there is overflow processing, the multipliers 22R, 22G, 22B are
Multiplied by a factor to prevent overflow. On the other hand, when there is no overflow processing in FIG. 36, the multiplier 22
R, 22G, and 22B are used to multiply the corrected image data by a coefficient for limiting the power. In FIG. 36, the high voltage power supply current value calculation circuit and the ABL circuit are surrounded by a broken line. 206 is a register, APL <Iama
"1" which is the coefficient G2 'when x is stored. The other operations are the same as those in the case where the overflow processing is performed, and thus the description thereof will be omitted.

By the control described above, the average current of the high-voltage power supply for one frame (that is, the power of the high-voltage power supply) can be calculated from the APL value and the ABL operation can be performed even when there is no overflow processing. .

When the overflow processing is not performed, the integrated value (APL value) of the image data is the current value (I
Although it corresponds to a) as it is, this indicates that the current value (Ia) of the high-voltage power supply can be accurately obtained by correcting the influence of the voltage drop of the scanning wiring. That is, if the effect of the voltage drop is not corrected, it goes without saying that even if the integrated value of the image data is simply obtained, the current value of the high-voltage power supply will not be accurately met.

Also in the third embodiment, as in the second embodiment, when the influence of the voltage drop of the scanning wiring is not corrected, the actually discharged charge amount is the voltage drop of the scanning wiring. The image data and the amount of discharged electric charges do not match because they change depending on Therefore, it is impossible to accurately calculate the current value of the high-voltage power supply and accurately perform the ABL operation by the signal processing of the present embodiment.

Next, the method of determining the preset current limit value (Iamax) of the high-voltage power supply in the second and third embodiments will be described.

(1) Determined from the power of the display device. Determine the maximum power specifications of the high-voltage power supply from the maximum power specifications of the display device. Then, the current limit value (Iamax) is determined by dividing the maximum power value of the high voltage power supply by the voltage of the high voltage power supply. Then, the value is stored in the register 202.

(2) Determined by the user. Determine the maximum power specifications of the high-voltage power supply from the maximum power specifications of the display device.
Further, the maximum power consumption specification (energy saving mode) smaller than the above specification is determined. Then, the current limit values (Iamax1 and Iamax2) of the high-voltage power supplies corresponding thereto are calculated in advance by the method described above and stored in the memory inside the controller (not shown).

The user can select the normal mode or the energy saving mode by the user interface means (for example, remote controller). The controller refers to the internal memory and writes the current limit value in the register 202 so that it becomes Iamax1 in the normal mode, and writes the current limit value in the register 202 so that it becomes Iamax2 in the energy saving mode.

(3) Determined by the external environment. Determine the maximum power specifications of the high-voltage power supply from the maximum power specifications of the display device. Further, a second maximum power consumption specification (dark place mode) smaller than the above specification is determined. Then, the current limit values (Iamax3, I
amax4) is calculated in advance by the method described above and stored in a memory inside the controller (not shown).

The controller has an illumination sensor (not shown), and when the environment is bright, refers to the internal memory,
Register 202 so that the current limit value becomes Iamax3
And write the current limit value to Iamax4 when the environment is dark.
The register 202 is written so that

As described above, the current limit value (Iama) of the high voltage power supply in the second and third embodiments is set.
x) can be determined. In particular, the method of (2) or (3),
Alternatively, by combining the methods of (2) and (3), it is possible to further reduce the power and display an image. Also,
These methods can also be applied to the first embodiment described above.

According to this embodiment, the corrected image data is prevented from overflowing the input range of the modulation means.
By multiplying the gain, the image could be displayed with high quality. Further, by multiplying the integrated result of the input image data by the gain and detecting it as the current value of the high voltage power source, the ABL operation can be accurately performed with a small amount of hardware.

(Fourth Embodiment) The display device of this embodiment has a function of multiplying a coefficient for adjusting the amplitude of the corrected image data so that the amplitude of the corrected image data corresponds to the input range of the modulation means. It has an amplitude adjusting means. Also,
Current value calculating means for calculating an average current value corresponding to the light emission brightness of the display device based on the integrated value of the input image data which is the required brightness value and the coefficient, and an electron emitting element based on the average current value and a predetermined reference current value. Driving condition changing means for changing the driving condition of.

It is preferable that the current value calculating means has an integrating means for integrating the input image data, and the result of multiplying the output of the integrating means by the coefficient is an average current value corresponding to the light emission luminance of the display device. .

The drive condition changing means compares the average current value with the reference current value, and when the average current value is larger than the reference current value, sets the drive voltage for limiting the electric power related to the emission brightness of the display device. It is preferable to determine.

It is preferable that the drive condition changing means determines the drive voltage so that the average current value does not exceed the reference current value.

It is preferable that the drive condition changing means has a function of changing the calculation parameter used for calculating the corrected image data.

The reference current value is preferably determined in advance at the manufacturing stage or can be changed by at least one of the user interface means and the external environment detecting means.

The amplitude adjusting means detects the maximum value of the output of the corrected image data calculating means for each frame, and adjusts the amplitude of the corrected image data so that the maximum value falls within the upper limit of the input range of the modulating means. It is preferable to adaptively calculate the coefficient of.

The amplitude adjusting means refers to the outputs of the corrected image data calculating means for a plurality of frames before the current frame, and adjusts the corrected image data so that their values correspond to the input range of the modulating means. It is preferable to adaptively calculate the coefficient for adjusting the amplitude of.

The coefficient for adjusting the amplitude of the corrected image data is preferably a predetermined coefficient that always has a constant value.

The coefficient for adjusting the amplitude of the corrected image data is preferably a coefficient determined so that the output of the corrected image data calculation means does not overflow the input range of the modulation means when the input image data is maximum. Is.

The corrected image data calculating means is a means for predicting and calculating the spatial distribution and temporal change of the voltage drop amount that should occur on the row wiring during one horizontal scanning period, corresponding to the input image data. It is preferable to include means for calculating corrected image data obtained by correcting the input image data from the amount of voltage drop.

The corrected image data calculating means discretely predicts and calculates the spatial distribution and the time change of the voltage drop amount that should occur on the row wiring during one horizontal scanning period, corresponding to the input image data. And means for calculating corrected image data obtained by correcting the input image data from the calculated voltage drop amount.

The corrected image data calculating means discretely predicts and calculates the spatial distribution and the temporal change of the voltage drop amount that should occur on the row wiring during one horizontal scanning period, corresponding to the input image data. A discrete correction image data calculation means for discretely calculating correction image data for the image data corresponding to the time when the voltage drop amount is calculated, at the spatial position where the voltage drop amount is calculated, from the calculated voltage drop amount; , Interpolating the output of the discrete correction image data calculation means,
It is preferable to include a corrected image data interpolating unit that calculates corrected image data corresponding to the size of the input image data and the horizontal display position.

The correction image data calculated by the correction image data calculating means is such that the emission charge amount of the correction image data becomes the emission charge amount of the input image data when there is no voltage drop amount that should occur on the row wiring. It is preferably adjusted.

The driving condition changing means changes the driving voltage of the display element as the driving condition, and the driving voltage is the selection potential output from the scanning means, the potential output from the modulation means or the high voltage generation means. The voltage is preferably determined by the electric potential or a combination of these electric potentials.

Further, the corrected image data calculating means for calculating the corrected image data, which is the image data in which the influence of the voltage drop caused by the resistance of the scanning wiring and the scanning means is corrected with respect to the input image data, and the corrected image data. The amplitude adjusting means has a function of multiplying a coefficient for adjusting the amplitude of the corrected image data so that the amplitude of the modulating means corresponds to the input range of the modulating means. A display device that receives the corrected image data as an input and outputs a modulation signal to the modulation wiring, and is not 0,
Display in which, when uniform image data is input, the pulse width of the pulse output from the modulation means near the output terminal of the scanning means is shorter than the pulse width of the pulse output from the modulation means far from the output terminal of the scanning means. In the device, current value calculation means for calculating an average current value corresponding to the emission brightness of the display device based on the integrated value of the input image data, and changing the driving condition of the electron-emitting device based on the average current value and a predetermined reference current value. It is preferable that the driving condition changing means is provided.

The drive condition changing means compares the average current value and the reference current value, and when the average current value is larger than the reference current value, sets the drive voltage for limiting the power related to the light emission brightness of the display device. It is preferable to determine.

The driving condition changing means, when the average current value is larger than the reference current value, is the condition for determining the driving voltage, that is, the selection potential output by the scanning means, the potential output by the modulating means and the potential of the high voltage generating means. It is preferable to reduce the absolute value of at least one of the potentials.

The characteristic configuration of the brightness control means according to the present embodiment will be described in detail.

FIG. 37 shows an example of a circuit configuration for performing signal processing for controlling the brightness of one frame. Here, description of the same components as those shown in FIGS. 14, 26, 31, 35 and 36 will be omitted.

In FIG. 37, the high voltage power supply current value calculating circuit (current value calculating means) and the ABL circuit (power limiting means) are surrounded by broken lines. Since the conversion unit 210 and the selection voltage generation unit 211 are also units for changing the driving conditions, they can also be referred to as driving condition changing units.

In the configuration of FIG. 37, the conversion means 210
Is a table memory to which the output of the multiplier 201 (Ia: corresponding to the current value of the high-voltage power supply) and the current limit value (Iamax: reference current value) of the high-voltage power supply set in the register 202 in advance are input. . Then, if the output of the multiplier 201 (corresponding to the current value of the high-voltage power supply) is larger than the preset current limit value (Iamax), the drive condition is changed in order to limit the power of the display device.

More specifically, as shown in FIG.
For the output of the multiplier 201 (Ia: corresponding to the current value of the high-voltage power supply) exceeding the current limit value (Iamax), A in FIG.
The drive voltage instruction value (SV _DRV ) is reduced as indicated by.

In FIG. 38, the horizontal axis represents the output of the multiplier 201 (Ia: corresponding to the current value of the high-voltage power supply), the vertical axis represents the drive voltage instruction value SV _DRV , and the potential (VPwm) of the output of the modulation means. _Is a numerical value (for example, digital amount data) corresponding to V _DRV that is a potential difference between the scanning circuit and the selection potential (Vs) of the scanning circuit. Further, in FIG. 38, SVsel is a drive voltage instruction value corresponding to the rated voltage V _SEL of the surface conduction electron-emitting device.

In the curve of the specific characteristic shown by A in FIG. 38, the output (Ia) of the multiplier 201 is the current limit value (Iam).
The curve was determined so that the actual power would not be higher if it was calculated to exceed ax).
An example in which the current limit value Iamax is set to be smaller is shown by the characteristic of B in FIG. Drive voltage instruction value SV _DR
It can be seen that _V decreases since the output Ia of the multiplier 201 is smaller.

[0487] The selection voltage generator 211 determines the drive voltage instruction value S
Convert V _DRV to the actual drive voltage (V _{DR V} ). As a method of changing the drive voltage, at least one of the output potential (Vpwm) of the modulation means 8 and the selection potential (Vs) of the scanning circuits 2 and 2 ′ may be changed. In this embodiment, only the selection potential (Vs) of the scanning circuits 2 and 2'is changed in order to limit the power.

FIG. 39 is a graph showing the characteristics of the selection voltage generator 211, where the horizontal axis represents the output of the multiplier 201 (Ia:
(Corresponding to the current value of the high-voltage power supply), and the vertical axis represents the selection potential (Vs) of the scanning circuits 2 and 2 '. Scanning circuits 2 and 2 '
The selection potential (Vs) is output at a drive voltage instruction value _{SV DRV} to the drive voltage of the selection voltage generating portion 211 _{(V DRV)}
So that Note that Vs0 is −0.5 × V
_It was determined to be _SEL .

The characteristic curves of A and B in FIG. 38 correspond to the characteristic curves of A and B in FIG. 39, respectively. Then, the selection voltage generator 211 changes the selection potential Vs of the scanning circuits 2 and 2 ′ so that the absolute value thereof becomes small when the output (Ia) of the multiplier 201 exceeds a predetermined value.
That is, the scanning circuits 2 and 2 ′ function as a sub power supply in which the selection potential Vs output from the scanning circuits 2 and 2 ′ changes according to the output of the selection voltage generation unit 211.

With the configuration in which the selection potentials of the scanning circuits 2 and 2'are changed in this way, the influence of the voltage drop can be corrected and further the ABL operation can be performed.

In the fourth embodiment, the conversion means 210
Is selected as a digital output, and the selection voltage generating section 211 is provided with an analog-digital converter therein to output an analog signal, which can be realized at a low cost in terms of circuit configuration.

In the fourth embodiment, the driving condition is such that the selection potential of the scanning circuits 2 and 2 ′, which is the driving voltage, is variable. Apart from this, the potential of the output of the modulation means 8 may be changed as the drive voltage, or both the selection potential of the scanning circuits 2 and 2 ′ and the potential of the output of the modulation means 8 may be changed. . Furthermore, the ABL operation can be performed even if the potential of the high voltage power supply is changed.

In the fourth embodiment, the influence of the voltage drop of the scanning wiring is corrected. Therefore, when the driving condition (driving voltage: V _DRV ) is largely changed, an error may occur in the calculation of the correction of the influence of the voltage drop of the scanning wiring. Next, a configuration for realizing a method for reducing this error will be described.

(Fifth Embodiment) FIG. 40 shows the structure of a display device of this embodiment.

The structural difference between FIG. 40 and FIG. 37 is that the brightness control means supplies the drive voltage instruction value SV _DRV output from the conversion means 210 to the correction data calculation means 14. Description of the same parts as those in the fourth embodiment will be omitted.

In FIG. 40, the conversion means 210 performs multiplication.
Set the output (Ia) of the instrument 201 and the register 202 in advance
The current limit value (Iamax) of the high voltage power supply
Drive conditions to receive power and limit the power of the display device
Drive voltage instruction value SV _DRVChange and output
It

As described above, the drive voltage instruction value SV _DRV is input to the selection voltage generator 211 and used to change the selection potential of the scanning circuits 2 and 2'and limit the power of the high voltage power supply of the display panel. To be Further, the drive voltage instruction value SV _DRV is sent to the correction data calculation means 14 through the wiring 220, and is used to change the calculation parameter of the voltage drop correction and calculate the correction image data, as described later.

Regarding the operation of the converting means 210, the following operation is more preferable in this method.

If SV _SEL is a drive voltage instruction value corresponding to the rated voltage of the surface conduction electron-emitting device, the conversion means 210
Determines SV _DRV as:

[Equation 34]

The conversion means 210 outputs the drive voltage instruction value (SV _DRV ) described above. Others operate as described above.

In this embodiment, the ABL operation could be performed even if the potential of the high voltage power supply was changed. When the high-voltage power supply is changed, the amount of voltage drop hardly changes, but the amount of emission current of the electron-emitting device slightly changes, so that amount is considered as a parameter.

In the present embodiment, even if the driving condition (driving voltage: V _DRV ) changes greatly, there is no error in the calculation of the correction of the influence of the voltage drop of the scanning wiring, and it is possible to obtain good results.
ABL operation was realized.

If the effect of the voltage drop of the scanning wiring is not corrected, the amount of electric charge actually discharged changes depending on the voltage drop of the scanning wiring, so the image data and the amount of discharged electric charge do not match. . Therefore, it may not be possible to perform an accurate ABL operation.

The current value calculation method and ABL of the high-voltage power supply have been described for the case where the overflow process is performed. However, when the voltage drop amount is small or the scanning time is long and the overflow process is not necessary, the gain is increased. G
Since 1 is 1, the maximum value detection circuit 20, the gain calculation means 21, and the multipliers 22 and 201 are unnecessary in the configuration of FIG.

When overflow processing is not performed,
The integrated value (APL value) of the image data directly corresponds to the current value (Ia) of the high-voltage power supply. This is because the current value (Ia) of the high-voltage power supply is accurately measured by correcting the influence of the voltage drop of the scanning wiring. ) Is required.
That is, it goes without saying that if the effect of the voltage drop is not corrected, simply calculating the integrated value of the image data does not accurately correspond to the current value of the high-voltage power supply.

(Shift Register, Latch Circuit) The corrected image data Dlim output from the limiter 24 is transferred from the serial data format by the shift register 5 to
The parallel image data ID1 to IDN for each modulation wiring are serial / parallel converted and output to the latch circuit 6. The latch circuit 6 latches the data from the shift register 5 by the timing signal Dataload immediately before the start of one horizontal period. The output of the latch circuit 6 is
The parallel image data D1 to DN are input to the modulation means 8.

In this embodiment, image data ID1 to ID
Each of N and D1 to DN is 8-bit image data. These operation timings are the timing control signals TSFT and Dataload from the timing generation circuit 4.
Work based on.

(Details of Modulating Means) The parallel image data D1 to DN output from the latch circuit 6 are supplied to the modulating means 8. The modulating means 8 has the structure shown in FIG. 18, and is the same as that of each of the above-described embodiments. The timing chart showing the operation of the modulation means 8 of this embodiment is
It is the same as that shown in FIG.

(Correction Data Calculation Means) The structure of the correction data calculation means 14 is the same as that shown in FIG. The configuration for discretely calculating the correction data is shown in FIG.
It is the same as that shown in 2.

(Sixth Embodiment) In the fourth and fifth embodiments, the maximum value of the corrected image data is detected, and the gain is adjusted so that the maximum value corresponds to the maximum value of the input range of the modulating means 8. The calculated value is multiplied by the corrected image data to prevent overflow.

On the other hand, in the sixth embodiment, the maximum value of the corrected image data is detected similarly to the fourth and fifth embodiments described above. In this embodiment, the maximum value corresponds to the maximum value of the input range of the modulation means 8,
Limit the size of image data before correction. That is, in order to prevent overflow, the image data input in advance is multiplied by a gain to reduce its amplitude range, and overflow is prevented.

[0512] As a method of calculating another gain,
In the configuration of this embodiment, the gain may be calculated by the fixed gain method.

In the present embodiment, the maximum value of the corrected image data Dout within one frame is MAX, the maximum value of the input range of the modulating means is INMAX, and the gain calculated by the gain calculating means for the previous frame is GB. At this time, the gain G2 is determined using (Expression 26) described above.

In the gain calculating means 21, the gain is updated in the vertical blanking period and the gain value is changed for each frame.

In this embodiment, the maximum value of the correction image data of the previous frame is used to calculate the gain by which the correction image data of the current frame is multiplied, that is, the correction image data (image It is configured to prevent overflow by using the correlation of (data). Therefore, strictly speaking, overflow may occur due to the difference in the corrected image data for each frame. In order to prevent this, it is also preferable to provide limiter means for the output of the multiplier that multiplies the corrected image data and the gain, and to design the circuit so that the output of the multiplier always falls within the input range of the modulating means. .

Besides the gain determining method described above, the gain may be calculated by another method as described below. That is, the maximum value of the corrected image data detected in the frame before the current frame is averaged, and the gain G2 applied to the corrected image data of the current frame is averaged using the average value AMAX (Equation 27). ). However, GB is the gain G2 calculated by the gain calculating means 21 for the previous frame.

As another method, the current gain may be calculated by calculating the gain G2 for each frame by (Equation 26) and averaging it.

Of the three methods, any method is preferable in the sense of preventing overflow, but in consideration of occurrence of flicker, it is preferable to calculate by the method of (Equation 27).

In the gain calculation method of (Equation 27), the number of frames for averaging the maximum value of the corrected image data was examined.
When the maximum values of the corrected image data up to 64 frames before were averaged, a preferable image with little flicker was obtained.

It is needless to say that it is preferable to provide the limiter 24 for limiting the output of the adder 12 to prevent the overflow completely also in this method.

Further, the method of calculating the gain may be changed by detecting the scene change as in the fourth embodiment.

Below, the high-voltage power supply current value calculation circuit and the ABL
The brightness control means including a circuit will be described.

The principle and configuration of the high-voltage power supply current value calculation circuit are the same as those in the fourth embodiment, and the description thereof will be omitted.

Conventionally, a resistance for current detection is added to the high-voltage power supply and the current value of the high-voltage power supply is obtained from the voltage. However, according to the configuration of this embodiment, as in the fourth embodiment, It was possible to calculate the current value of the high-voltage power supply only by calculating the data without adopting such a structure. In the implementation of ABL, which will be described later, in particular, the hardware cost can be reduced as in the fourth embodiment.

In FIG. 41, reference numeral 200 is an integrating unit (integrating means) for integrating image data, which is a required brightness value, by one frame, 201 is a multiplier, and 202 is a limit value (I
amax) is stored in the register, 210 is a conversion unit, and 211 is a selection voltage generation unit (selection voltage generation unit). In FIG. 41, as described above, the output of the multiplier 201 corresponds to the current value (Ia) of the high voltage power supply. Figure 41
Then, the high-voltage power supply current value calculation circuit (current value calculation means) and A
The BL circuit (power limiting means) is shown surrounded by a broken line.

Also in this embodiment, as in the fourth embodiment,
As a driving condition, a driving voltage V_DRV(Among them, scanning times
The selection potential of paths 2 and 2 ': Vs) was changed. This embodiment
In the state, the effect of the voltage drop of the scanning wiring is corrected and
Drive conditions (drive voltage: V _DRV), Run
Change the parameters of the calculation of the compensation of the voltage drop effect
To change.

41 is the same as that shown in FIG. 40 except that the position to which the gain G2 for overflow processing is multiplied is the same, and the description of each part is omitted.

In FIG. 41, the conversion means 210 outputs the output of the multiplier 201 (Ia: corresponding to the current value of the high voltage power supply),
The drive voltage instruction value SV is set as the drive condition in order to receive the input with the current limit value (Iamax) of the high-voltage power supply set in the register 202 in advance and limit the power of the display device.
Change _DRV and output.

The drive voltage instruction value SV _DRV is input to the selection voltage generating section 211 and is used to change the selection potential of the scanning circuits 2 and 2'and limit the power of the high voltage power source of the display panel. Further, the drive voltage instruction value SV _DRV is sent to the correction data calculation means 14 through the wiring 220, and is used to change the calculation parameter and calculate the correction image data.

With regard to the operation of the conversion means 210, the following operation is preferable in this method, as in the fifth embodiment.

If SV _SEL is the drive voltage instruction value corresponding to the rated voltage of the surface conduction electron-emitting device, the conversion means 210
Determines SV _DRV as in (Expression 32) and (Expression 33).

The conversion means 210 outputs the drive voltage instruction value (SV _DRV ) described above. Others operate as described above.

In this embodiment, the driving condition is
Drive voltage (among them, selection potential of scanning circuits 2 and 2 ')
However, of course, the potential of the output of the modulation means 8 or both may be changed. Further, the ABL operation can be performed even if the potential of the high voltage power supply is changed.

In the present embodiment, even if the driving condition (driving voltage: V _DRV ) changes significantly, there is no error in the calculation of the correction of the influence of the voltage drop of the scanning wiring, and it is good,
ABL operation was realized.

Similar to the fourth embodiment, when the driving condition (driving voltage: V _DRV ) does not change significantly, the wiring 220 is used.
Therefore, the display image quality was not affected even if the calculation for correcting the influence of the voltage drop of the scanning wiring was performed. Then, the ABL operation was successfully realized.

Even in the present embodiment, when the effect of the voltage drop of the scanning wiring is not corrected, the amount of electric charges actually discharged changes with the voltage drop of the scanning wiring, and therefore, the amount of the electric charges discharged with the image data is changed. The amount of electric charge does not match. Therefore, it may not be possible to perform an accurate ABL operation.

The preset current limit value (I of the high-voltage power supply in the fourth to sixth embodiments)
The method of determining amax) is the same as the method of determining in the second and third embodiments described above, and thus the repetitive description is omitted.

As described above, according to the display devices of the fourth and fifth embodiments, there has been a conventional problem.
It was possible to improve the deterioration of the displayed image due to the voltage drop on the scanning wiring.

Further, the image can be displayed in high quality by multiplying by the gain so that the corrected image data does not overflow the input range of the modulation means.

Furthermore, by multiplying the integrated result of the input image data by the gain and detecting it as the current value of the high-voltage power supply, it is possible to accurately perform the brightness control with less hardware.

The method including the correction process and the brightness control process described above can be realized as a one-chip semiconductor integrated circuit, and can be distributed as an IP core therefor.

[0542]

As described above, according to the present invention, it is possible to realize a display device capable of displaying an image with better image quality than ever before, and an image signal processing device and a drive control device therefor.

Further, it is possible to realize a display device which can improve the accuracy of voltage drop correction, and an image signal processing device and a drive control device therefor.

Furthermore, when the voltage drop correction is performed, A
A display device capable of performing BL, and an image signal processing device and a drive control device therefor can be realized.

[0545] Further, the current of the high-voltage power supply (anode current)
A display device capable of calculating and accurately performing ABL,
An image signal processing device and a drive control device therefor can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram of a display device according to a preferred embodiment of the present invention.

FIG. 2 is a diagram showing an overview of a display panel.

FIG. 3 is a diagram showing an electrical connection of a display panel.

FIG. 4 is a diagram showing an example of characteristics of a surface conduction electron-emitting device.

FIG. 5 is a diagram showing an example of a method of driving a display panel.

FIG. 6 is a diagram illustrating an influence of a voltage drop.

FIG. 7 is a diagram illustrating a degenerate model.

FIG. 8 is a graph showing a voltage drop amount calculated discretely.

FIG. 9 is a graph showing the amount of change in emission current calculated discretely.

FIG. 10 is a diagram showing an example of calculation of correction data when the size of image data is 64.

FIG. 11 is a diagram showing an example of calculation of correction data when the size of image data is 128.

FIG. 12 is a diagram showing an example of calculation of correction data when the size of image data is 192.

FIG. 13 is a diagram for explaining an interpolation method of correction data.

FIG. 14 is a block diagram showing a configuration of a signal processing system and a drive system of the display device according to the first embodiment of the present invention.

FIG. 15 is a block diagram showing a configuration of a scanning circuit.

FIG. 16 is a block diagram showing a configuration of an inverse γ processing unit.

FIG. 17 is a block diagram showing a configuration of a data array conversion unit.

FIG. 18 is a diagram for explaining the configuration and operation of a modulation circuit.

FIG. 19 is a timing chart for explaining the operation of the modulation circuit.

FIG. 20 is a diagram for explaining a drive voltage calculation unit.

FIG. 21 is a diagram for explaining correction data calculation means.

FIG. 22 is a block diagram showing a configuration of a discrete correction data calculation unit.

FIG. 23 is a block diagram showing a configuration of a correction data interpolation unit.

FIG. 24 is a block diagram showing a configuration of a linear approximation unit.

FIG. 25 is a timing chart for explaining the operation of the display device according to the embodiment of the present invention.

FIG. 26 is a block diagram showing a configuration of a display device according to a second embodiment of the present invention.

FIG. 27 is a block diagram showing a configuration of a scanning circuit.

FIG. 28 is a diagram showing an example of images of four consecutive frames.

FIG. 29 is a graph showing the size of image data in four consecutive frames.

FIG. 30 is a graph showing how the gain changes in successive frames.

FIG. 31 is a block diagram showing a configuration of a modified example of the display device according to the second embodiment of the present invention.

FIG. 32 is a timing chart for explaining the operation of the modulation means.

FIG. 33 is a block diagram showing a configuration of a correction data calculation means.

FIG. 34 is a block diagram showing a configuration of a discrete correction data calculation unit.

FIG. 35 is a block diagram showing a configuration of a display device according to a third embodiment of the present invention.

FIG. 36 is a block diagram showing a configuration of a modified example of the display device according to the third embodiment of the present invention.

FIG. 37 is a block diagram showing a configuration of a display device according to a fourth embodiment of the present invention.

FIG. 38 is a diagram showing conversion characteristics of the conversion means.

FIG. 39 is a diagram showing characteristics of the selection voltage generating means.

FIG. 40 is a block diagram showing a configuration of a display device according to a fifth embodiment of the present invention.

FIG. 41 is a block diagram showing a configuration of a display device according to a sixth embodiment of the present invention.

FIG. 42 is a block diagram showing a configuration of a conventional display device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 display panel 2, 2'scanning circuit 3 sync signal separation circuit 4 timing generation circuit 5 shift register 6 latch circuit 7 RGB converter 8 modulator 9 data array converter 12 adder 14 correction data calculator 17 inverse gamma processor 19 Delay circuit 20 Maximum value detection circuit 21 Gain calculation means 22 Multipliers 22R, 22G, 22B Multiplier 23 Selector 24 Limiters 100a, 100b, 100c, 100d Lighting number counting means 101a, 101b, 101c, 101d Register 102 CPU 103 Table memory 104 Temporary register 105 Program memory 106 Register group 107a, 107b, 107c Comparator 108, 109, 110 Adder 111 Table memory 2 112 Table memory 3 113 Register 120, 121, 122 Linear approximation Means 123, 124 Decoder 125, 126, 127, 128 Selector 200 Accumulator 201 Accumulator 201 Multiplier 202 Register 203 Comparator 204 Divider 205 Switch 210 Convertor 211 Select voltage generator 220 Wiring 221 Average luminance level detector 222 Drive voltage calculator 301 display panel 302 scanning circuit 303 modulation circuit 304 correction circuit 305 detection circuit 306A, 306B, 306C control circuit 1001 substrate 1002 cold cathode device 1003 row wiring (scanning wiring) 1004 column wiring (modulation wiring) 1005 rear plate 1006 side wall 1007 face plate 1008 Fluorescent film 1009 Metal back 2021R, 2021G, 2021B FIFO memory 2022 Selector

Front page continuation (51) Int.Cl. ⁷ Identification code FI theme code (reference) H04N 5/66 H04N 5/66 A (72) Inventor Naoto Abe 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. In-house (72) Inventor Yutaka Saito 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Takeshi Ikeda 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. F-term (Reference) 5C058 AA03 BA01 BA05 BA08 BB11 5C080 AA18 BB05 DD05 EE28 FF12 GG01 GG12 JJ01 JJ02 JJ03 JJ04 JJ05 JJ06

Claims (15)

[Claims] 1. A display panel provided with display elements arranged in a matrix and driven through a plurality of row wirings and column wirings, a scanning means for scanning the row wirings, and based on image data, A modulation unit that supplies a modulation signal to the column wiring; and a correction unit that performs a correction process on the image data to compensate for a change in display luminance due to the effect of a voltage drop caused by at least the resistance of the row wiring. A brightness control unit that controls the display brightness of the display panel based on the brightness information of the image data. 2. The display device according to claim 1, wherein the brightness control means changes a drive voltage applied to the display panel according to the brightness information. 3. The brightness control means changes the drive voltage applied to the display panel in accordance with the brightness information, and changes the correction processing parameter in the correction means. The display device according to 1. 4. The display device according to claim 1, wherein the brightness control means changes a brightness level of the image data before or after the correction processing according to the brightness information. 5. The apparatus further comprises a coefficient calculation means for determining a coefficient for keeping the width of the image data after the correction processing within a predetermined range, and the brightness control means includes the coefficient and the brightness. The display device according to claim 1, wherein the display brightness of the display panel is changed based on the information. 6. The image processing apparatus further comprises a coefficient calculation means for determining a coefficient for keeping the width of the image data after the correction processing within a predetermined range, and the brightness control means comprises the coefficient and the brightness. The value obtained from the information is compared with a predetermined luminance limit reference value, and the luminance level of the image data after the correction processing is changed based on the comparison result. Display device. 7. The display panel is a display panel having a common anode electrode, and further has a coefficient calculating means for determining a coefficient for keeping the width of the image data after the correction processing within a predetermined range. From the integrated value of the image data and the coefficient, a value corresponding to the current value flowing in the anode electrode is calculated, and the calculated value is compared with a predetermined brightness limit reference value, and the comparison result is obtained. The display device according to claim 1, wherein the display brightness of the display panel is changed based on the above. 8. The brightness control means changes the display brightness of the display panel in accordance with the brightness information and the set brightness restriction reference value, and the brightness restriction reference value is the brightness of the display device. The display device according to claim 1, wherein the display device can be changed by at least one of power consumption, user interface means, and external environment detection means. 9. A display panel provided with display elements which are arranged in a matrix and driven through a plurality of row wirings and column wirings, scanning means for scanning the row wirings, and based on incoming image data. An image signal processing device for processing image data to be input to a display device having a modulation means for supplying a modulation signal to the column wiring, and displaying by an influence of a voltage drop generated by at least the resistance of the row wiring. A correction unit that performs a correction process for compensating for fluctuations in brightness on the image data, and changes the brightness level of the image data to control the display brightness of the display panel based on the brightness information of the image data. An image signal processing device comprising: a brightness control unit. 10. A display panel provided with display elements arranged in a matrix and driven through a plurality of row wirings and column wirings, a scanning means for scanning the row wirings, and based on incoming image data. In the drive control device for controlling the drive of the display device having a modulation means for supplying a modulation signal to the column wiring, the fluctuation of the display luminance due to the influence of the voltage drop generated by at least the resistance of the row wiring is suppressed. A correction unit that performs a correction process for compensating the image data, and a brightness control unit that changes the drive voltage of the display panel to control the display brightness of the display panel based on the brightness information of the image data. A drive control device comprising: 11. The parameter of the correction process is changed according to the change of the drive voltage.
The drive control device according to item 0. 12. A display panel provided with display elements which are arranged in a matrix and driven through a plurality of row wirings and column wirings, a scanning means for scanning the row wirings, and based on incoming image data. An image signal processing method for processing image data to be input to a display device having a modulation means for supplying a modulation signal to the column wiring, and displaying by the influence of a voltage drop generated by at least the resistance of the row wiring. A correction step of performing a correction process for compensating for a variation in brightness on the image data, and changing the brightness level of the image data to control the display brightness of the display panel based on the brightness information of the image data. An image signal processing method, comprising: a brightness control step. 13. A display panel provided with display elements arranged in a matrix and driven through a plurality of row wirings and column wirings, a scanning means for scanning the row wirings, and based on incoming image data. In the drive control method for controlling the drive of the display device having a modulation means for supplying a modulation signal to the column wiring, the fluctuation of the display brightness due to the influence of the voltage drop caused by at least the resistance of the row wiring is suppressed. A correction step of performing a correction process for compensation on the image data, and a brightness control step of changing the drive voltage of the display panel to control the display brightness of the display panel based on the brightness information of the image data. A drive control method comprising: 14. The parameter of the correction process is changed according to the change of the drive voltage.
3. The drive control method according to item 3. 15. A display panel provided with display elements arranged in a matrix and driven through a plurality of row wirings and column wirings, a scanning unit for scanning the row wirings, and an input image data. A modulation unit that supplies a modulation signal to the column wiring based on the above, a common anode electrode facing the display element, and a variation in display brightness due to a voltage drop caused by at least the resistance of the row wiring is compensated. Correction processing for performing the correction processing for the image data, coefficient calculation means for determining a coefficient for keeping the width of the image data after the correction processing within a predetermined range, and an integrated value of the image data A current value calculation means for calculating a value corresponding to a value of a current flowing through the anode electrode from a multiplication result of the coefficient.