JP2003243827A - Manufacturing method of multilayer ceramic substrate - Google Patents
Manufacturing method of multilayer ceramic substrateInfo
- Publication number
- JP2003243827A JP2003243827A JP2002036506A JP2002036506A JP2003243827A JP 2003243827 A JP2003243827 A JP 2003243827A JP 2002036506 A JP2002036506 A JP 2002036506A JP 2002036506 A JP2002036506 A JP 2002036506A JP 2003243827 A JP2003243827 A JP 2003243827A
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- Prior art keywords
- ceramic layer
- conductor
- insulator
- ceramic
- laminated
- Prior art date
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Abstract
(57)【要約】
【課題】 導体と第１のセラミック層との界面に発生す
る構造欠陥を抑制することを目的とするものである。
【解決手段】 第１のセラミック層１１と導体１３ｂ，
１３ｃとを積層したものの表裏面に第２のセラミック層
１２を圧着して積層体を作製する第１の工程と、第１の
セラミック層１１が焼結しかつ第２のセラミック層１２
が焼結しない温度で前記積層体を焼成する第２の工程
と、前記積層体から第２のセラミック層１２を除去する
第３の工程を有し、少なくとも一方の第２のセラミック
層１２の第１のセラミック層１１に接する面に絶縁体１
５を形成し、絶縁体１５の少なくとも一部を被覆するよ
うに導体１３ａを形成する積層セラミック基板の製造方
法。
(57) Abstract: An object is to suppress structural defects occurring at an interface between a conductor and a first ceramic layer. SOLUTION: A first ceramic layer 11 and a conductor 13b,
13c, the first ceramic layer 11 is sintered and the second ceramic layer 12
A second step of firing the laminate at a temperature at which the second ceramic layer 12 is not sintered, and a third step of removing the second ceramic layer 12 from the laminate. Insulator 1 on the surface in contact with ceramic layer 11
5. A method for manufacturing a laminated ceramic substrate, wherein the conductor 13a is formed so as to cover at least a part of the insulator 15 by forming the conductor 5.
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、チップ部品、半導
体等を実装する積層セラミック基板の製造方法に関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a laminated ceramic substrate on which chip parts, semiconductors, etc. are mounted.
【０００２】[0002]
【従来の技術】従来の積層セラミック基板の製造方法に
ついて説明する。2. Description of the Related Art A conventional method for manufacturing a laminated ceramic substrate will be described.
【０００３】まずガラス成分を含む無機粉末に有機バイ
ンダ及び可塑剤などを混合して第１のセラミック層を作
製し、この上に導体ペーストを印刷することにより、導
体を形成する。First, an inorganic binder containing a glass component is mixed with an organic binder and a plasticizer to form a first ceramic layer, and a conductor paste is printed on the first ceramic layer to form a conductor.
【０００４】また、無機粉末に有機バインダ及び可塑剤
などを混合して第１のセラミック層の焼結温度では焼結
しない第２のセラミック層を作製し、この上に導体ペー
ストを印刷して導体を形成する。Further, an inorganic binder is mixed with an organic binder and a plasticizer to prepare a second ceramic layer that does not sinter at the sintering temperature of the first ceramic layer, and a conductor paste is printed on the second ceramic layer to form a conductor. To form.
【０００５】次に、導体付き第１のセラミック層を積層
し、表面に導体を有する一方の面には導体を形成してい
ない第２のセラミック層を、導体を有しない他方の面に
は導体付き第２のセラミック層を重ね合せて加熱及び加
圧することにより積層体を作製する。Next, a first ceramic layer with a conductor is laminated, a second ceramic layer having no conductor is formed on one surface having a conductor on the surface, and a conductor is formed on the other surface having no conductor. A laminated body is produced by stacking the attached second ceramic layers and heating and pressing.
【０００６】次いで、この積層体を第１のセラミック層
が焼結し、第２のセラミック層が焼結しない温度で焼成
する。この時、第２のセラミック層は、焼結せずほとん
ど収縮しないので、焼結により収縮しようとする第１の
セラミック層を拘束することになる。従って、第１のセ
ラミック層の平面方向の収縮を抑制することができる。Next, the laminate is fired at a temperature at which the first ceramic layer does not sinter and the second ceramic layer does not. At this time, since the second ceramic layer does not sinter and hardly shrinks, it constrains the first ceramic layer which tends to shrink by sintering. Therefore, the contraction of the first ceramic layer in the plane direction can be suppressed.
【０００７】その後、焼結していない第２のセラミック
層のみを除去することにより、平面精度に優れた積層セ
ラミック基板を得る。After that, only the second ceramic layer which is not sintered is removed to obtain a monolithic ceramic substrate excellent in plane accuracy.
【０００８】この積層セラミック基板に、ＳＡＷフィル
タなどのチップ部品や、ダイオードなどの半導体を実装
してモジュールを作製する。A module is manufactured by mounting a chip component such as a SAW filter and a semiconductor such as a diode on the laminated ceramic substrate.
【０００９】[0009]
【発明が解決しようとする課題】上記方法によると、焼
成時、第１のセラミック層は厚み方向のみに収縮しよう
とするが、導体は第１のセラミック層よりも収縮量が大
きい。According to the above method, the first ceramic layer tries to shrink only in the thickness direction during firing, but the conductor has a larger shrinkage amount than the first ceramic layer.
【００１０】従って、導体と第１のセラミック層の界面
の応力が大きく、衝撃などが加わった場合、導体と第１
のセラミック層との界面に、クラックなどの構造欠陥が
発生しやすいという問題点を有していた。Therefore, when the stress at the interface between the conductor and the first ceramic layer is large and a shock is applied, the conductor and the first ceramic layer
There is a problem that structural defects such as cracks are likely to occur at the interface with the ceramic layer.
【００１１】そこで本発明は、導体と第１のセラミック
層との界面に発生する構造欠陥を抑制することを目的と
するものである。Therefore, the present invention aims to suppress structural defects occurring at the interface between the conductor and the first ceramic layer.
【００１２】[0012]
【課題を解決するための手段】上記目的を達成するため
に、本発明は以下の構成を有するものである。In order to achieve the above object, the present invention has the following constitution.
【００１３】本発明の請求項１に記載の発明は、特に、
第２のセラミック層の表面に絶縁体を形成し、前記絶縁
体の少なくとも一部を被覆するように導体を形成したも
のを、導体と第１のセラミック層とを積層した積層体の
表裏面の少なくとも一方に導体が接するように第２のセ
ラミック層を圧着して焼成し、その後、第２のセラミッ
ク層を除去するものであり、絶縁体で導体の端部を被覆
しているのでこの部分の強度が向上し、構造欠陥の発生
を抑制することができる。The invention according to claim 1 of the present invention is
An insulating material is formed on the surface of the second ceramic layer, and a conductor is formed so as to cover at least a part of the insulating material. The second ceramic layer is pressed and fired so that the conductor is in contact with at least one side, and then the second ceramic layer is removed. Since the end portion of the conductor is covered with an insulator, The strength is improved and the occurrence of structural defects can be suppressed.
【００１４】本発明の請求項２に記載の発明は、特に、
表面あるいは裏面の少なくとも一方に導体を有する積層
体の前記導体の少なくとも端部を絶縁体で被覆した後、
前記積層体の表裏面に第２のセラミック層を圧着して焼
成し、その後前記第２のセラミック層を除去するもので
あり、絶縁体で導体の端部を被覆しているのでこの部分
の強度が向上し、構造欠陥の発生を抑制することができ
る。The invention according to claim 2 of the present invention is
After coating at least an end portion of the conductor of the laminate having a conductor on at least one of the front surface or the back surface with an insulator,
A second ceramic layer is pressure-bonded to the front and back surfaces of the laminate to be fired, and then the second ceramic layer is removed. Since the end portion of the conductor is covered with an insulator, the strength of this portion is increased. And the occurrence of structural defects can be suppressed.
【００１５】[0015]
【発明の実施の形態】（実施の形態１）以下、実施の形
態１を用いて本発明の特に、請求項１，２に記載の発明
について図面を参照して説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) Hereinafter, Embodiment 1 will be used to explain the present invention, particularly the inventions described in claims 1 and 2, with reference to the drawings.
【００１６】図１〜図５は、本実施の形態における積層
セラミック基板の製造工程を説明するための断面図であ
る。1 to 5 are cross-sectional views for explaining the manufacturing process of the laminated ceramic substrate according to the present embodiment.
【００１７】図において、１１は酸化アルミニウムなど
の無機粉末に、ガラス成分を含有する第１のセラミック
層、１２は酸化アルミニウムなどの無機粉末を含有する
第２のセラミック層、１３ａ，１３ｂ，１３ｃは、Ａ
ｇ，Ｐｔ，Ｐｄ，Ｃｕ，Ｗ，Ｍｏ，Ｎｉ等で、第１のセ
ラミック層１１を焼結する温度で焼結する導体である。
１５は酸化アルミニウムなどの絶縁体である。In the figure, 11 is a first ceramic layer containing an inorganic powder such as aluminum oxide and a glass component, 12 is a second ceramic layer containing an inorganic powder such as aluminum oxide, and 13a, 13b and 13c are shown. , A
The conductor is g, Pt, Pd, Cu, W, Mo, Ni or the like and is sintered at a temperature at which the first ceramic layer 11 is sintered.
Reference numeral 15 is an insulator such as aluminum oxide.
【００１８】まず、酸化アルミニウムなどの無機粉末
に、ガラス成分を、有機バインダ、可塑剤を混合して第
１のセラミック層１１を作製する。この第１のセラミッ
ク層１１はガラス成分を多く含むため焼結温度が低いも
のとなる。また、その厚みは、５〜３００μｍ程度であ
る。First, a glass component is mixed with an inorganic powder such as aluminum oxide, an organic binder and a plasticizer to form a first ceramic layer 11. Since the first ceramic layer 11 contains a large amount of glass component, the sintering temperature is low. The thickness is about 5 to 300 μm.
【００１９】次に、この第１のセラミック層１１にメカ
ニカルパンチング、もしくはレーザー等によりビアホー
ルを形成し、導体ペーストを埋め込むことにより導体１
３ｃを形成する。さらに所定の第１のセラミック層１１
の表面にスクリーン印刷等によりコンデンサ、インダク
タ等を形成する導体１３ｂを形成する。Next, a via hole is formed in the first ceramic layer 11 by mechanical punching or laser or the like, and a conductor paste is embedded in the via hole to form the conductor 1.
3c is formed. Further, the predetermined first ceramic layer 11
A conductor 13b forming a capacitor, an inductor, etc. is formed on the surface of the substrate by screen printing or the like.
【００２０】また酸化アルミニウムなどの無機粉末に有
機バインダ、可塑剤を混合して第２のセラミック層１２
を作製する。この第２のセラミック層１２の焼結温度
は、第１のセラミック層１１の焼結温度より高く、第１
のセラミック層１１の焼結温度においては、ほとんど収
縮しないものである。The second ceramic layer 12 is prepared by mixing an inorganic powder such as aluminum oxide with an organic binder and a plasticizer.
To make. The sintering temperature of the second ceramic layer 12 is higher than the sintering temperature of the first ceramic layer 11,
It hardly shrinks at the sintering temperature of the ceramic layer 11.
【００２１】この第２のセラミック層１２の表面にスク
リーン印刷などにより絶縁ペーストを塗布し、絶縁体１
５を作製する。An insulating paste is applied to the surface of the second ceramic layer 12 by screen printing or the like to form an insulator 1.
5 is produced.
【００２２】次にこの絶縁体１５の端部を覆うように第
２のセラミック層１２の上に導体１３ａを形成する。こ
の絶縁体１５は第１のセラミック層１１を構成する無機
材料（本実施の形態においては酸化アルミニウム）を用
いる。Next, a conductor 13a is formed on the second ceramic layer 12 so as to cover the end portion of the insulator 15. The insulator 15 uses an inorganic material (aluminum oxide in the present embodiment) that forms the first ceramic layer 11.
【００２３】その後、図１に示すように、絶縁体１５お
よび導体１３ａを形成した第２のセラミック層１２の上
に、導体１３ａが第１のセラミック層１１と接するよう
に導体１３ａ，１３ｂを形成した第１のセラミック層１
１を積層し、加熱および加圧を行い一体化させる。Thereafter, as shown in FIG. 1, conductors 13a and 13b are formed on the second ceramic layer 12 on which the insulator 15 and the conductor 13a are formed so that the conductor 13a is in contact with the first ceramic layer 11. First ceramic layer 1
1 is laminated and heated and pressed to be integrated.
【００２４】次に、導体１３ａ，１３ｂを形成した第１
のセラミック層１１を所定の構造となるように、積層
し、加熱および加圧を行い一体化させ、最上層に導体１
３ｂを有するようにする。Next, the first conductors 13a and 13b are formed.
The ceramic layers 11 are laminated so as to have a predetermined structure, heated and pressed to be integrated, and the conductor 1 is formed on the uppermost layer.
3b.
【００２５】次いで最上層の導体１３ｂの端部を被覆す
るように絶縁ペーストを印刷し、絶縁体１５を形成す
る。Next, an insulating paste is printed so as to cover the end of the uppermost conductor 13b to form the insulator 15.
【００２６】その後、この上に絶縁体１５および導体１
３ａを形成していない第２のセラミック層を積層し、加
熱および加圧することにより一体化して、図２に示すよ
うな仮積層体ブロックを作製する。After that, the insulator 15 and the conductor 1 are formed on this.
A second ceramic layer on which 3a is not formed is laminated and integrated by heating and pressing to produce a temporary laminate block as shown in FIG.
【００２７】次に、この仮積層体ブロックを先の工程で
行った加圧よりもさらに高い圧力で加圧し、図３に示す
積層体ブロックを得る。Next, this temporary laminate block is pressed at a pressure higher than the pressure applied in the previous step to obtain the laminate block shown in FIG.
【００２８】そしてこの積層体ブロックを第１のセラミ
ック層１１および導体１３ａ，１３ｂ，１３ｃが焼結
し、第２のセラミック層１２が焼結せずほとんど収縮し
ない温度で焼成し、図４に示す焼結体を得る。焼成時、
第２のセラミック層１２は、ほとんど収縮しないので、
焼結により収縮しようとする第１のセラミック層１１を
拘束することになる。従って、第１のセラミック層１１
の平面方向の収縮を抑制することができるのである。Then, the laminated body block is fired at a temperature at which the first ceramic layer 11 and the conductors 13a, 13b, 13c are sintered, and the second ceramic layer 12 is not sintered and shrinks little, as shown in FIG. Obtain a sintered body. When firing,
Since the second ceramic layer 12 hardly shrinks,
This will constrain the first ceramic layer 11 that is trying to shrink due to sintering. Therefore, the first ceramic layer 11
It is possible to suppress the contraction in the plane direction.
【００２９】その後、焼結していない第２のセラミック
層１２のみを除去することにより、図５に示すように平
面精度に優れた積層セラミック基板を得る。第２のセラ
ミック層１２は焼結していないので、第１のセラミック
層１１および表面の導体１３ａ，１３ｂをほとんど損傷
することなく、容易に除去することができる。Thereafter, only the second ceramic layer 12 which has not been sintered is removed to obtain a monolithic ceramic substrate having excellent planar accuracy as shown in FIG. Since the second ceramic layer 12 is not sintered, it can be easily removed with almost no damage to the first ceramic layer 11 and the conductors 13a and 13b on the surface.
【００３０】この基板の表、裏面の導体１３ａ，１３ｂ
は、端部を絶縁体１５で被覆しているので、この部分の
強度が向上し、衝撃にも強く、クラックなどの構造欠陥
の発生を抑制することができる。Conductors 13a and 13b on the front and back surfaces of this substrate
Since the end portion is covered with the insulator 15, the strength of this portion is improved, it is resistant to impact, and the occurrence of structural defects such as cracks can be suppressed.
【００３１】また絶縁体１５として、第１のセラミック
層１１を構成する無機材料を用いているので、焼成によ
りこの絶縁体１５と第１のセラミック層１１とが反応
し、絶縁体１５が第１のセラミック層１１と強固に結び
つき、接着強度をさらに向上させることができる。Further, since the inorganic material forming the first ceramic layer 11 is used as the insulator 15, the insulator 15 and the first ceramic layer 11 react with each other by firing, and the insulator 15 becomes the first insulator. It can be strongly bonded to the ceramic layer 11 and the adhesive strength can be further improved.
【００３２】なお、積層セラミック基板の表、裏面の導
体１３ａ，１３ｂは、半田濡れ性を確保するために、Ｎ
ｉ−Ａｕメッキ等を施すことが一般的である。The conductors 13a and 13b on the front and back surfaces of the monolithic ceramic substrate are made of N in order to secure solder wettability.
It is common to apply i-Au plating or the like.
【００３３】この積層セラミック基板の表面にＳＡＷフ
ィルタなどのチップ部品や、ダイオードなどの半導体を
実装し、裏面の導体１３ａを用いて、他の回路基板に実
装することにより小型で優れた特性を有する電子機器を
得ることができる。By mounting a chip component such as a SAW filter or a semiconductor such as a diode on the surface of this multilayer ceramic substrate and mounting it on another circuit substrate by using the conductor 13a on the back surface, it has a small size and excellent characteristics. Electronic equipment can be obtained.
【００３４】さて、本実施の形態の積層セラミック基板
と、従来の積層セラミック基板（表面の導体の端部が絶
縁体で被覆されていないもの）について落下試験を行っ
た。A drop test was conducted on the laminated ceramic substrate of the present embodiment and a conventional laminated ceramic substrate (one in which the end portions of the conductor on the surface are not covered with an insulator).
【００３５】用いた積層セラミック基板は、縦６．７ｍ
ｍ、横５．０ｍｍ、高さ０．７ｍｍである。The laminated ceramic substrate used has a length of 6.7 m.
m, width 5.0 mm, height 0.7 mm.
【００３６】落下試験は、積層セラミック基板を複数
個、プリント基板に実装し、このプリント基板の外周部
を１５０ｇの金属製の枠に嵌めて、この枠を１．８ｍの
高さから、各面を下に向けてそれぞれ３回ずつ落下させ
て、クラックの発生数を調査した。In the drop test, a plurality of laminated ceramic substrates were mounted on a printed circuit board, the outer peripheral portion of the printed circuit board was fitted into a metal frame of 150 g, and the frame was measured from a height of 1.8 m on each surface. Was dropped three times downward, and the number of cracks generated was examined.
【００３７】この結果を（表１）に示す。The results are shown in (Table 1).
【００３８】[0038]
【表１】 [Table 1]
【００３９】この表を見ると分かるように、本実施の形
態の積層セラミック基板は、表面の導体１３ａ，１３ｂ
の外周部を絶縁体１５で被覆しているので、落下衝撃に
対してクラックの発生を抑制することが可能である。As can be seen from this table, the laminated ceramic substrate of the present embodiment has the surface conductors 13a and 13b.
Since the outer peripheral portion of is covered with the insulator 15, it is possible to suppress the occurrence of cracks against a drop impact.
【００４０】また、本実施の形態で用いた絶縁体１５
は、積層セラミック基板の耐湿性を向上させることがで
きる。The insulator 15 used in this embodiment is also used.
Can improve the moisture resistance of the laminated ceramic substrate.
【００４１】このことを確認するために以下の結露試験
を行った。In order to confirm this, the following condensation test was conducted.
【００４２】積層セラミック基板の表面に、ラインアン
ドスペースが６０μｍ〜１２０μｍの櫛形電極を形成
し、この電極表面全体を絶縁体１５で被覆したもの及び
絶縁体１５で被覆しなかったものに電圧を印加しながら
５℃，６０％ＲＨで２０分放置し、続いて２５℃，９０
％ＲＨで２０分放置することを１サイクルとし、櫛型電
極の絶縁抵抗１０11未満になった時点で試験を終了し
た。A comb-shaped electrode having a line-and-space of 60 μm to 120 μm is formed on the surface of the monolithic ceramic substrate, and a voltage is applied to the electrode surface entirely covered with the insulator 15 and the electrode not covered with the insulator 15. While standing at 5 ° C and 60% RH for 20 minutes, then at 25 ° C and 90%
The test was terminated when the insulation resistance of the comb-shaped electrode was less than 10 11 as one cycle, which was allowed to stand at% RH for 20 minutes.
【００４３】この結果を（表２）に示す。The results are shown in (Table 2).
【００４４】[0044]
【表２】 [Table 2]
【００４５】この表からも、絶縁体１５を設けることに
より耐湿性が向上することが分かる。From this table, it can be seen that the moisture resistance is improved by providing the insulator 15.
【００４６】従って、積層セラミック基板の表面に設け
た導体１３ａ，１３ｂを被覆する絶縁体１５は、この導
体１３ａ，１３ｂの端部だけでなく、他の部品を実装あ
るいは他の部品に実装する部分を除いて、積層セラミッ
ク基板の表面全体を被覆することにより、構造欠陥の発
生を抑制するだけでなく、耐湿性も向上させることがで
きる。Therefore, the insulator 15 that covers the conductors 13a and 13b provided on the surface of the laminated ceramic substrate is not limited to the end portions of the conductors 13a and 13b, but is also a part where other components are mounted or mounted on other components. By covering the entire surface of the monolithic ceramic substrate except the above, not only the occurrence of structural defects can be suppressed but also the moisture resistance can be improved.
【００４７】なお、絶縁体１５を形成するための絶縁体
ペーストとしては、絶縁体１５となる無機材料が６５〜
８０ｗｔ％のものを用い、焼成後の絶縁体１５の厚みが
１０μｍ以上であることが好ましい。それより薄けれ
ば、第１のセラミック層１１よりもポーラスとなり、例
えばメッキ工程等を経る場合、メッキ液等が浸入し、絶
縁体１５に覆われた導体１３ａ，１３ｂにメッキが付着
したり、メッキ液に侵され導体１３ａ，１３ｂの剥離を
誘発する可能性がある。As the insulator paste for forming the insulator 15, the inorganic material forming the insulator 15 is 65-55.
It is preferable to use 80 wt% of the insulator, and the thickness of the insulator 15 after firing is 10 μm or more. If it is thinner than that, it becomes more porous than the first ceramic layer 11, and, for example, when a plating process or the like is performed, a plating solution or the like penetrates and the plating adheres to the conductors 13a and 13b covered with the insulator 15. There is a possibility that the conductors 13a and 13b may be attacked by the plating solution and may cause peeling of the conductors 13a and 13b.
【００４８】また、本実施の形態のように、積層セラミ
ック基板の表面の導体１３ａ，１３ｂを積層体と一体焼
成することにより、焼成後焼付けにて形成する方法と比
較して、工程数を減らすことが可能であり、生産性を向
上させることができる。Further, as in the present embodiment, the conductors 13a and 13b on the surface of the laminated ceramic substrate are integrally fired with the laminated body to reduce the number of steps as compared with the method of forming by firing and baking. It is possible to improve productivity.
【００４９】[0049]
【発明の効果】以上、本発明によると、積層セラミック
基板の表、裏面に設けた導体の少なくとも端部を絶縁体
で被覆することにより、衝撃に強く、クラックなどの構
造欠陥の発生を抑制することができる積層セラミック基
板を提供することができる。As described above, according to the present invention, by covering at least the end portions of the conductors provided on the front and back surfaces of the laminated ceramic substrate with an insulator, it is resistant to impact and suppresses the occurrence of structural defects such as cracks. It is possible to provide a laminated ceramic substrate that can be manufactured.
【図１】本発明の実施の形態１における積層セラミック
基板の製造工程を説明するための断面図FIG. 1 is a sectional view for explaining a manufacturing process of a laminated ceramic substrate according to a first embodiment of the present invention.
【図２】同断面図FIG. 2 is a sectional view of the same.
【図３】同断面図FIG. 3 is a sectional view of the same.
【図４】同断面図FIG. 4 is a sectional view of the same.
【図５】本発明の実施の形態１における積層セラミック
基板の断面図FIG. 5 is a sectional view of the laminated ceramic substrate according to the first embodiment of the present invention.
１１ 第１のセラミック層 １２ 第２のセラミック層 １３ａ 導体 １３ｂ 導体 １３ｃ 導体 １５ 絶縁体 11 First ceramic layer 12 Second ceramic layer 13a conductor 13b conductor 13c conductor 15 insulator
フロントページの続き (72)発明者 亀山 一郎 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 Ｆターム(参考） 5E346 AA12 AA15 CC18 CC32 CC35 CC36 CC37 CC39 DD22 DD34 DD45 EE24 EE27 FF18 GG04 GG05 GG06 GG07 GG08 GG09 HH11 HH33 Continued front page (72) Inventor Ichiro Kameyama 1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric Sangyo Co., Ltd. F-term (reference) 5E346 AA12 AA15 CC18 CC32 CC35 CC36 CC37 CC39 DD22 DD34 DD45 EE24 EE27 FF18 GG04 GG05 GG06 GG07 GG08 GG09 HH11 HH33
Claims (2)
ものの表裏面に第２のセラミック層を圧着して積層体を
作製する第１の工程と、前記第１のセラミック層が焼結
しかつ前記第２のセラミック層が焼結しない温度で前記
積層体を焼成する第２の工程と、前記積層体から前記第
２のセラミック層を除去する第３の工程を有し、少なく
とも一方の前記第２のセラミック層の前記第１のセラミ
ック層に接する面に絶縁体を形成し、前記絶縁体の少な
くとも一部を被覆するように導体を形成する積層セラミ
ック基板の製造方法。1. A first step of pressure-bonding a second ceramic layer to the front and back surfaces of a laminated body of a first ceramic layer and a conductor to produce a laminated body, and sintering the first ceramic layer. And a second step of firing the laminate at a temperature at which the second ceramic layer does not sinter, and a third step of removing the second ceramic layer from the laminate, and at least one of the above A method of manufacturing a laminated ceramic substrate, wherein an insulator is formed on a surface of the second ceramic layer which is in contact with the first ceramic layer, and a conductor is formed so as to cover at least a part of the insulator.
表面あるいは裏面の少なくとも一方に前記導体が配置さ
れる積層体を作製する第１の工程と、前記積層体の表面
あるいは裏面の導体の少なくとも端部を被覆する絶縁体
を形成する第２の工程と、前記積層体の表裏面に第２の
セラミック層を圧着する第３の工程と、前記第１のセラ
ミック層が焼結しかつ前記第２のセラミック層が焼結し
ない温度で前記積層体を焼成する第４の工程と、前記積
層体から前記第２のセラミック層を除去する第５の工程
を有する積層セラミック基板の製造方法。2. A first step of laminating a first ceramic layer and a conductor to produce a laminate in which the conductor is arranged on at least one of a front surface and a back surface, and a conductor on the front surface or the back surface of the laminate. A second step of forming an insulator covering at least an end of the laminate, a third step of crimping a second ceramic layer on the front and back surfaces of the laminate, and a step of sintering the first ceramic layer and A method for manufacturing a laminated ceramic substrate, comprising: a fourth step of firing the laminated body at a temperature at which the second ceramic layer is not sintered; and a fifth step of removing the second ceramic layer from the laminated body.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005109462A (en) * | 2003-09-09 | 2005-04-21 | Ngk Spark Plug Co Ltd | Manufacturing method of ceramic substrate, and the ceramic substrate |
| WO2007052619A1 (en) * | 2005-10-31 | 2007-05-10 | Matsushita Electric Industrial Co., Ltd. | Process for producing laminated ceramic substrate |
| WO2009119199A1 (en) * | 2008-03-28 | 2009-10-01 | 株式会社村田製作所 | Method for producing multilayer ceramic substrate and composite sheet |
-
2002
- 2002-02-14 JP JP2002036506A patent/JP3912129B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005109462A (en) * | 2003-09-09 | 2005-04-21 | Ngk Spark Plug Co Ltd | Manufacturing method of ceramic substrate, and the ceramic substrate |
| WO2007052619A1 (en) * | 2005-10-31 | 2007-05-10 | Matsushita Electric Industrial Co., Ltd. | Process for producing laminated ceramic substrate |
| WO2009119199A1 (en) * | 2008-03-28 | 2009-10-01 | 株式会社村田製作所 | Method for producing multilayer ceramic substrate and composite sheet |
| US8585842B2 (en) | 2008-03-28 | 2013-11-19 | Murata Manufacturing Co., Ltd. | Method for manufacturing multilayer ceramic substrate and composite sheet |
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| Publication number | Publication date |
|---|---|
| JP3912129B2 (en) | 2007-05-09 |
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