JP2003243661A - Thin film transistor and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a substrate having no warpage and thereby improve the manufacturing yield. <P>SOLUTION: A MIS type thin film transistor comprises a semiconductor layer formed of polycrystal silicon formed on the substrate. The gate of this thin film transistor is formed in separation from a wiring layer connected thereto. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and a method of manufacturing the same, and more particularly, to a thin film transistor in which lamp annealing is carried out in impurity activation annealing and a method of manufacturing the same.

[0002]

2. Description of the Related Art In a method of manufacturing a thin film transistor using a glass substrate, as a method of activating annealing of impurity ions, there are annealing by heat treatment using a diffusion furnace and lamp annealing performed by irradiating lamp light.

Lamp annealing is generally based on the principle that lamp light is irradiated from both upper and lower sides of a substrate, whereby light is absorbed in the semiconductor layer to generate heat and impurity ions are activated. .

Since this lamp annealing absorbs light in the semiconductor layer and generates heat, only the semiconductor layer can be heated to a high temperature in a short time. Therefore, a material such as glass that softens at a relatively low temperature is used for the substrate. It becomes possible. Further, since the semiconductor layer has a high temperature for a short time, the amount of impurity ions diffused in the lateral direction is small, which is a technique suitable for miniaturization.

Ion implantation is performed using the photoresist pattern used to form the gate electrode or the gate electrode pattern, and impurities are implanted to form the source electrode and the drain electrode in a self-aligned manner.
Features suitable for miniaturization can be effectively used. In order to perform this self-alignment, it is necessary to form a gate electrode before performing ion implantation, and it is necessary to perform lamp annealing with the gate electrode formed.

However, while the temperature of the semiconductor layer and the gate electrode which absorb the lamp light rapidly rises, the glass substrate allows the lamp light to pass therethrough, resulting in a large temperature difference between the semiconductor layer and the gate electrode and the substrate. Therefore, thermal stress is generated due to the local temperature difference. In order to avoid such non-uniform heating, a technique is known in which a light absorbing film is formed on the entire surface and then lamb annealing is performed (see Japanese Patent Laid-Open No. 2000-138177).

[0007]

However, in the above technique, even if the light absorbing film is formed on the entire surface, a temperature difference occurs between the front and back of the substrate, and the substrate warps and distorts. Furthermore, the glass substrate is heated by heat conduction, and when it is heated up to the glass point transfer, plastic deformation occurs in a distorted state, and it remains distorted even when cooled, so that it is not always effective particularly on a glass substrate with weak heat resistance. It couldn't be the means. The present invention is a self-aligned source,
It is an object of the present invention to provide a thin film transistor capable of suppressing distortion of a glass substrate and a manufacturing method thereof when applying a process of performing a lamp anneal after a gate electrode is first formed to form a drain electrode to the glass substrate.

[0008]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows. Means 1. The thin film transistor according to the present invention is, for example,
M using polycrystalline silicon formed on a substrate as a semiconductor layer
The IS type thin film transistor is characterized in that its gate electrode is formed separately from a wiring layer connected thereto.

Means 2. The thin film transistor according to the present invention is, for example, a thin film transistor obtained by activating impurity ions in polycrystalline silicon formed on a substrate by lamp annealing, and its gate electrode is connected to a wiring layer formed after the lamp annealing. It is characterized by being.

Means 3. A method of manufacturing a thin film transistor according to the present invention includes, for example, a step of forming polycrystalline silicon on a substrate, a step of forming a gate electrode on an upper surface of the polycrystalline silicon, and the polycrystalline silicon using the gate electrode as a mask. And a step of activating the impurity by lamp annealing, and a step of forming a wiring layer connected to the gate electrode.

Means 4. The method of manufacturing a thin film transistor according to the present invention includes, for example, a step of forming polycrystalline silicon on a substrate, a step of forming a gate electrode on the upper surface of the polycrystalline silicon, and a photo process for forming a pattern of the gate electrode. The method is characterized by including a step of doping the polycrystalline silicon with an impurity using a resist as a mask and activating the polycrystalline silicon by lamp annealing, and a step of forming a wiring layer connected to the gate electrode.

Means 5. The method of manufacturing a thin film transistor according to the present invention is, for example, on the premise of the constitution of means 4, characterized in that the pattern of the gate electrode is over-etched with respect to the pattern of the photoresist.

Means 6. In the method of manufacturing a thin film transistor according to the present invention, for example, on the premise of the constitution of means 5, after removing the photoresist, the gate electrode is used as a mask to dope the impurities to reduce the amount of impurities in the polycrystalline silicon in the vicinity of the gate electrode. It is characterized in that a dose amount region is formed.

Means 7. In the liquid crystal display device according to the present invention, for example, a plurality of gate signal lines arranged in parallel with each other on the liquid crystal side surface of one of the substrates opposed to each other with the liquid crystal interposed therebetween and the gate signal lines intersect each other. A thin film transistor in which a region surrounded by a plurality of drain signal lines juxtaposed in parallel is a pixel region, and the pixel region has a semiconductor layer of polycrystalline silicon operated by a scanning signal from a gate signal line; A pixel electrode to which a video signal is supplied from a drain signal line through the gate electrode of the thin film transistor and the gate signal line connected to the gate electrode are formed separately. Is.

Means 8. In the liquid crystal display device according to the present invention, for example, a plurality of gate signal lines arranged in parallel with each other on the liquid crystal side surface of one of the substrates opposed to each other with the liquid crystal interposed therebetween and the gate signal lines intersect each other. A region surrounded by a plurality of drain signal lines arranged in parallel as a pixel region, and in the pixel region, a thin film transistor operated by a scanning signal from the gate signal line and a drain signal line from the drain signal line A pixel electrode to which a video signal is supplied, the thin film transistor has a semiconductor layer obtained by activating impurity ions of polycrystalline silicon by lamp annealing, and the gate electrode thereof is formed after the lamp annealing. It is characterized in that it is connected to a gate signal line.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a liquid crystal display device according to the present invention will be described below with reference to the drawings. Example 1. << Overall Configuration >> FIG. 2 is an overall configuration diagram showing an embodiment of a liquid crystal display device according to the present invention. Although the figure shows an equivalent circuit, it is drawn corresponding to the actual geometrical arrangement.
A pair of transparent substrates SU arranged to face each other with a liquid crystal in between.
B1 and SUB2, and the liquid crystal is one transparent substrate SUB
It is enclosed by a sealing material SL which also serves to fix the other transparent substrate SUB2 to 1.

On the liquid crystal side surface of the one transparent substrate SUB1 surrounded by the sealing material SL, the gate signal lines GL extending in the x direction and juxtaposed in the y direction and x extending in the y direction are provided. A drain signal line DL is formed side by side in the direction. A region surrounded by each gate signal line GL and each drain signal line DL constitutes a pixel region, and a matrix-shaped aggregate of these pixel regions constitutes a liquid crystal display section AR.

Further, a common capacitance signal line CL running in each pixel region is formed in each of the pixel regions arranged in parallel in the x direction. The capacitance signal line CL is connected to one electrode of a capacitance element Cstg described later, and a constant voltage is applied.

In each pixel region, a thin film transistor TFT operated by a scanning signal from the gate signal line GL on one side and a pixel electrode to which a video signal from the drain signal line DL on one side is supplied via the thin film transistor TFT. PX is formed. Then, this pixel electrode PX
Between the capacitive signal line CL and the capacitive element Cstg
Are connected. The capacitive element Cstg is the pixel electrode P.
It is provided to store the video signal supplied to X for a relatively long time. The thin film transistor TF
The semiconductor layer of T is polycrystalline, for example, Si (p-Si).
It is composed of.

The pixel electrode PX is the other transparent substrate S.
An electric field is generated between the liquid crystal-side surface of the UB2 and a counter electrode commonly formed in each pixel region, and the light transmittance of the liquid crystal is controlled by this electric field.

One end of each of the gate signal lines GL extends beyond the sealing material SL, and the extended end is connected to a vertical scanning drive circuit V formed on the surface of the transparent substrate SUB1. ing. This vertical scanning drive circuit V
Are formed of a large number of MIS transistors and a wiring layer connecting them.

Similarly, one end of each of the drain signal lines DL extends beyond the sealing material SL, and the extending end is connected to the video signal drive circuit He formed on the surface of the transparent substrate SUB2. It is like this. The video signal drive circuit He is also formed of a large number of MIS transistors and a wiring layer connecting them.

Here, the semiconductor layer of the MIS transistor constituting the vertical scanning drive circuit V and the video signal drive circuit He is formed of a polycrystalline layer like that of the thin film transistor TFT. Therefore, the MI
The formation of the S-type transistor is usually performed in parallel with the formation of the thin film transistor TFT.

Further, the capacitance signal lines CL common to the respective pixel regions juxtaposed in the x direction are commonly connected, for example, at the end portion on the right side in the drawing, and the connection lines extend beyond the sealing material SL, A terminal CLT is formed at the extending end.
One of the gate signal lines GL is sequentially selected by a scanning signal from the vertical scanning circuit V.

A video signal is supplied to each of the drain signal lines DL by a video signal driving circuit He at the timing of selecting the gate signal line GL.

<< Pixel Configuration >> FIG. 1 is a plan view showing an embodiment of the pixel region. In addition, FIG. 3 shows III-III of FIG.
Figure 3 shows a cross-sectional view along the line. This pixel region is divided into two by, for example, an imaginary line running in the x direction, and the upper region is formed as a light transmission region and the lower region is formed as a light reflection region. A liquid crystal display device that can be switched and used.

In each drawing, first, a base layer GW1 made of, for example, SiN is formed on the surface of the transparent substrate SUB1 on the liquid crystal side, and a base layer GW2 made of, for example, SiO2 made of TEOS is formed on the upper surface thereof. ing. Each of these base layers is formed in order to prevent ionic impurities contained in the transparent substrate SUB1 from affecting the thin film transistor TFT described later.

A semiconductor layer PS made of, for example, a polysilicon layer is formed on the surface of the underlying layer GW. The semiconductor layer PS is, for example, an amorphous Si film formed by a plasma CVD apparatus and polycrystallized by an excimer laser. This semiconductor layer PS
Is formed as a strip-shaped pattern formed adjacent to a gate signal line GL described later and is used as a semiconductor layer of a thin film transistor TFT described later.

Then, on the surface of the transparent substrate SUB1 on which the semiconductor layer PS is thus formed, a first insulating film GI made of, for example, SiO ₂ or SiN is formed so as to cover the semiconductor layer PS as well. The first insulating film GI functions as a gate insulating film of the thin film transistor TFT. Then, the gate electrode GT is formed so as to cross the center of the first insulating film GI. The gate electrode GT is formed separately from a gate signal line GL described later, and has a minimum area so as to have its function.

After the formation of the gate electrode GT, impurities are ion-implanted through the first insulating film GI to make the region of the semiconductor layer PS except the region just below the gate electrode GT conductive. The source region S and the drain region D of the thin film transistor TFT are formed.

On the upper surface of the first insulating film GI, x in the figure
A gate signal line GL extending in the y direction and arranged in parallel in the y direction is formed, and the gate signal line GL defines a rectangular pixel region together with a drain signal line DL described later. In this case, a part of the gate signal line GL extends in the pixel region and overlaps with the gate electrode GT so that electrical connection can be achieved. The gate electrode GT and the gate signal line GL may be any conductive film having heat resistance, for example, Al, Cr, Ta, TiW.
Etc. are selected.

Further, a capacitance signal line CL extending in the x direction in the drawing is formed on the upper surface of the first insulating film GI in the center of the pixel region, and the capacitance signal line CL is a region below the pixel region in the drawing. It is formed integrally with the capacitor electrode CT extending to. The capacitance signal line CL (capacitance electrode CT) is formed in the same layer and the same material as the gate signal line GL, for example.

The gate signal line GL (gate electrode GT)
And the capacitance signal line CL (capacitance electrode CT)
The second insulating film IN is formed on the upper surface of the first insulating film GI by, for example, S.
iO _TwoAlternatively, it is made of SiN. Furthermore
In addition, almost half of the pixel area is formed on the upper surface of the second insulating film IN.
Pixel area (lower area in the figure)
The pole PX (R) is formed. This pixel electrode PX
(R) also serves as a reflective film, and in the area where it is formed
A light reflecting portion is formed.

Here, the pixel electrode PX (R) is composed of, for example, a sequentially laminated body of Ti, Al-Si and Ti, of which Ti on the upper surface functioning as a reflection film is removed, and the light reflection efficiency is good. The Al surface is exposed. The pixel electrode PX (R) is connected to the semiconductor layer PS through a contact hole CH1 formed in the second insulating film IN and the first insulating film GI in a portion close to the thin film transistor TFT.

The semiconductor layer PS connected to the pixel electrode PX (R) is a portion corresponding to the source region S of the thin film transistor TFT, while the drain region D of the thin film transistor TFT overlaps with the gate electrode GT. It is formed in the region of the semiconductor layer PS on the opposite side with the portion formed therebetween and is connected to the drain signal line DL described later through the contact hole CH2 in this portion.

Further, this pixel electrode PX (R) is formed so as to overlap with the capacitance electrode CT,
It constitutes one electrode of the capacitive element Cstg. Thus, the capacitive element Cstg constitutes a capacitive element having the second insulating film IN formed between the pixel electrode PX (R) and the capacitive electrode CT as a dielectric film.

On the upper surface of the second insulating layer IN, y in the drawing is shown.
The drain signal lines DL extending in the direction and arranged in parallel in the x direction are formed. The drain signal line DL and the gate signal line GL described above define a pixel area. The drain signal line DL is formed simultaneously with the pixel electrode PX (R), for example, when the pixel electrode PX (R) is formed.

As described above, the drain signal line DL is partially drained through the contact hole CH2 formed in the second insulating film IN and the first insulating film GI (the drain signal line DL).
And the side connected to the drain region is defined as a drain region). And this drain signal line D
The third insulating film PSV1 and the fourth insulating film P are formed on the upper surface of the second insulating film IN so as to cover L and the pixel electrode PX (R).
SV2 is formed by being sequentially laminated.

The third insulating film PSV is formed of, for example, SiO ₂ or SiN, and the fourth insulating film PSV2 is formed of, for example, an organic material layer. Here, by forming the fourth insulating film PSV2 as an organic material layer, the surface can be flattened and the alignment of the liquid crystal can be brought into a good state.

A pixel electrode PX (T) made of a translucent material such as an ITO (Indium-Tin-Oxide) film is formed on the upper surface of the third insulating film PSV, and the pixel electrode PX is formed.
(T) is formed so as to extend to a portion above the pixel region. About half of the pixel area excluding the light reflection area is formed as a light transmission area by the pixel electrode PX (T). This pixel electrode PX (T) is a thin film transistor T
In a portion adjacent to the FT, the pixel electrode PX (R) is connected through a contact hole CH3 formed in the third insulating film PSV.

As a result, the pixel electrode PX (T) is connected to the source region S of the thin film transistor TFT via the pixel electrode PX (R), and the drain signal line DL is turned on when the thin film transistor TFT is turned on. Image signal from the pixel electrode P through the thin film transistor TFT.
Not only X (R) but also the pixel electrode PX (T) is supplied.

The pixel electrodes PX (R), PX
(T) is common to each pixel region on the liquid crystal side surface of another transparent substrate SUB2 which is arranged to face the transparent substrate SUB1 on which these pixel electrodes PX (R) and PX (T) are formed with a liquid crystal interposed therebetween. An electric field is generated between the formed transparent counter electrode and the light transmittance of the liquid crystal is controlled by this electric field.

<< Manufacturing Method >> Next, one embodiment of a method of manufacturing the above-mentioned liquid crystal display device will be described below centering on the thin film transistor TFT. On a transparent substrate SUB1 made of a glass substrate, a base layer GW1 made of a plasma silicon nitride film for preventing alkali ion diffusion and a plasma TEOS
A base layer GW2 made of a SIO ₂ film and a semiconductor layer made of amorphous Si are continuously laminated by plasma CVD. Then, after the dehydrogenation process, the excimer laser is irradiated to crystallize the Si film, and the Si film is then photo-etched.
The film is processed into an island shape.

An insulating film GI is formed by forming a plasma TEOS SiO ₂ film. This TEOS Si
Boron (B) is doped with 10 ¹² / cm ² implantation from above the O ₂ film for the purpose of controlling the threshold value of the transistor.

Mo-1.6 wt% as the gate electrode GT
A Cr film or a Mo-8 wt% Zr film is formed by a sputtering method. After forming the resist pattern, wet etching is performed with a mixed acid composed of phosphoric acid, acetic acid, nitric acid, and water.
At this time, 0.75 μm to 1.2 on one side from the resist end surface.
The side etching width is controlled to be μm. As it is, phosphorus is implanted by 1 × 10 ¹⁵ / cm ² using the resist as a mask to form an n ⁺ region.

By using the gate electrode GI, it is possible to form an LDD structure in which the n ⁺ region and the n ⁻ region are formed in a self-aligned manner. At this time, the underlying p-TEOS SiO
_The n ⁻ region corresponding to the _two films is side-etched, but by using wet etching as a processing method, a sufficient number of LDD regions can be formed without damaging the base.

After ion implantation, activation is carried out by the rapid thermal annealing method (RTA). Here, the reason for using this method is that heating and cooling are rapidly performed to terminate activation before the transparent substrate SUB1 is sufficiently heated during annealing.

When heating is performed by the above method with the gate signal line GL and the capacitor electrode CT formed at this point, a large number of the gate signal line GL and the capacitor electrode CT having a large area are formed continuously. Will be absorbed, and the temperature of the transparent substrate SUB1 itself will rise above the softening point of the glass to deform the transparent substrate SUB1. That is, the deformation amount is caused by the pattern of the gate signal line GL, and the variation in deformation caused by the pattern is caused by the transparent substrate SU.
It will occur in B1.

FIG. 4 is a diagram for explaining this situation. Figure 4
FIG. 4A shows the warp amount of the transparent substrate SUB1 when the gate signal line GL is already formed and heated, whereas FIG. 4B shows the gate electrode GT having the minimum area. That is, the transparent substrate SUB1 is not warped at all even when they are heated.

After that, for example, a pure Mo film is formed on the surface of the transparent substrate SUB1, a resist pattern is formed for the purpose of forming the gate signal line GL, the capacitance electrode, and the gate terminal, and this resist pattern is used as a mask. Dry etching. In this case, Mo− which is the gate electrode GT
The Cr or Mo-Zr alloy needs to have an etching selection ratio with respect to the dry etching.

FIG. 5 shows S for various etching materials.
The etching rate using F ₆ gas is shown. As is clear from this figure, while the etching rate of pure Mo is 4 nm / s, the Mo-Cr or M
In the case of the o-Zr alloy, it is 0.2 nm / s and has a selectivity of about 10 or more.

Here, for example, M is used as the gate electrode GT.
When an o-50 wt% W alloy is used, the dry etching of pure Mo has a selection ratio of only about 2, so that the side etching of the gate electrode GT progresses during overetching in the dry etching. In such a case, an offset occurs between the LDD region and the gate electrode GT, an electric field from the gate electrode GT is not applied, and a high resistance region where carriers are not generated is formed.

From this, it is necessary that the etching rate of the gate signal line GL or the like has a selection ratio of 3 or more with respect to that of the gate electrode GT, and preferably 10 or more. . Here, in order to have a selection ratio of 10 or more, the addition amount of chromium (Cr) is 1 wt% or more and the addition amount of zirconium (Zr) is 5 wt.
It should be at least%.

Then, on the surface of the transparent substrate SUB1, for example, a p-TEOS film or S formed by the plasma CVD method is used.
An iN film is formed and used as an interlayer insulating film IN. Then, in the interlayer insulating film IN, a contact hole CH1 for exposing a part of the source region S and a part of the drain region of the thin film transistor TFT and a gate are formed by selective etching using buffered hydrofluoric acid (BHF) by a photolithography technique. An opening is formed to expose a part of the terminal. In this case, the interlayer insulating film IN and the pure Mo film exposed by the contact holes CH and the like have a sufficient selection ratio for wet etching with buffered hydrofluoric acid (BHF).

On the surface of the transparent substrate SUB1, a metal layer in which Ti (or Mo), Al-Si, and Ti (or Mo) are sequentially laminated is formed, and a drain signal is formed by selective etching using dry etching by a photolithography technique. Line DL, drain electrode SD1, source electrode SD
Form 2. BCl ₃ and Cl ₂ are used as a gas for dry etching.

Of the metal layer having a three-layer structure, the lower layer Ti (or Mo) functions as a barrier layer for interdiffusion of Si and Al, and the upper layer Ti (or Mo) is an Al hillock preventing cap layer or It has a function as a contact layer with another material layer described later.

The source electrode SD2 extends over the entire reflective region of the pixel region, and this extended portion functions as the pixel electrode PX (R) which also serves as the reflective electrode. Then, Ti in the upper layer of the portion that functions as the reflective electrode
(Alternatively, Mo) is removed by selective etching to expose the underlying Al-Si. This is because Al-Si has extremely high light reflection efficiency. The selective etching is performed by dry etching using a fluorine gas such as SF6 gas.

Here, in order to give the pixel electrode PX (R) a light-scattering function, irregularities such as through holes may be formed on the surface of the interlayer insulating film IN under the electrode. As a result, the irregularities are exposed on the surface of the pixel electrode PX (R), and reflected light composed of irregular reflection is obtained,
A wide reflective viewing angle characteristic can be achieved.

Further, the material of the drain signal line DL is Al, which has a low resistance, and must have heat resistance in the annealing treatment after the formation of the signal line. Therefore, as described above, A
A material having stress migration resistance such as an l-Si alloy is suitable. In addition, Al—Cu—Si or the like may be used, or a material having hillock resistance such as Al—Nd alloy or Al—Y alloy may be used.

However, as the amount of alloying element added increases, the heat resistance improves, but the specific resistance tends to increase. When it is necessary to suppress the additive element from the viewpoint of wiring resistance, by forming the Ti film or Mo film of the upper and lower barrier layers and the cap layer as thick as about 100 nm, diffusion of Al and, as a result, migration and hillock Can be stopped in the middle of both layers.

The protective film PSV1 is formed of a plasma SiN film. Further, a protective film PSV2 made of an organic material layer which can be formed by coating is laminated on the upper layer. A photosensitive material can be selected as the organic material layer. In this case, first, a through hole is formed by an exposure and development process, and the protective film PSV1 is dry-etched using the organic material layer as a mask. A through hole CH3 reaching the source electrode SD2 can be formed.

An amorphous indium tin oxide (a-ITO) film is formed on the surface of the transparent substrate SUB1 by sputtering, for example, and the pixel electrode P made of a translucent material is formed by selective etching by the photolithography technique.
Form X (T). The pixel electrode PX (T) is electrically connected to the source electrode SD2 through the through hole CH3. Since the amorphous indium tin oxide (a-ITO) film can be formed at room temperature, it is possible to prevent gas release from the organic material layer without heating during film formation, and to improve the adhesion of the a-ITO film to the organic material layer. You can keep it strong.

Here, by forming the pixel electrode PX (T) so as to overlap the drain signal line DL, the aperture ratio of the pixel region can be set to the maximum. When both are partially overlapped,
In order to prevent the increase in the drain capacity, it is preferable to set the film thickness of the lower organic material layer to about 3 μm or more. Further, the protective film PSV1 made of the SiN film has a high dielectric constant of 8.0, whereas the protective film PSV2 made of the organic material layer has a low dielectric constant of 3.0. Therefore, the drain signal line DL and the pixel electrode PX are The increase in capacity of (T) can be suppressed to a low level.

Example 2. In this embodiment, Ti may be used instead of pure Mo for the gate signal line GL, the capacitance signal line CL, and the peripheral terminals. Regarding the dry etch rate shown in FIG. 5, Ti has a dry etch rate almost similar to that of pure Mo. Therefore, when the Mo-Cr film or the Mo-Zr alloy having F-based dry etching resistance is used as the material of the gate electrode GT, T of the gate signal line GL or the like is used.
The dry etching selection ratio of i can be set to 10 or more. On the other hand, the specific resistance of pure Ti is about 50 μΩcm and pure M
Since it is 5 times as high as about 10 μΩcm, it is preferable to use a Mo-based alloy layer also for the signal line in order to form a low resistance wiring for forming the signal line. In addition, it is also preferable to form an electrode occupying a relatively large area such as the capacitor electrode CT with Ti

Example 3. In this embodiment, the gate electrode G
Pure Ti for T material, pure M for gate signal line GL, etc.
You may apply o or Mo alloy. In order to reduce the resistance of the signal line, pure Mo or Mo-W alloy, which has a low specific resistance and can realize a low sheet resistance with a thin film thickness, is preferable. The specific resistance of both is about 10 μΩcm for pure Mo and about 15 μΩcm for the Mo-W alloy, which is suitable for forming a signal line.

When pure Ti is used as the gate electrode GT
The LDD processing process of will be described below. That is, pure
The gate electrode GT of Ti is formed by dry etching.
U BCl _ThreeGas and Cl_TwoUsing gas, p-TE of the base
A length equivalent to the LDD length while ensuring the selection ratio with the OS film
It may be overetched by dry etching.

On the other hand, the dry etching may be divided into two times. That is, first, just etching is performed by dry etching, and phosphorus is ion-implanted using this as a mask to form an n ⁺ layer. After that, the resist is moved back by oxygen ashing by an amount corresponding to the length of LDD. After that, Ti is removed again by dry etching, and phosphorus is ion-implanted using this as a mask to form an n ⁻ layer.
Next, the resist on the remaining gate electrode is removed by full ashing.

Here, when the end surface of the resist pattern is not vertical and is formed in a forward taper shape, it may be difficult to control the resist ashing width. In this case, a halftone photomask may be used to form a thick resist film and a thin resist film from the beginning. By forming a thin resist only in the region to be removed by ashing for forming the LDD region, the resist receding length due to ashing,
That is, the LDD length can be controlled uniformly within the surface of the substrate. After that, in order to form the gate signal line GL and the like, pure M
o or Mo-20 wt% W alloy is deposited. After forming the resist, these are wet-etched with a mixed acid consisting of phosphoric acid, acetic acid and nitric acid.

FIG. 6 shows pure Ti, pure Mo and Mo-20 wt%.
The etch rate of the W alloy with the above etching solution is shown. Pure Ti can hardly be etched with the phosphoric acid-based etching solution, and both pure Mo and Mo-20 wt% W can secure an etching selection ratio of 10 or more. Therefore,
When the gate signal line GL is wet-etched, it is possible to prevent a gate offset due to side etching of the gate electrode GT.

Example 4. In this embodiment, the gate electrode G
As T, indium tin oxide (ITO) may be used instead of metal. Amorphous ITO (a-IT
The O) film is a weak acid such as oxalic acid or phosphoric acid, has a high etching selection ratio to the underlying p-TEOS film, and is subjected to side etching corresponding to the LDD length. Phosphorus is ion-implanted using this resist as a mask to form an n ⁺ region. Then, the resist is peeled off and phosphorus is ion-implanted using the ITO gate electrode GT as a mask to form an n ⁻ region.

After that, activation annealing is carried out by the RTA method. Since ITO is transparent in the visible wavelength region, R
Light absorption heating by TA is small, and therefore RTA does not deform the glass. After that, pure Mo or Mo—W alloy is formed for the purpose of forming the gate signal line GL, the peripheral terminal, and the capacitor electrode CT.

As shown in FIG. 6, a-ITO film and Mo,
Etching rates of the Mo-W alloy and the Mo-W alloy are almost the same, and there is no selection ratio. However, a-IT
The O film is polycrystalline ITO (poly-ITO) by RTA heating.
Crystallize into. This poly-ITO cannot be etched with a weak acid such as oxalic acid and phosphoric acid, and therefore M
In the wet etching of the gate signal line GL made of the o film, the selectivity with the gate electrode GT can be realized.

The wet etching rate of the ITO film is
Since the etching rate is greatly reduced only by the progress of partial crystallization, the selection ratio to the gate signal line GL made of the Mo film becomes 10 or more only by the thermal history of the rapid heating and cooling of the RTA. In order to crystallize more completely, thermal annealing at 240 ° C. for 20 minutes is performed together with RTA preheating.
You may carry out before TA. A pure Ti film may be used for the second gate layer instead of the Mo film. When Ti is used, dry etching is used for processing.

As shown in FIG. 6, since the selection ratio between the ITO film and the Ti film is as high as 10 or more, there is no film reduction of the first gate film. When the ITO film is used as the gate electrode GT, the translucent pixel electrode PX (T) may be formed using this ITO film. Since the light transmittance is good and there is no influence of heat storage during RTA, not only the gate electrode GT but also the pixel electrode PX (T) for transmission, which requires a relatively large area, is formed together.

Contact holes are formed not only on the source region S and the drain region D but also on the pixel electrode PX (T). The pixel electrode PX (T) is energized from the source electrode through the contact hole. Furthermore, through hole C
A voltage is also applied to the pixel electrode PX (R) made of an aluminum / molybdenum laminate via H3. As shown in FIG. 8, the visibility can be significantly improved by forming a diffusion layer in which the protective film PSV2 is processed to be uneven under the pixel electrode PX (R).

Example 5. In this embodiment, the gate electrode G
A pure Cr film may be used for T and a pure Mo film may be used for the gate signal line GL. Pure Cr can be subjected to 1 Ωm side etching by wet etching without damaging the base. After forming the n ⁻ layer by ion implantation, RTA is performed. After that, a Mo film is formed like a gate bus line,
Processing is performed by wet etching using phosphoric acid-based etching. Since Cr is not etched by the phosphoric acid type etching solution, the etching selection ratio can be secured. However, the Cr film cannot be removed because a chromium oxide film is easily formed on the surface during the RTA.

FIG. 7 is a graph showing the measured contact resistance between the gate electrode GT and the gate signal line GL formed after RTA. The contact resistance of the Cr / Mo laminated part is Cr
It becomes high due to the oxide film on the film surface. Mo alloy / Pure M
Since o and Mo / Ti have a low resistance value of Mo oxide and can be easily removed even when formed, the contact resistance of both is below the measurement limit. Since ITO is originally an oxide, RT
There is no influence of surface oxidation at A, and the contact resistance of Mo oxide formed on the surface is also small.

Example 6. The scanning signal drive circuit V or the video signal drive circuit He shown in FIG. 2 is formed of a large number of CMOS transistors. When making the CMOS transistor, pMOS type TF together with nMOS type
Form T. First, the first gate electrode is selectively processed by wet etching only in the pMOS formation region. At this time, the over-etching time is set to be short so that the side-etch width is as small as possible. After that, the resist is ashed by oxygen ashing to be retracted so that there is no overhang of the resist.

Alternatively, dry etching may be performed by chlorine-based dry etching. In this case, the resist is also etched at the same time and the same end face of the resist and the Mo alloy film is formed, so that the resist does not overhang. After that, ion implantation of polon (B) and p ⁺
After forming the region, the resist is peeled off. Since the pMOS has a sufficiently long transistor life, it is not necessary to form an LDD.

Next, in the nMOS region, the first
The gate electrode is processed by wet etching. nMOS
Then, in order to form the LDD, the region corresponding to the LDD width is side-etched by wet etching as described above. In the following, similar to the above-described embodiment, the n ⁺ region and n ⁻
Implant phosphorus (P) ions into the region. pMOS, nMO
After forming S as well, activation annealing is collectively performed by RTA.

Then, pure Mo or T is used as a second gate film.
An i film is formed, and the gate bus line, the load capacitance electrode, and the peripheral terminal electrode are processed by SF6 gas by dry etching. Hereinafter, similarly to the above-described embodiment, the interlayer insulating layer, the source / drain wiring, the reflective electrode, the passivation layer, and the transparent electrode are formed to form a polysilicon TFT substrate.

[0082]

As is apparent from the above description,
According to the thin film transistor and the method for manufacturing the same according to the present invention, it is possible to obtain a substrate having no warp and improve the yield.

[Brief description of drawings]

FIG. 1 is a plan view showing an embodiment of a pixel of a liquid crystal display device according to the present invention.

FIG. 2 is an overall configuration diagram showing an embodiment of a liquid crystal display device according to the present invention.

3 is a sectional view taken along line III-III in FIG.

FIG. 4 is a diagram for explaining the effect of the present invention.

FIG. 5 is a graph for explaining the effect of the present invention.

FIG. 6 is a graph for explaining the effect of the present invention.

FIG. 7 is a graph for explaining the effect of the present invention.

FIG. 8 is a cross-sectional view showing an example of a pixel of a liquid crystal display device according to the present invention.

[Explanation of symbols]

SUB1 ... Transparent substrate, PS ... Other crystals Si, GL ... Gate signal line, GT ... Gate electrode, DL ... Drain signal line, C
L ... Capacitance signal line, CT ... Capacitance electrode, TFT ... Thin film transistor, Cstg ... Capacitance element, PX (R) ... Pixel electrode (reflection electrode), PX (T) ... Pixel electrode (translucent), G
I ... 1st insulating film, IN ... 2nd insulating film, PSV1 ... 3rd insulating film, PSV2 ... 4th insulating film.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yu Saito             Hitachi, Ltd. 3300 Hayano, Mobara-shi, Chiba             Factory Display Group F-term (reference) 2H092 JA25 JA40 KA04 KB04 KB12                       KB22 KB24 MA05 MA08 MA17                       MA27 MA28 NA19 NA29                 4M104 AA01 AA08 AA09 BB02 BB13                       BB14 BB16 BB17 BB36 CC01                       CC05 DD09 DD16 DD17 DD37                       DD62 DD64 DD65 DD80 DD91                       EE03 EE16 EE17 FF17 FF22                       GG09 GG19 HH02 HH03 HH20                 5F110 AA23 AA26 AA30 BB01 BB02                       BB04 CC02 DD02 DD13 DD14                       EE03 EE04 EE06 EE07 EE38                       EE44 FF02 FF03 FF30 GG02                       GG13 GG32 HJ01 HJ13 HJ23                       HL03 HL04 HL05 HL06 HL12                       HM15 HM20 NN03 NN23 NN24                       NN27 NN35 NN72 NN73 PP03                       QQ04 QQ05 QQ09 QQ11

Claims (8)

[Claims] 1. A MIS type thin film transistor having a semiconductor layer of polycrystalline silicon formed on a substrate, the gate electrode of which is formed separately from a wiring layer connected thereto. Thin film transistor. 2. A thin film transistor in which impurity ions are activated by lamp annealing of polycrystalline silicon formed on a substrate, the gate electrode of which is connected to a wiring layer formed after the lamp annealing. A thin film transistor characterized by the above. 3. A step of forming polycrystalline silicon on a substrate, a step of forming a gate electrode on the upper surface of the polycrystalline silicon, and doping the polycrystalline silicon with impurities using the gate electrode as a mask, A method of manufacturing a thin film transistor, comprising: a step of activating this by lamp annealing; and a step of forming a wiring layer connected to the gate electrode. 4. A step of forming polycrystalline silicon on a substrate, a step of forming a gate electrode on an upper surface of the polycrystalline silicon, and a step of forming a pattern of the gate electrode by using a photoresist as a mask. A method of manufacturing a thin film transistor, comprising: a step of doping crystalline silicon with an impurity and activating the same by lamp annealing; and a step of forming a wiring layer connected to the gate electrode. 5. The method of claim 4, wherein the pattern of the gate electrode is over-etched with respect to the pattern of the photoresist. 6. The low dose region is formed in the polycrystalline silicon in the vicinity of the gate electrode by doping the impurities with the gate electrode as a mask after removing the photoresist. 7. A method of manufacturing a thin film transistor according to. 7. A plurality of gate signal lines juxtaposed to each other and a plurality of gate signal lines juxtaposed to each other are juxtaposed to each other on the liquid crystal side surface of one of the substrates opposed to each other with a liquid crystal interposed therebetween. A region surrounded by a plurality of drain signal lines is used as a pixel region, and a thin film transistor having a semiconductor layer of polycrystalline silicon operated by a scanning signal from a gate signal line is provided in the pixel region, and a drain signal is provided through the thin film transistor. A liquid crystal display device, comprising: a pixel electrode to which a video signal from a line is supplied; and the gate electrode of the thin film transistor and a gate signal line connected to the gate electrode are formed separately. 8. A plurality of gate signal lines juxtaposed to each other and a plurality of gate signal lines juxtaposed to each other are juxtaposed to each other on the liquid crystal side surface of one of the substrates opposed to each other with a liquid crystal interposed therebetween. A region surrounded by a plurality of drain signal lines is a pixel region, and a thin film transistor operated by a scan signal from a gate signal line and a video signal from the drain signal line are supplied to the pixel region through the thin film transistor. The thin film transistor has a semiconductor layer in which impurity ions are activated by lamp annealing of polycrystalline silicon, and its gate electrode is connected to the gate signal line formed after the lamp annealing. A thin film transistor which is characterized in that