JP2003243624A - Method of manufacturing ferroelectric memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a ferroelectric memory device in which a ferroelectric film is hardly reduced. A method of manufacturing a ferroelectric memory device includes:
(A) On the first conductive layer 212a, a ferroelectric layer 214a
(B) a step of patterning the ferroelectric layer 214a, and (c) a step of not generating hydrogen so as to fill the space between the ferroelectric layers 214a.
22. At least some of the constituent elements of the insulating layer 222 are the same as at least some of the constituent elements of the ferroelectric layer 214a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a ferroelectric memory device.

[0002]

2. Description of the Related Art In manufacturing a ferroelectric memory device, after forming a ferroelectric film, the ferroelectric film may be exposed to a hydrogen atmosphere in a step of forming an interlayer insulating layer or a dry etching step. . The ferroelectric film is generally made of metal oxide. Therefore, when the ferroelectric film is exposed to hydrogen, oxygen forming the ferroelectric film is reduced by this hydrogen. As a result, the ferroelectric film is damaged. For example, the ferroelectric film is SBT (SrBi ₂ T
In the case of a ₂ O ₉ ), when SBT is reduced by hydrogen, metal Bi is generated at the grain boundary portion, and the upper electrode and the lower electrode are short-circuited. In addition, peeling may occur at the interface between the electrode and the ferroelectric film.

[0003]

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a ferroelectric memory device in which the ferroelectric film is hard to be reduced.

[0004]

[Means for Solving the Problems] 1. First Method for Manufacturing Ferroelectric Memory Device The first method for manufacturing a ferroelectric memory device according to the present invention comprises:
(A) a step of forming a ferroelectric layer on the first conductive layer,
(B) a step of patterning the ferroelectric layer, (c)
The method includes a step of forming an insulating layer by a method that does not generate hydrogen so as to fill the space between the ferroelectric layers, and at least a part of the constituent elements of the insulating layer is a constituent element of the ferroelectric layer. At least partly the same.

According to the present invention, the insulating layer is formed by a method that does not generate hydrogen. Therefore, it is possible to prevent the ferroelectric layer from being reduced when the insulating layer is formed.

At least some of the constituent elements of the insulating layer are the same as at least some of the constituent elements of the ferroelectric layer. Therefore, even if the compositional deviation occurs on the side surface of the ferroelectric layer during the etching process or the heat treatment process, constituent atoms are replenished from the insulating layer into the ferroelectric layer and the crystal structure of the ferroelectric layer is recovered. You can also let it.

Further, the composition of the insulating layer and the composition of the ferroelectric layer can be the same. In this case, the insulating layer functions as a hydrogen barrier film, and the ferroelectric layer can be suppressed from being reduced by hydrogen generated in a later step. Moreover, since it is not necessary to separately form a hydrogen barrier film, the process can be simplified.

The step (c) can be performed by applying a material liquid for the insulating layer. This facilitates filling the insulating layer between the ferroelectric layers. The material liquid for the insulating layer may be applied in the form of mist.
By using the step (c) as a step of forming an insulating layer by the LSMCD method, unlike the spin coating method, it is difficult to depend on the pattern shape, and thus the insulating layer can be formed more uniformly.

Before the step (c), there is a step of surface-treating the surface region on which the insulating layer is to be deposited, the surface treatment being such that the surface region has an affinity with the material of the insulating layer. Can be done for. This allows
The material liquid of the insulating layer easily flows between the ferroelectric layers, and the embedding property can be improved. Before the step (c), a step of surface-treating the surface region on which the insulating layer is deposited is included, and the surface treatment is performed so that the insulating layer has an affinity with the surface region. be able to.

The surface treatment can be performed by forming a surface modification layer on the surface region. After the step (a), the method may include forming a second conductive layer on the ferroelectric layer, and in the step (b), the second conductive layer may be patterned.

2. Second Method for Manufacturing Ferroelectric Memory Device A second method for manufacturing a ferroelectric memory device according to the present invention is a method for manufacturing a memory cell array in which memory cells each composed of a ferroelectric capacitor are arranged in a matrix. , Including the following steps. (A) a step of forming a first conductive layer on a substrate, (b)
Forming a ferroelectric layer on the first conductive layer;
(C) forming a second conductive layer on the ferroelectric layer, and (d) at least the ferroelectric layer and the second layer.
A step of patterning a conductive layer, (e) hydrogen is not generated so as to fill the space between the stacked body including the first conductive layer, the ferroelectric layer and the second conductive layer on the substrate. Forming an insulating layer by a method, (f)
Removing the insulating layer until the upper surface of the second conductive layer is exposed, and (g) forming a third conductive layer having a predetermined pattern so as to partially overlap with the second conductive layer. .

According to the present invention, the operational effects of the first method for manufacturing a ferroelectric memory device of the present invention can be obtained.

According to the present invention, the second conductive layer is formed on the ferroelectric layer. Therefore, when the insulating layer is removed in the step (f), the ferroelectric layer is protected by the second conductive layer. Therefore, the structure of the surface of the ferroelectric layer is not disturbed, and deterioration of characteristics can be suppressed. That is, the damage to the capacitor can be suppressed.

3. Third Method for Manufacturing Ferroelectric Memory Device A third method for manufacturing a ferroelectric memory device according to the present invention is a ferroelectric memory having a memory cell array in which memory cells each composed of a ferroelectric capacitor are arranged in a matrix. A method for manufacturing a device, which includes the following steps. (A) a step of forming a first conductive layer on a substrate, (b)
Forming a ferroelectric layer on the first conductive layer;
(C) forming a second conductive layer on the ferroelectric layer, (d) forming a mask layer having a predetermined pattern on the second conductive layer, (e) the mask Patterning at least the ferroelectric layer and the second conductive layer using the layer as a mask; (f) the first conductive layer, the ferroelectric layer, the second conductive layer, and Forming an insulating layer by a method that does not generate hydrogen so as to cover the laminate including the mask layer, and (g) removing the insulating layer and the mask layer until the upper surface of the second conductive layer is exposed. And (h) a step of forming a third conductive layer having a predetermined pattern so as to partially overlap the second conductive layer.

According to the present invention, the operational effects of the second method for manufacturing a ferroelectric memory device of the present invention can be obtained.

Further, according to the present invention, not only the insulating layer but also the mask layer is etched in the step (g). Therefore, even if a fence is formed on the side wall of the mask layer in the step (e), the fence can be removed during the etching of the mask layer in the step (g).

In the second and third methods for manufacturing a ferroelectric memory device of the present invention, at least a part of the constituent elements of the insulating layer is the same as at least a part of the constituent elements of the ferroelectric layer. Can be taken.

The composition of the insulating layer may be the same as the composition of the ferroelectric layer.

The method for manufacturing the second and third ferroelectric memory devices of the present invention can take the aspect described in the section of the method for manufacturing the first ferroelectric memory device of the present invention.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will be described below with reference to the drawings.

1. First Embodiment 1.1 Device Structure FIG. 1 is a plan view schematically showing a ferroelectric memory device, and FIG. 2 is a ferroelectric memory device taken along line AA of FIG. It is sectional drawing which shows a part of FIG. FIG. 3 is a sectional view schematically showing a part of the ferroelectric memory device taken along the line BB of FIG. FIG. 4 is an enlarged schematic sectional view of the memory cell array in FIG. FIG. 5 is an enlarged schematic cross-sectional view of the memory cell array in FIG.

The ferroelectric memory device 1000 has a memory cell array 100 and a peripheral circuit section 200. The memory cell array 100 and the peripheral circuit section 200 are
They are formed in different layers. The peripheral circuit section 200 is formed in a region outside the memory cell array 100. Specifically, the peripheral circuit section formation region A200 is provided in a region outside the memory cell array formation region A100. In this example, the peripheral circuit section 20 is in the lower layer.
0 is the memory cell array 100 formed in the upper layer. Specific examples of the peripheral circuit unit 200 include a Y gate, a sense amplifier, an input / output buffer, an X address decoder, and a Y
An address decoder or address buffer can be mentioned.

In the memory cell array 100, a lower electrode (word line) 12 for selecting a row and an upper electrode (bit line) 16 for selecting a column are arranged orthogonal to each other. That is, the lower electrodes 12 are arranged at a predetermined pitch along the X direction, and the upper electrodes 16 are arranged at a predetermined pitch along the Y direction orthogonal to the X direction. The lower electrode 12 may be a bit line and the upper electrode 16 may be a word line.

The memory cell array 100 is provided on the first interlayer insulating layer 10, as shown in FIGS. As shown in FIGS. 4 and 5, the memory cell array 100 includes a lower electrode 12, a ferroelectric portion 14 forming a ferroelectric capacitor, an intermediate electrode 18, and an upper electrode (upper electrode) on the first interlayer insulating layer 10. ) 16 are laminated. The ferroelectric portion 14 and the intermediate electrode 18 are provided in the intersection region of the lower electrode 12 and the upper electrode 16. That is, a memory cell including the ferroelectric capacitor 20 is formed in the intersection region between the lower electrode 12 and the upper electrode 16.

As shown in FIG. 5, the ferroelectric capacitor 2
An insulating layer 70 is formed so as to cover at least the lower electrode 12 of 0. The insulating layer 70 is provided below the upper electrode 16. By providing the insulating layer 70, a short circuit between the lower electrode 12 and the intermediate electrode 18 or the upper electrode 16 is prevented. The insulating layer 70 is
For example, a first hydrogen barrier film 40 having an insulating property and a first hydrogen barrier film 40
It may have a laminated structure with the insulating layer 72. By forming the first hydrogen barrier film 40, reduction of the ferroelectric portion 14 of the ferroelectric capacitor 20 can be suppressed. The first hydrogen barrier film 40 may not be formed.

Further, as shown in FIGS. 4 and 5, the second hydrogen barrier film 4 is formed so as to cover the ferroelectric capacitor 20.
2 may be formed. By forming the second hydrogen barrier film 42, reduction of the ferroelectric portion 14 of the ferroelectric capacitor 20 can be suppressed.

As shown in FIGS. 2 and 3, the first interlayer insulating layer 10 is formed so as to cover the memory cell array 100.
A first protective layer 36 is formed on the above. Further, an insulating second protective layer 38 is formed on the first protective layer 36 so as to cover the second wiring layer 40. A first protective layer 36,
A third hydrogen barrier film 44 is formed between the second protective layer 38 and the second protective layer 38, if necessary. The third hydrogen barrier film 44 may be formed in the memory cell array region A100.
That is, the third hydrogen barrier film 44 is formed in the peripheral circuit region A2.
00 may not be formed. This allows
The peripheral circuit section A200 can be recovered by hydrogen, and at the same time, reduction of the memory cell array 100 by hydrogen can be suppressed.

The peripheral circuit section 200, as shown in FIG.
A first drive circuit 50 including various circuits for selectively writing or reading information to or from the memory cell, for example, for selectively controlling the lower electrode 12.
A second drive circuit 52 for selectively controlling the upper electrode 34, and a signal detection circuit (not shown) such as a sense amplifier.

The peripheral circuit section 200 also includes a MOS transistor 112 formed on a semiconductor substrate 110, as shown in FIG. The MOS transistor 112 includes a gate insulating layer 112a, a gate electrode 112b and a source / source electrode.
It has a drain region 112c. Each MOS transistor 112 is isolated by an element isolation region 114.
Semiconductor substrate 11 on which MOS transistor 112 is formed
A first interlayer insulating layer 10 is formed on the surface 0. The peripheral circuit section 200 and the memory cell array 100 are
It is electrically connected by the first wiring layer 40.

Next, an example of writing and reading operations in the ferroelectric memory device 1000 will be described.

First, in the read operation, the read voltage "V ₀ " is applied to the capacitor of the selected cell. This also serves as a write operation of "0". At this time, the current flowing through the selected bit line or the potential when the bit line is set to high impedance is read by the sense amplifier. At this time, a predetermined voltage is applied to the capacitors of the non-selected cells in order to prevent crosstalk during reading.

In the write operation, in the case of writing " ₁ ", the voltage "-V ₀ " is applied to the capacitor of the selected cell. In the case of writing "0", a voltage that does not invert the polarization of the selected cell is applied to the capacitor of the selected cell, and the "0" state written during the read operation is held. At this time, a predetermined voltage is applied to the capacitors of the non-selected cells in order to prevent crosstalk during writing.

1.2 Effects of Device The effects of the ferroelectric memory device 1000 will be described below.

The ferroelectric portion 14 is formed in the intersection region of the upper electrode 12 and the lower electrode 16. Therefore, it is possible to prevent the lines of electric force from protruding from the capacitor to the outside. As a result, the electric field in the ferroelectric portion 14 can be strengthened, so that the voltage required to make the ferroelectric portion 14 have a constant polarization value can be suppressed. Therefore,
The squareness of the hysteresis loop can be improved. That is, the hysteresis loop can be approximated to a square. As a result, according to the ferroelectric memory device 1000, the characteristics of the ferroelectric capacitor 20 can be improved.

1.3 Process Next, an example of a method of manufacturing the above-described ferroelectric memory device will be described. 6 to 14 show a ferroelectric memory device 1
000 is a cross-sectional view schematically showing the manufacturing process. In addition,
7 to 14 are sectional views showing only the memory cell array region.

As shown in FIG. 6, the peripheral circuit 200 is formed using a known LSI process. Specifically, the MOS transistor 112 is formed on the semiconductor substrate 110. For example, a device isolation region 114 is formed in a predetermined region on the semiconductor substrate 110 by using a trench isolation method, a LOCOS method or the like.
Then, the gate insulating layer 112a and the gate electrode 112b are formed, and then the semiconductor substrate 110 is doped with impurities to form the source / drain regions 112c. In this way, the peripheral circuit section 200 including various circuits such as the drive circuits 50 and 52 and the signal detection circuit 54.
Is formed. Then, the first interlayer insulating layer 10 is formed by a known method.

Next, a memory cell array is formed on the first interlayer insulating layer 10. Hereinafter, a method of forming the memory cell array 100 will be described with reference to FIGS.

First, as shown in FIG. 7, a first conductive layer 12a for the lower electrode 12 is formed on the first interlayer insulating layer 10. The material of the first conductive layer 12a is not particularly limited as long as it can serve as an electrode of the ferroelectric capacitor. The material of the first conductive layer 12a is, for example, I
r, IrO _x , Pt, Ru, RuO _x , SrRuO _x , L
aSrCoO _x can be mentioned. Further, as the first conductive layer 12a, a single layer or a laminate of a plurality of layers can be used. As a method of forming the first conductive layer 12a, a method such as sputtering, vacuum deposition, CVD or the like can be used.

Next, the ferroelectric layer 14a for the ferroelectric portion 14 is formed on the first conductive layer 12a. As a material of the ferroelectric layer 14a, any composition can be applied as long as it exhibits ferroelectricity and can be used as a capacitor insulating layer. Examples of such a ferroelectric include PZT (PbZr _z Ti _1-z O ₃ ), SBT (Sr
Bi ₂ Ta ₂ O ₉ ), and materials obtained by adding a metal such as niobium, nickel or magnesium to these materials can be used. The ferroelectric layer 14a may be formed by, for example, a spin coating method using a sol-gel material or a MOD material, a dipping method, a sputtering method, an M method.
The OCVD method, the laser ablation method, and the LSMCD method can be mentioned.

Next, a second conductive layer 18a for the intermediate electrode 18 is formed on the ferroelectric layer 14a. As the material and forming method of the second conductive layer 18a, the same material as that of the first conductive layer 12a can be applied.

Next, a mask layer 60 is formed on the entire surface, and the mask layer 60 having a predetermined pattern is patterned by lithography and etching. That is, the mask layer 60 is formed on the region where the lower electrode 12 is to be formed. The material of the mask layer 60 is the second conductive layer 18a,
The material is not particularly limited as long as it is a material that can function as a mask when etching the ferroelectric layer 14a and the first conductive layer 12a, and examples thereof include silicon nitride, silicon oxide, and titanium nitride. The mask layer 60 can be formed by, for example, a CVD method.

Next, as shown in FIG. 8, the second conductive layer 18 is etched by using the mask layer 60 as a mask to etch the second conductive layer 18a, the ferroelectric layer 14a and the first conductive layer 12a.
a, the ferroelectric layer 14a and the first conductive layer 12a are patterned. The lower electrode 12 having a predetermined pattern is formed by patterning the first conductive layer 12a. Examples of the etching method include RIE, sputter etching, and plasma etching. Hereinafter, the lower electrode 12, the ferroelectric layer 14a, the second
A laminated body of the conductive layer 18a and the mask layer 60 is simply referred to as a "laminated body".

Next, if necessary, as shown in FIG.
The first hydrogen barrier film 40 is formed on the entire surface. The material of the first hydrogen barrier film 40 is not particularly limited as long as it is a material that can prevent the ferroelectric layer 14a from being reduced by hydrogen, and examples thereof include aluminum oxide, titanium oxide, and magnesium oxide. it can. As the method of forming the first hydrogen barrier film 40, sputtering method, CVD
Method and laser ablation method. The step of forming the first hydrogen barrier film 40 is not essential and can be omitted.

Next, the deposition region of the first insulating layer 72 is surface-treated. This surface treatment is performed so that the surface of the deposition region of the first insulating layer 72 has an affinity with the material liquid (for example, mist) of the first insulating layer 72. A specific example of the surface treatment method will be described in the section "1.5 Surface treatment method" described later.

Next, the first insulating layer 72 is formed by a process that does not generate hydrogen so as to fill the space between the stacked bodies. Specifically, the first insulating layer 72 can be formed as follows.

The material liquid (mist) for the first insulating layer 72 is first
It is applied on the deposition region of the insulating layer 72. First insulating layer 72
Since the above-described surface treatment is performed on the deposition region of, the wettability between the material liquid of the first insulating layer 72 and the deposition region is enhanced, and the material liquid of the first insulating layer 72 flows between the stacked bodies. It will be easier. The method for depositing the material liquid of the first insulating layer 72 is
There is no particular limitation, and for example, LSMCD (Liquid Source)
Mist Chemical Deposition) method can be mentioned.
According to the LSMCD method, the material liquid of the first insulating layer 72 is more likely to flow between the stacked bodies and the step filling property is further improved. Further, according to the LSMCD method, it is difficult to depend on the pattern shape, and therefore the first insulating layer 72 can be formed uniformly in the deposition region of the first insulating layer 72. First
As the material liquid for the insulating layer 72, for example, a liquid raw material of silicon oxide can be used. Next, the first insulating layer 7
The first insulating layer 72 is formed by heat-treating the second material liquid. The material of the first insulating layer 72 is not limited to silicon oxide as long as it can be formed by a process that does not generate hydrogen. It is preferable that the material of the first insulating layer 72 be one that can have the same etching rate as that of the mask layer 60 in the subsequent etch back process of the first insulating layer 72.

Next, as shown in FIG. 10, the first insulating layer 7
A resist layer R1 is formed on top of 2. Resist layer R1
Is formed so that its upper surface is flat. The resist layer R12 can be formed by a spin coating method. The thickness of the resist layer R1 is about twice the depth of the recess formed in the first insulating layer 72 (for example, 0.8 μm).
Can be The resist layer R1 is not an essential step and can be omitted.

Next, as shown in FIG. 11, the first insulating layer 7
2 and the resist layer R1 are etched back. Simultaneously with this etch back, the mask layer 60 is removed to expose the upper surface of the second conductive layer 18a. As an etching method, for example, a dry etching such as RIE can be performed. In addition, the etching rates of the resist layer R1 and the first insulating layer 72 may be the same. As an etching etchant, for example, a mixed gas of CHF ₃ and O ₂ can be applied, and the resist layer R
The selection ratio between 1 and the first insulating layer 72 can be controlled by the mixing ratio of CHF ₃ and O ₂ . At the time of this etch back, the insulating layer 70 including the first insulating layer 72 and the first hydrogen barrier film 40 covers at least the side wall of the lower electrode 12.

Next, as shown in FIG. 12, a third layer is formed on the entire surface.
The conductive layer 16a is deposited. The material and forming method of the third conductive layer 16a can be the same as, for example, the material and forming method of the first conductive layer 12a.

Next, a resist layer R2 having a predetermined pattern is formed on the third conductive layer 16a. The resist layer R2 is formed on the region where the upper electrode 16 is to be formed.

Next, using the resist layer R2 as a mask, the third conductive layer 16a, the second conductive layer 18a, and the ferroelectric layer 14 are formed.
a, the first insulating layer 72 and the first hydrogen barrier film 40 are etched. Thus, as shown in FIG. 13, the upper electrode 16 is formed by patterning the third conductive layer 16a.
Is formed. In addition, the second conductive layer 18a and the ferroelectric layer 14a are patterned so that the upper electrode 1
An intermediate electrode layer 18 and a ferroelectric portion 14 are formed in the intersection region of 6 and the lower electrode 12. In addition, the first insulating layer 72 and the first hydrogen barrier film 40 are left under the upper electrode 16 other than the intersection region of the upper electrode 16 and the lower electrode 12. Thus, the memory cell array 100 is formed.

Next, as shown in FIGS. 1 and 14, if necessary, a second hydrogen barrier film 42 is formed on the memory cell array 100. As the material and forming method of the second hydrogen barrier film 42, those described for the first hydrogen barrier film 40 can be applied.

Next, the first protective layer 36 is formed on the second hydrogen barrier film 42 by a known method. Next, the 1st protective layer 36 is planarized as needed. Next, on the first protective layer, if necessary, the memory cell array region A1
00, the third hydrogen barrier film 44 is formed. Then, the second protective layer 36 and the third hydrogen barrier film 44 are formed on the second protective layer 36.
The protective layer 38 is formed.

1.4 Operational Effects of Process Hereinafter, operational effects of the method for manufacturing the ferroelectric memory device according to the present embodiment will be described.

(1) The first insulating layer 72 is formed by a process that does not generate hydrogen. Specifically, the first
The first insulating layer 72 is formed by applying a material liquid (mist) for the insulating layer 72 and performing heat treatment. For this reason,
When the first insulating layer 72 is formed, it is possible to prevent the ferroelectric layer 14a from being reduced.

(2) Further, the deposition region of the first insulating layer 72 is surface-treated so that the deposition region has an affinity with the material liquid of the first insulating layer 72. Therefore, the material liquid of the first insulating layer 72 can be made to easily flow between the stacked bodies.

(3) In the present embodiment, the second conductive layer 18a is formed on the ferroelectric layer 14a. For this reason, in the etch back process of the first insulating layer 72 and the mask layer 60, the ferroelectric layer 14a becomes the second conductive layer 18a.
Since it is covered with a, the ferroelectric layer 14a does not come into contact with the etchant. Therefore, the ferroelectric layer 14a
The structure of the surface of is not disturbed, and deterioration of characteristics can be suppressed. That is, the damage to the capacitor can be suppressed.

(4) In general, during etching of the conductive layer and the ferroelectric layer which form the ferroelectric capacitor, a fence made of a reaction product is not formed on the side wall of the mask,
The etching needs to be controlled. For example, it is necessary to etch at a high temperature or to have a tapered cross section.

However, in the present embodiment, the mask layer 60 is used as a mask for the first conductive layer 12a and the ferroelectric layer 1.
4a and the second conductive layer 18a are etched. Then, the mask layer 60 is removed in the etch back process of the first insulating layer 72. When removing the mask layer 60,
Even if the side wall of the mask layer 60 has a fence,
The fence will be removed. Therefore, the second
When the conductive layer 18a and the like are etched, even if etching is performed so that a fence is formed, the generated fence is removed, so that the problem caused by the fence does not occur. Therefore, it is not necessary to etch the second conductive layer 18a and the like so that the cross section has a tapered shape so that a fence is not formed, and thus a laminated body having a good cross sectional shape can be formed. Further, since it is not necessary to perform etching at a high temperature so that a fence cannot be formed, the second conductive layer 18a and the like can be etched by a normal etching device.

(5) The mask layer 60 is used to etch the second conductive layer 18a, the ferroelectric layer 14a, and the first conductive layer 12a. Since the mask layer 60 does not recede during etching unlike the resist layer, the thickness thereof can be made smaller than that of the resist layer. As a result, the mask layer enables fine processing.

(6) In this embodiment, the ferroelectric layer 14a is formed on the first conductive layer 12a before patterning. As a result, the ferroelectric layer 14a can be formed on the flat first conductive layer 12a.
4a is easily formed, and the degree of freedom of the ferroelectric film forming method is increased.

1.5 Surface Treatment Method The surface treatment method will be described with reference to FIG. The first
The description will be made in a mode that does not include the step of forming the hydrogen barrier film.

The surface modification layer 80 is formed on the surface of the deposition region of the first insulating layer 72. The surface modification layer 80 has an affinity with the material liquid (mist) of the first insulating layer 72.

The material of the surface modification layer 80 is the first insulating layer 72.
The material is not particularly limited as long as it has an affinity with the material liquid (mist), and examples thereof include hexamethyldisilazane, tetrahydrafuran, methanol, and methyl ethyl ketone.

The surface modification layer 80 is formed by sputtering or C
It may be formed by a vapor phase growth method such as a VD method, or may be formed by a method using a liquid phase such as an inkjet method, a spin coating method, a dip method and a mist deposition method. Alternatively, a substance dissolved in a solvent may be used. Hexamethyldisilazane,
A solvent selected from tetrahydrafuran, methanol, methyl ethyl ketone, etc. may be added to the raw material liquid for the insulating layer. This allows the insulating layer side to have an affinity for the surface modification layer, so that the same effect as when the surface modification layer is formed can be obtained.

The above surface treatment method can be applied to the second embodiment.

1.6 Modification The following modifications are possible in the first embodiment.

(1) At least a part of the constituent elements of the first insulating layer 72 can be the same as at least a part of the constituent elements of the ferroelectric layer 14a. Therefore, even if the compositional deviation occurs on the side surface of the ferroelectric layer in the etching step or the heat treatment step, the constituent atoms are replenished in the ferroelectric layer from the first insulating layer 72, and the crystal of the ferroelectric layer is formed. The structure can also be restored. Note that the first hydrogen barrier film 40 must not be formed in order to achieve this effect.

(2) Further, the composition of the first insulating layer 72 and the composition of the ferroelectric layer 14a can be the same. In this case, the first insulating layer 72 functions as a hydrogen barrier film, and it is possible to prevent the ferroelectric layer 14a from being reduced by hydrogen generated in a later step. Moreover, since it is not necessary to separately form a hydrogen barrier film, the process can be simplified.

(3) In this embodiment, the second conductive layer 18a and the ferroelectric layer 1 are used with the mask layer 60 as a mask.
4a and the first conductive layer 12a were etched. However, the present invention is not limited to this, and the second conductive layer 18a, the ferroelectric layer 14a, and the first conductive layer 12a may be etched using the resist layer as a mask without forming the mask layer 60.

(4) The flattening of the first insulating layer 72 is performed by CMP.
Can be done by law.

(5) If the insulating layer 70 covers at least the lower electrode 12 and the ferroelectric layer 14, the insulating layer 70 in the central portion between the laminated bodies as shown in FIG. 15 is completely removed. It may be a mode. Further, as shown in FIG. 16, the upper surface of the insulating layer 72 may be lower than the upper surface of the second conductive layer 18a. In addition, as shown in FIG.
The first hydrogen barrier film 40 may not be formed.

(6) In the above embodiment, the second conductive layer 18a, the ferroelectric layer 14a, and the first conductive layer 12a.
Were collectively patterned. However, the present invention is not limited to this, and the ferroelectric layer 14a and the first conductive layer 12a may be formed after the first conductive layer 12a is patterned.

(7) The peripheral circuit section 200 may be provided below the memory cell array.

2. Second Embodiment 2.1 Process Hereinafter, a method of manufacturing a ferroelectric memory device according to a second embodiment will be described. 18 to 22 are cross-sectional views schematically showing manufacturing steps of the ferroelectric memory device according to the second embodiment. Note that FIG. 20 is a cross-sectional view taken along a plane perpendicular to the paper surface of FIG. 19B (a plane including the CC line). 21 to 22 are cross-sectional views in a cross section similar to the cross section of FIG.

As shown in FIG. 18A, a barrier layer 218 is formed on a base body (for example, an interlayer insulating layer provided on a substrate) 210, if necessary. Barrier layer 21
8 can consist of titanium oxide, for example. For example, it is formed by forming a titanium film by a sputtering method and oxidizing the titanium film in an oxidation furnace.

Next, the first conductive layer 212a for the lower electrode is formed on the barrier layer 218. First conductive layer 21
The material and forming method of 2a are the same as those of the first embodiment.
The material and forming method of the conductive layer 12a can be applied. The thickness of the first conductive layer 212a is not particularly limited, but may be 200 nm, for example.

Next, a first mask layer 250 is formed on the first conductive layer 212a. As the forming method and material of the first mask layer 250, the forming method and material described in the first embodiment can be applied. First mask layer 2
The thickness of the first conductive layer 212 is not particularly limited.
It can be 1.5 to 2 times the thickness of a. The thickness of the first mask layer 212a may be 400 nm, for example.

Next, a resist layer R10 having a predetermined pattern is formed on the first mask layer 250. The resist layer R10 is formed on the region where the lower electrode is to be formed. The thickness of the resist layer R10 is not particularly limited and can be, for example, about 1 μm.

Next, as shown in FIG. 18B, the first mask layer 250 is etched using the resist layer R10 as a mask. The method of etching the first mask layer 250 may be a known dry etching method.
Specifically, the first mask layer 250 is formed of RIE (Reactive
It is possible to perform etching with a mixed gas of CHF ₃ and Ar using an etching device of Ion Etching).
Next, by using O ₂ plasma, for example, the resist layer R10
To remove.

Next, as shown in FIG. 18C, the first conductive layer 212a is etched using the first mask layer 250 as a mask to form the lower electrode 212. This etching can be performed by a dry etching method using, for example, a high density plasma dry etching apparatus (high density ICP etching apparatus). When a mixed gas of Cl ₂ and Ar is used as an etching gas and etching is performed at a low pressure of 1.0 Pa or less and a high bias power, etching with a small dimensional conversion difference can be performed. Further, when the substrate temperature is heated to about 350 ° C. and etching is performed, etching with a smaller dimensional change can be performed.

Next, as shown in 23 (A),
The first insulating layer 220 is formed. Examples of the material of the first insulating layer 220 include silicon oxide, silicon nitride, aluminum oxide, and tantalum oxide. As a method of forming the first insulating layer 220, for example, a CVD method can be cited. If the material and forming method of the first insulating layer 220 are the same as the material and forming method of the first mask layer 250, it is easy to make the etching rates of the first insulating layer 220 and the first mask layer 250 the same. Also,
The thickness of the first insulating layer 220 is, for example, the lower electrode 212.
The thickness may be greater than or equal to the thickness of the lower electrode 212 in consideration of filling the gap. Specifically, the first insulating layer 220 may have a thickness of 600 nm.

Next, a resist layer R12 is formed on the first insulating layer 220, if necessary. Resist layer R12
Is formed so that its upper surface is flat. The resist layer R12 can be formed by a spin coating method. The thickness of the resist layer R12 is the first insulating layer 220.
About twice the depth of the recess formed in the substrate (for example, 0.
8 μm).

Next, as shown in FIG. 19B, the first insulating layer 220 is etched back, and at the same time, the first mask layer 250 is etched to expose the upper surface of the lower electrode 212. At this time, when the lower electrode 212 is etched, the first
Even if a fence (reaction residue) is generated on the sidewall of the mask layer 250 by etching the first conductive layer 212a, the fence is also removed at the same time as the etching of the first mask layer 250. The first insulating layer 220 can be etched by, for example, a dry etching such as RIE. In addition, the etching rates of the resist layer R12 and the first insulating layer 220 may be the same. For example, as an etching etchant, CHF ₃
And a mixed gas of O ₂ can be applied, and the selection ratio of the resist layer R12 and the first insulating layer 220 is CHF ₃ and O ₂
It can be controlled by the mixing ratio with.

Next, as shown in FIG. 19C, the ferroelectric layer 2 is formed on the lower electrode 212 and the first insulating layer 220.
14a is formed. The thickness of the ferroelectric layer 214a is, for example, 120 nm. The method and material of forming the ferroelectric layer 214a are the same as those of the ferroelectric layer 14 according to the first embodiment.
The forming method and material of a can be applied.

Next, a second conductive layer 216a for the upper electrode is formed on the ferroelectric layer 214a. The material and forming method of the second conductive layer 216a can be the same as those of the first conductive layer 12a of the first embodiment.

FIG. 20 shows a cross section taken along a plane perpendicular to the plane of the paper of FIG. 19C (the plane including the line CC).
Hereinafter, description will be given based on the cross section shown in FIG.

Next, as shown in FIG. 21A, a second mask layer 252 having a predetermined pattern is formed on the second conductive layer 216a. The second mask layer 252 is formed so as to cover a region where the upper electrode is to be formed. Second
As the material and forming method of the mask layer 252, the same material as the first mask layer 250 can be applied.

Next, as shown in FIG. 21B, the second conductive layer 216a and the ferroelectric layer 214a are etched using the second mask layer 252 as a mask. This allows
The upper electrode 216 is formed.

Next, the surface of the laminated body of the first insulating layer 220, the ferroelectric layer 214a, the upper electrode 216 and the mask layer 252 is surface-treated. This surface treatment is performed so as to have an affinity with the material liquid of the second insulating layer 222. As the surface treatment method, the method shown in the first embodiment can be adopted.

Next, as shown in FIG. 22A, a process which does not generate hydrogen is performed so as to fill the entire surface between the stacked layers of the ferroelectric layer 214a, the upper electrode 216 and the mask layer 252. The second insulating layer 222 is formed. Specifically, the second insulating layer 222 can be formed similarly to the method of forming the first insulating layer 72 of the first embodiment. The thickness of the second insulating layer 222 can be, for example, greater than or equal to the thickness of the ferroelectric layer 214a and the upper electrode 216. At least part of the constituent elements of the second insulating layer 222 is the same as at least part of the constituent elements of the ferroelectric layer 214a. Preferably, the second insulating layer 2
It is preferable that the composition of 22 and the composition of the ferroelectric layer 214a are the same.

Next, a resist layer R14 is formed on the second insulating layer 222. When the second insulating layer 222 having a flat upper surface is formed by using the coating method, the resist layer R14
Need not be formed. The resist layer R14 can be formed in the same manner as the above resist layer R12.

Next, as shown in FIG. 22B, the second insulating layer 222 is etched back. At the same time, the second
The mask layer 252 is removed by etching. Note that if there is a fence formed on the side wall of the second mask layer 252 when the second conductive layer 216a is etched, it is removed when the second mask layer 252 is etched. Thus, the lower electrode 212, the ferroelectric layer 214a and the upper electrode 216.
A ferroelectric capacitor including is formed.

2.2 Effects Hereinafter, the function and effect of the second embodiment will be described.

(1) The second insulating layer 222 is formed by a process that does not generate hydrogen. Specifically, the second insulating layer 222 is formed by applying a material liquid (mist) for the second insulating layer 222 and performing heat treatment. Therefore, when the second insulating layer 222 is formed, the ferroelectric layer 214
The reduction of a can be suppressed.

(2) Furthermore, the deposition region is surface-treated so that the deposition region of the second insulating layer 222 and the material liquid of the second insulating layer 222 have an affinity. For this reason,
The material liquid of the second insulating layer 222 can easily flow between the stacked bodies.

(3) At least a part of the constituent elements of the second insulating layer 222 can be the same as at least a part of the constituent elements of the ferroelectric layer 214a. For this reason, when the compositional deviation occurs on the side surface of the ferroelectric layer in the etching step or the heat treatment step, constituent atoms are replenished from the insulating layer to the ferroelectric layer to recover the crystal structure of the ferroelectric layer. You can also

Also, the composition of the second insulating layer 222 and the composition of the ferroelectric layer 214a can be the same. In this case, the second insulating layer 222 functions as a hydrogen barrier film, and it is possible to prevent the ferroelectric layer 214a from being reduced by hydrogen generated in a later step. Also,
Since it is not necessary to separately form a hydrogen barrier film, the process can be simplified.

(4) In the present embodiment, the first conductive layer 212a is etched by using the first mask layer 250 as a mask, and the first insulating layer 220 is etched back to form the first conductive layer 212a.
The mask layer 250 is removed. Therefore, even if a fence is formed on the sidewall of the first mask layer 250 in the etch back process of the first insulating layer 220, the fence can be removed. Therefore, the lower electrode 212 having a good sectional shape can be formed. That is, the angle formed between the side surface of the lower electrode 212 and the surface of the base can be made substantially vertical. Further, since it is not necessary to perform etching at a high temperature so that a fence cannot be formed, the first conductive layer 212a can be etched with a normal etching device.

(5) In this embodiment, the second conductive layer 216a is etched using the second mask layer 252 as a mask, and the second insulating layer 222 is etched back.
The second mask layer 252 is removed. Therefore, the upper electrode 216 having a good cross-sectional shape can be formed. Further, the second conductive layer 216a can be etched with a normal etching apparatus.

(6) According to the present embodiment, the lower electrode 2
The first insulating layer 220 embedded between the layers 12 is etched back. Therefore, the upper surface of the first insulating layer 220 and the upper surface of the lower electrode 212 are substantially flush with each other, and the upper surfaces thereof are flat. Therefore, according to the present embodiment, the ferroelectric layer 214a can be easily formed.

3. Experimental Example It was examined how the hysteresis loops differ between the example and the comparative example. FIG. 23 is a diagram illustrating a hysteresis loop according to the example. FIG. 24 is a diagram showing a hysteresis loop according to the comparative example.

In the embodiment, the structure shown in FIGS. 2 to 5 is adopted as the structure of the memory cell array. In addition, in the examples, as a method of not generating hydrogen, LSMC
Hysteresis loops were investigated using a case where the insulating layer was formed by the D method and a case where SiO ₂ was formed as the insulating layer by the plasma TEOS CVD method as a method of generating hydrogen as a comparative example. In the comparative example,
The memory cell array has a structure in which a continuous ferroelectric layer is formed on a base body including a lower electrode, and an upper electrode is formed on the ferroelectric layer.

As shown in FIGS. 23 and 24, according to the example, it is understood that the hysteresis characteristic having a larger remanent polarization value is exhibited as compared with the comparative example.

In the present invention, since the insulating layer is formed by a method that does not generate hydrogen, it is possible to prevent the ferroelectric layer from being reduced and the polarization characteristics from being deteriorated when the insulating layer is formed. I know that

The present invention is not limited to the above embodiment, and various modifications can be made within the scope of the gist of the present invention.

[Brief description of drawings]

FIG. 1 is a plan view schematically showing a ferroelectric memory device.

FIG. 2 is a cross-sectional view schematically showing a part of the ferroelectric memory device taken along the line AA of FIG.

FIG. 3 is a cross-sectional view schematically showing a part of the ferroelectric memory device taken along the line BB of FIG.

FIG. 4 is an enlarged schematic cross-sectional view of the memory cell array in FIG.

5 is an enlarged schematic cross-sectional view of the memory cell array in FIG.

FIG. 6 is a cross-sectional view schematically showing the manufacturing process of the ferroelectric memory device.

FIG. 7 is a cross-sectional view schematically showing the manufacturing process of the ferroelectric memory device.

FIG. 8 is a cross-sectional view schematically showing the manufacturing process of the ferroelectric memory device.

FIG. 9 is a cross-sectional view schematically showing the manufacturing process of the ferroelectric memory device.

FIG. 10 is a cross-sectional view schematically showing the manufacturing process of the ferroelectric memory device.

FIG. 11 is a cross-sectional view schematically showing the manufacturing process of the ferroelectric memory device.

FIG. 12 is a cross-sectional view schematically showing the manufacturing process of the ferroelectric memory device.

FIG. 13 is a cross-sectional view schematically showing the manufacturing process of the ferroelectric memory device.

FIG. 14 is a cross-sectional view schematically showing the manufacturing process of the ferroelectric memory device.

FIG. 15 is a cross-sectional view schematically showing a modification of the first embodiment.

FIG. 16 is a cross-sectional view schematically showing a modified example of the first embodiment.

FIG. 17 is a sectional view schematically showing a surface treatment method.

FIG. 18 is a cross-sectional view schematically showing the manufacturing process of the ferroelectric memory device according to the second embodiment.

FIG. 19 is a cross-sectional view schematically showing the manufacturing process of the ferroelectric memory device according to the second embodiment.

FIG. 20 is a cross-sectional view schematically showing the manufacturing process of the ferroelectric memory device according to the second embodiment.

FIG. 21 is a cross-sectional view schematically showing the manufacturing process of the ferroelectric memory device according to the second embodiment.

FIG. 22 is a cross-sectional view schematically showing the manufacturing process of the ferroelectric memory device according to the second embodiment.

FIG. 23 is a diagram showing a hysteresis loop according to an example.

FIG. 24 is a diagram showing a hysteresis loop according to a comparative example.

[Explanation of symbols]

10 First interlayer insulating layer 12 Lower electrode 14 Ferroelectric part 16 Upper electrode 18 Intermediate electrode layer 36 First protective layer 38 Second protective layer 40 First hydrogen barrier film 42 Second hydrogen barrier film 44 Third Hydrogen Barrier Film 50 First drive circuit 52 Second drive circuit 60 mask layer 70 Insulation layer 72 First insulating layer 80 Surface modification layer 90 precursor layer 92 Charge layer 100 memory cell array 110 Semiconductor substrate 112 MOS transistor 112a gate insulating layer 112b gate electrode 112c Source / drain region 114 element isolation region 200 peripheral circuits 212 Lower electrode 214a Ferroelectric layer 216 Upper electrode 220 First insulating layer 222 Second insulating layer 250 First mask layer 252 second mask layer 1000 Ferroelectric memory device

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Eiji Natori             Seiko, 3-3-3 Yamato, Suwa City, Nagano Prefecture             -In Epson Corporation (72) Inventor Masao Nakayama             Seiko, 3-3-3 Yamato, Suwa City, Nagano Prefecture             -In Epson Corporation F-term (reference) 5F083 FR00 FR01 GA27 JA02 JA06                       JA15 JA17 JA19 JA38 JA40                       JA43 JA44 LA12 LA16 MA06                       MA19 PR03 PR39

Claims (13)

[Claims] 1. A step of: (a) forming a ferroelectric layer on the first conductive layer; (b) a step of patterning the ferroelectric layer; and (c) a space between the ferroelectric layers. As the filling, including a step of forming an insulating layer by a method that does not generate hydrogen, at least a portion of the constituent elements of the insulating layer is the same as at least a portion of the constituent elements of the ferroelectric layer, Method of manufacturing a dielectric memory device. 2. The method of manufacturing a ferroelectric memory device according to claim 1, wherein the composition of the insulating layer is the same as the composition of the ferroelectric layer. 3. The method of manufacturing a ferroelectric memory device according to claim 1, wherein the step (c) is performed by applying a material liquid for the insulating layer. 4. The method according to claim 3, further comprising a step of surface-treating a surface region on which the insulating layer is deposited, before the step (c), wherein the surface treatment is performed by using the material of the insulating layer as the surface region. A method of manufacturing a ferroelectric memory device, which is performed so as to have affinity. 5. The method of manufacturing a ferroelectric memory device according to claim 4, wherein the surface treatment is performed by forming a surface modification layer on the surface region. 6. The method according to claim 3, further comprising a step of surface-treating a surface region on which the insulating layer is deposited before the step (c), wherein the surface treatment has an affinity for the insulating layer with the surface region. A method of manufacturing a ferroelectric memory device, which is performed so as to have good property. 7. The method of manufacturing a ferroelectric memory device according to claim 3, wherein the material liquid for the insulating layer is applied in the form of mist. 8. The method for manufacturing a ferroelectric memory device according to claim 7, wherein the step (c) is a step of forming an insulating layer by the LSMCD method. 9. The method according to claim 1, further comprising a step of forming a second conductive layer on the ferroelectric layer after the step (a), the step (b) comprising: The method of manufacturing a ferroelectric memory device, wherein the second conductive layer is patterned. 10. A method of manufacturing a memory cell array in which memory cells each composed of a ferroelectric capacitor are arranged in a matrix, the method including the following steps. (A) a step of forming a first conductive layer on a substrate, (b)
Forming a ferroelectric layer on the first conductive layer;
(C) forming a second conductive layer on the ferroelectric layer, and (d) at least the ferroelectric layer and the second layer.
A step of patterning a conductive layer, (e) hydrogen is not generated so as to fill the space between the stacked body including the first conductive layer, the ferroelectric layer and the second conductive layer on the substrate. Forming an insulating layer by a method, (f)
Removing the insulating layer until the upper surface of the second conductive layer is exposed, and (g) forming a third conductive layer having a predetermined pattern so as to partially overlap with the second conductive layer. . 11. A method of manufacturing a ferroelectric memory device having a memory cell array in which memory cells each composed of a ferroelectric capacitor are arranged in a matrix, the method including the steps of: . (A) a step of forming a first conductive layer on a substrate, (b)
Forming a ferroelectric layer on the first conductive layer;
(C) forming a second conductive layer on the ferroelectric layer, (d) forming a mask layer having a predetermined pattern on the second conductive layer, (e) the mask Patterning at least the ferroelectric layer and the second conductive layer using the layer as a mask; (f) the first conductive layer, the ferroelectric layer, the second conductive layer, and Forming an insulating layer by a method that does not generate hydrogen so as to cover the laminate including the mask layer, and (g) removing the insulating layer and the mask layer until the upper surface of the second conductive layer is exposed. And (h) a step of forming a third conductive layer having a predetermined pattern so as to partially overlap the second conductive layer. 12. The method of manufacturing a ferroelectric memory device according to claim 10, wherein at least a part of constituent elements of the insulating layer is the same as at least a part of constituent elements of the ferroelectric layer. 13. The method of manufacturing a ferroelectric memory device according to claim 12, wherein the composition of the insulating layer is the same as the composition of the ferroelectric layer.