JP2003243532A - Complementary semiconductor device and method of manufacturing complementary semiconductor device - Google Patents

Abstract

[PROBLEMS] To provide a semiconductor device capable of selectively forming relatively shallow and high-concentration p-type and n-type buried layers on the same substrate, and a method of manufacturing the same. Provided is a complementary semiconductor device in which the activation rates of both p-type and n-type buried layers selectively formed on the same substrate are increased, and a method of manufacturing the same. A complementary semiconductor device according to the present invention is provided.
Are a first gate insulating film 50 formed on the n-type semiconductor region 20 and a first gate insulating film 50 formed on the first gate insulating film.
A first transistor 220 including a gate electrode 60 and a p-type source and drain layer 120 composed of a single crystal layer epitaxially grown in an n-type semiconductor region on both sides of the first gate electrode; Type semiconductor region 3
0, a second gate insulating film 50 formed on
Gate electrode 60 formed on the gate insulating film of FIG.
And a second transistor 230 including an n-type source layer and a drain layer 130 made of a single crystal layer epitaxially grown in a p-type semiconductor region on both sides of the second gate electrode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a complementary semiconductor device and a method of manufacturing the complementary semiconductor device.

[0002]

2. Description of the Related Art Conventionally, MOSFET (Metal Oxide Semico
A diffusion layer of a semiconductor device such as an nductor field effect transistor) has been formed by ion-implanting impurities into a semiconductor substrate. The impurities injected into this diffusion layer are activated by heat treatment by the RTA (Rapid Thermal Anneal) method.

However, with the recent miniaturization of semiconductor devices, it has been difficult to shallowly form a diffusion layer having a high impurity concentration by ion implantation and RTA.

For example, if the gate width of the MOSFET is 0.1 μm or less, the depth of the diffusion layer of the source and drain must be 40 nm or less in order to prevent the short channel effect. It has been difficult to form such a diffusion layer by ion implantation and RTA as in the past.

Therefore, there has been proposed a method (hereinafter referred to as a deposition method) of forming a deposition layer in which a material containing impurities is deposited in advance in a region where the diffusion layer is formed, instead of the diffusion layer.

[0006]

According to the deposition method, the depth of the source and drain single crystal layers can be 40 nm or less.

However, according to the deposition method, the n-type source layer and the n-type drain layer and the p-type source layer and the p-type drain layer could not be selectively formed on the same substrate. That is, the deposition method is a complementary MOS transistor (hereinafter referred to as CMOSFET (Complimentary Metal Oxide Semiconducer) having an n-type transistor and a p-type transistor.
(also called tor Field Effect Transistor)).

Further, in recent years, in order to increase the activation rate of impurities, SiGe in which Si (silicon) contains Ge (germanium) is sometimes used as a semiconductor material. In the case of a p-type semiconductor material containing B (boron) as an impurity, SiGe is better than a Si semiconductor material not containing Ge.
In semiconductor materials, the activation rate of B increases. However, in the case of an n-type semiconductor material containing As (arsenic) as an impurity, the activation rate of As does not increase even with a SiGe semiconductor material.

Therefore, when the SiGe semiconductor material is used for the CMOSFET, the activation rate of impurities in the source layer and drain layer of the p-type transistor increases, but the impurity activation rate of impurities in the source layer and drain layer of the n-type transistor increases. There is a problem that the activation rate does not increase.

Therefore, an object of the present invention is to make it possible to selectively form a relatively shallow and high-concentration p-type source and drain layer and an n-type source and drain layer on the same substrate. A semiconductor device and a method for manufacturing the same are provided.

Another object of the present invention is to increase the activation rates of both the p-type source / drain layer and the n-type source / drain layer selectively formed on the same substrate as compared with the prior art. Another object of the present invention is to provide a semiconductor device and a manufacturing method thereof.

[0012]

A complementary semiconductor device according to an embodiment of the present invention is a semiconductor device having a first conductivity type semiconductor region and a second conductivity type semiconductor region formed on a surface of a semiconductor substrate. A first gate insulating film formed on the second conductivity type semiconductor region; a first gate electrode formed on the first gate insulating film; and a first gate electrode formed on both sides of the first gate electrode. A first transistor including a first-conductivity-type source layer and a drain layer made of an epitaxial layer in a second-conductivity-type semiconductor region, and formed on the first-conductivity-type semiconductor region on the surface of the semiconductor substrate. Second gate insulating film, a second gate electrode formed on the second gate insulating film, and an epitaxial layer on the semiconductor region of the first conductivity type on both sides of the second gate electrode. Second conductivity type source consisting of And a second transistor including a drain layer.

Preferably, the first-conductivity-type source layer and the second-conductivity-type source layer are made of single crystals of different materials, and the first-conductivity-type drain layer and the second-conductivity-type source layer are formed. The drain layer is also a semiconductor layer made of single crystals made of different materials.

Preferably, the first conductivity type source layer and drain layer and the second conductivity type source layer and drain layer are at least Si (silicon), Ge (germanium) or C (carbon). It is a semiconductor containing one kind.

Preferably, the first conductivity type source layer and drain layer are n type source layers and drain layers containing As (arsenic) in SiGeC crystal, and the second conductivity type source layer. And the drain layer is B in the SiGe crystal.
It is a p-type source layer and a drain layer containing (boron) or its elements.

The first conductive type source layer and drain layer may be an n type source layer and drain layer containing P (phosphorus) in SiGe or SiGeC crystal, and the second conductive type source layer and drain layer. The source layer and the drain layer may be a p-type source layer and a drain layer in which B or a homologous element thereof is contained in SiGe crystal.

More preferably, the depth of the source and drain layers of the first conductivity type and the depth of the source and drain layers of the second conductivity type are 40 nm or less, and the depth of the first conductivity type is 40 nm or less. Both the impurity concentration in the source layer and the drain layer and the impurity concentration in the second conductivity type source layer and the drain layer are 1 × 10 ¹⁹ cm ⁻³ or more.

A method of manufacturing a complementary semiconductor device according to an embodiment of the present invention includes a step of forming a semiconductor region of a first conductivity type and a semiconductor region of a second conductivity type on a surface of a semiconductor substrate; Forming a gate insulating film on the surface of the substrate; forming a gate electrode on the gate insulating film; and etching the surface of the semiconductor substrate on both sides of the gate electrode to form a source layer and a drain layer And an etching step for forming a source / drain layer forming region, and a first source for selectively epitaxially growing a first conductive type semiconductor in the source / drain layer forming region in the second conductive type semiconductor region. -Drain layer forming step and the first step
A second source / drain layer forming step of selectively epitaxially growing a second conductive type semiconductor in the source / drain layer forming region of the conductive type semiconductor region.

Preferably, in the first source / drain layer forming step, a first protective film is formed on a surface of the source / drain layer forming region in the semiconductor region of the first conductivity type. A film formation step, and selectively epitaxially grow the first conductivity type semiconductor in the source / drain layer formation region in the second conductivity type semiconductor region where the first protection film is not formed. In the step of forming the second source / drain layer, the first protective film is removed and a second protective film is formed on the surface of the source / drain layer forming region in the semiconductor region of the second conductivity type. A second protective film forming step, wherein the second conductive type semiconductor is selected in the source / drain layer forming region in the first conductive type semiconductor region in which the second protective film is not formed. To Epitaxially grow.

Preferably, the first conductivity type semiconductor and the second conductivity type semiconductor are semiconductors containing at least one of Si (silicon), Ge (germanium), and C (carbon).

Preferably, the first conductivity type semiconductor is
It is an n-type semiconductor containing As (arsenic) in the crystal of SiGeC, and the second conductivity type semiconductor is a p-type semiconductor containing B (boron) or its homologous element in the crystal of SiGe. .

Preferably, the first conductivity type semiconductor is
It is an n-type semiconductor containing P (phosphorus) in the crystal of SiGe or SiGeC, and the semiconductor of the second conductivity type is a p-type semiconductor containing B or its homologous element in the crystal of SiGe.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. The present embodiment does not limit the present invention. Further, in the present specification, even if the conductivity type is changed to the p-type instead of the n-type and the conductivity type is changed to the n-type instead of the p-type, the effect described in the present specification is not lost.

1 to 11 are enlarged cross-sectional views of a semiconductor substrate showing a method of manufacturing a complementary semiconductor device (hereinafter, also simply referred to as a semiconductor device) according to a first embodiment of the present invention in the order of steps. Is.

Referring to FIG. 1, an n-type region 20 and a p-type region 30 are formed on a semiconductor substrate 10 using a photolithography technique.

For example, according to the present embodiment, a silicon substrate is used as the semiconductor substrate 10. In this silicon substrate, As, P, Sb, etc. are ion-implanted as n-type impurities, and B, Ga, In, etc. are ion-implanted as p-type impurities. N-type impurities and p-type impurities are diffused by heat treatment and each has a depth of about 1μ.
An n-type region 20 and a p-type region 30 of m are formed.

With reference to FIG. 2, next, the element isolation portion 40 is formed. According to the present embodiment, the element isolation section 40
Consists of a silicon oxide film with a thickness of about 400 nm.
ow Trench Isolation) method.

Next, a substrate protection film (not shown) is formed by oxidizing the surface 12 of the semiconductor substrate 10.
The substrate protection film is provided to protect the substrate from the impact of channel ion implantation for adjusting the threshold voltage of the MOS transistor. Further, channel ion implantation is performed and the substrate protective film is removed.

Referring to FIG. 3, next, gate insulating film 50 is formed.
Are formed on the surface 12 of the semiconductor substrate 10. In the present embodiment, gate insulating film 50 is a silicon oxide film formed by thermally oxidizing surface 12 of semiconductor substrate 10, and its thickness is about several nm. Gate insulating film 50
In addition to the silicon oxide film, is an oxynitride film containing several% of nitrogen in the silicon oxide film, TaO ₂ , ZrOx, HfOx.
A high dielectric material such as (x is a positive integer) may be used.

With reference to FIG. 4, next, polycrystalline silicon is deposited on the gate insulating film 50 by using, for example, a CVD (Chemical Vapor Deposition) method or the like. After that, the gate electrode 60 is formed by patterning the deposited polycrystalline silicon by using the photolithography technique. In the present embodiment, the gate electrode 60 has a thickness of about 150 nm.

Referring to FIG. 5, next, a silicon oxide film 70 covering the gate electrode 60 is formed. According to the present embodiment, the silicon oxide film 70 is formed by selectively oxidizing the gate electrode 60 with H ₂ O and H ₂ . The thickness of the silicon oxide film 70 is about 3 nm.

Further, a sidewall protection portion 80 made of silicon nitride is formed on the silicon oxide film 70. According to the present embodiment, a silicon nitride film is deposited on surface 12 and silicon oxide film 70. After that, the silicon nitride film is subjected to RIE (Reactive) so as to leave the sidewall protection portion 80 of the silicon nitride film that protects the sidewall of the gate electrode 60.
Ion Etching).

The silicon oxide film 70 is a liner.
As a layer, it has a role as an etching stopper when the silicon nitride film is etched. Further, the silicon oxide film 70 is formed on the gate electrode 60 due to the stress of the side wall protection portion 80.
Also has the role of protecting

Next, the gate insulating film 50 on the surface 12 of the semiconductor substrate 10 is removed. At this time, the gate electrode 60
The gate insulating film 50 underneath is left. According to the present embodiment, the gate insulating film 50 is wet-etched. Surface 1 of semiconductor substrate 10 after wet etching
In order to prevent the oxide film from being formed when 2 is exposed to air, the low pressure spin dry method or IPA is used.
A drying method or the like is adopted. The reduced pressure spin dry method is a drying method in which the semiconductor substrate 10 is rotated at a high speed in a low pressure atmosphere. The IPA drying method is a method in which the surface 12 is immersed in isopropyl alcohol (IPA (Isopropyl alcohol)) and then dried.

Referring to FIG. 6, next, of n-type region 20 and p-type region 30, source and drain regions 90a and 90b where the source and drain layers are to be formed are etched. In this embodiment, the p-type source and drain regions 90a are the recesses where the p-type source and drain layers are to be formed using the n-type region 20 as the n-type well. p-type region 30
The n-type source and drain regions 90b are the recesses where the n-type source and drain layers are to be formed with the p-type well as the p-type well.

According to the present embodiment, source and drain regions 90a and 90b are dry-etched at a temperature of about 700 ° C. using an etching gas such as CF ₄ or HCl. The depth d of the source and drain regions 90a and 90b is about 40 nm.

Referring to FIG. 7, next, mask layer 100 is formed on semiconductor substrate 10. The mask layer 100 is
It may be formed by depositing TEOS (Tetra Ethyl Ortho Silicate) or the like by the CVD method. Further, the mask layer 100 may be formed by thermally oxidizing the semiconductor substrate 10. According to the present embodiment, the mask layer 1
The thickness of 00 is about 5 nm.

Referring to FIG. 8, next, a photoresist 110 is formed on the mask layer 100 on the p-type region 30 by using a photolithography technique. Photoresist 1
Using 10 as a mask, the mask layer 100 on the n-type region 20 is removed. At this time, the mask layer 100 may be etched by either wet etching or dry etching. Then, the photoresist 110 is removed.

Referring to FIG. 9, using mask layer 100 existing in p type region 30 as a mask, p type source and drain buried layer 120 is formed in p type source region and drain region 90a of n type region 20. To be done. According to the present embodiment, the source and drain buried layer 120 is formed of LP-CV.
It is a single crystal layer formed by epitaxially growing SiGe containing B (boron) by a D (Low Pressure-Chemical Vapor Deposition) device. For example,
In this epitaxial growth, SiH ₂ Cl ₂ into H ₂
(Dichlorosilane), GeH ₄ (germane), HCl and B
A gas containing ₂ H ₆ (diborane) is used. The concentration of boron in the source and drain buried layer 120 is about
It is from 1 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²² cm ⁻³ .

The epitaxial growth method according to this embodiment is a so-called VPE (Vapor Phase Epitaxy) method. Therefore, the source and drain buried layer 120 has p
It can be selectively epitaxially grown on the mold source and drain regions 90a.

The epitaxial growth method is so-called SPE.
(Solid Phase Epitaxy) method may be used. In the case of the SPE method, after the amorphous silicon (not shown) is deposited, the amorphous silicon in the source region and the drain region 90a is heat-treated. Thereby, the amorphous silicon in the p-type source region and the drain region 90a is epitaxially grown into a silicon single crystal.
After that, the amorphous silicon is selectively etched,
A source and drain buried layer 120 is obtained.

Referring to FIG. 10, next, mask layer 105 is formed on n-type region 20. According to the present embodiment, the mask layer 105 is formed by depositing TEOS or the like by the CVD method. After the mask layer 105 is deposited on the semiconductor substrate 10, the mask layer 105 on the p-type region 30 is covered with a photoresist using a photolithography technique. Then, the mask layer 105 on the n-type region 20 is etched. At this time, the mask layer 10
5 may be etched by either wet etching or dry etching. In this way, the n-type source region and the drain region 90b of the p-type region 30 are exposed.

Referring to FIG. 11, source and drain buried layer 130 is formed in n type source region and drain region 90b of p type region 30, using mask layer 105 existing in n type region 20 as a mask. According to the present embodiment, the source and drain buried layer 130 is a single crystal layer formed by epitaxially growing SiGeC containing As (arsenic) by an LP-CVD device. For example, in this epitaxial growth, SiH ₂ into H ₂
Cl ₂ (dichlorosilane), GeH ₄ (germane), HCl, Si
A gas containing H ₃ CH ₃ and AsH ₃ (arsine) is used. The concentration of arsenic in the source and drain buried layer 130 is about 1 × 10 ¹⁹ to 1 × 10 ²² cm ⁻³ .

Further, the epitaxial growth method according to the present embodiment may be either the VPE method or the SPE method.
By either method, the source / drain buried layer 130 can be selectively epitaxially grown as in the case of forming the source / drain buried layer 120.

Further, source and drain electrodes (not shown), wiring and the like are formed, and the semiconductor device according to the present embodiment is completed.

As described above, according to the present invention, the portion of the semiconductor substrate where the source and drain layers are formed is removed, and the semiconductor material containing impurities is deposited (epitaxial growth) on the portion to fill the source and drain layers. An embedded layer is formed. This is called the burial method. That is, in the present invention, the source and drain layers are formed by using the burying method among the deposition methods.

According to the burying method, the depths of the source and drain buried layers 120 and 130 from the surface 12 are substantially determined by the depths d of the source and drain regions 90a and 90b. According to the present embodiment, since the depth d is about 40 nm, the depth of the source and drain buried layers 120 and 130 is about 40 nm. Moreover, according to the present embodiment, the source and drain regions 90a are formed.
And 90b are etched in the same step (see FIG. 6). Therefore, the depth d is substantially equal between the p-type source / drain region 90a and the n-type source / drain region 90b.

The source and drain buried layers 120,
Silicide may be formed on 130. Thereby, the contact resistance between the source / drain buried layers 120 and 130 and the source / drain electrodes can be reduced. In this case, the source and drain buried layer 12
Silicon single crystal layer (not shown) on top of 0 and 130
And the silicide may be formed using the silicon single crystal layer. That is, the so-called Elevated Source Dr
The ain structure may be used.

By the embedding method, the n-type source layer and the n-type drain layer, and the p-type source layer and the p-type drain layer can be selectively formed on the same substrate. According to the present embodiment, the embedding method can be applied to a CMOSFET having an n-type transistor and a p-type transistor.

Thereby, the p-type source layer and the p-type drain layer, and the n-type source layer and the n-type drain layer can be formed to a depth of 40 nm or less.

Further, the p-type source layer and the p-type drain layer and the n-type source layer and the n-type drain layer can be formed of different semiconductor materials. For example, according to the present embodiment, the p-type source / drain buried layer 120 is formed of SiGe, and the n-type source / drain buried layer 130 is formed of SiGeC.

FIG. 12 is a schematic cross sectional view of a semiconductor device 200 manufactured by the method of manufacturing a complementary semiconductor device according to the first embodiment. While explaining the structure of the semiconductor device 200 with reference to FIG. 12, the effect of the semiconductor device 200 will be described.

The semiconductor device 200 is a CMOSFET having a p-type transistor 220 formed in the n-type region 20 and an n-type transistor 230 formed in the p-type region 30.

The p-type transistor 220 includes the n-type region 20.
A gate insulating film 50 formed on the surface of the gate, a gate electrode 60 formed on the gate insulating film 50, and a gate electrode 6
0 and n-type regions 20 on both sides of 0, and a p-type source and drain buried layer 120 epitaxially grown.

The n-type transistor 230 has a p-type region 30.
A gate insulating film 50 formed on the surface of the gate, a gate electrode 60 formed on the gate insulating film 50, and a gate electrode 6
And n-type source and drain buried layers 130 formed of a single crystal layer epitaxially grown in p-type regions 30 on both sides of 0.

According to the present embodiment, the p-type source and drain buried layer 120 is made of SiGe from about 1 × 10 ¹⁹ to 1 ×.
It is doped with B (boron) at a concentration of 10 ²² cm ⁻³ . Compared to a p-type transistor using a Si semiconductor material not containing Ge, a p-type transistor using a SiGe semiconductor material is used.
The activation rate of B (boron) in the type transistor 220 is higher.

On the other hand, the n-type source and drain buried layer 130 is SiGeC doped with As (arsenic) at a concentration of about 1 × 10 ¹⁹ to 1 × 10 ²² cm ⁻³ .

Here, the interstitial distance of C (carbon) is Si
It is about 48% of the interstitial distance of (silicon). The interstitial distance of As is about 104% of the interstitial distance of Si. Therefore, As, which has a relatively large interstitial distance, is SiGeC as an impurity.
Even if it is contained in, the stress or strain that As gives to the surroundings is absorbed by C (carbon) having a relatively small interstitial distance. This makes it easy for As to replace atoms at any of the lattice positions of SiGeC. That is, As in SiGeC has a higher activation rate than As in SiGe containing no C.

According to the conventional thermal diffusion method, the impurity concentration in the source and drain buried layers is
It depends on the depth from the surface of the semiconductor substrate. But,
According to the present embodiment, the source and drain buried layer 1
Reference numerals 20 and 130 are single crystal layers formed by epitaxially growing a semiconductor material containing impurities in advance. Therefore, the impurity concentration of the source and drain buried layers 120 and 130 according to the present embodiment does not differ depending on the depth from the surface of the semiconductor substrate.

The p-type source and drain buried layer 1
20 depth and n-type source and drain buried layer 1
The depth of 30 is about 40 nm. Therefore, in the p-type transistor 220 and the n-type transistor 230, a short channel effect such as punch through is prevented.

FIG. 13 is a schematic sectional view of a semiconductor device 300 according to another embodiment of the present invention. In the semiconductor device 200, the gate electrode 60 is formed of a single layer, but the semiconductor device 300 is different in that the gate electrode 360 is formed of a plurality of layers.

According to the present embodiment, the gate electrode 360
Is a polycrystalline silicon layer 362 formed on the gate insulating film 50 and a WS formed on the polycrystalline silicon 362.
It has an iN layer 364, a W (tungsten) layer 366 formed on the WSiN layer 364, and a silicon nitride film 368 further formed on the W layer 366.

According to the present embodiment, the polycrystalline silicon layer 362, the WSiN layer 364, the W layer 366 and the silicon nitride film 368 have a thickness of about 100 nm, about 1 nm, about 50 nm and about 50 nm, respectively.
It is 50 nm.

The resistance value of the gate electrode 360 is reduced by having such a polymetal structure. As a result, the operating speed of the semiconductor device 300 becomes faster.

Next, a method of manufacturing the gate electrode 360 of the semiconductor device 300 will be described. First, a polycrystalline silicon layer is deposited on the gate insulating film 50 by using the CVD method or the like. As to the n-type region 20 and the p-type region 30, respectively.
(Arsenic) and B (boron) are doped. Then WSi
An N layer and a W layer are deposited by sputtering or the like, and a silicon nitride film is further deposited by LP-CVD.

Next, the silicon nitride film is etched by using the photolithography technique. Using the silicon nitride film 368 after this etching as a mask, the W layer, WSiN
The layer and the polycrystalline silicon layer are etched in this order. Thereby, the polycrystalline silicon layer 362, the WSiN layer 364,
A W layer 366 and a silicon nitride film 368 are formed.

After that, the semiconductor device 300 is manufactured in the same manner as the method of manufacturing the semiconductor device 200.

[0068]

According to the complementary semiconductor device and the method of manufacturing the complementary semiconductor device according to the present invention, a relatively shallow and high-concentration p-type source and drain layer and an n-type source and drain layer are formed on the same substrate. It became possible to form selectively.

According to the method of manufacturing the complementary semiconductor device of the present invention, the source and drain regions are formed by removing the portions of the semiconductor substrate where the n-type and p-type source and drain layers are formed. It Therefore, the depths of the source and drain layers from the surface of the semiconductor substrate can be substantially determined by the depths of the source and drain regions. The activation rates of both the p-type source and drain layers and the n-type source and drain layers selectively formed on the same substrate by the complementary semiconductor device and the method of manufacturing the complementary semiconductor device according to the present invention. Can be increased more than before.

[Brief description of drawings]

FIG. 1 is an enlarged cross-sectional view of a semiconductor substrate showing a method of manufacturing a complementary semiconductor device according to a first embodiment of the present invention in process order.

FIG. 2 is an enlarged cross-sectional view of a semiconductor substrate showing a method of manufacturing the complementary semiconductor device according to the first embodiment of the present invention in process order.

FIG. 3 is an enlarged cross-sectional view of the semiconductor substrate showing the method of manufacturing the complementary semiconductor device according to the first embodiment of the present invention in the order of steps.

FIG. 4 is an enlarged cross-sectional view of a semiconductor substrate showing a method of manufacturing the complementary semiconductor device according to the first embodiment of the present invention in the order of steps.

FIG. 5 is an enlarged cross-sectional view of the semiconductor substrate showing the method of manufacturing the complementary semiconductor device according to the first embodiment of the invention in the order of steps.

FIG. 6 is an enlarged cross-sectional view of the semiconductor substrate showing the method of manufacturing the complementary semiconductor device according to the first embodiment of the present invention in the order of steps.

FIG. 7 is an enlarged cross-sectional view of the semiconductor substrate showing the method of manufacturing the complementary semiconductor device according to the first embodiment of the present invention in the order of steps.

FIG. 8 is an enlarged cross-sectional view of the semiconductor substrate showing the method of manufacturing the complementary semiconductor device according to the first embodiment of the invention in the order of steps.

FIG. 9 is an enlarged cross-sectional view of the semiconductor substrate showing the method of manufacturing the complementary semiconductor device according to the first embodiment of the invention in the order of steps.

FIG. 10 is an enlarged cross-sectional view of the semiconductor substrate showing the method of manufacturing the complementary semiconductor device according to the first embodiment of the present invention in process order.

FIG. 11 is an enlarged cross-sectional view of the semiconductor substrate showing the method of manufacturing the complementary semiconductor device according to the first embodiment of the present invention in process order.

FIG. 12 is a schematic cross-sectional view of a semiconductor device 200 manufactured by the method for manufacturing a complementary semiconductor device according to the first embodiment.

FIG. 13 is a schematic cross-sectional view of a semiconductor device 300 according to another embodiment of the present invention.

[Explanation of symbols]

200, 300 Semiconductor device 10 Semiconductor substrate 20 n-type region 30 p-type region 40 element isolation part 50 Gate insulation film 60 gate electrode 70 Silicon oxide film 80 Side wall protector 90 Source and drain regions 100, 105 mask layer 110 photoresist 120 Source and drain buried layer 130 Source and drain buried layer 220 p-type transistor 230 n-type transistor 360 gate electrode

Claims (11)

[Claims] 1. A first gate insulating film formed on a second conductivity type semiconductor region of a surface of a semiconductor substrate on which a first conductivity type semiconductor region and a second conductivity type semiconductor region are formed. A first gate electrode formed on the first gate insulating film, and a first conductivity type source layer formed of an epitaxial layer in the second conductivity type semiconductor region on both sides of the first gate electrode A first transistor including a drain layer and a second gate insulating film formed on the semiconductor region of the first conductivity type on the surface of the semiconductor substrate; and on the second gate insulating film. A second transistor including a formed second gate electrode, and a second conductivity type source layer and a drain layer made of an epitaxial layer in the first conductivity type semiconductor region on both sides of the second gate electrode. Complementary semiconductor device with . 2. The first-conductivity-type source layer and the second-conductivity-type source layer are semiconductor layers made of single crystals made of different materials, and the first-conductivity-type drain layer and the second-conductivity-type semiconductor layer. 2. The complementary semiconductor device according to claim 1, wherein the conductive drain layers are also semiconductor layers made of single crystals made of different materials. 3. The source and drain layers of the first conductivity type and the source and drain layers of the second conductivity type are Si (silicon), Ge (germanium) or C.
The complementary semiconductor device according to claim 1, which is a semiconductor containing at least one of (carbon). 4. The first-conductivity-type source and drain layers are n-type source- and drain-layers containing As (arsenic) in SiGeC crystals, and the second-conductivity-type source and drain-layers. 4. The complementary semiconductor device according to claim 2, wherein the drain layer is a p-type source layer and a drain layer containing B (boron) or its homologous element in SiGe crystal. 5. The source and drain layers of the first conductivity type are n-type source and drain layers containing P (phosphorus) in SiGe or SiGeC crystal, and the source of the second conductivity type. 4. The complementary semiconductor device according to claim 1, wherein the layer and the drain layer are a p-type source layer and a drain layer containing B or a homologous element thereof in SiGe crystal. 6. The depth of the source and drain layers of the first conductivity type and the depth of the source and drain layers of the second conductivity type are 40 nm or less, and the source of the first conductivity type is used. The impurity concentration in each of the layer and the drain layer and the impurity concentration in each of the second-conductivity-type source layer and the drain layer are both 1 × 10 ¹⁹ cm ⁻³ or more. 6. The complementary semiconductor device according to any one of 5 above. 7. A step of forming a semiconductor region of a first conductivity type and a semiconductor region of a second conductivity type on a surface of a semiconductor substrate; a step of forming a gate insulating film on the surface of the semiconductor substrate; A step of forming a gate electrode on the insulating film; an etching step of etching a surface of the semiconductor substrate on both sides of the gate electrode to form a source / drain layer forming region for forming a source layer and a drain layer; A first source / drain layer forming step of selectively epitaxially growing a semiconductor of the first conductivity type in the source / drain layer formation region of the semiconductor region of the second conductivity type; A second source for selectively epitaxially growing a second conductivity type semiconductor in the source / drain layer formation region Method of manufacturing a complementary semiconductor device including a drain layer formed step. 8. The step of forming the first source / drain layer comprises forming the source / drain layer in the semiconductor region of the first conductivity type.
There is a first protective film forming step of forming a first protective film on the surface of the drain layer forming region, and the source / source in the semiconductor region of the second conductivity type in which the first protective film is not formed. In the drain layer forming region, the first conductive type semiconductor is selectively epitaxially grown, and in the second source / drain layer forming step, the first protective film is removed to form the second conductive type semiconductor region. A second protective film forming step of forming a second protective film on the surface of a certain source / drain layer forming region, wherein the first conductive type semiconductor region in which the second protective film is not formed; 8. The method of manufacturing a complementary semiconductor device according to claim 7, wherein the second conductivity type semiconductor is selectively epitaxially grown in a certain source / drain layer formation region. 9. The first conductivity type semiconductor and the second conductivity type semiconductor are semiconductors containing at least one of Si (silicon), Ge (germanium), and C (carbon). 9. The method for manufacturing a complementary semiconductor device according to claim 7, 10. The first-conductivity-type semiconductor is an n-type semiconductor containing As (arsenic) in a SiGeC crystal, and the second-conductivity-type semiconductor is B (boron) in a SiGe crystal. Or a p-type semiconductor containing a homologous element thereof, the method for manufacturing a complementary semiconductor device according to claim 9. 11. The first conductivity type semiconductor is an n-type semiconductor containing P (phosphorus) in a SiGe or SiGeC crystal, and the second conductivity type semiconductor is a BGe in a SiGe crystal. 10. The method of manufacturing a complementary semiconductor device according to claim 9, wherein the semiconductor device is a p-type semiconductor containing the same family element.