JP2003242044A - Microcomputer circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a microcomputer circuit which can prevent a program from being in an infeasible state even with troubles in the initial processing by solving problem that, if any troubles occur in the initial processing to transfer an application program to a RAM from a flash memory in the initial processing of the program, all subsequent programs are not executed and the operation is stopped. <P>SOLUTION: The microcomputer circuit is provided with a means which performs the two-side mounting of the flash memory for program storage on the microcomputer circuit in a control device to store the program in both memories, starts the microcomputer by the program stored in one flash memory, and monitors whether or not the initial processing procedure is normally advanced. If any trouble occurs in the initial processing, a CPU is reset by the means, and the microcomputer is forcibly re-started by the program stored in the other flash memory. <P>COPYRIGHT: (C)2003,JPO

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program operation backup of a microcomputer circuit. In the prior art, a flash memory for storing a program is mounted on a microcomputer circuit in a control device on two sides or twice or more of a program capacity, and a program is written in each flash memory area. Backed up. Here, a flash memory is a memory that can electrically write and erase data and that can retain data contents even when the power is turned off. Since the writing speed is slower than that of a random access memory (hereinafter abbreviated as RAM), it is mainly used for storing programs and data. The flash memory to be accessed when the initial processing program is executed after the circuit reset is determined. In the initial processing, the program stored in the flash memory is transferred to the RAM for program execution and RA
A program is executed on a central processing unit (hereinafter referred to as a CP).
(Abbreviated as U) to select a flash memory or a flash memory area to be accessed, and to cope with remote program rewriting such as remote maintenance. In the conventional circuit configuration, the initial processing
The program stored in the program storage flash memory is transferred to the RAM, and the application program is executed on the program execution RAM. When the application program is running, the operation is monitored.However, the operation is not monitored for the initial processing program.If there is a failure such as a malfunction of the flash memory itself during the operation of the initial processing program, However, there is a problem that the subsequent initial processing program and application program are not executed and the operation is stopped. [0003] In the above-mentioned prior art,
Although the program was backed up, the flash memory to be accessed after reset was determined.If a failure occurred in the initial process of transferring the program from the flash memory to the random access memory in the program stored in the flash memory, All subsequent programs are not executed and the operation stops. An object of the present invention is to prevent a program from falling into an execution suspended state even when a failure occurs during the initial processing. According to the present invention, in order to achieve the above object, two flash memories for storing a program are mounted on a microcomputer circuit in a control device, and a program is stored in both flash memories. The state of which of the two flash memories is selected is C
The data can be read by the PU, and the flash memory select information is loaded into the CPU. A means is provided for monitoring whether or not the processing procedure of the initial processing program is proceeding normally. If a failure occurs in the initial processing, the means resets the CPU and forcibly loads the other flash memory. Restart with the stored program. After resetting, the CPU identifies which flash memory is being accessed, compares it with the state before and after the reset, and if a different flash memory is selected, recognizes that a failure has occurred in the initial processing, and Failure information is stored as logging information so that it can be read later. An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. FIG. 1 is a block diagram showing the overall configuration of the present invention. 1 is a CPU, 2 is a flash memory A, 3 is a flash memory B, 4 is a random access memory SDRAM, 5 is a pulse monitor, 6 is an error counter, 7 is a flash memory selector, 8 is a flash memory select status signal, 9 is a flash memory change signal A for switching the flash memory when a program failure is detected, 10 is a flash memory select signal, 11 is a flash memory A select signal, 12
Is a flash memory B select signal, 13 is an SDRAM
A select signal, 14 is a power-on reset signal, 15 is a reset signal for the CPU 1 and the error counter 6, 16 is a system bus signal which is a data and address bus, 1
Reference numeral 7 denotes a flash memory change signal B for designating the flash memory A or B from the CPU during remote maintenance. FIG. 2 shows an embodiment of the memory arrangement according to the present invention, which is an example in which the memory is arranged in the memory space of the CPU 1. The flash memory A2 and the flash memory B3 are arranged on the same space area. The insides of the flash memory A2 and the flash memory B3 have the same address, and are composed of an initial processing program, an application program, and an unused area. The initial processing program includes an operating system and a loader for transferring and loading the program from the flash memory to the SDRAM. The application program is an execution program for operating the control device. In operation, when power is first turned on, the flash memory selector 7 and the error counter 6 are reset by the power-on reset signal 14. By the reset,
The flash memory A select signal 11 output from the flash memory selector 7 is enabled, the flash memory B select signal 12 is disabled, and the flash memory A2 is selected. Further, the flash memory select status signal 8 notifies the CPU 1 that the flash memory A2 has been selected. C
PU1 reads the flash memory select status signal 8, recognizes that the flash memory A2 has been selected, and stores select information. Then, the initial processing program of the flash memory A2 operates to transfer and load the application program in the flash memory A2 to the SDRAM 4. When the loading is completed, the initial processing program on the flash memory A2 and the application program loaded on the SDRAM 4 are combined to start operation. In the initial processing program operation, the watchdog timer in the pulse monitoring unit 5 used in the application program operation is used, and a pulse for releasing the watchdog timer is periodically transmitted from the CPU 1 to the pulse monitoring unit 5, so that the initial processing is performed. It monitors whether the processing operation is proceeding normally in the program.
If the watchdog timer release pulse is periodically C
When the signal is not output from the PU 1 to the pulse monitoring unit 5, the pulse monitoring unit 5 outputs a reset signal 15 as an error output. The reset signal 15 is output to the CPU 1 and the error counter 6. The CPU 1 is reset by the reset signal 15, and the error counter 6 counts the reset signal 15. When the error counter 6 receives a reset signal 15 indicating that a predetermined number of errors have occurred, the error counter 6 sends a flash memory select change signal A9 to the flash memory selector 7 and
The contents of the error counter 6 are cleared. Upon receiving the flash memory select change signal A9, the flash memory selector 7 disables the flash memory A select signal 11 sent to the flash memory A2, enables the flash memory B select signal 12, and sets the flash memory select status. The signal 8 notifies the CPU 1 that the flash memory B3 has been selected. After the reset, the CPU 1 is restarted by the program stored in the flash memory B3. After the completion of the initial processing, the flash memory select status signal 8 is read and compared with the flash memory select information stored before the reset to identify that a flash memory different from that before the reset has been selected. Is recognized, and the failure status is recorded and stored in, for example, a logging information area of the SDRAM so that it can be read out later. According to the present invention, even if a failure occurs during the operation of the initial processing program, the program can be restarted by the backed-up program so that normal operation can be performed.
It is possible to recognize the situation in which a failure has occurred during the operation of the initial processing program, save the situation information, read out the failure situation later, and use it for failure history management and the like.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the overall configuration of the present invention. FIG. 2 is an embodiment of a memory arrangement of the present invention. [Description of References] 1: CPU, 2: Flash memory A, 3: Flash Memory B, 4: SDRAM, 5: Pulse monitoring unit, 6: Error counter, 7: Flash memory selector, 8: Flash memory select status signal, 9: Flash memory change signal A, 10: Flash memory select signal, 11: Flash Memory A select signal, 1
2: Flash memory B select signal, 13: SDRA
M select signal, 14: power-on reset signal, 1
5: reset signal, 16: system bus signal, 17: flash memory change signal B

Claims (1)

Claims 1. A microcomputer circuit including a central processing unit, a program storage memory, and a program execution memory, wherein a flash memory storing a program is stored on two or more surfaces or twice the program capacity. A flash memory having a capacity equal to or greater than the program capacity, a random access memory having a capacity equal to or greater than the program capacity as a program execution memory, and transferring a program stored in one flash memory to the random access memory; In the microcomputer circuit for executing the program and transferring the program from the other flash memory to the random access memory when the program operation fails, and operating the program, the random access memory is read from the one flash memory. Means for monitoring that the initial processing procedure does not proceed according to a predetermined flow at the time of initial processing for transferring the program to the memory, resetting the central processing unit by the means, and A microcomputer circuit comprising means for transferring a program back to a computer and backing up a program operation.