JP2003234421A - Nonvolatile semiconductor memory device and method of manufacturing the same - Google Patents

Abstract

[PROBLEMS] To provide a nonvolatile semiconductor memory device in which the resistance of a selected word line is reduced and the chip area is reduced, and a method of manufacturing the same. SOLUTION: A selected word line 21 having an upper gate electrode 5, a lower gate electrode 3, an inter-electrode insulating film 4 located between the gate electrodes 5, 3 and wherein the upper gate electrode 5 is partially removed. And an inter-electrode insulating film 4 located between the upper gate electrode 5, the lower gate electrode 3, and the gate electrodes 5, 3.
And a contact 12 disposed in a region where the upper gate electrode 5 is partially removed so as to be in electrical contact with the lower gate electrode 3.
And a contact 12 arranged so as to be in electrical contact with the upper gate electrode 5. The lower gate electrode 3 is made of polycrystalline silicon or amorphous silicon, A silicide layer 11 is provided on at least a part of the side surface of the electrode 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device having a select transistor and a memory transistor, and a method for manufacturing the same.

[0002]

2. Description of the Related Art A non-volatile semiconductor memory device having a select transistor and a memory transistor will be described. Such a non-volatile semiconductor memory device is disclosed in, for example, Japanese Patent Laid-Open No. 11-177068.

FIG. 9A is a sectional view showing the structure of a conventional nonvolatile semiconductor memory device. A tunnel film 102 is formed on a silicon substrate 101, and a select word line 121 which is a constituent element of a select transistor is formed on the tunnel film 102.
And a memory cell word line 122 which is a constituent element of the memory transistor. Selected word line 121 and memory cell word line 122
Are the upper gate electrode 105 and the lower gate electrode 1 respectively.
03 and the interelectrode insulating film 104, the interelectrode insulating film 1
04 is an upper gate electrode 105 and a lower gate electrode 103
Located between.

First and second impurity diffusion layers 107 and 109 are formed on the silicon substrate 101 on both sides of the selected word line 121 and the memory cell word line 122. A sidewall insulating film 108 is provided on the sidewalls of the selected word line 121 and the memory cell word line 122, and the upper portions of the selected word line 121 and the memory cell word line 122 and the impurity diffusion layers 107 and 109.
The surface is covered with the silicide layer 111.

Further, FIG. 9B is a sectional view taken along the line AA 'in FIG. 9A.
FIG. 6 is a cross-sectional view showing a contact 112 of the selected word line 121 connected to a wiring layer (not shown).
The contact 112 is formed on the silicon substrate 101 where the element isolation insulating film 106, which is an insulator, is formed. As shown in FIG. 9B, a part of the upper gate electrode 105 and the inter-electrode insulating film 104 is opened, a silicide layer 111 is formed on the lower gate electrode 103, and connected to the contact 112. .

[0006]

Although not shown,
In order to connect the memory cell word line 122 to the wiring layer, the contact 112 is placed on the upper gate electrode 105. As shown in FIG. 9A, the upper gate electrode 105
Since the silicide layer 111 having a low resistance is formed in the memory cell word line 122, the resistance of the memory cell word line 122 can be sufficiently reduced.

On the other hand, in the case of the selected word line 121,
The contact 112 is placed on the lower gate electrode 103. As shown in FIG. 9B, in the lower gate electrode 103, the silicide layer 111 having a low resistance is formed only in the portion where the contact 112 is formed, and the other portions are all insulated. Surrounded by membranes. Therefore, the resistance is not lowered. Therefore, the selected word line 121 is the memory cell word line 122.
It has an extremely large resistance value compared with. To overcome the delays that result, it is necessary to form a large number of backing contacts. The number of backing contacts is limited by the resistance of the selected word line 121, and actually requires a large number. Therefore, there is a problem that the chip area of the nonvolatile semiconductor memory device increases.

The present invention has been made in view of the above circumstances, realizes a low resistance of a selected word line, and
An object of the present invention is to provide a non-volatile semiconductor memory device having a reduced chip area and a manufacturing method thereof.

[0009]

A nonvolatile semiconductor memory device according to the present invention includes a first upper gate electrode, a first lower gate electrode, the first upper gate electrode, and the first lower gate electrode. A first inter-electrode insulating film located,
And a selected word line in which the first upper gate electrode is partially removed, a second upper gate electrode, a second lower gate electrode, the second upper gate electrode, and the second lower gate electrode. A memory cell word line having a second inter-electrode insulating film located between the memory cell word line and a region where the first upper gate electrode is partially removed is electrically connected to the first lower gate electrode. First arranged as
And a second contact arranged so as to make electrical contact with the second upper gate electrode, wherein the first lower gate electrode is made of polycrystalline silicon. Alternatively, it is formed of amorphous silicon and has a silicide layer on at least a part of a side surface of the first lower gate electrode. As a result, the selected word line is provided with the silicide layer having a low resistance, so that the resistance is significantly reduced and the number of backing contacts can be reduced. Therefore, the area of the chip can be reduced.

Further, preferably, an element isolation insulating film is formed at a predetermined position on the semiconductor substrate where the selected word line and the memory cell word line are formed, and at least one of the selected word lines is located between the selected word lines. The element isolation insulating film is opened, and an impurity diffusion layer is provided on the exposed surface of the silicon substrate. As a result, the source line is formed by only the diffusion layer in a self-aligned manner,
The distance between the selected word lines or the memory cell word lines can be set to the minimum, and the chip area can be reduced.

Further, the silicide layer may be present only on one of the side surfaces of the selected word line.

A method of manufacturing a nonvolatile semiconductor memory device according to the present invention comprises a step of forming an element isolation insulating film on a part of a semiconductor substrate, a tunnel insulating film, a lower gate electrode, an interelectrode insulating film and an upper gate electrode. Stacking to form a selected word line and a memory cell word line; removing at least a portion of the upper gate electrode of the selected word line; and sidewalls of the selected word line and the memory cell word line. Forming a sidewall insulating film on the sidewall of the selected word line, etching the sidewall insulating film of the selected word line until a part of the sidewall of the lower gate electrode of the selected word line is exposed, and lowering the sidewall of the selected word line. And a step of silicidizing at least a part of the gate electrode. Thereby, the selected word line including the silicide layer having a low resistance can be formed. Therefore, the number of backing contacts of the nonvolatile semiconductor memory device can be reduced and the chip area can be reduced.

Further, preferably, in the step of etching back the side wall insulating film of the selected word line until a part of the side wall of the lower gate electrode of the selected word line is exposed, at the same time, the device isolation insulating film is formed. At least a part of the semiconductor substrate is removed to expose the semiconductor substrate. Thereby, the source line is formed in a self-aligned manner. Therefore, the distance between the selected word lines or the memory cell word lines can be set to the minimum without increasing the manufacturing process, and the chip area can be further reduced.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A nonvolatile semiconductor memory device according to a first embodiment of the present invention and a method for manufacturing the same will be described with reference to the drawings.

1 and 2 are sectional views showing a manufacturing process of a nonvolatile semiconductor memory device. Note that FIG. 2 corresponds to FIG.
The subsequent process of is shown. In addition, FIG. 3 and FIG.
It is a cross-sectional view showing a manufacturing process on the element isolation insulating film,
That is, it is a cross-sectional view of an element isolation region that forms a contact that electrically connects the selected word line 21 and the memory cell word line 22 to the wiring layer. Note that FIG. 4 is a process subsequent to FIG.

First, as shown in FIG. 3A, an element isolation insulating film 6 is formed on a silicon substrate 1 which is a semiconductor substrate in an element isolation region. Next, FIG. 1A and FIG.
As shown in (a), the selected word line 21 and the memory cell word line 22 are formed on the silicon substrate 1 and the element isolation insulating film 6. Specifically, first, the tunnel film 2 is formed to have a thickness of 10 nm. An n-type polycrystalline silicon film is deposited on the tunnel film 2 in a thickness of 100 to 300 nm to form a lower gate electrode 3. A laminated film of a silicon oxide film, a silicon nitride film, and a silicon oxide film is deposited on the lower gate electrode 3 in a thickness of 10 to 30 nm in terms of a silicon oxide film to form an interelectrode insulating film 4. An n-type polycrystalline silicon film is deposited on the inter-electrode insulating film 4 to a thickness of 100 to 300 nm to form an upper gate electrode 5. After that, using the photoresist as a mask, patterning is performed at a predetermined position, and the selected word line 2
1 and the memory cell word line 22 are formed. The upper gate electrode 5 and the lower gate electrode 3 may be formed using amorphous silicon.

Further, as shown in FIG. 3B, the upper gate electrode 5 and the interelectrode insulating film 4 of the selected word line 21 are removed.

Next, as shown in FIG. 1B, a first impurity diffusion layer 7 is formed on the silicon substrate 1, for example, P ⁺ : 1.
It is formed under the conditions of 0 to 50 keV and 5 × 10 ^{−12 to} 5 × 10 ⁻¹⁵ cm ⁻² .

Next, a silicon oxide film is formed on the surface by 100 to 2
After depositing 00 nm, the entire surface is etched back to form the sidewall insulating film 8 on the sidewalls of the selected word line 21 and the memory cell word line 22, as shown in FIGS. 1C and 3C.

Next, as shown in FIG. 1D, a second impurity diffusion layer 9 is formed on the silicon substrate 1, for example, As ⁺ : 10.
˜50 keV, 1 × 10 ⁻¹⁴ to 1 × 10 ⁻¹⁶ cm ⁻² .

Next, as shown in FIGS. 2E and 3D, a photoresist 10 is formed by opening so that the selected word line 21 is exposed. Thus, as shown in FIG. 2E, the sidewall insulating film 8 is etched back until at least a part of the upper gate electrode 5 and the lower gate electrode 3 of the selected word line 21 is exposed. Also,
On the element isolation insulating film 6, as shown in FIG. 3D, the side surface of the lower gate electrode 3 of the selected word line 21 is exposed, and part of the element isolation insulating film 6 is removed by etching.

Next, the photoresist 10 is removed, a refractory metal such as titanium or cobalt is deposited on the entire surface, and a heat treatment is performed, as shown in FIGS. 2 (f) and 4 (e). A silicide layer 11 is formed on the exposed portion of silicon. 2F, the silicide layer is not formed on the side surface of the interelectrode insulating film 4, but the silicide layer 11 is also formed on the side surface of the interelectrode insulating film 4 depending on the silicidation conditions. Upper gate electrode 5
There is also a case where the lower gate electrode 3 is completely short-circuited.

Finally, as shown in FIG. 4F, the contact 1 is formed on the lower gate electrode 3 of the selected word line 21 and the upper gate electrode 5 of the memory cell word line 22.
2 is formed to complete the nonvolatile semiconductor memory device. The contact 12 is for electrically connecting the selected word line 21 and the memory cell word line 22 to a wiring layer (not shown). At this time, although not shown, contacts are also formed on the drain and source diffusion layers.

According to the nonvolatile semiconductor memory device manufactured as described above, silicide is formed on the side surface of the lower gate electrode 3 of the selected word line 21 as shown in FIGS. 2 (f) and 4 (f). The layer 11 is formed. As a result, the resistance of the selected word line 21 is significantly reduced,
It is possible to reduce the number of backing contacts. Therefore, the chip area of the nonvolatile semiconductor memory device can be further reduced.

(Second Embodiment) A nonvolatile semiconductor memory device according to a second embodiment of the present invention and a method for manufacturing the same will be described with reference to the drawings.

5 and 6 are cross-sectional views showing the manufacturing process of the nonvolatile semiconductor memory device. Note that FIG. 6 corresponds to FIG.
The subsequent process of is shown. In addition, FIG. 7 and FIG.
It is a cross-sectional view showing a manufacturing process on the element isolation insulating film,
That is, it is a cross-sectional view of an element isolation region that forms a contact that electrically connects the selected word line 21 and the memory cell word line 22 to the wiring layer. Note that FIG. 8 is a process following on from FIG. 7.

First, as shown in FIG. 7A, the element isolation insulating film 6 is formed on the silicon substrate 1 which is a semiconductor substrate in the element isolation region. Next, FIG. 5 (a) and FIG.
As shown in (a), the selected word line 21 and the memory cell word line 22 are formed on the silicon substrate 1 and the element isolation insulating film 6. Specifically, first, the tunnel film 2 is formed to have a thickness of 10 nm. An n-type polycrystalline silicon film is deposited on the tunnel film 2 in a thickness of 100 to 300 nm to form a lower gate electrode 3. A laminated film of a silicon oxide film, a silicon nitride film, and a silicon oxide film is deposited on the lower gate electrode 3 in a thickness of 10 to 30 nm in terms of a silicon oxide film to form an interelectrode insulating film 4. An n-type polycrystalline silicon film is deposited on the inter-electrode insulating film 4 to a thickness of 100 to 300 nm to form an upper gate electrode 5. After that, using the photoresist as a mask, patterning is performed at a predetermined position, and the selected word line 2
1 and the memory cell word line 22 are formed. The upper gate electrode 5 and the lower gate electrode 3 may be formed using amorphous silicon.

Further, as shown in FIG. 7B, the upper gate electrode 5 and the interelectrode insulating film 4 of the selected word line 21 are removed.

Next, as shown in FIG. 5B, a first impurity diffusion layer 7 is formed on the silicon substrate 1, for example, P ⁺ :
It is formed under the conditions of 10 to 50 keV and 5 × 10 ^{−12 to} 5 × 10 ⁻¹⁵ cm ⁻² .

Next, 100 to 2 silicon oxide film is formed on the surface.
After being deposited to a thickness of 00 nm, the entire surface is etched back to form the sidewall insulating film 8 on the sidewalls of the selected word line 21 and the memory cell word line 22, as shown in FIGS. 5 (c) and 7 (c).

Next, as shown in FIGS. 5 (d) and 8 (d), the photoresist 10a is applied to the selected word line 21.
The opening is formed so that one side surface of is exposed. Thus, as shown in FIG. 5D, the sidewall insulating film 8 is etched back on each side of the selected word line 21 until at least a part of the upper gate electrode 5 and the lower gate electrode 3 is exposed. On the element isolation insulating film 6, as shown in FIG. 8D, one side surface of the lower gate electrode 3 of the selected word line 21 is exposed, and a part of the element isolation insulating film 6 is removed by etching. A part of the silicon substrate 1 is exposed.

Next, the photoresist 10a is removed,
As shown in FIGS. 6E and 8E, the second impurity diffusion layer 9 is formed, for example, with As ⁺ : 10 to 50 keV, 1 × 10.
^It is formed on the silicon substrate 1 under the condition of ^-14 to 1 x 10 ^-16 cm ^-2 . As shown in FIG. 8E, the second impurity diffusion layer 9 is also formed at the location where the element isolation insulating film 6 is formed, and the source line formed of only the diffusion layer is formed in a self-aligned manner.

Next, a refractory metal such as titanium or cobalt is deposited on the entire surface and a heat treatment is performed, so that FIG.
Then, as shown in FIG. 8F, the silicide layer 11 is formed in the portion where the silicon is exposed. Note that FIG.
In (f), the silicide layer is not formed on the side surface of the inter-electrode insulating film 4, but the silicide layer 11 is also formed on the side surface of the inter-electrode insulating film 4 depending on the silicidation conditions. There is also a case where the lower gate electrode 3 is completely short-circuited.

Finally, as shown in FIG. 8G, the contact 12 is formed on the selected word line 21 and the memory cell word line 22 to complete the nonvolatile semiconductor memory device. The contact 12 is for electrically connecting the selected word line 21 and the memory cell word line 22 to a wiring layer (not shown). At this time, although not shown, a contact is formed on the drain diffusion layer, but no contact is formed on the source diffusion layer. This is because the source of each element is short-circuited by the second impurity diffusion layer 9 formed at the element isolation insulating film 6 in the step of FIG. 8E, and the source line is completed in a self-aligned manner. Is. Thereby, the manufacturing process is not increased.

According to the nonvolatile semiconductor memory device manufactured as described above, the silicide is formed on the side surface of the lower gate electrode 3 of the selected word line 21 as shown in FIGS. 6 (f) and 8 (g). The layer 11 is formed. As a result, the resistance of the selected word line 21 is significantly reduced,
It is possible to reduce the number of backing contacts. Therefore, the chip area of the nonvolatile semiconductor memory device can be further reduced.

Further, since the source line is formed of only the diffusion layer in a self-aligning manner, it becomes possible to set the distance between the selected word lines 21 or the memory cell word lines 22 to the minimum, and the nonvolatile semiconductor memory. The chip area of the device can be further reduced.

[0037]

According to the nonvolatile semiconductor memory device of the present invention, the resistance of the selected word line is significantly reduced and the number of backing contacts can be reduced, so that the chip area can be reduced.

Further, according to the method of manufacturing the nonvolatile semiconductor memory device of the present invention, the source line formed of only the diffusion layer is formed in a self-aligning manner without increasing the number of manufacturing steps. The chip area of the device can be reduced.

[Brief description of drawings]

FIG. 1 is a sectional view showing a manufacturing process of a nonvolatile semiconductor memory device according to a first exemplary embodiment of the present invention.

2 is a sectional view showing a continuation of the manufacturing process of FIG. 1. FIG.

FIG. 3 is a sectional view showing a manufacturing process of an element isolation region of the nonvolatile semiconductor memory device according to the first exemplary embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a continuation of the manufacturing process of FIG.

FIG. 5 is a sectional view showing a manufacturing process of the nonvolatile semiconductor memory device according to the second embodiment of the present invention.

6 is a sectional view showing the continuation of the manufacturing process of FIG.

FIG. 7 is a sectional view showing a manufacturing process of an element isolation region of a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

8 is a cross-sectional view showing the continuation of the manufacturing process of FIG.

FIG. 9 is a sectional view showing a configuration of a conventional nonvolatile semiconductor memory device.

[Explanation of symbols]

1, 101 Silicon substrate 2,102 tunnel film 3, 103 Lower gate electrode 4, 104 Inter-electrode insulating film 5,105 Upper gate electrode 6,106 Element isolation insulating film 7, 107 first impurity diffusion layer 8, 108 Side wall insulating film 9, 109 second impurity diffusion layer 10, 10a photoresist 11,111 Silicide layer 12,112 contacts 21,121 Selected word line 22, 122 memory cell word line

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5F083 EP02 EP23 EP32 EP34 GA02                       GA09 JA33 JA35 JA39 JA53                       KA02 KA14 PR43 PR44 PR45                       PR53 PR54 PR55                 5F101 BA01 BB05 BD22 BH14 BH19                       BH21

Claims (5)

[Claims] 1. A first upper gate electrode, a first lower gate electrode, and a first inter-electrode insulating film located between the first upper gate electrode and the first lower gate electrode, And a selected word line in which the first upper gate electrode is partially removed, a second upper gate electrode, a second lower gate electrode, the second upper gate electrode, and the second lower gate electrode. A memory cell word line having a second inter-electrode insulating film located between the memory cell word line and the first lower gate electrode is electrically contacted in a region where the first upper gate electrode is partially removed. A non-volatile semiconductor memory device having a first contact arranged in such a manner and a second contact arranged so as to be in electrical contact with the second upper gate electrode, wherein the first lower portion The gate electrode is polycrystalline It is formed by silicon or amorphous silicon, a non-volatile semiconductor memory device characterized by comprising a silicide layer on at least a portion of the side surface of the first lower gate electrode. 2. An element isolation insulating film is formed at a predetermined location on the semiconductor substrate where the selected word line and the memory cell word line are formed, and at least a part of the space between the selected word lines is formed. The element isolation insulating film is opened, and an impurity diffusion layer is provided on the exposed surface of the semiconductor substrate.
The non-volatile semiconductor memory device described in 1. 3. The non-volatile semiconductor memory device according to claim 1, wherein the silicide layer is present only on one of the side surfaces of the selected word line. 4. A step of forming an element isolation insulating film on a part of a semiconductor substrate, and a tunnel insulating film, a lower gate electrode, an interelectrode insulating film and an upper gate electrode are stacked to form a selected word line and a memory cell. Forming a word line; removing at least a portion of the upper gate electrode of the selected word line; forming a sidewall insulating film on sidewalls of the selected word line and the memory cell word line; Etching back the sidewall insulating film of the selected word line until a portion of the sidewall of the lower gate electrode of the selected word line is exposed; and silicifying at least a portion of the lower gate electrode of the selected word line. A method for manufacturing a nonvolatile semiconductor memory device, comprising: 5. The step of etching back the side wall insulating film of the selected word line until a part of the side wall of the lower gate electrode of the selected word line is exposed, and at the same time, at least a part of the element isolation insulating film. 5. The method for manufacturing a nonvolatile semiconductor memory device according to claim 4, wherein the semiconductor substrate is exposed by removing.