JP2003229580A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a small-sized and high-speed semiconductor device having a display part, for which defects associated with the mounting of a substrate of an IC chip or the like are reduced. <P>SOLUTION: On the substrate having an insulating surface, a semiconductor display part and other circuit blocks are integrally formed by using a TFT manufacturing process realizing high mobility. More specifically, the crystallization process of a semiconductor active layer using a continuous oscillation laser is used. Further, by selectively performing the crystallization process by the continuous oscillation laser only to the circuit block requiring a high- speed operation, high production efficiency is realized. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a display section. In particular, the present invention relates to a semiconductor device in which a thin film transistor is formed over a substrate having an insulating surface.

[0002]

2. Description of the Related Art In recent years, semiconductor devices, in particular, electronic equipment having a semiconductor display section have been remarkably developed, and its application examples include game machines, notebook computers, portable equipment such as mobile phones, liquid crystal televisions, liquid crystal displays, and ELs. There are various displays, etc. The semiconductor display unit can be made lighter and thinner than conventional CRTs and consumes less power.

As a conventional semiconductor display part, a passive matrix type semiconductor display part having pixel regions in which stripe electrodes are formed so as to intersect each other with a liquid crystal layer or a light emitting layer interposed therebetween, and a thin film transistor (TF).
An active matrix type semiconductor display section having a pixel region in which T) is arranged in a matrix is known.

In recent years, the technology for forming a TFT on a substrate has advanced, and application development of an active matrix type semiconductor display section has been advanced. In particular, TF using a polysilicon film
T has a higher electric field effect mobility (also referred to as mobility) than a conventional TFT using an amorphous silicon film, and pixel control that was conventionally performed by a drive circuit outside the substrate is formed on the same substrate as the pixel. It is possible to do with the drive circuit.

Next, the configuration of a conventional electronic device having a semiconductor display portion will be described. FIG. 21 is a simplified block diagram of a portion related to image display.

In FIG. 21, a semiconductor device 301 is a device for capturing or creating image data, processing the image data and converting the format, and displaying the image. As the semiconductor device 301, for example, a game machine, a video camera, a car navigation, a personal computer, etc. can be considered.

In the semiconductor device 301, the pixel region 31
9, scanning line drive circuit 318 and signal line drive circuit 317
Although the semiconductor display unit 302 configured by is integrally formed on a substrate having an insulating surface, other circuit blocks are formed on different silicon substrates and mounted as an IC chip. Some circuit blocks may be formed on the same silicon substrate.

The semiconductor device 301 includes an input terminal 311, a first control circuit 312, a second control circuit 313 and a CPU 3.
14, the first memory 315, the second memory 316, and the semiconductor display unit 302. Input terminal 31
From 1, the data that is the basis of the image data is input according to each electronic device. For example, in a broadcast receiver, it is input data from an antenna, and in a video camera, it is C
This is the input data from the CD. It may be input data from a DV tape or a memory card. Input terminal 311
The data input from is converted into an image signal by the first control circuit 312. In the first control circuit 312,
Decoding processing of image data compressed and coded according to the MPEG standard, tape format, etc., and image signal processing such as image interpolation and resizing are performed. First control circuit 31
The image signal output from the device 2 or the image signal created or processed by the CPU 314 is input to the second control circuit 313 and converted into a format (for example, a scanning format) suitable for the semiconductor display unit 302. Second control circuit 3
From 13, a format-converted image signal and a control signal are output.

The CPU 314 includes a first control circuit 312,
The signal processing in the second control circuit 313 and other interface circuits is efficiently controlled. It also creates and processes image data. First memory 315
Is a memory area for storing the image data output from the first control circuit 312 and the image data output from the second control circuit 313, a work memory area for the control by the CPU, and the image data is created by the CPU. It is used as a work memory area, etc. First memory 3
DRAM or SRAM is used as 15. Second
The memory 316 is a memory area for storing color data and character data, which is necessary when the CPU 314 creates or processes image data, and includes a mask ROM and an E
It is composed of a PROM.

The semiconductor display section 302 includes the signal line driving circuit 3
17, the scanning line drive circuit 318, and the pixel region 319. The signal line drive circuit 317 is the second control circuit 3
13 receives an image signal and a control signal (clock signal, start pulse, etc.) from each other, and the scanning line driving circuit 318 receives a control signal (clock signal, start pulse, etc.) from the second control circuit 313, respectively. indicate.

Note that the electronic device having the semiconductor display portion may have various configurations other than the configuration shown in FIG. As the simplest configuration, a configuration having a semiconductor display section, an input / output terminal, and a simple control circuit is conceivable. For example, a liquid crystal display or an EL display can be considered. If the CPU load is too high with the architecture shown in FIG. 21, as in a high-performance game machine,
In some cases, a new image processing processor is provided to reduce the load on the CPU.

[0012]

In the electronic device having the conventional semiconductor display section described above, the circuit blocks other than the drive circuit are formed and mounted on a substrate different from the substrate on which the pixels are formed.

With the widespread use of portable electronic devices, miniaturization of electronic devices has become an important issue. In a semiconductor device having such a structure, a large number of IC chips are provided separately from the substrate on which pixels are formed. Since it is necessary to mount it, it is difficult to realize miniaturization. In particular, even if the circuit block in the IC chip can be made small, it is difficult to reduce the size of the entire device because the margin for mounting is large. On the other hand, if an attempt is made to reduce the mounting margin in order to reduce the size of the device, an advanced mounting technique is required, which causes problems in cost and reliability in the mounting portion. There is also the problem of wiring capacitance. That is, when mounting with an IC chip, there is a problem that it is difficult to perform high-speed operation because the load of wiring increases.

As one of the methods for solving such problems, it is expected that the circuit block is formed integrally with the semiconductor display section.

However, when forming a circuit block on a substrate having an insulating surface, the operating speed often becomes a problem. This is because a TFT formed on a substrate having an insulating surface such as a glass substrate has inferior mobility and threshold characteristics as compared with a transistor formed on a single crystal silicon substrate.

As a result, when a conventional semiconductor device is operated at a certain frequency, it operates in a semiconductor device in which a circuit block is mounted by an IC chip, but operates in a semiconductor device in which the circuit block is formed on a substrate having an insulating surface. It can happen that you don't.

The present invention has been made in view of these problems. It is an object of the present invention to provide an electronic device having a semiconductor display portion that can be downsized, reduce defects due to mounting of a substrate such as an IC chip, and realize high-speed operation.

[0018]

In order to solve the above problems, the present invention integrally forms a semiconductor display portion and other circuit blocks on a substrate having an insulating surface.

Further, in order to reduce the problem of operating speed when a circuit block is formed on a substrate having an insulating surface, a TFT manufacturing process which realizes high mobility is used.

As a TFT manufacturing process for realizing high mobility, an active layer is formed by irradiating a semiconductor film with an energy beam to form a melt zone and continuously scanning the melt zone in the channel direction for crystallization. Forming process is used. The details will be described in Examples, but specifically, this is performed using a continuous wave laser.

The circuit block composed of the TFTs thus manufactured has a high operating frequency because the mobility of each TFT is higher than that of the conventional circuit block using polysilicon as an active layer of the TFT. improves.

As a result, the display section and other circuit blocks can be integrally formed on the substrate having an insulating surface, and high-speed operation can be realized. In other words, the present invention makes it possible to put into practical use a circuit block that could not be put into practical use by forming it on a substrate having an insulating surface due to the problem of operating speed.

Further, according to the present invention, the throughput is improved as follows while maintaining such a high operating frequency.

As the continuous wave laser, YVO ₄ laser, Y
LF laser, YAG laser, etc. are known, but the current output is weak at about 10 W even if it is high. Therefore, in order to perform crystallization by irradiating the active layer with continuous wave laser light, it is necessary to significantly narrow down the laser light, and the beam width thereof is about 50 to 500 μm (typically 200 μm).

For example, a laser beam having a width of 200 μm is applied to the entire surface of a 600 mm × 720 mm glass substrate at a scanning speed of 50 cm.
When scanning at / sec, it takes 72 minutes per sheet.
Actually, it takes more time to change the scanning direction of the laser light or accelerate the laser light. That is, one faces the problem of low throughput.

The present invention is characterized in that the crystallization process by the continuous wave laser is selectively performed only on the circuit block that requires high-speed operation. As a result, the throughput of the crystallization process using the continuous wave laser is significantly improved.

For example, by suppressing the area irradiated with continuous wave laser light to 50% or less (preferably 30% or less) of the substrate area, the time required for the crystallization process by continuous wave laser is approximately 50% (preferably 30%). %Less than)
Can be reduced to

Further, in order to suppress the moving distance of the continuous wave laser beam or the substrate, it is preferable to dispose the circuit blocks that require high speed operation in the regions as close as possible. By doing so, the throughput of the crystallization process by the continuous wave laser is further improved.

Further, in order to improve the operating frequency of the circuit block, it is preferable to make the channel length direction of the TFT coincide with the scanning direction of the laser light. This is because in the crystallization process of the semiconductor film by the continuous wave laser, the highest mobility is obtained when the channel direction of the TFT and the scanning direction of the laser light with respect to the substrate are substantially parallel (preferably -30 ° to 30 °). Is obtained. The TFT thus manufactured has an active layer made of a polycrystalline semiconductor in which crystal grains extend in the channel direction. Further, this means that the crystal grain boundaries are formed substantially along the channel direction, so that the electrical characteristics of the active layer differ between the channel direction and the direction perpendicular thereto. That is, the active layer has electrical anisotropy in the channel direction.

Note that the semiconductor active layer included in the circuit block or the pixel region which is not subjected to the crystallization process by the continuous wave laser may be manufactured by a known manufacturing method.

Particularly, it is preferable to apply a crystallization process having a higher throughput than the crystallization process using the continuous wave laser.

In particular, the method of crystallizing a semiconductor film (thermal crystallization using a metal catalyst) disclosed in JP-A-7-183540 is preferable. In this case, in the region where the semiconductor film is crystallized by the continuous wave laser, a combined process of thermal crystallization using a metal catalyst and crystallization by the continuous wave laser is performed. In such a process, a TFT having a mobility equal to or higher than that of a case where only crystallization by a continuous wave laser is performed is manufactured.

A laser crystallization method using a pulse oscillation laser may be used for the semiconductor active layer in the region where the crystallization process by the continuous oscillation laser is not performed. Since a pulsed laser can achieve high output, it can emit a beam having a width of 100 mm or more and has high throughput. From the viewpoint of operating frequency and cost, the practitioner may freely combine known active layer manufacturing methods including these methods. In the TFT manufactured by such a known manufacturing method, unlike the crystallization process by the continuous wave laser, the crystallization process by the continuous wave laser does not have electrical anisotropy in the channel direction, or even if it has it. It has an active layer with weaker electrical anisotropy.

As described above, according to the present invention, the pixel region and the circuit block are formed on the same substrate, and the crystallization process by the continuous wave laser is selectively performed only on the circuit block that needs high-speed operation. It is possible to provide a semiconductor device that is small in size, reduces defects caused by mounting a substrate such as an IC chip, and has a high operating frequency and high throughput. In addition, a high operating speed can be realized from the viewpoint of wiring capacity.

The semiconductor device in the present invention refers to all devices that function by utilizing semiconductor characteristics, and has, for example, a semiconductor display device represented by a liquid crystal display device or a light emitting device, or a semiconductor display portion. Electronic equipment is included in its category. Note that the semiconductor display portion refers to a display portion in which an electrode or a thin film transistor is formed over a substrate having an insulating surface, for example, a liquid crystal display portion, a light-emitting display portion, or
The passive matrix display portion and the active matrix display portion are included in the category. Note that, in the obvious case, the semiconductor display unit is also simply referred to as a display unit.

The circuit block referred to in the present invention refers to a block of an electric circuit having a characteristic function composed of circuit elements such as a transistor, a capacitive element, and a resistive element, and examples thereof include a signal line driving circuit and a scanning line. Drive circuit, register, decoder, counter, frequency divider, memory, CPU,
Includes DSP in its category. In particular, in this specification, since the circuit block is formed on the substrate having an insulating surface, a thin film transistor (hereinafter referred to as TFT) is a main constituent element of the circuit block. A thin film transistor (TFT)
Refers to the entire transistor formed using SOI technology.

The structure of the present invention is shown below.

According to the present invention, the pixel region, the scanning line driving circuit, and the signal line driving circuit are provided on the same substrate,
A first TFT having a first active layer and a second TFT having a second active layer, wherein the first active layer irradiates the semiconductor film with an energy beam to form a melt zone, and the melt zone is used as a channel. The second active layer is formed by crystallizing by continuously scanning in a long direction, the second active layer is formed by crystallizing a semiconductor film by heat treatment, and the pixel region is formed by the second TFT. A semiconductor device is provided in which the scanning line drive circuit is configured by the second TFT, and the signal line drive circuit is configured by the first TFT.

According to the present invention, the pixel region, the scanning line driving circuit, and the signal line driving circuit are provided on the same substrate,
A first TFT having a first active layer and a second TFT having a second active layer, wherein the first active layer irradiates the semiconductor film with an energy beam to form a melt zone, and the melt zone is used as a channel. The second active layer is formed by crystallizing by continuously scanning in the long direction, wherein the second active layer is formed by adding a metal element to a semiconductor film and crystallizing by heat treatment. A semiconductor device is provided in which a pixel region is configured by the second TFT, the scanning line driving circuit is configured by the second TFT, and the signal line driving circuit is configured by the first TFT.

The energy beam may be continuous wave laser light.

According to the present invention, the pixel region, the scanning line driving circuit, and the signal line driving circuit are provided on the same substrate,
A first TFT having a first active layer and a second TFT having a second active layer, wherein the first active layer irradiates the semiconductor film with an energy beam to form a melt zone, and the melt zone is used as a channel. The second active layer is formed by crystallizing the semiconductor film by irradiating it with a pulsed energy beam, The pixel region is composed of the second TFT, the scanning line driving circuit is composed of the second TFT,
A semiconductor device is provided in which the signal line drive circuit is configured by the first TFT.

The energy beam may be pulsed laser light.

According to the present invention, the pixel region, the scanning line driving circuit, and the signal line driving circuit are provided on the same substrate,
A first TFT having a first active layer and a second TFT having a second active layer, wherein the first active layer is formed of a polycrystalline semiconductor in which crystal grains extend in the channel direction,
The second active layer is formed of a polycrystalline semiconductor whose crystal grains have no anisotropy in the channel direction, the pixel region is formed of the second TFT, and the scanning line driving circuit is formed of the second TFT. In addition, a semiconductor device is provided in which the signal line drive circuit includes the first TFT.

According to the present invention, the pixel region, the scanning line driving circuit, and the signal line driving circuit are provided on the same substrate,
A first TFT having a first active layer and a second TFT having a second active layer, wherein the first active layer is formed of a polycrystalline semiconductor in which crystal grains extend in the channel direction,
The second active layer is formed of a polycrystalline semiconductor whose crystal grain shape anisotropy in the channel direction is weaker than that of the first active layer, the pixel region is formed of the second TFT, and the scanning line driving circuit is formed. A semiconductor device is provided which is configured by the second TFT and the signal line drive circuit is configured by the first TFT.

According to the present invention, the pixel region, the scanning line driving circuit, and the signal line driving circuit are provided on the same substrate,
A first TFT having a first active layer and a second TFT having a second active layer, wherein the first active layer is formed of a polycrystalline semiconductor having electrical anisotropy in a channel direction. The 2 active layer is formed of a polycrystalline semiconductor having no electrical anisotropy in the channel direction, the pixel region is formed of the second TFT, the scanning line drive circuit is formed of the second TFT, and the signal There is provided a semiconductor device in which the line driving circuit includes the first TFT.

According to the present invention, the pixel region, the scanning line driving circuit, and the signal line driving circuit are provided on the same substrate,
A first TFT having a first active layer and a second TFT having a second active layer, wherein the first active layer is formed of a polycrystalline semiconductor having electrical anisotropy in a channel direction. The second active layer is formed of a polycrystalline semiconductor whose electrical anisotropy in the channel direction is weaker than that of the first active layer, the pixel region is formed of the second TFT, and the scanning line driving circuit is formed of the second TFT. A semiconductor device is provided in which the signal line drive circuit is configured by the first TFT.

According to the present invention, the pixel region, the scanning line driving circuit, and the signal line driving circuit are provided on the same substrate,
The first active layer has a first TFT having a first active layer and a second TFT having a second active layer. The first active layer has crystal grains extending in the channel direction and a grain size in the minor axis direction of 0. 5-100
μm and the particle diameter in the major axis direction is 3 to 10000 μm,
The second active layer is formed of a polycrystalline semiconductor having a grain size of 0.01 μm to 10 μm, the pixel region is formed of the second TFT, and the scanning line driving circuit is formed. Is provided with the second TFT, and the signal line drive circuit is provided with the first TFT.

The driving frequency of the scanning line driving circuit is 1 k.
It is preferable that the frequency is from 1 Hz to 1 MHz, and the drive frequency of the signal line driving circuit is from 100 kHz to 100 MHz.

According to the present invention, the pixel region, the scanning line driving circuit, and the signal line driving circuit are provided on the same substrate,
A first TFT having a first active layer and a second TFT having a second active layer, wherein the first active layer irradiates the semiconductor film with an energy beam to form a melt zone, and the melt zone is used as a channel. The second active layer is formed by crystallizing by continuously scanning in a long direction, the second active layer is formed by crystallizing a semiconductor film by heat treatment, and the pixel region is formed by the second TFT. A semiconductor device is provided in which the scanning line drive circuit is configured by the first TFT, and the signal line drive circuit is configured by the first TFT.

According to the present invention, the pixel region, the scanning line driving circuit, and the signal line driving circuit are provided on the same substrate,
A first TFT having a first active layer and a second TFT having a second active layer, wherein the first active layer irradiates the semiconductor film with an energy beam to form a melt zone, and the melt zone is used as a channel. The second active layer is formed by crystallizing by continuously scanning in the long direction, wherein the second active layer is formed by adding a metal element to a semiconductor film and crystallizing by heat treatment. A semiconductor device is provided in which a pixel region is configured by the second TFT, the scanning line drive circuit is configured by the first TFT, and the signal line drive circuit is configured by the first TFT.

The energy beam may be continuous wave laser light.

According to the present invention, the pixel region, the scanning line driving circuit, and the signal line driving circuit are provided on the same substrate,
A first TFT having a first active layer and a second TFT having a second active layer, wherein the first active layer irradiates the semiconductor film with an energy beam to form a melt zone, and the melt zone is used as a channel. The second active layer is formed by crystallizing the semiconductor film by irradiating it with a pulsed energy beam, The pixel region is composed of the second TFT, the scanning line driving circuit is composed of the first TFT,
A semiconductor device is provided in which the signal line drive circuit is configured by the first TFT.

The energy beam may be pulsed laser light.

According to the present invention, the pixel region, the scanning line driving circuit, and the signal line driving circuit are provided on the same substrate,
A first TFT having a first active layer and a second TFT having a second active layer, wherein the first active layer is formed of a polycrystalline semiconductor in which crystal grains extend in the channel direction,
The second active layer is formed of a polycrystalline semiconductor whose crystal grains have no anisotropy in the channel direction, the pixel region is formed of the second TFT, and the scanning line driving circuit is formed of the first TFT. In addition, a semiconductor device is provided in which the signal line drive circuit includes the first TFT.

According to the present invention, the pixel region, the scanning line driving circuit, and the signal line driving circuit are provided on the same substrate,
A first TFT having a first active layer and a second TFT having a second active layer, wherein the first active layer is formed of a polycrystalline semiconductor in which crystal grains extend in the channel direction,
The second active layer is formed of a polycrystalline semiconductor whose crystal grain shape anisotropy in the channel direction is weaker than that of the first active layer, the pixel region is formed of the second TFT, and the scanning line driving circuit is formed. There is provided a semiconductor device including the first TFT and the signal line drive circuit including the first TFT.

According to the present invention, the pixel region, the scanning line driving circuit, and the signal line driving circuit are provided on the same substrate,
A first TFT having a first active layer and a second TFT having a second active layer, wherein the first active layer is formed of a polycrystalline semiconductor having electrical anisotropy in a channel direction. The 2 active layer is formed of a polycrystalline semiconductor having no electrical anisotropy in the channel direction, the pixel region is formed of the second TFT, the scanning line drive circuit is formed of the first TFT, and the signal There is provided a semiconductor device in which the line driving circuit includes the first TFT.

According to the present invention, the pixel region, the scanning line driving circuit, and the signal line driving circuit are provided on the same substrate,
A first TFT having a first active layer and a second TFT having a second active layer, wherein the first active layer is formed of a polycrystalline semiconductor having electrical anisotropy in a channel direction. The second active layer is formed of a polycrystalline semiconductor whose electrical anisotropy in the channel direction is weaker than that of the first active layer, the pixel region is formed of the second TFT, and the scanning line driving circuit is formed of the first TFT. A semiconductor device is provided in which the signal line drive circuit is configured by the first TFT.

According to the present invention, the pixel region, the scanning line driving circuit and the signal line driving circuit are provided on the same substrate,
The first active layer has a first TFT having a first active layer and a second TFT having a second active layer. The first active layer has crystal grains extending in the channel direction and a grain size in the minor axis direction of 0. 5-100
The second active layer is formed of a polycrystalline semiconductor having a grain diameter of 0.01 μm to 10 μm, and the second active layer is formed of a polycrystalline semiconductor having a grain diameter of 0.01 μm to 10 μm. A semiconductor device is provided in which a region is formed by the second TFT, the scanning line drive circuit is formed by the first TFT, and the signal line drive circuit is formed by the first TFT.

The driving frequency of the scanning line driving circuit is 10
It is preferable that the frequency is from 1 kHz to 1 MHz, and the drive frequency of the signal line driving circuit is from 100 kHz to 100 MHz.

In the semiconductor device, a memory is provided on the same substrate as the pixel region, and the memory is the first memory.
It may be composed of a TFT.

The memory is an SRAM, and the SRAM
The read cycle time may be 200 nsec or less.

The memory is a DRAM, and the DRAM
The read cycle time may be 1 μsec or less.

In the semiconductor device, a CPU is provided on the same substrate as the pixel region, and the CPU has the first
It may be composed of a TFT.

The operating frequency of the CPU is preferably 5 MHz or higher.

In the semiconductor device, an image processing circuit may be provided on the same substrate as the pixel region, and the image processing circuit may be composed of the first TFT.

The operating frequency of the image processing circuit is 5 MHz.
The above is preferable.

In the semiconductor device, a DSP is provided on the same substrate as the pixel area, and the DSP is the first substrate.
It may be composed of a TFT.

The operating frequency of the image processing circuit is 5 MHz.
The above is preferable.

In the semiconductor device, the timing generation circuit may be provided on the same substrate as the pixel region, and the timing generation circuit may be composed of the first TFT.

The substrate having an insulating surface may be any one of a plastic substrate, a glass substrate and a quartz substrate.

The area of the circuit constituted by the first TFT is preferably 50% or less of the area of the substrate.

It is preferable that the circuit formed by the first TFT is formed within 1 to 10 rectangular areas, and the total area of the rectangular areas is 50% or less of the area of the substrate.

The semiconductor device may be a liquid crystal display device.

The semiconductor device may be a light emitting device.

The semiconductor device may be one selected from a game machine, a video camera, a head-mounted display, a DVD player, a personal computer, a mobile phone, and a car audio.

[0076]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) As a typical form of a semiconductor device having a display portion of the present invention, an active matrix type semiconductor display device will be described as an example.

FIG. 2 is a block diagram of the active matrix semiconductor display device of the present invention when viewed from above. 2, the active matrix semiconductor display device includes a pixel region 202 formed on a substrate 201, a scanning line driving circuit 204, a signal line driving circuit 203, and a wiring 20.
5 and the FPC 206.

The operation of the active matrix semiconductor display device will be briefly described.

The signal line driving circuit 203 receives the image signal, the clock signal and the start pulse, and the scanning line driving circuit 204 receives the clock signal and the start pulse from the outside by the FPC 206.
Respectively, and display an image in the pixel area 202.

In the pixel region, a plurality of signal lines and a plurality of scanning lines are arranged so as to intersect with each other, and pixel TFTs are arranged at respective intersections of the signal lines and the scanning lines. A scanning line is connected to the gate electrode of the pixel TFT, a signal line is connected to one of the source electrode or the drain electrode, and a liquid crystal element is connected to the remaining one of the source electrode or the drain electrode.

The display operation in each pixel will be described.
When a scanning line is selected, the pixel TFT connected to the selected scanning line is turned on. When data is input to the signal line connected to the pixel TFT during that time, the potential of the signal line is applied to the liquid crystal element, and the liquid crystal element changes the light transmittance according to the applied voltage. In this way, the brightness in each pixel is determined and display is performed.

One image is formed by sequentially selecting all the scanning lines. Further, while each scanning line is selected, data is input to all signal lines sequentially or all at once, and image data is input to the selected row. A period in which one image is displayed is called one frame, and preferably 60 frames per second or more.

According to the operation method described above, once the number of pixels is determined, the approximate drive frequency required for the drive circuit is determined. For example, in the color VGA standard, the number of pixels is 6
Since it is 40 × 480 × RGB, assuming that it operates at 60 frames / sec, the period for selecting one scanning line is approximately Tg = 1/60/480 sec = 35 μsec. Also,
Assuming that the image data is captured in RGB × 1 pixel per clock, 1 clock is Td = Tg / 640 sec =
It should be about 54 nsec. Note that the time for inputting data to the pixel is about a period (Tg = 35 μsec) for selecting one scanning line in line-sequential driving.

The actual operating frequency depends on the number of divisions of the image data, the frame frequency, the blanking period, etc., but the pixel and scanning line driving circuits operate at a frequency of 1 to 100 kHz, and the signal line driving circuit It is required to operate at a frequency of 0.1-100 MHz.

The case of the liquid crystal display device has been described here. In a display device having a light emitting layer represented by an EL layer, a driving method is slightly different, but one image is formed by sequentially selecting all scanning lines,
A common method is that data is input to all signal lines sequentially or all at once while each scanning line is selected, and image data is input to the selected row. Therefore, the same idea can be applied to the drive frequency.

In the first embodiment, based on such consideration of the operating frequency, the case where the high-mobility TFT manufacturing process is applied to the region including the signal line driving circuit 203 which requires high-speed operation is shown. That is, in FIG. 2, the method of crystallizing a semiconductor film using a continuous wave laser is applied only to the first region 207. A known active layer forming technique may be used for the regions other than the first region.

In FIG. 2, the first region 207 can be 30% or less (preferably 10% or less) of the substrate 201, and the time required for the continuous wave laser process is continuous with respect to the entire substrate. Approximately 30% or less (preferably 10%) as compared with the case of performing an oscillation laser process
The following can be set.

In the first embodiment, the active matrix semiconductor display in which the high speed operation of the entire device is achieved by using the high mobility TFT manufacturing process in the first region 207 including the signal line driving circuit which becomes the rate controlling The device is realized. In addition, high throughput is achieved despite the use of a crystallization process using a continuous wave laser.

In the first embodiment, the process of manufacturing the TFT having high mobility is applied to the region including the signal line driving circuit, but of course, it may be applied to the region including the scanning line driving circuit. It may be applied to a region including pixels. In particular, even when applying a process of manufacturing a TFT having high mobility to a region including all TFTs,
Throughput is preferable as compared with the case of applying to the entire substrate.

(Second Embodiment) A semiconductor device having a display portion will be described as an example of a typical embodiment of a semiconductor device having a display portion of the present invention.

FIG. 1 is a structural view of a semiconductor device having a display portion of the present invention when viewed from above. In FIG. 1, a semiconductor device having a display portion includes a semiconductor display portion 102 formed over a substrate 101, a first control circuit 112,
Second control circuit 113, CPU 114, first memory 1
15, the second memory 116, and the input / output terminal 111. Further, the semiconductor display unit 102 includes a pixel region 119, a signal line driving circuit 117, and a scanning line driving circuit 11.
It is composed of 8.

The semiconductor device shown in FIG. 1 is a device for capturing or creating image data, processing the image data and converting the format, and displaying the image. The block configuration is the same as the block diagram shown in FIG. 21, and the operation and function are the same as those described with reference to FIG. 21, so description thereof will be omitted here.

Regarding the operating frequency of each circuit block,
Although it cannot be generally stated because it depends on the individual semiconductor device,
Other circuit blocks normally operate in synchronization with the operating frequency of the CPU. Therefore, it is preferable to improve the operating frequency of each circuit block connected to the CPU 114 and the bus.

Therefore, in the second embodiment, the CPU 11
4 and the first control circuit 112 connected to the bus, the second control circuit 113, the first memory 115, the second memory 1
16 and the signal line driver circuit 117, a manufacturing process of a high mobility TFT is applied. That is, in FIG. 1, the method of crystallizing the semiconductor active layer using the continuous wave laser is applied only to the first region 103. A known active layer forming technique may be used for the regions other than the first region.

In FIG. 1, the first region 103 can be 50% or less (preferably 30% or less) of the substrate, and the time required for the continuous oscillation laser process is continuous oscillation for the entire substrate. Compared with the case of performing the laser process, it is possible to set the amount to about 50% or less (preferably 30% or less).

From the viewpoint of throughput, it is preferable that the region to which the crystallization of the semiconductor active layer using the continuous wave laser is applied is localized as much as possible. In the configuration shown in FIG. 1, the positions of the signal line driver circuit and the scanning line driver circuit can be interchanged, but the signal line driver circuit that requires high-speed operation is connected to the CPU 114 and the first control circuit connected to the bus. The first region is localized on the substrate by being arranged in the vicinity of 112, the second control circuit 113, the first memory 115, and the second memory 116.

By arranging in this way, it is not necessary to move the irradiation position of the continuous wave laser beam over the entire surface of the substrate, and compared with the case where the continuous wave laser beam is irradiated to a plurality of regions having the same area and scattered on the substrate. As a result, the time required for crystallization can be shortened.

As described above, the irradiation position of continuous wave laser light is preferably localized on the substrate. Further, the continuous wave laser light or the movement of the substrate is preferably simple, and the continuous wave laser light irradiation region is preferably rectangular. That is, it is preferable that the continuous wave laser beam irradiation region is a region (preferably 1 to 10) represented by a rectangle.

In the second embodiment, the first area 103 including the system including the CPU 114 which is required to operate at high speed.
In addition, by using a high-mobility TFT manufacturing process, a semiconductor device achieving high-speed operation of the entire device was realized. In addition, by reducing the ratio of the first region to the substrate, high throughput was realized despite using a crystallization process using a continuous wave laser.

In the second embodiment, the CPU 114,
A process of manufacturing a high mobility TFT was applied to a region including the first control circuit 112, the second control circuit 113, the first memory 115, the second memory 116, and the signal line driver circuit 117. Depending on the block configuration, the characteristics required for the TFT differ even when operating at the same frequency.

For example, when particularly high characteristics are required for the TFTs forming the CPU 114, the first control circuit 112, and the first memory 115, the TFTs having high mobility are formed only in the region including them. Applying the process is also effective.

Even in such a case, the CP is controlled so that the crystallization time of the active layer by the continuous wave laser is shortened.
U114, first control circuit 112, first memory 115
It is preferable to devise the arrangement method of. Such an example is shown in FIG.

Of course, not only the first region, but a process of manufacturing a TFT having high mobility may be applied to a region including a scanning line driving circuit or a region including pixels.
Especially, TF with high mobility for the area including all TFTs.
Even when the process of producing T is applied, the throughput is increased as compared with the case of applying it to the entire substrate, which is preferable.

In this embodiment, the circuit is divided into rough circuit blocks such as a CPU and a memory, but the present invention is not limited to this. As the circuit block, a smaller circuit configuration such as a register or a frequency dividing circuit may be handled. Then, application of a crystallization process using a continuous wave laser may be selected for such a small block.

When the crystallization process using the continuous wave laser is applied to a large circuit block such as a CPU or a memory, it is not always necessary to apply it to the entire surface. It is also possible to selectively apply only to a region where the operating frequency is relatively high in the circuit block.

Examples of the present invention will be shown below.

[0107]

[Embodiment 1] In this embodiment, a method for irradiating an arbitrary region on a substrate with laser light will be described with reference to FIGS. 6 and 20.

FIG. 6 shows an outline of an apparatus for forming a linear beam and irradiating it on a substrate.

The laser light emitted from the laser 601 is
The light enters the convex lens 603 via the mirror 602.
Here, the laser 601 may be a continuous wave or pulsed solid-state laser, a gas laser, or a metal laser. In this embodiment, a continuous wave YAG laser is used. The laser light emitted from the laser 601 may be converted into a harmonic by a non-linear optical element. Also, the laser 60
A beam expander may be installed between the mirror 1 and the mirror 602 or between the mirror 602 and the convex lens 603 to expand the beam to a desired size in each of the long and short directions. The beam expander is particularly effective when the shape of the laser light emitted from the laser is small. Further, the mirror may not be installed, or a plurality of mirrors may be installed.

The laser light is obliquely incident on the convex lens 603. By doing so, the focal position shifts due to aberrations such as astigmatism, and the linear beam 606 can be formed on the irradiation surface or in the vicinity thereof. It is preferable that the convex lens 603 is made of synthetic quartz glass because a high transmittance can be obtained. Further, it is desirable that the convex lens is an aspherical lens whose spherical aberration is corrected. If an aspherical lens is used, the light-collecting property is improved, the aspect ratio is improved, and the energy density distribution is improved.

The term "linear" as used herein does not mean "line" in a strict sense, but means a rectangle or a long ellipse having a large aspect ratio. For example, the aspect ratio is 2 or more (preferably 10 to 10,000). The linear shape is provided to ensure an energy density for performing sufficient annealing on the irradiation target. The linear beam does not have to be strictly linear.

Then, while irradiating the linear beam 606 formed in this way, by moving relative to the irradiation object 604 in the direction indicated by 607 or the direction indicated by 608, the irradiation object is irradiated. At 604, the desired area or entire surface can be illuminated.

Then, while irradiating the linear beam thus formed, for example, the direction indicated by 607 or 6
By moving relative to the irradiated body 604 in the direction indicated by 08, a desired region of the irradiated body 604 can be irradiated. FIG. 20 shows how the laser is applied to the base. The arrow drawn on the laser irradiation region 609 represents the locus of the irradiation laser.

The optical system for generating the laser may be another known one. [Embodiment 2] In this embodiment, a method of crystallizing a semiconductor film using a continuous wave laser used in a manufacturing process of a high mobility TFT in a semiconductor device of the present invention will be described.

Plasma C is used as a base film on a glass substrate.
Silicon oxynitride film (composition ratio Si = 32%, O
= 59%, N = 7%, H = 2%) 400 nm. Subsequently, an amorphous silicon film of 150 nm was formed as a semiconductor film on the base film by a plasma CVD method. Then, heat treatment was performed at 500 ° C. for 3 hours to release hydrogen contained in the semiconductor film, and then the semiconductor film was crystallized by a laser annealing method.

As the laser used in the laser annealing method, a continuous wave YVO ₄ laser was used. As the condition of the laser annealing method, the second harmonic (wavelength 532 nm) of the YVO ₄ laser was used as the laser light. The semiconductor film formed on the substrate surface was irradiated with laser light as a beam having a predetermined shape by an optical system.

The optical system used for irradiating the semiconductor film formed on the surface of the substrate with the laser light is the same as in Example 1.
The optical system (see FIG. 6) described in 1. was used.

In this embodiment, the incident angle φ of the laser beam with respect to the convex lens is set to about 20 ° to form an elliptical beam of 200 μm × 50 μm and the glass substrate 105 is set to 50 cm / s.
The semiconductor film was crystallized by irradiation while moving at a speed of.

The relative scanning direction of the elliptical beam was set to the direction perpendicular to the major axis of the elliptical beam.

The crystalline semiconductor film thus obtained was subjected to Secco etching, and the surface was observed by SEM at 10,000 times. The results are shown in FIG. The Secco solution for Secco etching is HF: H ₂ O = 2: 1 and K ₂ as an additive.
It is produced using Cr ₂ O ₇ . FIG. 7 is obtained by relatively scanning the laser beam in the direction indicated by the arrow in the figure. It can be seen that large-sized crystal grains are formed parallel to the scanning direction of the laser light. That is, the crystal is grown so as to extend in the scanning direction of the laser light.

As described above, large-sized crystal grains are formed in the semiconductor film crystallized by the method of this embodiment. Therefore, when a TFT is manufactured using the semiconductor film as a semiconductor active layer, the number of crystal grain boundaries included in the channel formation region of the TFT can be reduced.
In addition, since the inside of each crystal grain has crystallinity that can be regarded as a substantially single crystal, high mobility (field effect mobility) similar to that of a transistor including a single crystal semiconductor can be obtained.

Further, by disposing the TFT so that the carrier moving direction is aligned with the extending direction of the formed crystal grains, the number of times the carriers cross the crystal grain boundaries can be extremely reduced. Therefore, variations in the on-current value (the drain current value that flows when the TFT is in the on state), the off current value (the drain current value that flows when the TFT is in the off state), the threshold voltage, the S value, and the field effect mobility. Can be reduced, and the electrical characteristics are significantly improved.

In order to irradiate the elliptical beam 606 over a wide area of the semiconductor film, the operation of irradiating the semiconductor film by scanning the elliptical beam 606 in the direction perpendicular to its major axis (hereinafter referred to as scanning). Have been done multiple times. Here, the position of the elliptical beam 606 is shifted in a direction parallel to the major axis of each scan. Further, the scanning direction is reversed between successive scans. here,
In two consecutive scans, one is called a forward scan and the other is called a backward scan.

The size of shifting the position of the elliptical beam 606 in the direction parallel to the long axis for each scan is expressed as the pitch d. In addition, in the forward scan, FIG.
The length in the direction perpendicular to the scanning direction of the elliptical beam 606 in the region where the crystal grains of large grain size as shown in FIG.
Notated as 1. In the backward scan, the length in the direction perpendicular to the scanning direction of the elliptical beam 606 in the region where the crystal grains of large grain size as shown in FIG. 7 are formed is denoted by D2. The average value of D1 and D2 is D.

At this time, the overlap rate R _OL [%]
Is defined by equation (1).

R _OL = (1−d / D) × 100 Equation (1)

In this embodiment, the overlap ratio R _{OL is set} to 0 [%].

[Embodiment 3] In this embodiment, a semiconductor film crystallization method using a continuous wave laser used in the manufacturing process of the high mobility TFT in the semiconductor device of the present invention is described as Embodiment 2. Shows a different example.

The steps up to the formation of the amorphous silicon film as the semiconductor film are the same as in the second embodiment. After that, JP-A-7
Using the method described in Japanese Patent Application Laid-Open No. 183540, a nickel acetate aqueous solution (concentration in weight: 5 ppm, volume: 10 ml) is applied onto the semiconductor film by spin coating, and 5
Heat treatment was performed in a nitrogen atmosphere of 00 ° C. for 1 hour and in a nitrogen atmosphere of 550 ° C. for 12 hours. Subsequently, the crystallinity of the semiconductor film was improved by a laser annealing method.

As the laser used in the laser annealing method, a continuous wave YVO ₄ laser was used. The condition of the laser annealing method is 200 μm × when the second harmonic (wavelength 532 nm) of the YVO ₄ laser is used as the laser beam and the incident angle φ of the laser beam with respect to the convex lens 103 in the optical system shown in FIG. 6 is about 20 °. An elliptical beam of 50 μm was formed. The crystallinity of the semiconductor film was improved by irradiating the elliptical beam while moving the glass substrate 105 at a speed of 50 cm / s.

The relative scanning direction of the elliptical beam 606 was set to the direction perpendicular to the major axis of the elliptical beam 606.

The crystalline semiconductor film thus obtained was subjected to Secco etching, and the surface was observed by SEM at 10,000 times. The result is shown in FIG. FIG. 8 is obtained by relatively scanning the laser beam in the direction indicated by the arrow in the figure, and shows a state in which large-sized crystal grains are formed extending in the scanning direction. Recognize.

As described above, since large-sized crystal grains are formed in the semiconductor film crystallized using the present invention,
When a TFT is manufactured using the semiconductor film, the number of crystal grain boundaries included in the channel formation region can be reduced. In addition, since each crystal grain has crystallinity that can be regarded as a single crystal, high mobility (field effect mobility) equivalent to that of a transistor using a single crystal semiconductor.
It is also possible to obtain

Furthermore, the formed crystal grains are aligned in one direction. Therefore, by arranging the TFT so that the moving direction of the carrier is aligned with the extending direction of the formed crystal grain, the number of times the carrier crosses the crystal grain boundary can be extremely reduced. Therefore, the ON current value, OFF current value,
It is also possible to reduce variations in threshold voltage, S value, and field effect mobility, and electrical characteristics are significantly improved.

In order to irradiate the elliptical beam 606 over a wide area of the semiconductor film, the operation (scan) of scanning the elliptical beam 606 in the direction perpendicular to the major axis and irradiating the semiconductor film is performed a plurality of times. ing. Here, the position of the elliptical beam 606 is shifted in a direction parallel to the major axis of each scan. Further, the scanning direction is reversed between successive scans. Here, in two consecutive scans, one is called a forward scan and the other is called a backward scan.

The size of shifting the position of the elliptical beam 606 in the direction parallel to the long axis for each scan is expressed as the pitch d. In addition, in the forward scan, FIG.
The length in the direction perpendicular to the scanning direction of the elliptical beam 606 in the region where the crystal grains of large grain size as shown in FIG.
Notated as 1. In the backward scan, the length in the direction perpendicular to the scanning direction of the elliptical beam 606 in the region in which large-sized crystal grains are formed as shown in FIG. 8 is denoted by D2. The average value of D1 and D2 is D.

At this time, the overlap ratio R _OL [%] is defined as in the case of the equation (1). In this embodiment, the overlap ratio R _{OL is set} to 0 [%].

Further, the result of Raman scattering spectroscopy of the semiconductor film (indicated as Improved CG-Silicon in the figure) obtained by the above crystallization method is shown in FIG. 9 by a bold line. Here, for comparison, the results of Raman scattering spectroscopy of single crystal silicon (indicated as ref. (100) Si Wafer in the figure) are shown by thin lines. After the amorphous silicon film is formed, heat treatment is performed to release hydrogen contained in the semiconductor film, and the semiconductor film is crystallized using a pulse oscillation excimer laser (in the figure, excimer laser an
The result of Raman scattering spectroscopy (denoted as "nealing") is shown by a dotted line in FIG.

Semiconductor film obtained by the method of this embodiment
Raman shift of 517.3 cm ^-1Has a peak of
It Also, the full width at half maximum is 4.96 cm.^-1Is. On the other hand, simple
Raman shift of crystalline silicon is 520.7 cm^-1No pi
Have a ark. Also, the full width at half maximum is 4.44 cm^-1And
It Crystallization was performed using a pulsed excimer laser
Raman shift of the semiconductor film is 516.3 cm.^-1Is.
Also, the full width at half maximum is 6.16 cm^-1Is.

From the results of FIG. 9, the crystallinity of the semiconductor film obtained by the crystallization method shown in this embodiment is higher than that of the semiconductor film crystallized by using the pulsed excimer laser. , It is close to single crystal silicon.

[Embodiment 4] In this embodiment, an example in which a TFT is manufactured by using the semiconductor film crystallized by the method shown in Embodiment 2 will be described with reference to FIGS. 6, 10 and 11.

In this embodiment, a glass substrate is used as the substrate 20, and plasma C is used as the base film 21 on the glass substrate.
Silicon oxynitride film (composition ratio Si = 32%, O
= 27%, N = 24%, H = 17%) 50 nm, silicon oxynitride film (composition ratio Si = 32%, O = 59%, N = 7)
%, H = 2%) 100 nm. Next, an amorphous silicon film of 150 nm was formed as a semiconductor film 22 on the base film 21 by a plasma CVD method. And 500 ℃
Then, heat treatment was performed for 3 hours to release hydrogen contained in the semiconductor film. (Fig. 10 (A))

Then, continuous oscillation YVO was used as laser light.
_Using the second harmonic of _four lasers (wavelength 532 nm, 5.5 W), the incident angle φ of the laser beam with respect to the convex lens 603 in the optical system shown in FIG.
An elliptical beam of 50 μm was formed. The semiconductor film 22 was irradiated with the elliptical beam relatively scanned at a speed of 50 cm / s. (Figure 10 (B))

Then, the first doping process is performed. This is the channel dope for controlling the threshold.
B ₂ H ₆ was used as the material gas, the gas flow rate was 30 sccm,
The current density was 0.05 μA, the acceleration voltage was 60 keV, and the dose was 1 × 10 ¹⁴ / cm ² . (Figure 10 (C))

Then, after patterning is performed to etch the semiconductor film 24 into a desired shape, plasma CV is used as a gate insulating film 27 covering the etched semiconductor film.
A silicon oxynitride film having a thickness of 115 nm is formed by the D method. Then, a film having a thickness of 3 is formed as a conductive film on the gate insulating film 27.
A 0 nm TaN film 28 and a 370 nm-thickness W film 29 are laminated. (Figure 10 (D))

A mask (not shown) made of a resist is formed by photolithography, and the W film and TaN are formed.
The film and the gate insulating film are etched.

Then, the resist mask is removed, a new mask 33 is formed, and a second doping process is performed to introduce an impurity element imparting n-type to the semiconductor film. In this case, the conductive layers 30 and 31 serve as masks for the impurity element imparting n-type, and the impurity regions 34 are formed in a self-aligned manner. In this example, the second doping process was performed under two conditions because the thickness of the semiconductor film was as thick as 150 nm. In this embodiment, phosphine (PH ₃ ) is used as the material gas, the dose amount is set to 2 × 10 ¹³ / cm ² , the acceleration voltage is set to 90 keV, and then the dose amount is set to 5 × 10 ¹⁴ / cm ² , and the acceleration is performed. The voltage was set to 10 keV. (Fig. 10 (E))

Next, after removing the mask 33 made of resist, a new mask 35 made of resist is formed and a third doping process is performed. By the third doping treatment, an impurity region 36 in which an impurity element imparting a conductivity type opposite to the one conductivity type is added is formed in the semiconductor film to be the active layer of the p-channel TFT. Conductive layers 30, 31
Is used as a mask for the impurity element, and the impurity element imparting p-type is added to form the impurity region 36 in a self-aligned manner. In the present embodiment, the third doping process was also performed under two conditions because the thickness of the semiconductor film was as thick as 150 nm. In this example, diborane (B ₂ H ₆ ) was used as the material gas, the dose amount was set to 2 × 10 ¹³ / cm ² , the acceleration voltage was set to 90 keV, and then the dose amount was set to 1 × 10 ¹⁵ / cm ^2. The acceleration voltage was set to 10 keV. (Figure 10 (F))

Through the above steps, the impurity regions 34 and 36 are formed in the respective semiconductor layers.

Next, the mask 35 made of resist is removed, and the first interlayer insulating film 37 is formed by the plasma CVD method.
As a silicon oxynitride film having a film thickness of 50 nm (composition ratio Si = 3
2.8%, O = 63.7%, N = 3.5%).

Next, heat treatment is performed to recover the crystallinity of the semiconductor layers and activate the impurity elements added to the respective semiconductor layers. In this embodiment, a thermal annealing method using a furnace annealing furnace is used to perform 550 ° C. 4 in a nitrogen atmosphere.
Heat treatment was performed for an hour. (Fig. 10 (G))

Then, a second interlayer insulating film 38 made of an inorganic insulating film material or an organic insulating material is formed on the first interlayer insulating film 37. In this embodiment, a silicon nitride film having a thickness of 50 nm is formed by the CVD method, and then a silicon oxide film having a thickness of 400 nm is formed.

When heat treatment is performed, hydrogenation treatment can be performed. In this example, a furnace annealing furnace was used to perform heat treatment at 410 ° C. for 1 hour in a nitrogen atmosphere.

Subsequently, the wiring 39 electrically connected to each impurity region is formed. In this embodiment, the film thickness is 50
A Ti film having a thickness of 500 nm, an Al-Si film having a thickness of 500 nm, and a Ti film having a thickness of 50 nm are formed by patterning. Of course, the structure is not limited to the two-layer structure, and may be a single-layer structure or a laminated structure of three or more layers. The material of the wiring is not limited to Al and Ti. For example, wiring may be formed by forming Al or Cu on the TaN film and then patterning the laminated film on which the Ti film is formed. (Fig. 10
(H))

As described above, the n-channel TFT 51 and the p-channel TFT 52 having the channel length of 6 μm and the channel width of 4 μm were formed.

The results of measuring these electrical characteristics are shown in FIG.
Shown in 1. The electrical characteristics of the n-channel TFT 51 are shown in FIG.
The electrical characteristics of the p-channel TFT 52 are shown in FIG. 1 (A) and FIG. 11 (B). The electrical characteristics were measured at two measurement points, the gate voltage Vg = -16 to 16V, and the drain voltage Vd = 1V and 5V. In FIG. 11, the drain current (ID) and the gate current (IG) are shown by solid lines, and the mobility (μFE) is shown by dotted lines.

Since large-sized crystal grains are formed in the semiconductor film crystallized by the above method, when a TFT is manufactured using the semiconductor film, the crystal grain boundaries included in the channel formation region are formed. The number of can be reduced. Furthermore, since the formed crystal grains are aligned in one direction, T
By making the channel direction of the FT substantially parallel to the scanning direction of the laser light, the number of times carriers cross the crystal grain boundaries can be extremely reduced. Therefore, a TFT having good electric characteristics can be obtained as shown in FIG. Especially, the mobility is 524 cm ² / Vs in the n-channel TFT,
It can be seen that the p-channel type TFT has 205 cm ² / Vs.

The method for activating a semiconductor film using the continuous wave laser described in this embodiment can be applied to the TFT which constitutes a circuit block which requires high speed operation in the present invention. In particular, by making the channel direction of the TFT and the scanning direction of the laser light substantially parallel (within 30 °), it is possible to realize a circuit block having substantially the same operating characteristics as those formed on a single crystal silicon substrate. .

[Embodiment 5] In this embodiment, an example in which a TFT is manufactured by using the semiconductor film crystallized by the method shown in Embodiment 3 will be described with reference to FIGS. explain.

The steps up to the formation of the amorphous silicon film as the semiconductor film are the same as in the fourth embodiment. The amorphous silicon film was formed to a thickness of 150 nm. (Fig. 12 (A))

Then, using the method described in JP-A-7-183540, a nickel acetate aqueous solution (concentration in terms of weight: 5 ppm,
A volume of 10 ml) is applied to form the metal-containing layer 41.
Then, heat treatment was performed in a nitrogen atmosphere at 500 ° C. for 1 hour and in a nitrogen atmosphere at 550 ° C. for 12 hours. Thus, the semiconductor film 42 was obtained. (Fig. 12 (B))

Subsequently, the crystallinity of the semiconductor film 42 is improved by the laser annealing method.

The condition of the laser annealing method is that the second harmonic (wavelength 532) of the continuous oscillation YVO ₄ laser is used as the laser light.
nm, 5.5 W), the incident angle φ of the laser beam with respect to the convex lens 603 in the optical system shown in FIG.
As a result, an elliptical beam of 200 μm × 50 μm was formed. The elliptical beam is applied to the substrate at 20 cm / s or 5
Irradiation was performed while moving at a speed of 0 cm / s to improve the crystallinity of the semiconductor film 42. Thus, the semiconductor film 43 was obtained. (Figure 12 (C))

The steps after crystallization of the semiconductor film of FIG. 12C are shown in FIGS. 10C to 10 shown in the fifth embodiment.
This is the same as the step (H). Thus, the channel length is 6μ
An n-channel TFT 51 and a p-channel TFT 52 having an m and a channel width of 4 μm were formed. These electrical characteristics were measured.

The electrical characteristics of the TFT manufactured by the above steps are shown in FIGS. 13, 14 and 15.

12 (A) and 13 (B).
In the laser annealing step of (C), the substrate speed is set to 2
The electrical characteristics of the TFT manufactured by moving at 0 cm / s are shown. FIG. 13A shows the electrical characteristics of the n-channel TFT 51. In addition, in FIG. 13B, p-channel TF
The electrical characteristics of T52 are shown. 14A and 14B show electrical characteristics of a TFT manufactured by moving the substrate at a speed of 50 cm / s in the laser annealing step of FIG. 12C. FIG. 14A shows the electrical characteristics of the n-channel TFT 51. In addition, FIG. 14 (B)
The electrical characteristics of the p-channel TFT 52 are shown in FIG.

The electrical characteristics were measured under the conditions of gate voltage Vg = -16 to 16V and drain voltage Vd =
It was set to 1V and 5V. In addition, in FIG. 13 and FIG.
The drain current (ID) and gate current (IG) are solid lines,
Mobility (μFE) is indicated by the dotted line.

Since large crystal grains are formed in the crystallized semiconductor film shown in this embodiment, when a TFT is manufactured using the semiconductor film, crystals included in the channel formation region are formed. The number of grain boundaries can be reduced.
Furthermore, since the formed crystal grains are aligned in one direction and few grain boundaries are formed in a direction intersecting the relative scanning direction of the laser light, the number of times carriers cross the crystal grain boundaries is extremely small. Can be reduced.

Therefore, a TFT having good electric characteristics can be obtained as shown in FIGS. Especially mobility
In FIG. 13, the n-channel TFT has 510 cm ² /
200 cm ² / V in Vs, p-channel TFT
s, and in FIG. 14, it is 59 in the n-channel TFT.
5 cm ² / Vs, 199c in p-channel TFT
It can be seen that it is very excellent at m ² / Vs. And
When a semiconductor device is manufactured using such a TFT, its operating characteristics and reliability can be improved.

Further, FIG. 15 shows electrical characteristics of a TFT manufactured by moving the substrate at a speed of 50 cm / s in the laser annealing step of FIG. Figure 15
(A) shows the electrical characteristics of the n-channel TFT 51. Further, FIG. 15B shows electric characteristics of the p-channel TFT 52.

The electrical characteristics are measured under the conditions of gate voltage Vg = -16 to 16V and drain voltage Vd =
It was set to 0.1V and 5V.

As shown in FIG. 15, T having good electrical characteristics
FT is obtained. In particular, the mobility is 657 cm ² / Vs in the n-channel TFT shown in FIG.
219c in the p-channel TFT shown in FIG.
It can be seen that it is very excellent at m ² / Vs. And
When a semiconductor device is manufactured using such a TFT, its operating characteristics and reliability can be improved.

The method for activating a semiconductor film using the continuous wave laser shown in this embodiment can be applied to the TFTs constituting the circuit block which requires high speed operation in the present invention. In particular, by making the channel direction of the TFT and the scanning direction of the laser light substantially parallel (within 30 °), it is possible to realize a circuit block having substantially the same operating characteristics as those formed on a single crystal silicon substrate. .

[Embodiment 6] In this embodiment, a manufacturing process of a semiconductor device in which a plurality of circuits and an active matrix liquid crystal display portion are formed over one substrate will be described with reference to FIGS.

The cross-sectional views shown in FIGS. 3 and 4 are composed of a first region, a second region and a third region.
The first region is a circuit block (e.g., CPU, signal line drive circuit, etc.) that requires particularly high-speed operation, and is a region for performing the method of crystallizing a semiconductor film using a continuous wave laser in the present invention. Further, the second region shows other circuit blocks (for example, a scanning line driving circuit), and the third region shows a pixel region.

Note that, in FIGS. 3 and 4, an N-channel TFT and a P-channel TFT are represented on behalf of the circuit blocks.
The N-channel TFT (pixel TF
T) and the storage capacity.

As the substrate 5000, a quartz substrate, a silicon substrate, a metal, a substrate, or a stainless steel substrate having an insulating film formed on its surface is used. Alternatively, a plastic substrate having heat resistance that can withstand the processing temperature of this manufacturing process may be used.
In this example, a substrate 5000 made of glass such as barium borosilicate glass or aluminoborosilicate glass was used.

Next, a base film 5001 made of an insulating film such as a silicon oxide film, a silicon nitride film or a silicon oxynitride film is formed on the substrate 5000. The base film 5001 of this embodiment is 2
Although the insulating film has a layered structure, it may have a single layer structure of the insulating film or a structure in which two or more insulating films are laminated.

In this example, as the first layer of the base film 5001, a silicon nitride oxide film 5 formed by using a plasma CVD method using SiH ₄ , NH ₃ and N ₂ O as reaction gases.
001a is 10 to 200 [nm] (preferably 50 to 100)
[nm]). In this embodiment, the silicon nitride oxide film 5001a is formed to a thickness of 50 [nm]. Next, as a second layer of the base film 5001, a silicon oxynitride film 5001b formed by using a plasma CVD method using SiH ₄ and N ₂ O as reaction gases is 50 to 200 [nm] (preferably 100 to 150 [nm]. nm]). In this embodiment, the silicon oxynitride film 5001b is formed to a thickness of 100 [nm].

Subsequently, the semiconductor layer 50 is formed on the base film 5001.
02 to 5006, 6002 and 6003 are formed. The semiconductor layers 5002 to 5005, 6002, and 6003 are known means (sputtering method, LPCVD method, plasma CVD method, etc.)
Thus, a semiconductor film is formed with a thickness of 25 to 80 [nm] (preferably 30 to 60 [nm]). As the semiconductor film,
A compound semiconductor film having an amorphous structure such as an amorphous semiconductor film, a microcrystalline semiconductor film, a crystalline semiconductor film, or an amorphous silicon germanium film may be used.

Next, the first crystallization is performed on the semiconductor film in the second region and the third region, or in the entire region of the substrate. As the first crystallization method, use of a known crystallization method (laser crystallization method, thermal crystallization method using RTA or furnace annealing, thermal crystallization method using a metal element that promotes crystallization, etc.) You can

In this example, an amorphous silicon film having a film thickness of 55 [nm] was formed by the plasma CVD method. And
As a first crystallization method, a solution containing nickel is held on an amorphous silicon film, and this amorphous silicon film is dehydrogenated (50
After performing 0 [℃] for 1 hour, thermal crystallization (550 [℃], 4
Time) to form a first crystalline silicon film.

When the first crystalline semiconductor film is formed by the laser crystallization method, only the second region and the third region may be selectively formed, or the semiconductor film over the entire substrate may be formed. Alternatively, crystallization may be performed. As the laser, a pulsed gas laser or a solid-state laser may be used. Examples of the former gas laser include excimer laser, YAG laser, and YVO.
₄ laser, YLF laser, YAlO ₃ laser, glass laser, ruby laser, Ti: sapphire laser, etc. can be used. As the latter solid-state laser, Cr,
A laser using a crystal of YAG, YVO ₄ , YLF, YAlO ₃ or the like doped with Nd, Er, Ho, Ce, Co, Ti or Tm can be used. The fundamental wave of the laser depends on the doping material and is 1 [μ
A laser beam having a fundamental wave around m] can be obtained. The harmonic wave with respect to the fundamental wave can be obtained by using a non-linear optical element.

The crystallization conditions are appropriately set. When an excimer laser is used, the pulse oscillation frequency is 300 [Hz] and the laser energy density is 100 to 700 [mJ / cm ² ].
(Typically, 200 to 300 [mJ / cm ² ]) is recommended. When a YAG laser is used, its second harmonic is used to set the pulse oscillation frequency to 1 to 300 [Hz] and the laser energy density to 300 to 1000 [mJ / cm ² ] (typically 350 to 500 [ mJ / cm ² ]) is good. And width 10
A linearly focused laser beam of 0 to 1000 [μm] (preferably a width of 400 [μm]) is radiated over the entire surface of the substrate, and the overlapping ratio (overlap ratio) of the linear beams at this time is 50.
~ 98 [%] may be used.

Then, second crystallization is performed on the semiconductor film in the first region. In the second crystallization method, crystallization using a continuous wave laser is performed. As a crystallization method using a continuous wave laser, the methods shown in Examples 2 and 3 can be used. Thus, the second crystalline silicon is obtained.

By such a crystallization process of the semiconductor film, the first crystalline silicon film is formed in the first region including the circuit logic which is required to operate at high speed, and the second crystalline film is formed in the other regions. Silicon films are formed respectively.

Since the first crystalline silicon film extends in the relative scanning direction of the laser beam and large crystal grains are formed, the first crystalline silicon film is used as an active layer. TF to have
T has high electrical characteristics. In particular, when the channel direction is formed substantially parallel to the relative scanning direction of the laser light, the number of times the carriers cross the crystal grain boundary can be extremely reduced, and therefore, it is formed on the single crystal silicon. It is also possible to achieve the same electrical characteristics as a transistor.

On the other hand, since the continuous wave laser has a narrow beam width (50 to 500 μm), applying this crystallization process to a wide region is disadvantageous from the viewpoint of throughput. In the present invention, the throughput is improved by limiting the crystallization using the continuous wave laser to a limited region on the substrate.

Next, the semiconductor layers 5002 to 5005, 6 are formed by a patterning process using the photolithography method.
002 and 6003 were formed.

In this example, since the amorphous silicon film was crystallized by using the metal element that promotes crystallization, the metal element remains in the crystalline silicon film. Therefore, an amorphous silicon film having a thickness of 50 to 100 [nm] is formed on the crystalline silicon film, and a heat treatment (RTA method, thermal annealing using a furnace annealing furnace, etc.) is performed to perform the amorphous silicon film. The metal element is diffused therein, and the amorphous silicon film is removed by etching after the heat treatment. As a result, the content of the metal element in the first crystalline silicon film can be reduced or removed.

The semiconductor layers 5002 to 5005, 600
After forming 2,6003, a slight amount of impurity element (boron or phosphorus) may be doped to control the threshold value of the TFT.

Then, the semiconductor layers 5002 to 5005, 6
A gate insulating film 5006 which covers 002 and 6003 is formed. The gate insulating film 5006 is formed of an insulating film containing silicon with a thickness of 40 to 150 [nm] by a plasma CVD method or a sputtering method. In this embodiment, the gate insulating film 50
As the silicon oxide oxynitride film 06, the silicon oxynitride film 1
It was formed to a thickness of 10 [nm]. Of course, the gate insulating film 500
6 is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a laminated structure.

When a silicon oxide film is used as the gate insulating film 5006, TEOS (Tet (Tet)
Raethyl Orthosilicate) and O ₂ are mixed, and reaction pressure is 4
0 [Pa], substrate temperature 300-400 [° C], high frequency (1
It may be formed by discharging at a power density of 0.5 to 0.8 [W / cm ² ]. The silicon oxide film manufactured through the above steps can be provided with favorable characteristics as the gate insulating film 5006 by subsequent thermal annealing at 400 to 500 [° C.].

Then, a film having a thickness of 2 is formed on the gate insulating film 5006.
A first conductive film 5007 having a thickness of 0 to 100 [nm] and a film thickness of 100
A second conductive film 5008 having a thickness of 400 [n] m is formed by lamination. In this embodiment, a first conductive film 5007 made of a TaN film having a film thickness of 30 nm and a second conductive film 5008 made of a W film having a film thickness of 370 nm are laminated and formed.

In this embodiment, the TaN film which is the first conductive film 5007 is formed by the sputtering method, and is formed by using the Ta target in the atmosphere containing nitrogen.
The W film which is the second conductive film 5008 was formed by a sputtering method using a W target. Alternatively, it can be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ).

Note that in this embodiment, the first conductive film 5007 is used.
Was used as the TaN film and the second conductive film 5008 was used as the W film, but the materials forming the first conductive film 5007 and the second conductive film 5008 are not particularly limited. The first conductive film 5007 and the second conductive film 5008 are formed of Ta, W, Ti, Mo, A.
It may be formed of an element selected from 1, Cu, Cr, and Nd, or an alloy material or a compound material containing the above element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus or an AgPdCu alloy may be used.

Next, a mask 5009 made of a resist is formed by photolithography, and a first etching treatment for forming electrodes and wirings is performed. The first etching process is performed under the first and second etching conditions. (Fig. 3 (B))

In this embodiment, as the first etching condition, ICP (Inductively Coupled Plasma) etching method is used, and C is used as an etching gas.
Using F ₄ , Cl ₂ and O ₂ , each gas flow rate ratio is set to 2
At 5:25:10 [sccm], RF (13.56 [MHz]) RF of 500 [W] is applied to the coil type electrode at a pressure of 1.0 [Pa] to generate plasma for etching. went. Also on the substrate side (sample stage) is 150 [W] RF (13.56 [MH]
z]) Power was applied and a substantially negative self-bias voltage was applied. Then, the W film was etched under the first etching condition to make the end portion of the first conductive layer 5007 tapered.

Subsequently, a mask 5009 made of resist
Was changed to the second etching condition without removing the gas, CF ₄ and Cl ₂ were used as etching gases, and the respective gas flow ratios were set to 30:30 [sccm] and the pressure was 1.0 [Pa]. An RF (13.56 [MHz]) power of 500 [W] was applied to the coil type electrode to generate plasma, and etching was performed for about 15 seconds. 20 [W] RF (1
(3.56 [MHz]) was applied and a substantially negative self-bias voltage was applied. Under the second etching conditions, the first conductive layer 5007 and the second conductive layer 5008 were etched to the same degree. Note that in order to perform etching without leaving a residue on the gate insulating film 5006, 10 to 20
It is advisable to increase the etching time at a rate of about [%].

In the above-mentioned first etching treatment, the shape of the mask made of resist is made suitable, and the first conductive layer 5007 and the second conductive layer 5008 are formed by the effect of the bias voltage applied to the substrate side. End has a tapered shape. Thus, the first shape conductive layers 5010 to 5014, 6010 including the first conductive layer 5007 and the second conductive layer 5008 are formed by the first etching treatment.
6011 was formed. In the gate insulating film 5006, the first shape conductive layers 5010 to 5014 and 601 are formed.
A region not covered with 0, 6011 was etched by about 20 to 50 nm, so that a region having a reduced film thickness was formed.

Next, a mask 5009 made of resist
The second etching process is performed without removing the. (Fig. 3
(C)) In the second etching process, S is used as an etching gas.
Using F ₆ , Cl ₂ and O ₂ , each gas flow rate ratio is 2
It was set to 4:12:24 (sccm), 700 W of RF (13.56 MHz) power was applied to the coil side power at a pressure of 1.3 Pa, plasma was generated, and etching was performed for about 25 seconds. 10W RF (13.56MHz) on the substrate side (sample stage)
Power was applied and a substantially negative self-bias voltage was applied. In this way, the W film is selectively etched to form the second shape conductive layers 5015 to 5019, 6015, and 6016.
Was formed. At this time, the first conductive layers 5015a-50
18a, 6015a, and 6016a are hardly etched.

Then, a mask 5009 made of resist
The first doping process is performed without removing the
An impurity element imparting N-type is added to 002 to 5005, 6002, and 6003 at a low concentration. The first doping treatment may be performed by an ion doping method or an ion implantation method. The condition of the ion doping method is that the dose amount is 1 × 10 ^{13 to} 5 × 10 5.
¹⁴ [atoms / cm ² ] and the acceleration voltage is 40 to 80 [keV]. In this embodiment, the dose amount is 5.0 × 10 ¹³ [atoms / c
m ² ], and the acceleration voltage was 50 [keV]. As the impurity element imparting N-type, an element belonging to Group 15 may be used, and typically phosphorus (P) or arsenic (As) is used. In this embodiment, phosphorus (P) was used. In this case, the second shape conductive layers 5015 to 5019, 6015, 60
16 serves as a mask for the impurity element imparting N-type and serves as a first impurity region (N--region) 5020 in a self-aligned manner.
~ 5023, 6020, 6021 were formed. Then, the first impurity regions 5020 to 5023, 6020, and 602
1 was added with an impurity element imparting N-type in the concentration range of 1 × 10 ¹⁸ to 1 × 10 ²⁰ [atoms / cm ³ ].

Subsequently, after removing the mask 5009 made of resist, a new mask 5024 made of resist is formed, and the second doping process is performed at an acceleration voltage higher than that in the first doping process. The condition of the ion doping method is that the dose amount is 1 × 10 ^{13 to} 3 × 10 ¹⁵ [atoms / cm ² ],
The acceleration voltage is set to 60 to 120 [keV]. In this embodiment, the dose amount is 3.0 × 10 ¹⁵ [atoms / cm ² ] and the acceleration voltage is 65 [keV]. The second doping process is performed on the second conductive layers 5015b to 5018b, 6015b,
By using 6016b as a mask for the impurity element, the first conductive layers 5015a to 5018a, 6015a, 60
Doping is performed so that the impurity element is added to the semiconductor layer below the tapered portion 16a. Subsequently, the acceleration voltage is lowered from the second doping process and the third doping process is performed to obtain the state of FIG. The condition of the ion doping method is that the dose amount is 1 × 10 ¹⁵ to 1 × 10 ¹⁷ [atoms / cm ² ] and the acceleration voltage is 50 to 100 keV.

As a result of performing the above-mentioned second doping treatment and third doping treatment, a second conductive layer overlapping the first conductive layer is formed.
Impurity regions (N-region, Lov region) 5026, 6026
N in the concentration range of 1 × 10 ^{18 to} 5 × 10 ¹⁹ [atoms / cm ³ ].
An impurity element that imparts mold is added. Further, the third impurity regions (N + regions) 5025, 5028, and 6025 have 1
An impurity element imparting N-type was added within a concentration range of × 10 ^{19 to} 5 × 10 ²¹ [atoms / cm ³ ]. After performing the first and second doping treatments, the semiconductor layers 5002 to 500
5, 6002 and 6003, a region to which no impurity element was added or a region to which a trace amount of impurity element was added was formed. In this embodiment, regions to which no impurity element is added or regions to which a trace amount of impurity element is added are referred to as channel regions 5027, 5030, and 6027. Also, the first impurity regions (N--regions) 5020 to 5023, 6020, 60 formed by the first doping process.
Resist 5 in the second doping process out of 21
Although there is a region covered with 024, in the present embodiment, the first impurity region (N--region, LDD region) 5 is continued.
Call it 029.

In this embodiment, the second impurity regions (N− regions) 5026, 6 are formed only by the second doping process.
026 and the third impurity region (N + region) 5025, 50
28 and 6025 are formed, but are not limited thereto. It may be formed by performing the doping process a plurality of times by appropriately changing the conditions for performing the doping process.

Next, as shown in FIG. 4A, after removing the resist mask 5024, a new resist mask 5031 is formed. After that, a fourth doping process is performed. A fourth impurity region (P + region) in which an impurity element imparting a conductivity type opposite to that of the first conductivity type is added to the semiconductor layer which becomes the active layer of the P-channel TFT by the fourth doping process. 5032, 5034, 6
032 and the fifth impurity region (P− region) 5033, 50
35 and 6033 are formed.

In the fourth doping process, the second conductive layers 5016b and 5018b are used as a mask for the impurity element. Thus, the impurity element imparting P-type conductivity is added, and the fourth impurity region (P + region) 503 is self-aligned.
2, 5034, 6032 and fifth impurity regions (P− regions) 5033, 5035, 6033 are formed.

In this embodiment, the fourth impurity region 503 is used.
2, 5034, 6032 and fifth impurity region 503
3, 5035 and 6033 are formed by an ion doping method using diborane (B ₂ H ₆ ). As conditions for the ion doping method, the dose amount was 1 × 10 ¹⁶ [atoms / cm ² ], and the acceleration voltage was 80 [keV].

In the fourth doping process, N
The semiconductor layer forming the channel type TFT is covered with a mask 5031 made of resist.

Here, the fourth impurity regions (P + regions) 5032 and 503 are formed by the first and second doping processes.
4, 6032 and fifth impurity region (P-region) 503
Phosphorus is added to 3, 5035, and 6033 at different concentrations. However, in any of the fourth impurity regions (P + regions) 5032, 5034, 6032 and the fifth impurity regions (P− regions) 5033, 5035, 6033, P-type is imparted by the fourth doping process. The concentration of the impurity element is 1 × 10 ^{19 to} 5 × 10 ²¹
Doping treatment is performed so that [atoms / cm ³ ]. Thus, the fourth impurity regions (P + regions) 5032, 503
4, 6032 and fifth impurity region (P-region) 503
3, 5035 and 6033 function as a source region and a drain region of the P-channel TFT without any problem.

In this embodiment, the fourth impurity regions (P + regions) 5032, 5 are formed only by the fourth doping process.
034, 6032 and fifth impurity region (P− region) 50
33, 5035, and 6033 are formed, but the present invention is not limited to this. It may be formed by performing the doping process a plurality of times by appropriately changing the conditions for performing the doping process.

Next, as shown in FIG. 4B, the mask 5031 made of resist is removed to remove the first interlayer insulating film 50.
36 is formed. The first interlayer insulating film 5036 is formed of an insulating film containing silicon with a thickness of 100 to 200 [nm] by a plasma CVD method or a sputtering method. In this embodiment, a film thickness of 100 is formed by the plasma CVD method.
A [nm] silicon oxynitride film was formed. Of course, the first interlayer insulating film 5036 is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a laminated structure.

Then, as shown in FIG. 4C, heat treatment is performed.
(Heat treatment) is performed to recover the crystallinity of the semiconductor layer and activate the impurity element added to the semiconductor layer. This heat treatment is performed by a thermal annealing method using a furnace annealing furnace.
The thermal annealing method is 400 to 70 in a nitrogen atmosphere having an oxygen concentration of 1 [ppm] or less, preferably 0.1 [ppm] or less.
It may be performed at 0 [° C.], and in this embodiment, the activation treatment was performed by heat treatment at 410 [° C.] for 1 hour. In addition to the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.

Further, heat treatment may be performed before forming the first interlayer insulating film 5036. However, the first conductive layers 5015a to 5019a, 6015a, and 6016a and the second conductive layers 5015b to 5019b and 6015 are included.
When the material forming the b and 6016b is weak to heat, the first interlayer insulating film 5036 (insulating film containing silicon as a main component, for example, a silicon nitride film) is used to protect wirings and the like as in this embodiment. Heat treatment is preferably performed after the formation.

As described above, the first interlayer insulating film 5036
By performing heat treatment after forming (an insulating film containing silicon as a main component, for example, a silicon nitride film), at the same time as the activation treatment,
Hydrogenation of the semiconductor layer can also be performed. In the hydrogenation step, dangling bonds in the semiconductor layer are terminated by hydrogen contained in the first interlayer insulating film 5036.

Note that heat treatment for hydrogenation may be performed separately from heat treatment for activation treatment.

Here, the semiconductor layer can be hydrogenated regardless of the presence of the first interlayer insulating film 5036. As another means of hydrogenation, a means using plasma-excited hydrogen (plasma hydrogenation) or an atmosphere containing 3 to 100% of hydrogen at 300 to 450 [° C.] is 1 to 1: 1.
Means for performing heat treatment for 2 hours may be used.

Next, on the first interlayer insulating film 5036,
A second interlayer insulating film 5037 is formed. An inorganic insulating film can be used as the second interlayer insulating film 5037. For example, a silicon oxide film formed by the CVD method, a silicon oxide film applied by the SOG (Spin On Glass) method, or the like can be used. An organic insulating film can be used as the second interlayer insulating film 5037.
For example, a film of polyimide, polyamide, BCB (benzocyclobutene), acrylic, or the like can be used. Alternatively, a stacked structure of an acrylic film and a silicon oxynitride film may be used.

In this example, an acrylic film having a thickness of 1.6 [μm] was formed. The second interlayer insulating film 5037 reduces unevenness due to the TFT formed on the substrate 5000,
It can be flattened. In particular, the second interlayer insulating film 50
Since 37 has a strong meaning of flattening, a film having excellent flatness is preferable.

Then, the second interlayer insulating film 5037, the first interlayer insulating film 5036, and the gate insulating film 5006 are etched by dry etching or wet etching, and the third impurity regions 5025, 5028, and 6 are etched.
025 fourth impurity regions 5032, 5034, 6032
Contact hole is formed.

Subsequently, wirings 5038 to 5041, 6038 and 6039 which are electrically connected to the respective impurity regions are provided.
And a pixel electrode 5042 is formed. These wirings are formed by patterning a laminated film of a Ti film having a film thickness of 50 nm and an alloy film (alloy film of Al and Ti) having a film thickness of 500 nm. Of course, the structure is not limited to the two-layer structure, and may be a single-layer structure or a laminated structure of three or more layers. The wiring material is not limited to Al and Ti. For example, Ta
An Al film or a Cu film may be formed on the N film, and a laminated film having a Ti film formed thereon may be patterned to form the wiring, but it is preferable to use a material having excellent reflectivity.

Subsequently, an alignment film 5043 is formed on a portion including at least the pixel electrode 5042 and rubbing treatment is performed. In this embodiment, before forming the alignment film 5043, a columnar spacer 5045 for holding the space between the substrates is formed at a desired position by patterning an organic resin film such as an acrylic resin film. Further, spherical spacers may be dispersed over the entire surface of the substrate instead of the columnar spacers.

Next, a counter substrate 5046 is prepared. A colored layer (color filter) 5047 is formed on the counter substrate 5046.
˜5049, a planarization film 5050 is formed. At this time,
The first colored layer 5047 and the second colored layer 5048 are overlapped with each other to form a light-blocking portion. Further, the first coloring layer 5047 and the third coloring layer 5049 may be partially overlapped with each other to form a light-shielding portion, or the second coloring layer 5048 and the third coloring layer 50 may be formed.
It is also possible to form a light shielding part by partially overlapping with 49.

As described above, it is possible to reduce the number of steps by shielding the gaps between the pixels with the light-shielding portion formed of the stacked colored layers without newly forming a light-shielding layer.

Next, a counter electrode 5051 made of a transparent conductive film was formed on at least the flattening film 5050 in at least the pixel region, an alignment film 5052 was formed on the entire surface of the counter substrate, and a rubbing treatment was performed.

The active matrix substrate on which the pixel region and the driving circuit are formed and the counter substrate are sealed with a sealing material 50.
Stick together at 44. A filler is mixed in the sealing material 5044, and the two substrates are bonded to each other with a uniform interval by the filler and the columnar spacers. After that, a liquid crystal material 5053 is injected between both substrates and completely sealed with a sealant (not shown). Liquid crystal material 505
A known liquid crystal material may be used for 3. Thus, the liquid crystal display device shown in FIG. 4D is completed. Then, if necessary, the active matrix substrate or the counter substrate is cut into a desired shape. Furthermore, a polarizing plate and an FPC
(Not shown) was attached.

As described above, by making the activation process of the semiconductor film different between the region requiring high speed operation and the region not requiring high speed operation, a semiconductor device having high speed operation as a whole device can be manufactured by a high throughput manufacturing process. It becomes possible to produce.

In particular, in the first region (the region having a circuit block which requires high-speed operation), crystallization using a continuous wave laser is performed to form a semiconductor in which large-sized crystal grains are formed. A TFT having a film is manufactured to realize a circuit block that can operate at high speed.

Note that the TFT manufactured in this embodiment may have a bottom gate structure or a dual gate structure. [Embodiment 7] In this embodiment, a manufacturing process of a substrate in which a circuit block including a thin film transistor and an EL display portion are formed over the same substrate will be described.

Note that the steps up to FIG.
3A to 3D and the process shown in FIG. 4A.

The same parts as those in FIGS. 3 and 4 are designated by the same reference numerals, and the description thereof will be omitted.

As shown in FIG. 5A, a first interlayer insulating film 5101 is formed. This first interlayer insulating film 5101
As a plasma CVD method or a sputtering method,
It is formed of an insulating film containing silicon with a thickness of 100 to 200 nm. In this embodiment, the film thickness is 10 by the plasma CVD method.
A 0 nm silicon oxynitride film was formed. Of course, the first interlayer insulating film 5101 is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a laminated structure.

Next, as shown in FIG. 5B, heat treatment (heat treatment) is performed to recover the crystallinity of the semiconductor layer and activate the impurity element added to the semiconductor layer. This heat treatment is performed by a thermal annealing method using a furnace annealing furnace. As the thermal annealing method, the oxygen concentration is 400 to 70 in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less.
The activation treatment may be performed at 0 ° C., and in this embodiment, the heat treatment is performed at 410 ° C. for 1 hour. In addition to the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.

Heat treatment may be performed before forming the first interlayer insulating film 5101. However, the first conductive layers 5015a to 5019a and the second conductive layer 5015b.
If 5050b is weak to heat, heat treatment is performed after the first interlayer insulating film 5101 (insulating film containing silicon as a main component, for example, a silicon nitride film) is formed to protect wirings and the like as in this embodiment. Is preferably performed.

As described above, the first interlayer insulating film 5101
By performing heat treatment after forming (an insulating film containing silicon as a main component, for example, a silicon nitride film), hydrogenation of the semiconductor layer can be performed at the same time as the activation process. In the hydrogenation step, dangling bonds in the semiconductor layer are terminated by hydrogen contained in the first interlayer insulating film 5001.

Note that heat treatment for hydrogenation may be performed separately from heat treatment for activation treatment.

Here, the semiconductor layer can be hydrogenated regardless of the existence of the first interlayer insulating film 5101. As another means of hydrogenation, a means using hydrogen excited by plasma (plasma hydrogenation) or 1 to 12 at 300 to 450 ° C. in an atmosphere containing 3 to 100% hydrogen is used.
Means for performing heat treatment for a time may be used.

Through the above steps, a CMOS including an N-channel TFT and a P-channel TFT is formed in the lower region of the pixel.
A circuit can be formed.

Next, on the first interlayer insulating film 5101,
A second interlayer insulating film 5102 is formed. An inorganic insulating film can be used as the second interlayer insulating film 5102. For example, a silicon oxide film formed by the CVD method, a silicon oxide film applied by the SOG (Spin On Glass) method, or the like can be used. An organic insulating film can be used as the second interlayer insulating film 5102. For example, a film of polyimide, polyamide, BCB (benzocyclobutene), acrylic, or the like can be used. Alternatively, a stacked structure of an acrylic film and a silicon oxide film may be used. Alternatively, a stacked-layer structure of an acrylic film and a silicon nitride film or a silicon nitride oxide film formed by a sputtering method may be used.

Next, the first interlayer insulating film 5101, the second interlayer insulating film 5102, and the gate insulating film 5006 are etched by dry etching or wet etching, and the impurity regions (third regions) of the TFTs forming the circuit block are formed. Impurity region (N +) and the fourth impurity region (P
+)) To form a contact hole.

Then, wirings 5103 to 5109, 6103, 610 electrically connected to the respective impurity regions are provided.
4 is formed. Note that in this embodiment, the wirings 5103 to 51
09, 6103, and 6104 are formed by continuously forming a laminated film of a Ti film having a film thickness of 100 nm, an Al film having a film thickness of 350 nm, and a Ti film having a film thickness of 100 nm by a sputtering method, and patterning into a desired shape. .

Of course, the structure is not limited to the three-layer structure, and may be a single-layer structure, a two-layer structure, or a laminated structure of four or more layers. The material of the wiring is not limited to Al and Ti, but other conductive films may be used. For example, wiring may be formed by forming Al or Cu on the TaN film and then patterning the laminated film on which the Ti film is formed.

Next, as shown in FIG. 5C, a third interlayer insulating film 5110 is formed. Third interlayer insulating film 511
As 0, an inorganic insulating film or an organic insulating film can be used. As the inorganic insulating film, a silicon oxide film formed by a CVD method, a silicon oxide film applied by an SOG (Spin On Glass) method, or the like can be used. Also,
An acrylic resin film or the like can be used as the organic insulating film. Alternatively, a stacked-layer structure of an acrylic film and a silicon nitride film or a silicon nitride oxide film formed by a sputtering method may be used.

By the third interlayer insulating film 5110, unevenness due to the TFT formed on the substrate 5000 can be alleviated and planarized. In particular, the third interlayer insulating film 511
Since 0 has a strong meaning of flattening, a film having excellent flatness is preferable.

Next, by dry etching or wet etching, a contact hole reaching the wiring 5108 is formed in the third interlayer insulating film 5110.

Next, the conductive film is patterned to form a pixel electrode 5111. In this embodiment, an alloy film of aluminum and lithium is used as the conductive film. Of course, a known MgAg film (alloy film of magnesium and silver) may be used. The pixel electrode 5111 corresponds to the cathode of the EL element. As the cathode material, a conductive film made of an element belonging to Group 1 or 2 of the periodic table or a conductive film to which those elements are added can be freely used.

The pixel electrode 5111 is the third interlayer insulating film 5
The wiring 5 is formed by the contact hole formed in 110.
An electrical connection is made with 108. In this way, the pixel electrode 5111 is electrically connected to one of the source region and the drain region of the TFT included in the driver circuit.

Next, as shown in FIG. 5D, a bank 5112 is formed in order to paint the EL layer between each pixel separately. The bank 5112 is formed using an inorganic insulating film or an organic insulating film. As the inorganic insulating film, a silicon nitride film or a silicon nitride oxide film formed by a sputtering method, CV
A silicon oxide film formed by the D method, a silicon oxide film applied by the SOG method, or the like can be used. An acrylic resin film or the like can be used as the organic insulating film.

Here, when forming the bank 5112, it is possible to easily form a tapered side wall by using a wet etching method. If the side wall of the bank 5112 is not sufficiently gentle, the deterioration of the EL layer due to the step difference becomes a significant problem, so caution is required.

Third interlayer insulating film 5110 and bank 5112
An example of the combination of is given below.

As the third interlayer insulating film 5110, a laminated film of acrylic and a silicon nitride film or silicon oxynitride film formed by a sputtering method is used.
There is a combination of using a silicon nitride film or a silicon oxynitride film formed by a sputtering method. A silicon oxide film formed by a plasma CVD method is used as the third interlayer insulating film 5110, and a plasma CVD is also used as the bank 5112.
There is a combination using a silicon oxide film formed by the method. Further, there is a combination in which a silicon oxide film formed by the SOG method is used as the third interlayer insulating film 5110 and a silicon oxide film formed by the SOG method is used as the bank 5112. Further, as the third interlayer insulating film 5110,
Silicon oxide film formed by SOG method and plasma CVD
Using a laminated film of silicon oxide films formed by the
There is a combination in which a silicon oxide film formed by a plasma CVD method is used as 112. In addition, there is a combination in which acrylic is used as the third interlayer insulating film 5110 and acrylic is used as the bank 5112. Further, as the third interlayer insulating film 5110, acrylic and plasma CVD are used.
Using a laminated film of silicon oxide films formed by the
There is a combination in which a silicon oxide film formed by a plasma CVD method is used as 112. Further, there is a combination in which a silicon oxide film formed by a plasma CVD method is used as the third interlayer insulating film 5110 and acrylic is used as the bank 5112.

Carbon particles or metal particles may be added to the bank 5112 to lower the resistivity and suppress the generation of static electricity. At this time, the resistivity is 1 × 10 ⁶ to 1 × 10 ¹² Ωm
The addition amount of carbon particles or metal particles may be adjusted so as to be (preferably 1 × 10 ⁸ to 1 × 10 ¹⁰ Ωm).

Next, an EL layer 5113 is formed on the exposed pixel electrode 5038 surrounded by the bank 5112.

As the EL layer 5113, a known organic light emitting material or inorganic light emitting material can be used.

As the organic light emitting material, a low molecular weight organic light emitting material, a high molecular weight organic light emitting material, or a medium molecular weight organic light emitting material can be freely used. In the present specification,
The medium-molecular-weight organic light-emitting material means an organic light-emitting material which has no sublimability and has a number of molecules of 20 or less or a chained molecule length of 10 μm or less.

The EL layer 5113 usually has a laminated structure.
Typically, Kodak Eastman Company Ta
The laminated structure of “hole transport layer / light emitting layer / electron transport layer” proposed by ng et al. In addition, an electron transport layer / a light emitting layer / a hole transport layer / a hole injection layer, or an electron injection layer / an electron transport layer / a light emitting layer / a hole transport layer / a hole injection layer are laminated in this order on the cathode. The structure is fine. You may dope a fluorescent dye etc. with respect to a light emitting layer. However, the charge excited state before light emission may be triplet or singlet.

Further, in the present specification, the light-emitting element refers to one that utilizes light emission (fluorescence) at the time of transition from singlet excitons to the ground state and that at the time of transition from triplet excitons to the ground state. Both of those utilizing luminescence (phosphorescence) are shown.

[0258] In this embodiment, the EL layer 5113 is formed using a low molecular weight organic light emitting material by an evaporation method. Specifically, a 70 nm thick tris-8-quinolinolato aluminum complex (Alq ₃ ) film is provided as a light emitting layer, and on top of that,
20 nm thick copper phthalocyanine (CuP) as a hole injection layer
c) It has a laminated structure provided with a film. The emission color can be controlled by adding a fluorescent dye such as quinacridone, perylene or DCM1 to Alq ₃ .

Although only one pixel is shown in FIG. 5D, a plurality of colors such as R (red), G (green), and B are used.
The EL layer 5113 corresponding to each color of (blue) can be separately formed.

As an example of using a polymer organic light emitting material, as a hole injecting layer, polythiophene (PE) having a thickness of 20 nm is used.
A DOT film is provided by a spin coating method, and a polyphenylene vinylene (PP) film having a thickness of about 100 nm is formed thereon as a light emitting layer.
V) or PPV derivative film has a laminated structure
The layer 5113 may be formed. Note that the emission wavelength can be selected from red to blue by using PPV or a derivative of PPV which is a π-conjugated polymer. It is also possible to use an inorganic material such as silicon carbide for the electron transport layer and the electron injection layer.

Note that the EL layer 5113 is not limited to a layer in which a hole injecting layer, a hole transporting layer, a light emitting layer, an electron transporting layer, an electron injecting layer, or the like has a clearly distinguished laminated structure. That is, the EL layer 5113 may have a structure including a layer in which materials forming the hole injecting layer, the hole transporting layer, the light emitting layer, the electron transporting layer, the electron injecting layer, and the like are mixed.

For example, a mixed layer composed of a material forming the electron transport layer (hereinafter referred to as an electron transport material) and a material forming the light emitting layer (hereinafter referred to as a light emitting material) is used as an electron transport layer. E having a structure between the layer and the light emitting layer
It may be the L layer 5113.

Next, a pixel electrode 5114 made of a transparent conductive film is formed on the EL layer 5113. As the transparent conductive film, a compound of indium oxide and tin oxide (IT
O), a compound of indium oxide and zinc oxide, zinc oxide,
Tin oxide, indium oxide, or the like can be used. Moreover, you may use what added the gallium to the said transparent conductive film. The pixel electrode 5114 corresponds to the anode of the EL element.

[0264] When the pixel electrode 5114 is formed, E
The L element is completed. Note that an EL element means a pixel electrode (cathode) 5111, an EL layer 5113, and a pixel electrode (anode) 5
Refers to the diode formed at 114.

It is effective to provide a protective film (passivation film) 5115 so as to completely cover the EL element. The protective film 5115 is formed of an insulating film including a carbon film, a silicon nitride film, or a silicon nitride oxide film, and the insulating film can be used as a single layer or a stacked layer in which they are combined.

When the light emitted from the EL element is emitted from the pixel electrode 5114 side as in this embodiment, the protective film 5 is used.
It is necessary to use a film that transmits light as 115.

It should be noted that the steps from the formation of the bank 5112 to the formation of the protective film 5115 can be performed continuously by using a multi-chamber type (or in-line type) film forming apparatus without exposing to the atmosphere. It is valid.

In practice, when the state shown in FIG. 5D is completed, a protective film (laminate film, UV curable resin film, etc.) having high airtightness and less degassing is provided so as not to be exposed to the outside air. It is preferable to perform packaging (encapsulation) with a sealing material. At that time, if the inside of the sealing material is made an inert atmosphere or a hygroscopic material (for example, barium oxide) is arranged inside, the EL
The reliability of the device is improved.

When the airtightness is improved by a process such as packaging, a connector (flexible printed circuit: FP) for connecting a terminal routed from an element or circuit formed on the substrate 5000 and an external signal terminal.
C) is attached to complete the product.

Note that the TFT manufactured in this embodiment may have a bottom gate structure or a dual gate structure having two gate electrodes arranged above and below a channel region with an insulating film interposed therebetween.

[Embodiment 8] In this embodiment, an example of the semiconductor device of the present invention will be described with reference to FIG.

In FIG. 16, the semiconductor device includes a pixel region 1600, a scanning line driving circuit 1601, and a signal line driving circuit 1.
602, VRAM 1603, CPU 1604, memory 1
605 and interface circuit 1606 are integrally formed on a substrate having an insulating surface.

The operation of the semiconductor device shown in FIG. 16 will be described. Image data and control signals for external devices are communicated between the CPU 1604 and external devices via the interface circuit 1606 and the system bus 1607.
Examples of the external device include a keyboard and a ROM. The CPU 1604 temporarily stores the image data being processed and the control signal of the logic circuit in the memory 1605, and the processed image data is stored in the VRAM 1603. V
The image data stored in the RAM 1603 is displayed in the pixel region 1600 by the signal line driver circuit 1602 and the scan line driver circuit 1601.

The VRAM is a memory for storing image data and is composed of a volatile memory such as SRAM or DRAM. Also, the memory 1605
Also, a volatile memory such as SRAM or DRAM is used. The interface circuit is a circuit that temporarily stores a signal input from an external device, converts it into a format used internally, and performs other control.

In this embodiment, since the circuit blocks included in the area 1 are required to operate at a high speed in particular, for example, the embodiment 3
A high-mobility TFT manufacturing process using a crystallization process of a semiconductor film using a continuous wave laser as shown in FIGS.

By applying the high mobility TFT manufacturing process to the region 1, the circuit blocks included in the region 1 realize high speed operation.

If SRAM is used as the memory,
The read cycle is 200 nsec, and when the DRAM is used, the read cycle is 1 μsec or less.

The operating frequency of the CPU is 5 MHz or higher.

In this embodiment, the high mobility T is set in the area 1.
Although the FT manufacturing process is applied, the present invention is not limited to this. The practitioner may apply the high-mobility TFT manufacturing process to an arbitrary region according to the application of the semiconductor device.

In that case, the ratio of the area to which the high-mobility TFT manufacturing process is applied to the entire area of the substrate 1608 is preferably 50% or less (preferably 30% or less). Moreover, it is preferable that the region 1 is formed of a small number of rectangular regions (preferably 10 or less).

This embodiment can be used in combination with Embodiments 1 to 7.

[Embodiment 9] In this embodiment, an example of a semiconductor device of the present invention will be described with reference to FIG.

In FIG. 17, the semiconductor device includes a pixel region 1700, a scanning line driving circuit 1701, and a signal line driving circuit 1.
702, a frame memory 1703, a timing generation circuit 1705, and a format conversion unit 1704 are integrally formed on a substrate having an insulating surface.

The configuration of this embodiment will be described below.

The timing generation circuit 1705 generates a clock signal which determines the operation timing of the scanning line drive circuit 1701 and the signal line drive circuit 1702. The format conversion unit 1704 performs expansion / decoding of a compression-encoded signal input from an external device via the FPC 1706, image processing such as image interpolation and resizing. The format-converted image data is stored in the frame memory 1703. Then, the image data stored in the frame memory 1703 is displayed on the pixel 1700 by the scan line driver circuit 1701 and the signal line driver circuit 1702.

In this embodiment, the circuit blocks included in the area 1 are required to operate at a particularly high speed.
A high-mobility TFT manufacturing process using a crystallization process of a semiconductor film using a continuous wave laser as shown in FIGS.

When the SRAM is used as the frame memory, the read cycle is 200 nsec, DR
When using AM, the read cycle is 1 μs
ec or less is realized.

In this embodiment, the driving frequency of the logic circuit included in the area 1 is 5 MHz or higher.

In this embodiment, the high mobility T is set in the area 1.
Although the FT manufacturing process is applied, the present invention is not limited to this. The practitioner may apply the high-mobility TFT manufacturing process to an arbitrary region according to the application of the semiconductor device.

In that case, the ratio of the area to which the high-mobility TFT manufacturing process is applied to the entire area of the substrate 1608 is preferably 50% or less (preferably 30% or less). Moreover, it is preferable that the region 2 is formed by a small number of rectangular regions (preferably 10 or less).

This embodiment can be used in combination with Embodiments 1 to 7.

[Embodiment 10] In this embodiment, an example of the semiconductor device of the present invention will be described with reference to FIG.

In FIG. 18, the semiconductor device includes a pixel region 1800, a scanning line driving circuit 1801, and a signal line driving circuit 1.
802, VRAM 1803, mask ROM 1804, arithmetic processing circuit 1805, image processing circuit 1806, memory 1
An interface circuit 807 and an interface circuit 1808 are integrally formed on a substrate having an insulating surface.

The configuration of this embodiment is shown below.

Control signals are communicated with an external device via the interface circuit 1808 and the system bus 1809. The external device may be a keyboard or the like. The mask ROM 1804 stores program data and image data. The data stored in the mask ROM is stored in the memory 180 by the CPU 1805.
It is processed while reading and writing from and to 7 at any time. The image data is subjected to processing such as resizing by the image processing circuit 1806 and stored in the VRAM 1803. VRAM1803
The data stored in (1) is displayed in the pixel region 1800 by the scan line driver circuit 1801 and the signal line driver circuit 1802.

SRAM or DR as memory or VRAM
AM is used.

In this embodiment, the operating frequency of the image processing circuit is 5 MHz or higher. The operating frequency of the CPU is 5 MHz or higher.

In this embodiment, the circuit blocks included in the region 1 are required to operate at a particularly high speed.
A high-mobility TFT manufacturing process using a crystallization process of a semiconductor film using a continuous wave laser as shown in FIGS.

In this embodiment, the high mobility T is set in the area 1.
Although the FT manufacturing process is applied, the present invention is not limited to this. The practitioner may apply the high-mobility TFT manufacturing process to an arbitrary region according to the application of the semiconductor device.

In that case, the ratio of the area to which the high-mobility TFT manufacturing process is applied to the entire area of the substrate 1608 is preferably 50% or less (preferably 30% or less). Moreover, it is preferable that the region 2 is formed by a small number of rectangular regions (preferably 10 or less).

This embodiment can be used in combination with Embodiments 1 to 7.

[Embodiment 11] As electronic equipment using the present invention, a video camera, a digital camera, a goggle type display (head mounted display), a navigation system, a sound reproducing device (car audio, audio component system, etc.), a notebook type personal computer. Computers, game machines, personal digital assistants (mobile computers, mobile phones, hand-held game machines, electronic books, etc.), image reproducing devices equipped with recording media (specifically, Digital Versatile Discs)
(A device equipped with a display capable of reproducing a recording medium such as (DVD) and displaying the image). Specific examples of these electronic devices are shown in FIGS.

FIG. 19A shows a display device, which is a housing 14
01, a support base 1402, and a display unit 1403. The present invention can be applied to a display device having the display portion 1403.

FIG. 19B shows a video camera, which includes a main body 1411, a display portion 1412, a voice input 1413, operation switches 1414, a battery 1415, and an image receiving portion 1416.
Etc. The present invention has a display portion 1412.
It can be applied to a display device having.

FIG. 19C shows a laptop personal computer, which is composed of a main body 1421, a housing 1422, a display portion 1423, a keyboard 1424, and the like. The present invention can be applied to a display device having the display portion 1423.

FIG. 19D shows a portable information terminal, which includes a main body 1431, a stylus 1432, a display portion 1433, operation buttons 1434, an external interface 1435, and the like. The present invention can be applied to a display device having the display portion 1433.

[0307] FIG. 19E shows an audio reproducing device, more specifically, an audio device mounted on a vehicle, which includes a main body 1441, a display portion 1442, operation switches 1443 and 1444, and the like. The present invention can be applied to a display device having the display portion 1442. Further, although the vehicle-mounted audio device is taken as an example this time, it may be used as a portable or home audio device.

FIG. 19F shows a digital camera including a main body 1451, a display portion (A) 1452, an eyepiece portion 1453,
The operation switch 1454, the display portion (B) 1455, the battery 1456, and the like are included. The present invention can be applied to a display device having a display portion (A) 1452 and a display portion (B) 1455.

FIG. 19G shows a mobile phone, which has a main body 14
61, voice output unit 1462, voice input unit 1463, display unit 1464, operation switch 1465, antenna 1466.
Etc. The present invention has a display portion 1464.
It can be applied to a display device having.

A display device used in these electronic devices can use not only a glass substrate but also a heat-resistant plastic substrate. Thereby, the weight can be further reduced.

It should be noted that the examples shown in the present embodiment are just examples and the present invention is not limited to these applications.

This embodiment can be implemented by being freely combined with Embodiment Mode and Embodiments 1 to 7.

[0313]

According to the present invention, a TFT manufacturing process that realizes high mobility is used on a substrate having an insulating surface.
The semiconductor display unit and other circuit blocks are integrally formed.
A crystallization process of a semiconductor active layer using a continuous wave laser is used as a TFT manufacturing process for realizing high mobility.

As a result, a semiconductor device having a display portion which is small in size and has improved reliability in mounting a substrate such as an IC chip is provided, and at the same time, the wiring capacitance is reduced and the circuit characteristics are improved by the integration. A semiconductor device that achieves a high operating frequency is provided.

Further, the present invention is characterized in that the crystallization process by the continuous wave laser is selectively performed only on the circuit block which requires high speed operation. This significantly improves the throughput of the crystallization process without reducing the operation speed of the semiconductor device. In addition, a semiconductor device having a low-cost display portion is provided due to a large reduction in the number of substrates on which IC chips and the like are mounted and high throughput.

[Brief description of drawings]

FIG. 1 is a top view of a semiconductor device of the present invention.

FIG. 2 is a top view of a semiconductor device of the present invention.

3A to 3C are cross-sectional views illustrating a manufacturing process of a TFT included in a semiconductor device of the present invention.

4A to 4C are cross-sectional views showing a manufacturing process of a TFT included in the semiconductor device of the present invention.

5A to 5C are cross-sectional views showing a manufacturing process of a TFT included in a semiconductor device of the present invention.

FIG. 6 is a schematic diagram of an optical system used when irradiating a laser beam.

FIG. 7 is an SEM image of the surface of the crystalline semiconductor film.

FIG. 8 is an SEM image of the surface of the crystalline semiconductor film.

FIG. 9: Raman scattering spectrum of semiconductor film

FIG. 10 is a cross-sectional view showing a manufacturing process of a TFT.

FIG. 11 is a graph showing electrical characteristics of TFT.

FIG. 12 is a cross-sectional view showing a step of crystallizing a semiconductor.

FIG. 13 is a graph showing electrical characteristics of TFT.

FIG. 14 is a graph showing electrical characteristics of TFT.

FIG. 15 is a graph showing electrical characteristics of TFT.

FIG. 16 is a block diagram of a semiconductor device of the present invention.

FIG. 17 is a block diagram of a semiconductor device of the present invention.

FIG. 18 is a block diagram of a semiconductor device of the present invention.

FIG. 19 is an electronic device using the semiconductor display unit of the present invention.

FIG. 20 is a diagram showing a method of irradiating laser light.

FIG. 21 is a block diagram of a conventional semiconductor device.

FIG. 22 is a top view of a semiconductor device of the present invention.

─────────────────────────────────────────────────── ─── Continued Front Page (51) Int.Cl. ⁷ Identification Code FI Theme Coat (Reference) H05B 33/14 H01L 29/78 627G 613B F Term (Reference) 2H092 GA11 JA24 JB22 JB31 MA07 MA13 MA17 MA29 MA30 NA05 NA25 PA01 PA03 PA06 PA07 PA08 RA10 3K007 AB18 DB03 GA00 5F052 AA02 AA11 AA17 AA24 BA01 BA02 BA07 BA18 BB02 BB05 BB07 DA01 DA02 DA03 DB02 DB03 DB07 FA06 FA19 JA01 JA02 DD04 CC15 DD07 CC02 BB04 BB07 BB04 BB01 BB05 BB05 BB05 BB05 BB05 EE01 EE02 EE03 EE04 EE06 EE09 EE14 EE23 EE44 EE45 FF02 FF04 FF09 FF28 FF30 FF36 GG01 GG02 GG13 GG16 GG25 GG28 GG29 GG32 GG34 GG43 GG45 GG47 GG51 HJ01 HJ04 HJ07 HJ12 HJ23 HL01 HL02 HL03 HL04 HL05 HL06 HL11 HL12 HL23 HM15 NN03 NN04 NN22 NN23 NN24 NN27 NN34 NN35 NN36 NN72 NN78 PP01 PP02 PP03 PP05 PP06 PP10 PP13 PP24 PP29 PP34 PP35 QQ04 QQ09 QQ1 1 QQ19 QQ23 QQ24 QQ25

Claims (36)

[Claims] 1. A pixel region, a scanning line drive circuit, and a signal line drive circuit are provided on the same substrate, and a first TFT having a first active layer and a second TFT having a second active layer are provided. The first active layer is formed by irradiating the semiconductor film with an energy beam to form a melt zone, and continuously crystallizing the melt zone by scanning the melt zone in the channel length direction,
The second active layer is formed by crystallizing a semiconductor film by heat treatment, and the pixel region has the second TF.
A semiconductor device comprising T, the scanning line drive circuit is configured by the second TFT, and the signal line drive circuit is configured by the first TFT. 2. A pixel region, a scanning line drive circuit, and a signal line drive circuit are provided on the same substrate, and a first TFT having a first active layer and a second TFT having a second active layer are provided. The first active layer is formed by irradiating the semiconductor film with an energy beam to form a melt zone, and continuously crystallizing the melt zone by scanning the melt zone in the channel length direction,
The second active layer is formed by adding a metal element to a semiconductor film and crystallizing the semiconductor film by heat treatment. The pixel region is formed of the second TFT, and the scanning line driving circuit is formed of the second TFT. A semiconductor device, wherein the signal line drive circuit is configured by the first TFT. 3. The semiconductor device according to claim 1, wherein the energy beam is continuous wave laser light. 4. A pixel region, a scanning line drive circuit, and a signal line drive circuit are provided on the same substrate, and a first TFT having a first active layer and a second TFT having a second active layer are provided. The first active layer is formed by irradiating the semiconductor film with an energy beam to form a melt zone, and continuously crystallizing the melt zone by scanning the melt zone in the channel length direction,
The second active layer is formed by crystallizing a semiconductor film by irradiating it with a pulsed energy beam, the pixel region is formed of the second TFT, and the scanning line driving circuit is formed of the second TFT. A semiconductor device, wherein the signal line drive circuit is configured by the first TFT. 5. The semiconductor device according to claim 4, wherein the energy beam is continuous wave laser light. 6. A pixel area, a scanning line driving circuit, and a signal line driving circuit are provided on the same substrate, and a first TFT having a first active layer and a second TFT having a second active layer are provided. The first active layer is formed of a polycrystalline semiconductor having crystal grains extending in the channel direction, and the second active layer is formed of a polycrystalline semiconductor having crystal grains not extending in the channel direction. A semiconductor device characterized in that a pixel region is composed of the second TFT, the scanning line drive circuit is composed of the second TFT, and the signal line drive circuit is composed of the first TFT. 7. A pixel area, a scanning line driving circuit, and a signal line driving circuit are provided on the same substrate, and a first TFT having a first active layer and a second TFT having a second active layer are provided. The first active layer is formed of a polycrystalline semiconductor having electrical anisotropy in the channel direction, and the second active layer is formed of a polycrystalline semiconductor having no electrical anisotropy in the channel direction. And the pixel region is formed on the second TFT.
The semiconductor device is characterized in that the scanning line driving circuit is composed of the second TFT, and the signal line driving circuit is composed of the first TFT. 8. A pixel region, a scanning line drive circuit, and a signal line drive circuit are provided on the same substrate, and a first TFT having a first active layer and a second TFT having a second active layer are provided. And the first active layer is formed of a polycrystalline semiconductor having electrical anisotropy in the channel direction, and the second active layer has electrical anisotropy in the channel direction more than that of the first active layer. It is formed of a weak polycrystalline semiconductor, the pixel region is composed of the second TFT, the scanning line drive circuit is composed of the second TFT, and the signal line drive circuit is composed of the first TFT. Semiconductor device. 9. A pixel region, a scanning line drive circuit, and a signal line drive circuit are provided on the same substrate, and a first TFT having a first active layer and a second TFT having a second active layer are provided. And the first active layer is formed of a polycrystalline semiconductor having crystal grains extending in the channel direction, a grain diameter in the minor axis direction of 0.5 to 100 μm, and a grain diameter in the major axis direction of 3 to 10000 μm. The second active layer has a crystal grain size of 0.
The pixel region is formed of the second TFT, the scanning line drive circuit is formed of the second TFT, and the signal line drive circuit is formed of the first TFT. A semiconductor device characterized by the above. 10. The driving frequency of the scanning line driving circuit according to claim 1, wherein the driving frequency is 1 kHz.
˜1 MHz, and the drive frequency of the signal line drive circuit is 100 kHz to 100 MHz. 11. A pixel region, a scanning line driving circuit, and a signal line driving circuit are provided on the same substrate, a first TFT having a first active layer, and a second TFT having a second active layer.
Wherein the first active layer is formed by irradiating the semiconductor film with an energy beam to form a melt zone, and continuously crystallizing the melt zone by scanning in the channel length direction, The second active layer is formed by crystallizing a semiconductor film by heat treatment, and the pixel region has the second active layer.
The scanning line driving circuit is composed of a TFT
The semiconductor device is characterized in that it is configured by T and the signal line drive circuit is configured by the first TFT. 12. A pixel area, a scanning line driving circuit, and a signal line driving circuit are provided on the same substrate, a first TFT having a first active layer, and a second TFT having a second active layer.
Wherein the first active layer is formed by irradiating the semiconductor film with an energy beam to form a melt zone, and continuously crystallizing the melt zone by scanning in the channel length direction, The second active layer is formed by adding a metal element to a semiconductor film and crystallizing the semiconductor film by heat treatment. The pixel region includes the second TFT, and the scanning line driving circuit includes the first TFT. A semiconductor device, wherein the signal line drive circuit is configured by the first TFT. 13. The method according to claim 11 or 12,
The semiconductor device, wherein the energy beam is continuous wave laser light. 14. A pixel region, a scanning line drive circuit, and a signal line drive circuit are provided on the same substrate, and a first TFT having a first active layer and a second TFT having a second active layer are provided.
Wherein the first active layer is formed by irradiating the semiconductor film with an energy beam to form a melt zone, and continuously crystallizing the melt zone by scanning in the channel length direction, The second active layer is formed by irradiating a semiconductor film with a pulsed energy beam to crystallize the semiconductor film.
The semiconductor device, wherein the pixel region is composed of the second TFT, the scanning line drive circuit is composed of the first TFT, and the signal line drive circuit is composed of the first TFT. 15. The semiconductor device according to claim 14, wherein the energy beam is continuous wave laser light. 16. A pixel region, a scanning line drive circuit, and a signal line drive circuit are provided on the same substrate, and a first TFT having a first active layer and a second TFT having a second active layer are provided.
The first active layer is formed of a polycrystalline semiconductor in which crystal grains extend in the channel direction, and the second active layer is formed of a polycrystalline semiconductor in which crystal grains do not extend in the channel direction, The semiconductor device, wherein the pixel region is composed of the second TFT, the scanning line drive circuit is composed of the first TFT, and the signal line drive circuit is composed of the first TFT. 17. A pixel region, a scanning line drive circuit, and a signal line drive circuit are provided on the same substrate, and a first TFT having a first active layer and a second TFT having a second active layer are provided.
And the first active layer is formed of a polycrystalline semiconductor having electrical anisotropy in the channel direction, and the second active layer has a polycrystalline semiconductor having no electrical anisotropy in the channel direction. And the pixel region is formed by the second TF.
A semiconductor device, wherein the semiconductor device is configured by T, the scanning line drive circuit is configured by the first TFT, and the signal line drive circuit is configured by the first TFT. 18. A pixel area, a scanning line drive circuit, and a signal line drive circuit are provided on the same substrate, and a first TFT having a first active layer and a second TFT having a second active layer are provided.
And the first active layer is formed of a polycrystalline semiconductor having electrical anisotropy in the channel direction, and the second active layer has electrical anisotropy in the channel direction higher than that of the first active layer. Is formed of a weak polycrystalline semiconductor, the pixel region is composed of the second TFT, the scanning line drive circuit is composed of the first TFT, and the signal line drive circuit is composed of the first TFT. Semiconductor device. 19. A pixel area, a scanning line drive circuit, and a signal line drive circuit are provided on the same substrate, and a first TFT having a first active layer and a second TFT having a second active layer are provided.
And the first active layer is made of a polycrystalline semiconductor having crystal grains extending in the channel direction, a grain diameter in the minor axis direction of 0.5 to 100 μm, and a grain diameter in the major axis direction of 3 to 10000 μm. The second active layer is formed of a polycrystalline semiconductor having a crystal grain size of 0.01 μm to 10 μm, the pixel region is formed of the second TFT, and the scan line driving circuit is formed of the first TFT. And the signal line drive circuit is composed of the first TFT. 20. The driving frequency of the scanning line driving circuit according to claim 11,
The semiconductor device is characterized in that the driving frequency of the signal line driving circuit is 100 kHz to 100 MHz. 21. The semiconductor device according to any one of claims 1 to 20, wherein a memory is provided on the same substrate as the pixel region, and the memory is the first T
A semiconductor device comprising an FT. 22. The memory according to claim 21, wherein the memory is SR.
AM, and the read cycle time of the SRAM is 20
A semiconductor device characterized by being 0 nsec or less. 23. The memory according to claim 21, wherein the memory is a DR.
AM, and the read cycle time of the DRAM is 1 μ
A semiconductor device characterized by being less than or equal to sec. 24. The semiconductor device according to claim 1, wherein a CPU is provided on the same substrate as the pixel region in the semiconductor device, and the CPU is the first T
A semiconductor device comprising an FT. 25. The semiconductor device according to claim 24, wherein the operating frequency of the CPU is 5 MHz or higher. 26. The semiconductor device according to any one of claims 1 to 20, wherein an image processing circuit is provided on the same substrate as the pixel region, and the image processing circuit includes the first TFT. A semiconductor device comprising: 27. The semiconductor device according to claim 26, wherein the operating frequency of the image processing circuit is 5 MHz or higher. 28. The semiconductor device according to any one of claims 1 to 20, wherein a DSP is provided on the same substrate as the pixel region, and the DSP is the first T
A semiconductor device comprising an FT. 29. The semiconductor device according to claim 28, wherein the operating frequency of the DSP is 5 MHz or higher. 30. In the semiconductor device according to any one of claims 1 to 20, a timing generation circuit is provided on the same substrate as the pixel region in the semiconductor device, and the timing generation circuit is the first TFT. A semiconductor device comprising: 31. The semiconductor device according to claim 1, wherein the substrate is any one of a plastic substrate, a glass substrate and a quartz substrate. 32. In any one of claims 1 to 31, the area of the circuit constituted by the first TFT is
A semiconductor device, which is 50% or less of the area of the substrate. 33. In any one of claims 1 to 32, the circuit constituted by the first TFT is 1 to 1
A semiconductor device, wherein the semiconductor device is formed in 0 rectangular regions, and the area of the rectangular regions is 50% or less of the area of the substrate. 34. The semiconductor device according to any one of claims 1 to 33, wherein the semiconductor device is a liquid crystal display device. 35. The semiconductor device according to any one of claims 1 to 33, wherein the semiconductor device is a light emitting device. 36. The semiconductor device according to any one of claims 1 to 34, wherein the semiconductor device is selected from a game machine, a video camera, a head-mounted display, a DVD player, a personal computer, a mobile phone, and a car audio. A semiconductor device characterized by being one of the following.