JP2003218323A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device including an SRAM, which has a structure where holding data is not easily destroyed due to an α beam software error. <P>SOLUTION: The semiconductor device includes a memory cell region 100 including the SRAM, a peripheral circuit region 200 including the peripheral circuit of the SRAM and a dummy cell region 300 positioned between the memory cell region and the peripheral circuit region on the same silicon substrate 40. The silicon substrate 40 has a first conductive type (p-type). The memory cell region 100 and the dummy cell region 300 include a first conductive (p-type) first well 42, a second conductive (n-type) second well 44 and a second conductive embedded layer 50. The embedded layer 50 is positioned at least below the first well 42 in contact with the first well, and formed such that the end 50a on the side of the peripheral circuit region 200 is positioned in the dummy cell region 300. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to SRAM (Static Random Access Memory)
The present invention relates to a semiconductor device including.

[0002]

BACKGROUND ART AND PROBLEMS TO BE SOLVED BY THE INVENTION SRA
In M, the problem of α ray soft error is known. The α-ray soft error is a phenomenon in which retained data is destroyed due to α-rays. Specifically, when α rays enter a semiconductor substrate having a depletion layer, electron-hole pairs are generated along the locus. When the generated minority carriers flow into the diffusion layer, the potential of the diffusion layer changes and the information is inverted, and the retained data is destroyed.

An object of the present invention is to provide an SRAM having a structure in which the retained data is less likely to be destroyed by an α ray soft error.
It is to provide a semiconductor device including:

[0004]

In a semiconductor device according to the present invention, a memory cell region including an SRAM, a peripheral circuit region including a peripheral circuit of the SRAM, a memory cell region and the periphery are formed on the same semiconductor substrate. A dummy cell region located between the semiconductor substrate and the circuit region, the semiconductor substrate having a first conductivity type, the memory cell region and the dummy cell region having a first well of a first conductivity type, and a second well. A second well of conductivity type and a buried layer of second conductivity type, wherein the buried layer is formed at least under the first well, in contact with the first well, and the periphery The end on the circuit region side is formed so as to be located in the dummy cell region. Here, the "end portion on the peripheral circuit region side" means a region in which the impurity concentration profile of the buried layer is inclined with respect to the surface of the semiconductor substrate. And, "the end is located in the dummy cell region" means that the end is located outside the boundary between the memory cell region and the dummy cell region as viewed from the memory cell region, and the dummy cell region and It means to be located inside the boundary with the peripheral circuit region.

According to the semiconductor device of the present invention, by having the buried layer, it is possible to prevent the stored data from being destroyed due to the α-ray soft error. The reason will be described later in detail. The buried layer is formed such that the end portion on the peripheral circuit region side is located in the dummy cell region, so that the first well of the first conductivity type is the semiconductor substrate of the first conductivity type. It has a part that contacts with. As a result, the first well can be set to the substrate potential, and the potential of the well can be stabilized.

The semiconductor device according to the present invention can take the forms exemplified below.

(A) The first conductivity type may be p-type and the second conductivity type may be n-type. In the case of such a conductivity type, a soft error due to α rays is particularly likely to occur. According to the present invention, it is possible to prevent a soft error due to α-rays not only in such a conductivity type but also in the opposite conductivity type.

(B) The buried layer may be formed over the entire memory cell region.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view showing a layout of a semiconductor device according to this embodiment. FIG. 2 is a plan view showing the layout of the memory cell. FIG. 3 is an A-A line of FIG.
It is sectional drawing which followed the line. FIG. 4 is a sectional view taken along the line BB of FIG.

The semiconductor device according to the present embodiment has the SRA
The memory cell region 100 including M, the peripheral circuit region 200 including the peripheral circuit of the SRAM, and the dummy cell region 3 located between the memory cell region 100 and the peripheral circuit region 200.
Including 00 and.

First, a well structure of a semiconductor device will be described with reference to FIGS.

In memory cell region 100 and dummy cell region 300, as shown in FIG. 1, first wells 42 and second wells 44 are alternately arranged in the Y direction. The first well 42 and the second well 44 are formed in the first conductivity type (p type in this example) silicon substrate 40. The first well 42 has the first conductivity type (p type). The second well 44 has a second conductivity type (n-type in this example).
Have. Hereinafter, the first well is referred to as a "p well" and the second well is referred to as an "n well". Each well 42 and 4
The upper part of 4 is isolated by the element isolation region 18.

In the peripheral circuit region 200, a p-type well and an n-type well are arranged in a p-type silicon substrate 40 in a predetermined layout. 3 and 4, the n-type third well 46 is shown in the peripheral circuit region 200. The well of the peripheral circuit region 200 is formed by the peripheral circuit element 20.
Various modes can be adopted according to the characteristics and layout. In the illustrated example, the second well (n-well) 44 in the memory cell region 100 and the third well 4 in the peripheral circuit region 200.
6 can be formed in the same ion implantation step. Although not shown, the p-type well formed in the peripheral circuit region 200 is a first well (p well).
It can be formed in the same ion implantation process as 42.

The buried layer 50 is formed in the memory cell region 100.
And the dummy cell region 300. Then, the end portion 50a of the buried layer 50 (peripheral circuit region 200
The side) is located in the dummy cell region 300. Specifically, as shown in FIG. 3 and FIG.
Are formed over the entire memory cell region 100,
Moreover, the end portion 50a of the buried layer 50 has the dummy cell region 300.
It is located outside the center of the inside. Buried layer 50
The formation area of the area corresponds to the area indicated by the broken line in FIG.

The buried layer 50 is composed of a second conductivity type (n type) impurity diffusion layer. The buried layer 50 is located under the p well 42 and the n well 44,
Further, it is in contact with these p well 42 and n well 44. The detailed function of the buried layer 50 will be described later. The buried layer 50 can be formed by ion implantation.

Further, as shown in FIGS. 3 and 4, the buried layer 50 has a gently changing impurity concentration profile at the end 50a thereof. This is for the following reasons. That is, the buried layer 50 is the p well 4
Since the buried layer 50 is formed below the 2 and n wells 44, that is, at a deep position in the silicon substrate 40, the buried layer 50 is formed by performing ion implantation with high energy.
In this ion implantation step, as a resist mask provided in a region where the buried layer 50 is not formed, it is necessary to use a thick film resist that does not penetrate the silicon substrate 40 even when ions are implanted with high energy. However, as shown in FIG. 6, the resist 8 having such a film thickness is formed.
With 0, a taper is inevitably generated at the end. Then, under the influence of the taper formed at the end portion of the resist 80, the buried layer 50 is formed so that the impurity profile is gently inclined at the end portion 50a. As a result, in the region where the formation depth of the buried layer 50 is not constant, that is, in the transistor formed on the end portion 50a of the buried layer 50, since the formation depth of the buried layer 50 is not constant, the threshold value of the transistor is It will be affected by variations. In the present invention, the end portion 50a where the formation depth of the buried layer 50 is not constant can be located in the dummy cell region 300. Therefore, at least the depth of the buried layer 50 formed in the memory cell region 100 can be made constant, so that the variation in the threshold value of the transistors formed in the memory cell region 100 can be prevented and the desired threshold value in the memory cell region 100 can be prevented. Can be formed.

In the present invention, since the buried layer 50 is not formed over the entire dummy cell region 300, a region where the p type silicon substrate 40 and the p well 42 are in contact can be secured. Therefore, the end portion 50a of the buried layer 50 is set back from the end portion of the dummy cell region 300 on the peripheral circuit region 200 side so that the p-type silicon substrate 40 and the p well 42 can contact each other in a desired range. Is set.

Next, referring to FIGS. 1, 2 and 5,
The memory cell region 100 will be described. FIG. 5 is a cross-sectional view showing electrical connection of each transistor of the memory cell and electron-hole pairs generated by α rays.

In the memory cell region 100, the memory cells 10 are arranged in a grid pattern in the X and Y directions to form a memory cell array.

As shown in FIG. 2, the memory cell 10 has four memory cells.
N-channel MOS transistors Q1, Q2, Q
3, Q4 and two p-channel MOS transistors Q
5 and Q6. The transistors Q1 and Q2 are transfer transistors, the transistors Q3 and Q4 are drive transistors, and the transistors Q5 and Q6 are load transistors. The load transistor Q5 and the drive transistor Q3 form an inverter, and the load transistor Q6 and the drive transistor Q4 form an inverter. A flip-flop is formed by these inverters.

The n-well 44 has a load transistor Q.
5 and Q6 are formed. Load transistors Q5, Q
6 is a p-channel type MOS transistor. As shown in FIGS. 2 and 5, the load transistors Q5 and Q6 include a gate electrode 14, a p-type source 2a, and a p-type drain 4a, respectively. The source 2a is connected to the power supply line V _DD . Further, an n-type well contact region 6n is formed in the n-well 44. A wire for fixing the potential of the n well 44 is connected to the well contact region 6n. In the example shown,
The well contact region 6n is connected to the power supply line V _DD .

The p-well 42 has a drive transistor Q.
3 and Q4 are formed. Drive transistors Q3, Q
Reference numeral 4 is an n-channel MOS transistor. The drive transistors Q3 and Q4 have gate electrodes 14 and
It has an n-type source 2b and an n-type drain 4b. Each source 2b is connected to the ground line V _SS . Each drain 4b has a load transistor Q
5, the drains 4a of Q6 are connected.

The p-well 42 has a transfer transistor Q.
1, Q2 are formed. Transfer transistors Q1, Q
Reference numeral 2 is an n-channel MOS transistor. Each of the transfer transistors Q1 and Q2 includes a gate electrode (word line) 16, a source 2c and a drain 4c. The sources 2c of the transfer transistors Q1 and Q2 and the drains 4b of the drive transistors Q3 and Q4 are made of the same impurity region. Each drain 4c is connected to each bit line BL.

A p-type well contact region 6p is formed in the p-well 42. A wiring for fixing the potential of the p well 42 is connected to the well contact region 6p. In the illustrated example, the well contact region 6p is connected to the ground line V _SS .

The inverter constituted by the load transistors Q5 and Q6 and the drive transistors Q3 and Q4 and the transfer transistors Q1 and Q2 are electrically connected by the cell node 8. The drain 4a, the drain 4b and the source 2c are a part of the cell node 8.

In the dummy cell region 300, as shown in FIG.
As shown in FIGS. 3 and 4, dummy cells 30 are arranged on the outermost periphery of the memory cell array in the memory cell region 100. By providing such a dummy cell region 300, it is possible to absorb the dimensional variation in patterning in this region. The dummy cell 30 is an extra cell in terms of circuit operation and is connected so that it does not operate. In the dummy cell 30, as shown in FIGS. 3 and 4, the impurity layers 2 and 4 corresponding to the source or drain of the MOS transistor and the conductive layers 14 and 16 corresponding to the gate electrode are the same as those of the memory cell 10. It is formed through a patterning process.

Next, the reason why the stored data is prevented from being destroyed due to the α ray soft error will be described.

As shown in FIG. 5, the cell node 8 has a voltage of 3V.
(That is, when the drain 4b of the drive transistor Q3 has a voltage of 3V), the α line indicates the drain 4b, the p-well 42,
It is assumed that electron-hole pairs are generated by passing through the buried layer 50 and the silicon substrate 40. The ground wire V
_SS is 0V and the power supply line _VDD is 3V.

In the well contact region 6n, the power supply line V
_DD is connected. Therefore, the potential of the buried layer 50 is a positive potential (potential that prevents electrons from flowing into the p-well 42). Therefore, as shown in FIG. 5, electrons in the buried layer 50 and the silicon substrate 40 flow from the buried layer 50 through the n well 44 to the well contact region 6n. Therefore, the electrons flowing into the drain 4b of the drive transistor Q3 are only the electrons in the p-well 42.

In a semiconductor device having no buried layer 50, all the electrons generated on the trajectory of α rays flow into the drain. The distance of this locus is a value obtained by adding the depth of the p-well and the depth of the silicon substrate. On the other hand, in the semiconductor device shown in FIG. 5, there is only the depth of the p well 42.
Therefore, in the semiconductor device of the present embodiment, the drop of the drain voltage is significantly smaller than that in the semiconductor device having no buried layer 50, and as a result, the retained data is not destroyed.
The holes are the ground lines V connected to the silicon substrate 40.
Ground line V _SS connected to _SS and well contact region 6p
And so on. As described above, in the present embodiment, the embedded layer 50 prevents the α ray from adversely affecting the data holding function.

By contacting the buried layer 50 with the n-well 44, the potential of the buried layer 50 can be fixed to a potential that prevents electrons in the buried layer 50 from flowing into the p-well 42.

In the semiconductor device of this embodiment, the silicon substrate 40 is p-type. Therefore, the memory cell region 10
The 0 p-wells 42 are connected to each other through the silicon substrate 40, and the p-well 42 can be set to the substrate potential.
As a result, the potential of the p well 42 can be stabilized and the resistance of the p well 42 can be lowered. Further, of the n-channel MOS transistor and the p-channel MOS transistor in memory cell region 100, an increase in the substrate potential in the formation region of the n-channel MOS transistor having a relatively large substrate current can be suppressed.

Although one embodiment of the present invention has been described above, the present invention is not limited to this and can be appropriately modified within the scope of the gist of the invention.

For example, the buried layer 50 is formed in the p well 4
The above effect can be achieved even if the n-type drain 36 is formed below the region where the n-type drain 36 is located. Alternatively, the buried layer 50 may be brought into a predetermined potential by bringing the buried layer 50 into contact with another well without contacting the n-well 44.

[Brief description of drawings]

FIG. 1 is a plan view schematically showing a layout of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a plan view showing a layout of a main part of a memory cell.

3 is a cross-sectional view taken along the line AA of FIG.

FIG. 4 is a cross-sectional view taken along the line BB of FIG.

FIG. 5 is a cross-sectional view for explaining the reason why the occurrence of α-ray soft error is prevented.

FIG. 6 is a cross-sectional view showing a buried layer and a method for forming the buried layer.

[Explanation of symbols]

2a, 2b, 2c source 4a, 4b, 4c drain 6n, 6p well contact region 10 memory cells 14,16 Gate layer 18 element isolation region 20 peripheral circuit elements 30 dummy cells 40 Silicon substrate 42 1st well 44 Second well 46 Third well 50 Embedded layer 100 memory cell area 200 peripheral circuit area 300 dummy cell area Q1, Q2 transfer transistor Q3, Q4 drive transistor Q5, Q6 load transistor

Claims (3)

[Claims] 1. A memory cell area including an SRAM, a peripheral circuit area including a peripheral circuit of the SRAM, and a dummy cell area located between the memory cell area and the peripheral circuit area on the same semiconductor substrate. The semiconductor substrate has a first conductivity type, and the memory cell region and the dummy cell region have a first well of a first conductivity type, a second well of a second conductivity type, and a second conductivity type. Embedded layer, the embedded layer is formed at least under the first well, is in contact with the first well, and has an end on the peripheral circuit region side in the dummy cell region. A semiconductor device formed to be positioned. 2. The semiconductor device according to claim 1, wherein the first conductivity type is p type and the second conductivity type is n type. 3. The semiconductor device according to claim 1, wherein the buried layer is formed over the entire memory cell region.