JP2003217295A - Nonvolatile semiconductor memory medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile storage medium in which use efficiency of layout area of a memory array region is improved, and size can be reduced effectively. <P>SOLUTION: A main memory array is connected to a direct addition memory array and virtual ground array structure is constituted. Respective memory array regions 150 are provided with a plurality of bit lines and a plurality of ground lines. Respective memory cells are provided with a common source formed in a base and a common drain. Respective bit lines are connected electrically to drains of the prescribed number of memory cells arranged. Respective ground lines are connected electrically to sources of the prescribed number of memory cells arranged. Further, the device has a peripheral circuit region 120, and is provided with a main memory ground line decoder connected electrically to ground lines of respective memory array regions 150, an addition memory ground line decoder, and signal transmission lines 136, 138 of at least two or more lines of which both ends are connected electrically to respective decoders. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile storage medium, and more particularly to a non-volatile storage medium in which a main memory array and an additional memory array are directly connected.

[0002]

2. Description of the Related Art Recent nonvolatile storage media include so-called additional memory arrays in addition to conventional main memory arrays. The additional memory array is a structure that is completely similar to the main memory array and is an alternative to storage elements found ineffective in the main memory array. Thus, such non-volatile storage media can tolerate relatively large manufacturing defects when manufacturing the storage elements of the main memory array.
The yield of the entire nonvolatile storage medium can be increased.

FIG. 1 discloses a block diagram showing the structure of a conventional nonvolatile storage medium 10. Nonvolatile storage medium 10
Is manufactured on a base (not shown) of a semiconductor chip. The non-volatile storage medium 10 includes a peripheral circuit area 20 and a memory array area 50. The memory array area 50 includes a main memory array 60 and an additional memory array 80. The peripheral circuit area 20 includes an address buffer 22 and
Addressable memory unit 24 for storing address data of storage elements in which storage in main memory array 60 is not valid, main memory array ground line decoder 26, and a plurality of grounds electrically connected to main memory array 60. Line GL, main memory bit line decoder 27, additional memory array ground line decoder 28
, A plurality of ground lines RGL electrically connected to the additional memory array 80, and an additional memory array bit line decoder 29.

Each bit line BL, RBL is
The main memory array bit line decoder 27 is electrically connected to the pass transistor, the main memory array bit line decoder 27 is electrically connected to the gate electrode of the pass transistor, and the additional memory array bit line decoder 29 is also electrically connected to the pass transistor gate electrode. To electrically connect each bit line BL, RBL to a data line.

2A illustrates the structure of the memory array area 50 of the conventional nonvolatile storage medium 10, and FIG. 2B illustrates the circuit of the memory array area 50 of the conventional nonvolatile storage medium 10. The nonvolatile storage medium 10 is provided on the base portion 42 of the semiconductor chip 40. The memory array 50 is provided between the main memory array 60, the additional memory array 80, the main memory array 60, and the main memory array 60 and the additional memory array 80, and separates the field oxide layer 70 from each other. And the main memory array 6 provided on both sides of the field oxide layer 70 in the manufacturing process of the field oxide layer 70.
0 and two dummy memories for isolating the additional memory array 80 so that the influence on the additional memory array 80 does not occur.

The main memory array 60 includes M bit lines BL _{1 to} BL _M and M + 1 ground lines GL _{1 to} GL.
_{M + 1} and a plurality of memory cells. Each memory cell comprises a source 54 and a drain 56, which are formed in the base 42 of the semiconductor chip 40 and a gate pole 58 is formed on the base 42. Each ground line GL is electrically connected to a source 54 of a predetermined number of memory cells in the main memory array 60, and each bit line BL is a drain of a predetermined number of memory cells in the main memory array 60. Connect to 56. Of the M + 1 ground lines, GL _{2 to} GL _M are used to operate the memory cells on both sides, and the ground lines GL _{2 to} GL _M are shared with the memory cells on both sides. Further, the ground lines GL ₁ and GL _{M + 1} can operate only one adjacent memory cell. Also, BL _{1 to} B
L _M is used to operate the memory cells on both sides. That is, the bit lines BL _{1 to} BL _{M + 1} are shared by the memory cells on both sides.

The additional memory array 80 includes N bit lines RBL _{1 to} RBL _N and N + 1 ground lines RGL _1.
.About.RG _{LN + 1} and a plurality of memory cells. Each memory cell includes a source 54 and a drain 56, is formed in the base 42 of the semiconductor chip 40, and further has a gate pole 58 on the base 42. Each ground line RGL is electrically connected to a source 54 of a predetermined number of memory cells in the additional memory array 80, and each bit line RBL is a drain of a predetermined number of memory cells in the additional memory array 80. Electrically connected to 56. N
Of the +1 ground lines, RGL _{2 to} RGL _N are used to operate the memory cells on both sides. That is, the ground line RGL
_{2 to} GL _N are shared with the memory cells on both sides. Further, the ground lines RGL ₁ and RGL _{N + 1} can operate only one adjacent memory cell. RBL _{1 to} RBL _N are used to operate the memory cells on both sides. That is, the bit lines RBL _{1 to} RBL _M are shared by the memory cells on both sides.

As shown in FIG. 2B, the nonvolatile storage medium 1
When performing an operation on the memory cell M2 in 0, the ground line GL ₂ , the bit line BL _1, and the word line W are first
An address is arranged in L ₁ and the source 56 of the memory cell is
, The drain 54, and the gate electrode 38 can be controlled separately to start the operation of the memory cell M2 for the first time. The address buffer 22 receives the address signal from the addressable memory unit 24, the main memory array ground line decoder 26, the main memory bit line decoder 27, and the additional memory array ground line decoder 2.
8 and the additional memory array bit line decoder 29, respectively, and outputs an address signal. The main memory array ground line decoder 26 decodes the address signal based on the address signal and places the address on the ground line GL ₂ . The main memory array bit line decoder 27 decodes based on the address signal, activates (turns on) each pass gate, and places an address on the address bit line BL ₁ . The address arrangement method of the word line WL ₁ is performed by a similar method based on the same principle.

If the transmitted address signal matches the address stored in the addressable memory unit 24, the addressable memory unit 24 generates a matching signal to generate the additional memory array ground line decoder 28 and the additional memory array bit. The line decoder 29 is turned on. The additional memory array ground line decoder 28 performs decoding on the basis of the address signal output from the address buffer 22 to perform the address arrangement of the additional ground line. The additional memory cell bit line decoder 29 is the address buffer 2
Decoding is performed on the basis of the address signal output by 2 and each pass gate is turned on to perform the address allocation to the additional bit.

In the memory array area of the conventional non-volatile storage medium 10, a field oxide layer is provided mainly between the main memory array 60 and the additional memory array 80, and two field oxide layers are provided on both sides of the field oxide layer. By providing the dummy memory, the main memory array 60 and the additional memory array 80 are separated. However, the provision of the field oxide layer and the dummy memory 72 that cannot store data is not possible in the memory array area 50.
Layout area will be increased. Therefore, when designing to reduce the size in the manufacturing of semiconductors,
An important issue is how to reduce the area occupied by the field oxide layer and the dummy memory 72 to improve the use efficiency of the layout area of the memory array region.

[0011]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a non-volatile storage medium which can improve the use efficiency of the layout area of the memory array region and effectively reduce the size of the semiconductor.

[0012]

Therefore, the present inventor has conducted extensive studies in view of the drawbacks of the prior art, and has a non-volatile memory having a virtual ground array structure in which a main memory array and an additional memory array are merged. Focusing on the structure of the medium, the present invention has been developed based on this finding.

That is, according to the present invention, the field oxide layer for separating the main memory array and the additional memory array and the dummy memory are removed, the main memory array is directly connected to the additional memory array, and the virtual ground array is used. Adopted structure. The main memory array area and the additional memory array area each include a plurality of memory cells, a plurality of bit lines, and a plurality of ground lines, and each of the memory cells is within the base of the semiconductor chip. Shared source and drain commonly formed, and each bit line is electrically connected to a drain of a predetermined number of memory cells in the main memory array or additional memory array. Further, each ground line is electrically connected to the sources of a predetermined number of memory cells provided in the main memory array or the additional memory array.

The non-volatile storage medium according to claim 1 is
A non-volatile storage medium provided at the base of a semiconductor chip, comprising a main memory array, an additional memory array directly connected to the main memory array, and a shared source. The main memory array includes at least one memory cell including a source and a drain provided in a base of the semiconductor chip, at least one bit line electrically connected to the drain of the memory cell, and At least one ground line electrically connected to the source of the memory cell. The additional memory array is
An additional memory cell provided in the base of the semiconductor chip, the additional memory cell including an additional source and an additional drain, and at least one electrically connected to the additional drain of the additional memory cell.
The additional bit line and at least one additional ground line electrically connected to the additional source of the additional memory cell are provided, and the common source is a source at a position where the main memory array and the additional memory array are in contact with each other. And as an additional drain.

A non-volatile storage medium according to a second aspect is
The non-volatile storage medium according to claim 1, further comprising a peripheral circuit region, wherein the peripheral circuit region has a main memory ground line decoder electrically connected to a ground line of the main memory array, and an additional ground of the additional memory array. An additional memory ground line decoder electrically connected to the line, and at least two or more signal transmission lines, and both ends of the signal transmission line serve as the main memory ground line decoder and the additional memory ground line decoder, respectively. Connect electrically.

A non-volatile storage medium according to a third aspect is
When the shared source according to claim 2 is electrically connected to the shared ground line and the main memory ground line decoder performs address arrangement on the shared ground line, the main memory ground line decoder adds the signal via the signal transmission line. A signal is transmitted to a memory ground line decoder to determine a voltage of the shared ground line and an electrical connection between the shared ground line and the additional memory ground line decoder forms an open circuit state; When the additional memory ground line decoder performs the address arrangement on the shared ground line, the additional memory ground line decoder transmits a signal to the main memory ground line decoder via another signal transmission line to generate the voltage of the shared ground line. And the common ground wire,
The electrical connection with the main memory ground line decoder is configured to form an open circuit condition.

A nonvolatile storage medium according to a fourth aspect is
The main memory ground line decoder according to claim 3, comprising a sub-decoder electrically connected to the common ground line, the sub-decoder having a 3-input N for receiving an address signal.
An AND gate, an inverter, and a 3-mode inverter, the input terminal of the inverter is electrically connected to the output terminal of the 3-input NAND gate, and the control terminal of the 3-mode inverter is the additional ground line decoder. It is electrically connected to the output terminal of the 4-input NAND gate of the sub decoder electrically connected to the common ground line. In the additional memory ground line decoder, a sub-decoder electrically connected to the shared ground line receives an address signal and a sign signal.
It comprises a 4-input NAND gate, an inverter, and a 3-mode inverter, the input terminal of the inverter being the 4-input NAND.
The control terminal of the 3-mode inverter is electrically connected to the output terminal of the AND gate, and the control terminal of the 3-mode inverter is electrically connected to the shared ground line in the main memory ground line decoder. Connect electrically.

A nonvolatile storage medium according to a fifth aspect is
When the shared source according to claim 2 is electrically connected to the shared ground line and the main memory ground line decoder performs an address arrangement on the shared ground line, the main memory ground line decoder outputs a signal via a signal transmission line. Is transmitted to the additional memory ground line decoder to electrically connect to the shared ground line, both sub decoders are selected, and an equivalent voltage is output. When the additional memory ground line decoder performs address arrangement on the shared ground line, the additional memory ground line decoder transmits a signal to the main memory ground line decoder via a signal transmission line to electrically connect to the shared ground line. Any of the sub-decoders that are connected to is selected and outputs an equivalent voltage.

A nonvolatile storage medium according to a sixth aspect is
6. The main memory ground line decoder according to claim 5, comprising a sub-decoder electrically connected to the shared ground line, the sub-decoder having a 3-input N for receiving an address signal.
An AND gate, a 2-input NAND gate, and an inverter, wherein the 1-input end of the 2-input NAND gate is electrically connected to the output end of the 3-input NAND gate, and the other of the 2-input NAND gate is connected. The input terminal is electrically connected to the output terminal of the NAND gate of the sub decoder electrically connected to the common ground line in the additional ground line decoder. A sub-decoder electrically connected to the shared ground line in the additional memory ground line decoder has a 4-input N for receiving an address signal and a sign signal.
An AND gate, a 2-input NAND gate, and an inverter, wherein the 1-input terminal of the 2-input NAND gate is electrically connected to the output terminal of the 4-input NAND gate, and the 2-input NAND gate has another input terminal. The input terminal is electrically connected to the output terminal of the 3-input NAND gate of the sub decoder electrically connected to the shared ground line in the main memory ground line decoder.

A non-volatile storage medium according to a seventh aspect is the non-volatile storage medium according to the first aspect having a virtual ground line array structure.

A non-volatile storage medium according to claim 8 is a non-volatile storage medium provided on a base of a semiconductor chip, and includes a main memory array, an additional memory array directly connected to the main memory array, and a shared drain. Be equipped with. The main memory array includes at least one memory cell including a source and a drain provided in a base of the semiconductor chip, at least one bit line electrically connected to the drain of the memory cell, and At least one ground line electrically connected to a source of the memory cell, the additional memory array, the additional memory cell including an additional source and an additional drain provided in a base of the semiconductor chip; At least one additional bit line electrically connected to the additional drain of the additional memory cell and at least one additional ground line electrically connected to the additional source of the additional memory cell. The shared drain is a source at a position where the main memory array and the additional memory array are in contact with each other,
And as an additional drain.

A non-volatile storage medium according to a ninth aspect is
9. The non-volatile storage medium according to claim 8, further comprising a peripheral circuit area, wherein the peripheral circuit area further includes a main memory bit line decoder electrically connected to a bit line of the main memory array, and the additional memory array. An additional memory bit line decoder electrically connected to the bit line, and at least two or more signal transmission lines,
Further, both ends of the signal transmission line are electrically connected to the main memory bit line decoder and the additional memory bit line decoder, respectively.

According to another aspect of the non-volatile storage medium of the present invention, when the shared drain of claim 9 is electrically connected to the shared bit line and the main memory bit line decoder performs address arrangement on the shared bit line, The main memory bit line decoder transmits a signal to the additional memory bit line decoder via a signal transmission line to determine the voltage of the shared bit line and between the shared bit line and the additional memory bit line decoder. Of the main memory through the other signal transmission line when the additional memory bit line decoder makes an address arrangement on the shared bit line so that the electrical connection of the main memory forms an open circuit state. Transmitting a signal to a bit line decoder to determine the voltage of the shared bit line, and A shared bit line, the electrical connection between the main memory bit line decoder is configured to form a circuit open condition.

The non-volatile storage medium according to claim 11 comprises a sub-decoder in which the main memory bit line decoder according to claim 10 is electrically connected to the shared bit line, wherein the sub-decoder is an address signal. A three-input NAND gate for receiving, an inverter, and a three-mode inverter, the input end of the inverter is electrically connected to the output end of the three-input NAND gate, and the control end of the three-mode inverter is Electrically connected to the output of a 4-input NAND gate of a sub-decoder electrically connected to the shared bit line in the additional bit line decoder. In the additional memory bit line decoder,
The sub-decoder electrically connected to the shared bit line includes a 4-input NAND gate that receives an address signal and a sign signal, an inverter, and a 3-mode inverter, the input terminal of the inverter being the 4-input NAND gate. An output end of a three-input NAND gate of a sub-decoder electrically connected to an output end of an input NAND gate and an input end of the three-mode inverter electrically connected to the shared bit line in the main memory bit line decoder. Electrically connect to.

The non-volatile storage medium according to claim 12 is
When the shared drain of claim 9 is electrically connected to the shared bit line and the main memory bit line decoder performs an address arrangement on the shared bit line, the main memory bit line decoder outputs a signal via a signal transmission line. To the additional memory bit line decoder to electrically connect to the shared bit line, both sub decoders are selected, and the same voltage is output. When the additional memory bit line decoder performs address arrangement on the shared bit line, the additional memory bit line decoder transmits a signal to the main memory bit line decoder via a signal transmission line to electrically connect to the shared bit line. Any of the sub-decoders that are connected to is selected and outputs an equivalent voltage.

A non-volatile storage medium according to a thirteenth aspect is a sub memory in which the main memory bit line decoder according to the twelfth aspect is electrically connected to the shared bit line.
A sub-decoder, the sub-decoder comprising a 3-input NAND gate for receiving an address signal, and a 2-input NAND gate,
An inverter, the one input terminal of the two-input NAND gate is electrically connected to the output terminal of the three-input NAND gate,
The other input of the input NAND gate is electrically connected to the output of the 4-input NAND gate of the sub-decoder which is electrically connected to the shared bit line in the additional bit line decoder. A sub-decoder electrically connected to the shared bit line in the additional memory bit line decoder has a 4-input NAN for receiving an address signal and a sign signal.
A D-gate, a 2-input NAND gate, and an inverter, wherein one input terminal of the 2-input NAND gate is electrically connected to the output terminal of the 4-input NAND gate, and the other of the 2-input NAND gate is connected. The input terminal is electrically connected to the output terminal of the 3-input NAND gate of the sub decoder electrically connected to the shared bit line in the main memory bit line decoder.

A non-volatile storage medium according to a fourteenth aspect is a non-volatile storage medium having a virtual ground array structure.

A non-volatile storage medium according to a fifteenth aspect is a non-volatile storage medium provided on a base of a semiconductor chip, and includes a main memory array, an additional memory array, and a shared doping region. The main memory array has at least one or more memory cells.
The additional memory array is directly connected to the main memory array and has at least one or more memory cells. The shared doping region is provided at a position where the main memory array and the additional memory array are in contact with each other, and is electrically connected to the memory cell and the additional memory cell that are adjacent to each other on both side edges.

A non-volatile storage medium according to a sixteenth aspect comprises the memory cell and the additional memory cell according to the fifteenth aspect, each including a source and a drain provided in a base of the semiconductor chip, and the doping region. Is a shared source of the memory cell and the additional memory cell which are adjacent to each other in the contact position of the main memory array and the additional memory array.

A non-volatile storage medium according to a seventeenth aspect comprises the memory cell and the additional memory cell according to the fifteenth aspect, each including a source and a drain provided in a base of the semiconductor chip, and the doping region. Is a shared drain of the memory cell and the additional memory cell which are adjacent to each other at the contact position of the main memory array and the additional memory array.

A method of controlling a non-volatile storage medium according to claim 18 is a method of controlling a non-volatile storage medium having a virtual ground array structure, wherein the non-volatile storage medium comprises a main memory array and a main memory array. And a shared doping region provided at a contact position between the main memory array and the additional memory array, the main memory array including at least one or more memory cells. A bit line electrically connected to the drain of the memory cell, and a ground line electrically connected to the source of the memory cell. The additional memory array includes at least one additional memory cell, an additional bit line electrically connected to the drain of the additional memory cell, and an additional ground line electrically connected to the source of the additional memory cell. A main memory ground line decoder electrically connected to a ground line of the main memory array in the peripheral circuit region,
An additional memory ground line decoder electrically connected to an additional ground line of the additional memory array, and at least first and second
Signal transmission lines, and both ends of each signal transmission line are connected to the main memory ground line decoder and the additional memory ground line decoder. A method of controlling a non-volatile storage medium having such a configuration includes the following steps, in which an address is arranged on a shared ground line electrically connected to the shared doping region using the main memory ground line decoder. The main memory ground line decoder transmits a signal to the additional memory ground line decoder via a first signal transmission line to determine the voltage of the shared ground line, and the shared ground line and additional memory ground line decoder When an open circuit state is formed in the electrical connection between the additional memory bit line decoder and the shared memory ground line by using the additional memory bit line decoder, the additional memory ground line decoder connects the second signal transmission line A signal to the main memory ground line decoder to determine the voltage of the common ground line and a circuit for electrical connection between the common ground line and the main memory ground line decoder. Form an open state.

A method for controlling a non-volatile storage medium according to a nineteenth aspect is a method for controlling a non-volatile storage medium having a virtual ground array structure, wherein the non-volatile storage medium is a main memory array and the main memory array. An additional memory array directly connected to the main memory array, a peripheral circuit area, and a shared doping area provided at a contact position between the main memory array and the additional memory array, the main memory array including at least one or more memories. A cell and a bit line electrically connected to the drain of the memory cell,
And a grounding line electrically connected to the source of the memory cell, the additional memory array includes at least one or more additional memory cells, and an additional bit line electrically connected to a drain of the additional memory cell. , And an additional ground line electrically connected to the source of the additional memory cell. A main memory ground line decoder electrically connected to the ground line of the main memory array, an additional memory ground line decoder electrically connected to an additional ground line of the additional memory array, and At least
The first and second signal transmission lines are provided, and both ends of each signal transmission line are connected to the main memory ground line decoder and the additional memory ground line decoder. A method of controlling a non-volatile storage medium having such a configuration includes the following steps, and when the address is arranged on a shared ground line electrically connected to the shared doping region by using the main memory ground line decoder. , The main memory ground line decoder transmits a signal to the additional memory ground line decoder via a first signal transmission line so that both the common ground line and each sub-decoder are selected, and an equivalent voltage is applied. When the additional memory ground line decoder is used to perform address arrangement on the shared ground line by using the output, the additional memory ground line decoder outputs a signal via the second signal transmission line to the main memory ground line decoder. So that both the common ground line and the respective sub-decoders are selected and the same voltage is output.

A method for controlling a non-volatile storage medium according to a twentieth aspect is a method for controlling a non-volatile storage medium having a virtual ground array structure, wherein the non-volatile storage medium is a main memory array and the main memory array. An additional memory array directly connected to the main memory array, a peripheral circuit area, and a shared doping area provided at a contact position between the main memory array and the additional memory array, the main memory array including at least one or more memories. A cell and a bit line electrically connected to the drain of the memory cell,
And a ground line electrically connected to the source of the memory cell, wherein the additional memory array includes at least one additional memory cell and an additional bit line electrically connected to the drain of the additional memory cell. And an additional ground line electrically connected to the source of the additional memory cell. A main memory bit line decoder electrically connected to a bit line of the main memory array, an additional memory bit line decoder electrically connected to an additional bit line of the additional memory array, and At least first and second signal transmission lines are provided, and both ends of each signal transmission line are connected to the main memory bit line decoder and the additional memory bit line decoder. A method of controlling a non-volatile storage medium having such a configuration includes the following steps, in which an address is arranged on a shared bit line electrically connected to the shared doping region by using the main memory bit line decoder. The main memory bit line decoder transmits a signal to the additional memory bit line decoder via a first signal transmission line to determine the voltage of the shared bit line, and the shared bit line and the additional memory bit When a circuit open state is formed in the electrical connection with the line decoder and an address is arranged in the shared bit line by using the additional memory bit line decoder,
The additional memory bit line decoder transmits a signal to the memory bit line decoder via a second signal transmission line to determine the voltage of the shared bit line, and the shared bit line and the main memory bit line decoder. Forming an open circuit condition in the electrical connection between the and.

A method for controlling a non-volatile storage medium according to a twenty-first aspect is a method for controlling a non-volatile storage medium having a virtual ground array structure, wherein the non-volatile storage medium is a main memory array and the main memory array. An additional memory array directly connected to the main memory array, a peripheral circuit area, and a shared doping area provided at a contact position between the main memory array and the additional memory array, the main memory array including at least one or more memories. A cell and a bit line electrically connected to the drain of the memory cell,
And a ground line electrically connected to the source of the memory cell, wherein the additional memory array includes at least one additional memory cell and an additional bit line electrically connected to the drain of the additional memory cell. And an additional ground line electrically connected to the source of the additional memory cell. A main memory bit line decoder electrically connected to a bit line of the main memory array, an additional memory bit line decoder electrically connected to an additional bit line of the additional memory array, and At least first and second signal transmission lines are provided, and both ends of each signal transmission line are connected to the main memory bit line decoder and the additional memory bit line decoder. A method of controlling a non-volatile storage medium having such a configuration includes the following steps, in which an address is arranged on a shared bit line electrically connected to the shared doping region by using the main memory bit line decoder. , The main memory bit line decoder transmits a signal to the additional memory bit line decoder via a first signal transmission line so that the shared bit line and each sub-decoder are both selected, and an equivalent voltage is applied. When the additional memory bit line decoder is used to perform address arrangement on the shared bit line by using the additional memory bit line decoder, the additional memory bit line decoder outputs a signal via the second signal transmission line to the main memory bit line decoder. To the shared bit line and each of the sub-decoders, and So as to output a voltage equal.

A non-volatile storage medium according to a twenty-second aspect is a non-volatile storage medium provided on a base of a semiconductor chip, and includes a main memory array including at least one or more memory cells, and the main memory array. An additional memory array, which is directly connected and includes at least one or more additional memory cells, is provided at a position where the main memory array and the additional memory array are in contact with each other, and the additional memory cells are adjacent to both side edges. A shared doping area shared by the cells and a peripheral circuit area including at least one decoder are provided.

In the non-volatile storage medium according to a twenty-third aspect, the decoder according to the twenty-second aspect includes a main memory decoder, an additional memory decoder, and a common decoder.

In the non-volatile storage medium according to a twenty-fourth aspect, the common decoder according to the twenty-third aspect is a common ground line decoder.

In the non-volatile storage medium described in claim 25, the shared decoder in claim 23 is a shared bit line decoder.

A non-volatile storage medium according to a twenty-sixth aspect is a non-volatile storage medium provided on a base of a semiconductor chip, and includes a main memory array, an additional memory array directly connected to the main memory array, and a peripheral circuit area. The main memory array comprises at least one memory cell having a source and a drain provided in the base of the semiconductor chip, a bit line electrically connected to the drain of the memory cell, and A ground line electrically connected to a source of the memory cell, the additional memory array having at least one additional memory cell having an additional source and an additional drain provided in the base of the semiconductor chip; An additional bit line electrically connected to the additional drain of the additional memory cell and an additional source of the additional memory cell. Comprises and additional ground line to the gas-connecting, and the additional memory array share a common doped region with the main memory array, in the peripheral circuit region includes at least one or more decoders.

According to a twenty-seventh aspect of the present invention, there is provided a nonvolatile memory medium, wherein the decoder according to the twenty-sixth aspect is a main memory ground line decoder electrically connected to the ground line of the main memory array, and an additional ground line of the additional memory array. An additional memory ground line decoder electrically connected to each other, and at least two or more signal transmission lines, and both ends of each signal transmission line are electrically connected to the main memory ground line decoder and the additional memory ground line decoder. Connect to.

In the non-volatile storage medium according to claim 28, the decoder according to claim 27 further includes a shared ground line decoder.

According to a twenty-ninth aspect of the non-volatile storage medium, the shared doping region of the twenty-sixth aspect serves as a source at a position where the main memory array and the additional memory array are in contact with each other, and also serves as an additional source.

According to a thirtieth aspect of the present invention, there is provided a nonvolatile storage medium, wherein the decoder according to the twenty-sixth aspect is a main memory bit line decoder electrically connected to a bit line of the main memory array, and an additional bit line of the additional memory array. An additional memory bit line decoder electrically connected to the main memory bit line decoder and at least two signal transmission lines, and both ends of each signal transmission line are electrically connected to the main memory bit line decoder and the additional memory bit line decoder. Connect to.

In the non-volatile storage medium according to claim 31, the decoder according to claim 3 further includes a shared bit line decoder.

In the non-volatile storage medium according to a thirty-second aspect, the shared doping region according to the twenty-sixth aspect serves as a drain at a position where the main memory array and the additional memory array are in contact with each other, and also serves as an additional drain.

[0046]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention is a non-volatile storage medium capable of increasing the use efficiency of the layout area of the memory array region and effectively reducing the size of the semiconductor.
A virtual ground array structure is formed by directly connecting the main memory array and the additional memory array. That is, the present invention removes the field oxide layer for separating the main memory array and the additional memory array and the dummy memory, and directly connects the main memory array to the additional memory array.

Specific examples will be given to explain the structure and characteristics of such a non-volatile storage medium, and will be described in detail below with reference to the drawings.

[0048]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 3 shows a nonvolatile storage medium 11 according to the present invention.
The block diagram showing the partial structure of 0 is shown. The non-volatile storage medium 110 includes a peripheral circuit area 120 and a memory array area 150. The memory array area 150 includes a main memory array 160 and an additional memory array 170, and the peripheral circuit area 120 includes an address buffer 122.
And an addressable memory unit 124, a ground line decoder 130, and an additional ground line decoder 140. Addressable memory unit 124 is provided to store address data of stale memory units in main memory array 160. In addition, the ground line decoder 130 receives the main memory array 16 via the ground line GL.
0, and the additional ground line decoder 140 is electrically connected to the additional memory array via the ground line RGL.

FIG. 4 shows a nonvolatile storage medium 1 according to the present invention.
10 is a circuit diagram of the memory array area 150 of FIG.
3 shows a structure of the memory array area 150 of the nonvolatile storage medium 110 according to the present invention. As illustrated, the nonvolatile storage medium 110 is formed on the base 182 of the semiconductor chip 180. The memory array area 150 includes a main memory array 160 and an additional memory array 170. The main memory array 160 is directly connected to the additional memory array 170. Ground line _{GL M + 1} position falls edges of the main memory array 160 is a common ground line GL _C coupled to the ground line RGL ₁ position falls edge of the additional memory array 170. That is, the main source and the additional source at the position where the main memory array 160 and the additional memory array 170 are in contact with each other serve as a common doping region.

The main memory array 160 includes M bit lines BL _{1 to} BL _M and M + 1 ground lines GL _{1 to} G.
It includes L _{M + 1} and a plurality of memory cells. Each memory cell includes a source 184 and a drain 186, is formed in the base 182 of the semiconductor chip 180, and a gate electrode 188 is formed on the base 182. Gate pole 1
88 may be a control gate or a flow gate. Each ground line GL is connected to the main memory array 16
Each bit line BL is electrically connected to a source 184 of a predetermined number of memory cells in 0, and each bit line BL is electrically connected to a drain 186 of a predetermined number of memory cells in the main memory array 160. Of the M + 1 ground lines, GL _{2 to} GL _{M + 1} are used to operate the memory cells on both sides. That is, the ground lines GL _{2 to} GL _{M + 1} are shared with the memory cells on both sides. Further, since the ground line GL ₁ is located at the edge of the main memory array 160, only the cells on one side can be operated.

The additional memory array 170 includes N bit lines RBL _{1 to} RBL _N and N + 1 ground lines RGL.
_{1 to} RGL _{N + 1} and a plurality of memory cells.
Each memory cell has a source 184 and a drain 186.
Is formed in the base 182 of the semiconductor chip 180, and the gate electrode 188 is further provided on the base 182.
Each ground line RGL is electrically connected to a source 184 of a predetermined number of memory cells in the additional memory array 170, and each bit line RBL is a drain of a predetermined number of memory cells in the additional memory array 170. Electrically connected to 186. Of the N + 1 ground lines, RGL _1-
RGL _N is used to operate the memory cells on both sides.
That is, the ground lines RGL _{1 to} GL _N are shared with the memory cells on both sides. Further, the ground line RGL _{N + 1} is the additional memory array 1
Since it is located at the edge of 70, only one side cell can be operated.

FIG. 6A is a logic circuit diagram of the ground line decoder 130 'and the additional ground line decoder 140' in the embodiment. As shown, the ground line decoder 130 'is M +
One sub-decoder 131 _-1 ′ to 131 _{−M + 1} ′
And each sub-decoder 131 ′ is provided corresponding to each ground line GL ′ of the main memory array 160. Also, the sub-decoders 131 _-1 ′ and 1
31- _{M + 1} 'except for each sub-decoder 131
_-2 'to 131 _-M ' are two 3-input NAND gates for receiving address signals and one 2-input NA.
And an ND gate. An input terminal of the 2-input NAND gate is electrically connected to two output terminals of the 3-input NAND gate and an inverter, and an input terminal of the inverter is electrically connected to an output terminal of the NAND gate.

The sub-decoder 131- _{M + 1} 'corresponding to the ground line GL _{M + 1} ' has one 3-input NAND gate 132 for receiving an address signal and one 2-input NAN.
The D gate 133 and one inverter 134 are provided. One input terminal of the NAND gate 133 is electrically connected to the output terminal of the NAND gate 132, and the other input terminal is electrically connected to the signal transmission line 136 '.

The additional ground line decoder 140 'includes N + 1 sub-decoders 141-1' to 141 _{- N + 1} ', and each sub-decoder 141' is provided corresponding to the ground line RGL 'of the additional memory array 170. To be Each decoder _{141 -2 '~141 -N'} excluding sub decoder _{141 -1} 'and _{141 -N + 1'} are each two 4-input NAND gate for receiving an address signal and code signal, one of the two inputs A NAND gate, the input ends of the two-input NAND gates are electrically connected to the output ends of the two four-input end NAND gates and the inverter, respectively, and the input end of the inverter is connected to the output end of the NAND gate. Connect electrically.

The sub-decoder 141 _-1 ′ corresponding to the ground line RGL ₁ ′ includes a 4-input NAND gate 142 that receives an address signal and a sign signal, a 2-input NAND gate 143, and an inverter 144. NAND
In the gate 143, the input terminal 1 is electrically connected to the output terminal of the NAND gate 142, and the other input terminal is electrically connected to the signal transmission line 13.
8'electrically connected.

Both ends of the signal transmission line 136 'are connected to one input terminal of the two-input NAND gate 133 of the sub decoder 131- _{M + 1} ' and four terminals of the sub decoder 141-1 ', respectively.
It is electrically connected to the output terminal of the input NAND gate 142. Further, both ends of the signal transmission line 138 ′ are respectively connected to the 2-input NAND gate 143 of the sub-decoder 141-1 ′.
, And the output terminal of the 3-input NAND gate 132 of the sub-decoder 131 _{-M + 1} '.

When the nonvolatile storage medium 110 is operated, the address buffer 122 receives the address signal from the ground decoder 130 'and the addressable memory unit 124.
And the ground line decoder 130 'decodes the signal transmitted from the signal transmission line 136' based on the address signal, and selects the appropriate ground line GL of the main memory array 160. If the transmitted address signal matches the address stored in the addressable memory unit 124, the addressable memory unit 1
24 generates a code signal, drives the additional ground line decoder 140 'by the code signal, decodes the signal transmitted from the signal transmission line 138' based on the address signal, and appropriately grounds the additional memory array 170. Select line RGL.

[0058] By way of example, 'if the attempts to drive a shared ground line GL _C, sub-decoder ₁₃₁ outputs the ground line _{GL M + 1} of _{-M + 1'} ground line decoder 130 is selected, the sub-ground line decoder 130 '・ Decoder 131
_{-M + 1} additional ground decoder 140 operation corresponding signal via the 'signal transmission line 138''sub-decoders 141 _-
1 and the sub-decoder 141 _-1 ′ outputs R
Make sure that GL ₁ 'is also selected. Therefore sub-decoder _{131 -M + 1 ', 141 -1} ' none of is selected (i.e., outputs a voltage). If added to the reverse ground line decoder 140 'is GL C ground line _shared' attempts to drive the output ground line RG sub decoder 141 -1 _'
L _'1 is selected, the ground line decoder 140' outputs a "sub-decoders _{131 -M + 1} 'of the additional ground decoder 130 operation corresponding signal via the' signal transmission line 136 'sub-decoders _{141 -1,} Sub decoder 131
_The GL _{M + 1} 'output by _{-M + 1} ' is also selected. Therefore, the sub-decoder 131 _{-M + 1} ', 14
Any of 1 ₋₁ ′ is selected (that is, a voltage is output).

FIG. 6B is a logic circuit diagram of a ground line decoder 130 ″ and an additional ground line decoder 140 ″ according to another embodiment. The embodiment according to the figures shows the ground line GL.
_{M + 1} ″ sub-decoder 131 _{−M + 1} ″ includes a 3-input NAND gate 132 for receiving an address signal,
It is different from FIG. 5 in that it includes a three-mode output inverter 135. The one input end of the inverter 134 is electrically connected to the output end of the NAND gate 132, and the one input end of the three-mode output inverter 135 is the inverter 13
4 and the control end of the 3-mode output inverter 135 is electrically connected to the signal transmission line 136 ''.

The sub-decoder 141-1 '' comprises a 4-mode input NAND gate 142 for receiving an address signal and a sign signal, an inverter 144 and a 3-mode output inverter 145. One input terminal of the inverter 144 is N
The output terminal of the AND gate 142 is electrically connected, and the input terminal of the 3-mode output inverter 145 is electrically connected to the output terminal of the inverter 144. Further, the control end of the three-mode output inverter 145 is electrically connected to the signal transmission line 138 ″.

Both ends of the signal transmission line 136 ″ are respectively connected to the control end of the three-mode inverter 135 of the sub-decoder 131 _{−M + 1} ″ and the output end of the four-input NAND gate 142 of the sub-decoder 141 ₋₁ ″. Connect electrically. Further, the signal transmission line 138 '' ends of the sub-decoder 141 _{-1 'respectively} and a control terminal of the inverter 145', electrically to the output terminal of the 3-mode input NAND gate 132 of the sub-decoders _{131 -M + 1 ''} Connect to.

Similar to the operation procedure described above with reference to FIG. 6A, when the nonvolatile storage medium 110 is operated, the address buffer 122 outputs the address signal to the ground line decoder 13.
0 ″ and the addressable memory unit 124, respectively. The ground line decoder 130 ″ decodes the signal transmitted from the signal transmission line 136 ″ based on the address signal and selects the appropriate ground line GL ″ of the main memory array 160. If the transmitted address signal matches the address stored in the addressable memory unit 124, the addressable memory unit 124 generates a matching signal and drives the additional ground line decoder 140 '' by the matching signal. , The signal transmitted from the signal transmission line 138 ″ is decoded based on the address signal, and an appropriate ground line RG of the additional memory array 170 is decoded.
Select L ''.

By way of example, ground line decoder 130 ''.
Want to drive the common ground line GL _C ″, the output ground line GL of the sub-decoder 131 _{−M + 1} ″
_{M + 1} ″ is selected and the sub-decoder 131 of the ground line decoder 130 ″ _−the signal transmission line 13 of _{M + 1} ″ is selected.
An operation corresponding signal is added to the grounded decoder 14 through 8 ''.
0 'output to' sub decoder 141 _{-1 ','} RGL outputs of 'sub decoder 141 _{-1' 1} ''
The output circuit open state is formed at. Therefore, the common ground line G
It becomes impossible to operate Lc ''. That is, the voltage of the common ground line GLc ″ is the same as the sub-decoder 131.
It is determined by the output of _{-M + 1} ''. On the contrary, when the additional ground line decoder 140 ″ attempts to drive the common ground line GL _C ″, the output ground line RGL ₁ ″ of the sub decoder 141 ₋₁ ″ is selected, and the ground line decoder 14 is selected.
0 "sub-decoder 141 _-1 " signal transmission line 1
An operation-corresponding signal is sent via 36 'to the additional ground decoder 13
0 "sub-decoder 131- _{M + 1} "
Sub-decoder 131 _{-M + 1} '' output ground line GL
_{M + 1} '' forms an output circuit open state, and the common ground line G
It becomes impossible to operate L _C ″. That is, the voltage of the common ground line GLc ″ is
It is determined by the output of 1 ₋₁ ″.

Therefore, in the present invention, the ground line decoders 130 '/ 130''and the additional ground line decoder 14 are used.
The main memory array 160 and the additional memory array 170 can be directly connected by controlling 0 '/ 140''. In the above embodiment, the main memory array 160 shares the source with the additional memory array 170 to form a common ground line, and the ground line decoder 130 '.
/ 130 "signal transmission line 138 '/ 138" utilizing the operation corresponding signal transmitted from the additional ground line decoder 1
40 '/ 140'', and the signal transmission line 136' / 13 of the additional ground line decoder 140 '/ 140''
The operation-corresponding signal transmitted from 6 ″ is used to control the ground line decoders 130 ′ / 130 ″ so that the respective voltages are accurately applied to the common ground line.

Besides sharing one ground line, one bit line may be used to connect the main memory array 160 and the additional memory array 170. FIG. 7 is a partial block diagram of the nonvolatile storage medium 210 according to the present invention. The non-volatile storage medium 210 includes a peripheral circuit area 220 and a memory array area 250. However, the part related to the ground line is not shown in FIG. The memory array area 250 includes a main memory array 260 and an additional memory array 270, and the peripheral circuit area 220 includes a buffer 222.
The addressable memory unit 224 for storing the address data of the invalid memory unit in the main memory array 260, the bit line decoder 230 electrically connected to the bit line BL of the main memory array 260, and the additional memory array 270. Bit line RB
Additional bit line decoder 240 electrically connected to L
Comprises and.

FIG. 8 shows a nonvolatile storage medium 2 according to the present invention.
10 is a circuit diagram of the memory array area 250 of FIG.
The structure of the memory array area 250 of the nonvolatile storage medium 210 according to the present invention is shown in FIG. The nonvolatile storage medium 210 is formed on the base 282 of the semiconductor chip 280. The memory array area 250 includes a main memory array 260,
And an additional memory array 270. The main memory array 260 is directly connected to the additional memory array 270. The bit line BL _{M + 1 at the} position corresponding to the edge of the main memory array 260 is connected to the bit line RBL _{1 at the} position corresponding to the edge of the additional memory array 270 to form the shared bit line BL _C. That is, the main memory array 26
The main source and the additional source at the position where 0 and the additional memory array 270 contact each other form a common doping region.

The main memory array 260 includes M + 1 bit lines BL _{1 to} BL _{M + 1} and M ground lines GL _1.
And ~GL _M, comprising a plurality of memory cells. Each memory cell includes a source 286 and a drain 284, which are formed in the base 282 of the semiconductor chip 280 and a gate pole 288 is formed on the base 282. Each ground line GL is electrically connected to a source 286 of a predetermined number of memory cells in the main memory array 260, and each bit line BL is a drain of a predetermined number of memory cells in the main memory array 60. Electrically connected to 284. BL ₂ out of M + 1 bit lines
~ BL _{M + 1} are used to operate the memory cells on both sides. That is, the bit line _BL 2 _{~BL M + 1} is shared with the memory cell on both sides. Also, since the bit line BL ₁ is located at the edge of the main memory array 260, only the cell on one side can be operated.

The additional memory array 270 includes N + 1 bit lines RBL _{1 to} RBL _{N + 1} and N ground lines R.
GL _{1 to} RGL _{N + 1} and a plurality of memory cells. Each memory cell has a source 286 and a drain 2
And 84 are formed in the base 282 of the semiconductor chip 280, and a gate pole 288 is further provided on the base 282. Each ground line RGL is connected to the additional memory array 2
70 electrically connected to the sources 286 of the predetermined number of memory cells in 70, and each bit line RBL has a drain 2 of the predetermined number of memory cells in the additional memory array 270.
Electrically connected to 84. Of the N + 1 bit lines, RBL _{1 to} RBL _N are used to operate the memory cells on both sides. That is, the bit lines RBL _{1 to} GBL _N
Are shared with the memory cells on both sides. Also, the bit line line R
BL _{N + 1} can only operate cells on one side.

FIG. 10A is a logic circuit diagram of the bit line decoder 230 'and the additional ground line decoder 240' in the embodiment. Bit line decoder 230 'is M +
One sub-decoder 231 ₋₁ ′ to 231 _{−M + 1} ′
Each sub-decoder 231 ′ is provided corresponding to each bit line BL ′ of the main memory array 260. The sub decoder _{231 -1} '
And 231- _{M + 1} ', each sub-decoder 231-2' to 231 _{- M} 'includes two 3-input NAND gates for receiving an address signal and one 2-input NAND gate. An input terminal of the 2-input NAND gate is electrically connected to two output terminals of the 3-input NAND gate and an inverter 234, and an input terminal of the inverter is electrically connected to an output terminal of the NAND gate. .

The additional bit decoder 240 'includes N + 1 sub-decoders 241-1' to 241 _{- N + 1} ', and each sub-decoder 241' is provided corresponding to the bit line RBL 'of the additional memory array 270. . Each decoder _{241 -2 '~241 -N'} excluding sub decoder 241 'and _{241 N + 1'} are each two 4-input NAND gate for receiving an address signal and code signal, and a two-input NAND gate The input ends of the 2-input NAND gates are electrically connected to the output ends of the two 4-input NAND gates, respectively, and to the inverter. Further, 'the sub decoder _{241 -1} corresponding to' bit line RBL ₁ is 4-input NAND gate 242 which receives an address signal and a sign signal
And a 2-input NAND gate 243. The NAND gate 243 has an input end 1 electrically connected to the output end of the NAND gate 242 and another input end connected to the signal transmission line 23.
8'electrically connected.

Both ends of the signal transmission line 236 'are respectively connected to one input end of the 2-input NAND gate 233 of the sub-decoder 231- _{M + 1} ' and 4 inputs of the sub-decoder 241-1 '.
It is electrically connected to the output terminal of the input NAND gate 242. Further, both ends of the signal transmission line 238 'are respectively connected to the 2-input NAND gate 243 of the sub-decoder 241-1'.
Of the three input NAND gate 232 of the sub-decoder 231 _{-M + 1} '.

When the non-volatile storage medium 210 is operated, the address buffer 222 outputs the address signal to the bit line decoder 230 'and the addressable memory unit 224, respectively.
30 'decodes the address signal and selects an appropriate bit line BL of the main memory array 260. If the transmitted address signal matches the address stored in the addressable memory unit 224, the addressable memory unit 224 generates a matching signal,
The additional ground line decoder 240 'is driven by the code signal, the signal transmitted from the signal transmission line 236' is decoded based on the address signal, and the appropriate bit line line RBL 'of the additional memory array 270 is selected.

The bit line decoder 230 'is a shared bit
Tryin BL_CWhen trying to drive a sub-decor
Da 231_{-M + 1}'Output bit line BL_{M + 1}'But
Selected sub-decor of bit line decoder 230 '
231_{-M + 1}'Signal transmission line 238'
Add a signal corresponding to the work to the sub of the bit line decoder 240 '.
・ Decoder 241_-1’, And the sub-decoder 24
1_-1′ Output bit line RBL₁'Is also selected
To do so. Therefore, the sub decoder 23
1 _{-M + 1}', 241_-1'Is selected
(That is, the voltage is output). Conversely, add bit line deco
The grounding line GL shared by the feeder 240 '._CTry to drive
Sub decoder 241_-1'Output bit line
RBL ’₁Is selected and the bit line decoder 24
0'sub decoder 241_-1'Signal transmission line 23
An operation corresponding signal is transmitted to the bit line decoder 23 via 6 '.
0'sub-decoder 231_{-M + 1}’, The sub
・ Decoder 231_{-M + 1}′ Output bit line B
L_{M + 1}’Also be selected. Therefore, the sub
Coder 231 _{-M + 1}', 241_-1’
Selected (ie, output voltage).

FIG. 10B is a logic circuit diagram of a ground line decoder 230 ″ and an additional ground line decoder 240 ″ according to another embodiment. The sub-decoder 131 _{−M + 1} ″ corresponding to the bit line BL _{M + 1} ″ has a 3-input NA.
The control terminal of the 3-mode output inverter 235 includes an ND gate 232, an inverter 234, and a 3-mode output inverter 235, and is electrically connected to the signal transmission line 236 ″. In addition, the sub-decoder 241-1 ″ corresponding to the bit line RBL ₁ ″ has a 4-input mode NAND gate 242 for receiving an address signal and a sign signal.
, Inverter 244, and three-mode output inverter 24
5 is provided. The control end of the inverter 245 is the signal transmission line 2
38 ″ electrically connected.

In the embodiment according to FIGS. 10A and 10B described above, the bit line decoder 230 '/ 23.
0 ″, and additional bit line decoder 240 ′ / 24
By controlling the 0 '', the main memory array 26
0 and the additional memory array 270 are directly connected. That is,
The main memory array 260 and the additional memory array 270 share the drain to form a shared bit line, and the bit line decoder 230 '/ 230 "transmits the signal via the signal transmission lines 238' / 238". Additional bit line decoder 240 '/ 24 depending on signal
0 ″ is controlled, and the additional bit line decoder 240 ′ / 240 ″ controls the signal transmission line 236 ′ / 23.
By controlling the bit line decoders 230 ′ / 230 ″ by the operation corresponding signals transmitted through the 6 ″, the respective voltages are accurately applied to the shared bit lines.

In the conventional nonvolatile storage medium, since the field oxide layer and the dummy memory are provided between the main memory array and the additional memory array, the layout area is used more than necessary. The present invention directly connects the main memory array and the additional memory array by controlling the main memory array decoder and the additional memory decoder. Therefore, it is not necessary to provide the field oxide layer and the dummy memory to separate the main memory array from the additional memory array, and the layout area of the memory array can be reduced. That is, the non-volatile storage medium according to the present invention is a non-volatile storage medium having a kind of virtual ground array structure.

The above is the preferred embodiment of the present invention.
It does not limit the scope of the present invention. Therefore,
Any modifications and changes that can be made by those skilled in the art that have an equivalent effect on the present invention shall belong to the claims of the present invention.

[0078]

The non-volatile storage medium according to the present invention can improve the use efficiency of the layout area of the memory array region and effectively reduce the size of the semiconductor.

[Brief description of drawings]

FIG. 1 is a block diagram of a conventional nonvolatile storage medium.

FIG. 2A is an explanatory diagram illustrating a structure of a memory array of a conventional nonvolatile storage medium.

FIG. 2B is a circuit diagram of a memory array of a conventional nonvolatile storage medium.

FIG. 3 is a partial block diagram of a nonvolatile storage medium according to the present invention.

FIG. 4 is a circuit diagram of a memory array of a non-volatile storage medium according to the present invention.

FIG. 5 is a circuit diagram of a memory array of a nonvolatile storage medium according to the present invention.

FIG. 6A is a logic circuit diagram of an embodiment of a ground line decoder and an additional ground line decoder according to the present invention.

FIG. 6B is a logic circuit diagram of a ground line decoder and an additional ground line decoder according to another embodiment of the present invention.

FIG. 7 is a partial block diagram of a nonvolatile storage medium according to the present invention.

FIG. 8 is a circuit diagram of a memory array of a nonvolatile storage medium according to the present invention.

FIG. 9 is an explanatory diagram showing a structure of a memory array of a nonvolatile storage medium according to the present invention.

FIG. 10A is a logic circuit diagram of one embodiment of a bit line decoder and an additional bit line decoder according to the present invention.

FIG. 10B is a logic circuit diagram of a bit line decoder and an additional bit line decoder according to another embodiment of the present invention.

[Explanation of symbols]

110, 210 Non-volatile storage medium 120, 220 Peripheral circuit area 124, 224 Addressable memory unit 122, 222 Address buffer 130, 130 ', 130 "Ground line decoder 131', 131", 141 ', 141 ", 231, 2
31 ', 231 ", 241, 241', 241" Sub-decoders 132, 133, 142, 143 NAND gates 134, 144, 234, 244 Inverters 135, 145, 235, 245 Three-mode output inverters 140, 140 ', 140 "Additional ground line decoders 136, 136 ', 136", 138, 138', 13
8 ", 236, 236 ', 236", 238, 23
8 ', 238 "Signal transmission line 150, 250 Memory array area 160, 260 Main memory array 170, 270 Additional memory array 180, 280 Semiconductor chip 182, 282 Base 184, 286 Source 186, 284 Drain 188 Gate pole 230, 230' , 230 "bit line decoder 232, 233, 242, 243 NAND gate pole 240, 240 ', 240" additional bit line decoder 288 gate pole GL, RGL ground line BL, RBL bit line

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/788 G11C 17/00 634A 29/792

Claims (32)

[Claims] 1. A non-volatile storage medium provided on a base of a semiconductor chip, comprising a main memory array, an additional memory array directly connected to the main memory array, and a shared source. Is at least 1 comprising a source and drain provided in the base of the semiconductor chip
The additional memory array includes the above memory cell, at least one bit line electrically connected to the drain of the memory cell, and at least one ground line electrically connected to the source of the memory cell. Is an additional memory cell including an additional source and an additional drain provided in the base of the semiconductor chip, at least one additional bit line electrically connected to the additional drain of the additional memory cell, and the additional memory. At least one additional ground line electrically connected to an additional source of the cell, wherein the shared source is a source at a position where the main memory array and the additional memory array are in contact with each other, and an additional drain. And a non-volatile storage medium. 2. The non-volatile storage medium further comprises a peripheral circuit area, in the peripheral circuit area, a main memory ground line decoder electrically connected to a ground line of the main memory array, and the additional memory array. An additional memory ground line decoder electrically connected to the additional ground line and at least two or more signal transmission lines, and both ends of the signal transmission line are the main memory ground line decoder and the additional memory ground line, respectively. The non-volatile storage medium according to claim 1, which is electrically connected to a decoder. 3. When the shared source is electrically connected to the shared ground line and the main memory ground line decoder performs address arrangement on the shared ground line, the main memory ground line decoder is configured to perform the address arrangement via the signal transmission line. Transmitting a signal to the additional memory ground line decoder to determine the voltage of the shared ground line and causing the electrical connection between the shared ground line and the additional memory ground line decoder to form an open circuit condition; When the additional memory ground line decoder performs address arrangement on the common ground line, the additional memory ground line decoder transmits a signal to the main memory ground line decoder via another signal transmission line to transmit the shared ground line. 3. The circuit of claim 2 wherein the voltage is determined and the electrical connection between the shared ground line and the main memory ground line decoder is configured to form an open circuit condition. Volatile storage medium. 4. The main memory ground line decoder comprises a sub-decoder electrically connected to the shared ground line, the sub-decoder being a 3-input NAND for receiving an address signal.
A gate, an inverter, and a three-mode inverter, the input end of the inverter is electrically connected to the output end of the three-input NAND gate, and the control end of the three-mode inverter is in the additional ground line decoder. In the additional memory ground line decoder, the sub-decoder electrically connected to the output terminal of the 4-input NAND gate of the sub-decoder electrically connected to the common ground line in The decoder includes a 4-input NAND gate that receives an address signal and a sign signal, an inverter, and a 3-mode inverter, the input terminal of the inverter being electrically connected to the output terminal of the 4-input NAND gate. , A control terminal of the 3-mode inverter is electrically connected to an output terminal of a 3-input NAND gate of a sub decoder electrically connected to the shared ground line in the main memory ground line decoder. Nonvolatile storage medium according to claim 3, characterized in that. 5. The shared source is electrically connected to the shared ground line, and when the main memory ground line decoder makes an address arrangement on the shared ground line, the main memory ground line decoder causes the shared ground line to pass through a signal transmission line. A sub-decoder for transmitting a signal to the additional memory ground line decoder to electrically connect to the shared ground line and outputting an equivalent voltage. When address allocation is performed on a line, the additional memory ground line decoder transmits a signal to the main memory ground line decoder via a signal transmission line to electrically connect to the shared ground line. The nonvolatile storage medium according to claim 2, wherein the nonvolatile storage medium outputs the same voltage. 6. The main memory ground line decoder comprises a sub-decoder electrically connected to the shared ground line, the sub-decoder being a 3-input NAND for receiving an address signal.
A gate, a two-input NAND gate, and an inverter, one input terminal of the two-input NAND gate is electrically connected to an output terminal of the three-input NAND gate, and the other input of the two-input NAND gate The end is electrically connected to the output end of the NAND gate of the sub-decoder electrically connected to the shared ground line in the additional ground line decoder, and electrically connected to the shared ground line in the additional memory ground line decoder. The sub-decoder connected to is composed of a 4-input NAND gate that receives an address signal and a sign signal, a 2-input NAND gate, and an inverter, and the 1-input terminal of the 2-input NAND gate has a 4-input NAND gate. The output of the 3-input NAND gate of the sub-decoder electrically connected to the output terminal of the gate and the other input terminal of the 2-input NAND gate electrically connected to the shared ground line in the main memory ground line decoder. To electrically connect to the end Non-volatile storage medium of claim 5, symptoms. 7. The non-volatile storage medium according to claim 1, wherein the non-volatile storage medium is a non-volatile storage medium having a virtual ground line array structure. 8. A non-volatile storage medium provided on a base of a semiconductor chip, comprising a main memory array, an additional memory array directly connected to the main memory array, and a shared drain. Is at least 1 comprising a source and drain provided in the base of the semiconductor chip
The additional memory array comprising the above memory cell, at least one bit line electrically connected to the drain of the memory cell, and at least one ground line electrically connected to the source of the memory cell. Is an additional memory cell provided in the base of the semiconductor chip, the additional memory cell including an additional source and an additional drain, at least one additional bit line electrically connected to the additional drain of the additional memory cell, and the additional memory. At least one additional ground line electrically connected to an additional source of the cell, wherein the shared drain is a source at a position where the main memory array and the additional memory array are in contact with each other, and is an additional drain. And a non-volatile storage medium. 9. The non-volatile storage medium further comprises a peripheral circuit area, in the peripheral circuit area, a main memory bit line decoder electrically connected to a bit line of the main memory array, and the additional memory array. An additional memory bit line decoder electrically connected to the additional bit line of
9. At least two signal transmission lines are provided, and both ends of the signal transmission lines are electrically connected to the main memory bit line decoder and the additional memory bit line decoder, respectively. The nonvolatile storage medium described. 10. When the shared drain is electrically connected to the shared bit line and the main memory bit line decoder performs an address arrangement on the shared bit line, the main memory bit line decoder is connected via a signal transmission line. A signal is transmitted to the additional memory bit line decoder to determine a voltage of the shared bit line and an electrical connection between the shared bit line and the additional memory bit line decoder forms an open circuit state. When the additional memory bit line decoder performs address arrangement on the shared bit line, the additional memory bit line decoder transmits a signal to the main memory bit line decoder via another signal transmission line to transmit the shared bit line. Of the common bit line and the main memory bit line Non-volatile storage medium of claim 9, the electrical connection between the coder is equal to or configured to form a circuit open condition. 11. The main memory bit line decoder comprises a sub-decoder electrically connected to the shared bit line, the sub-decoder being a 3-input NAND for receiving an address signal.
A gate, an inverter, and a three-mode inverter, the input end of the inverter is electrically connected to the output end of the three-input NAND gate, and the control end of the three-mode inverter is in the additional bit line decoder. At the output terminal of the 4-input NAND gate of the sub-decoder electrically connected to the shared bit line at, and in the additional memory bit line decoder electrically connected to the shared bit line The decoder includes a 4-input NAND gate that receives an address signal and a sign signal, an inverter, and a 3-mode inverter, the input terminal of the inverter being electrically connected to the output terminal of the 4-input NAND gate. A sub-decoder in which an input terminal of the three-mode inverter is electrically connected to the shared bit line in the main memory bit line decoder of
11. The nonvolatile storage medium according to claim 10, which is electrically connected to an output terminal of a 3-input NAND gate. 12. The shared drain is electrically connected to the shared bit line, and when the main memory bit line decoder performs address arrangement on the shared bit line,
The main memory bit line decoder transmits a signal to the additional memory bit line decoder via a signal transmission line to electrically select the sub-decoders electrically connected to the shared bit line, and outputs the same voltage. Then, when the additional memory bit line decoder performs address arrangement on the shared bit line, the additional memory bit line decoder transmits a signal to the main memory bit line decoder via a signal transmission line to the shared bit line. All sub-decoders that are electrically connected are selected,
10. The nonvolatile storage medium according to claim 9, wherein the nonvolatile storage medium outputs the same voltage. 13. The main memory bit line decoder comprises a sub-decoder electrically connected to the shared bit line, the sub-decoder being a 3-input NAND for receiving an address signal.
A gate, a two-input NAND gate, and an inverter, one input terminal of the two-input NAND gate is electrically connected to an output terminal of the three-input NAND gate, and the other input of the two-input NAND gate An end electrically connected to an output end of a 4-input NAND gate of a sub-decoder electrically connected to the shared bit line in the additional bit line decoder, and connected to the shared bit line in the additional memory bit line decoder. The electrically connected sub-decoder includes a 4-input NAND gate that receives an address signal and a sign signal, a 2-input NAND gate, and an inverter,
One input terminal of the two-input NAND gate is electrically connected to the output terminal of the four-input NAND gate, and the other input terminal of the two-input NAND gate is electrically connected to the shared bit line in the main memory bit line decoder. Of sub decoders
13. The nonvolatile storage medium according to claim 12, which is electrically connected to an output end of a 3-input NAND gate. 14. The non-volatile storage medium according to claim 8, wherein the non-volatile storage medium is a non-volatile storage medium having a virtual ground array structure. 15. A non-volatile storage medium provided on a base of a semiconductor chip, comprising a main memory array, an additional memory array and a shared doping region, the main memory array comprising at least one memory. A cell, the additional memory array is directly connected to the main memory array and has at least one memory cell, and the shared doping region is in contact with the main memory array and the additional memory array. A non-volatile storage medium, characterized in that it is electrically connected to the additional memory cell and the memory cell provided on the both sides and adjacent to each other on both side edges. 16. The memory cell and the additional memory cell respectively include a source and a drain provided in the base of the semiconductor chip, and the doping region is in contact with the main memory array and the additional memory array. 16. The non-volatile storage medium according to claim 15, wherein the non-volatile storage medium serves as a shared source of a memory cell and an additional memory cell which are adjacent to each other in position. 17. The memory cell and the additional memory cell respectively include a source and a drain provided in a base of the semiconductor chip, and the doping region is in contact with the main memory array and the additional memory array. The non-volatile storage medium according to claim 15, wherein the non-volatile storage medium serves as a shared drain of a memory cell and an additional memory cell which are adjacent to each other at a position. 18. A method of controlling a non-volatile storage medium having a virtual ground array structure, wherein the non-volatile storage medium comprises a main memory array, an additional memory array directly connected to the main memory array, a peripheral circuit area, and A shared doping region provided at a contact position between the main memory array and the additional memory array, the main memory array including at least one memory cell and a bit electrically connected to a drain of the memory cell. A line, and a ground line electrically connected to a source of the memory cell, the additional memory array including at least one or more additional memory cells and an additional electrically connected to a drain of the additional memory cells. A bit line and an additional ground line electrically connected to the source of the additional memory cell, A main memory ground line decoder electrically connected to a ground line of the main memory array, an additional memory ground line decoder electrically connected to an additional ground line of the additional memory array, and at least a first region in the path region. A method of controlling a non-volatile storage medium, comprising: first and second signal transmission lines, wherein both ends of each signal transmission line are connected to the main memory ground line decoder and the additional memory ground line decoder. Includes the steps of: when the main memory ground line decoder is used to perform address placement on a shared ground line electrically connected to the shared doping region, the main memory ground line decoder A signal to the additional memory ground line decoder to determine the voltage of the shared ground line, and the shared ground line and the additional memory ground line decoder. In the case where an open circuit state is formed in the electrical connection with the memory and an address is arranged on the shared ground line by using the additional memory bit line decoder, the additional memory ground line decoder operates as a second signal transmission line. A signal to the main memory ground line decoder to determine the voltage of the common ground line and form an open circuit state in the electrical connection between the common ground line and the main memory ground line decoder. A method for controlling a non-volatile storage medium, comprising: 19. A method of controlling a non-volatile storage medium having a virtual ground array structure, wherein the non-volatile storage medium comprises a main memory array, an additional memory array directly connected to the main memory array, a peripheral circuit area, and A shared doping region provided at a contact position between the main memory array and the additional memory array, the main memory array including at least one memory cell and a bit electrically connected to a drain of the memory cell. A line and a ground line electrically connected to a source of the memory cell, the additional memory array electrically connected to at least one additional memory cell and a drain of the additional memory cell. An additional bit line and an additional ground line electrically connected to the source of the additional memory cell, In the circuit area, a main memory ground line decoder electrically connected to a ground line of the main memory array, an additional memory ground line decoder electrically connected to an additional ground line of the additional memory array, and at least a first A method of controlling a non-volatile storage medium, comprising: first and second signal transmission lines, wherein both ends of each signal transmission line are connected to the main memory ground line decoder and the additional memory ground line decoder. When the address arrangement is performed on the shared ground line electrically connected to the shared doping region by using the main memory ground line decoder, the main memory ground line decoder A signal is transmitted to the additional memory ground line decoder via the signal transmission line of the above, and both the common ground line and each sub-decoder are selected and equivalent When the address allocation is performed on the shared ground line by using the additional memory ground line decoder, the additional memory ground line decoder outputs a signal through the second signal transmission line to the main memory. It is transmitted to the ground line decoder and the common ground line and each sub
A method for controlling a non-volatile storage medium, characterized in that all the decoders are selected and the same voltage is output. 20. A method of controlling a non-volatile storage medium having a virtual ground array structure, wherein the non-volatile storage medium includes a main memory array, an additional memory array directly connected to the main memory array, a peripheral circuit area, and A shared doping region provided at a contact position between the main memory array and the additional memory array, the main memory array including at least one memory cell and a bit electrically connected to a drain of the memory cell. A line and a ground line electrically connected to a source of the memory cell, the additional memory array electrically connected to at least one additional memory cell and a drain of the additional memory cell. An additional bit line and an additional ground line electrically connected to the source of the additional memory cell, In the circuit area, a main memory bit line decoder electrically connected to a bit line of the main memory array, an additional memory bit line decoder electrically connected to an additional bit line of the additional memory array, and at least a first A method of controlling a non-volatile storage medium, comprising: first and second signal transmission lines, wherein both ends of each signal transmission line are connected to the main memory bit line decoder and the additional memory bit line decoder. Includes the steps of: when using the main memory bit line decoder to perform an address arrangement on a shared bit line electrically connected to the shared doping region, the main memory bit line decoder The signal is transmitted to the additional memory bit line decoder through the signal transmission line of Determining the voltage of the bit line and forming an open circuit state in the electrical connection between the shared bit line and the additional memory bit line decoder, and utilizing the additional memory bit line decoder to perform the shared bit line Address allocation to the shared bit line, the additional memory bit line decoder transmits a signal to the memory bit line decoder via a second signal transmission line to determine the voltage of the shared bit line, and A method for controlling a non-volatile storage medium, characterized in that a circuit open state is formed in an electrical connection with the main memory bit line decoder. 21. A method of controlling a non-volatile storage medium having a virtual ground array structure, wherein the non-volatile storage medium comprises a main memory array, an additional memory array directly connected to the main memory array, a peripheral circuit area, and A shared doping region provided at a contact position between the main memory array and the additional memory array, the main memory array including at least one memory cell and a bit electrically connected to a drain of the memory cell. A line and a ground line electrically connected to a source of the memory cell, the additional memory array electrically connected to at least one additional memory cell and a drain of the additional memory cell. An additional bit line and an additional ground line electrically connected to the source of the additional memory cell, In the circuit area, a main memory bit line decoder electrically connected to a bit line of the main memory array, an additional memory bit line decoder electrically connected to an additional bit line of the additional memory array, and at least a first A method for controlling a non-volatile storage medium according to the above-mentioned configuration, which comprises a first signal transmission line and a second signal transmission line, and both ends of each signal transmission line are connected to the main memory bit line decoder and the additional memory bit line decoder, respectively. If the address arrangement is performed on a shared bit line electrically connected to the shared doping region by using the main memory bit line decoder, the main memory bit line decoder A signal is transmitted to the additional memory bit line decoder through a signal transmission line to transmit the shared bit line decoder. IN and the respective sub-decoders are both selected and output the same voltage, and when the address allocation is performed on the shared bit line using the additional memory bit line decoder, the additional memory bit line decoder Transmits a signal to the main memory bit line decoder via a second signal transmission line so that the shared bit line and each sub-decoder are both selected and output the same voltage. And a method for controlling a non-volatile storage medium. 22. A non-volatile storage medium provided on a base of a semiconductor chip, comprising: a main memory array including at least one or more memory cells; and at least 1 directly connected to the main memory array.
An additional memory array including the above additional memory cells, the memory cell provided at a position where the main memory array and the additional memory array are in contact with each other, and the shared doping shared by the additional memory cells. A non-volatile storage medium comprising: an area; and a peripheral circuit area including at least one decoder. 23. The non-volatile storage medium according to claim 22, wherein the decoder includes a main memory decoder, an additional memory decoder, and a shared decoder. 24. The non-volatile storage medium according to claim 23, wherein the shared decoder is a shared ground line decoder. 25. The non-volatile storage medium of claim 23, wherein the shared decoder is a shared bit line decoder. 26. A non-volatile storage medium provided on a base of a semiconductor chip, comprising a main memory array, an additional memory array directly connected to the main memory array, and a peripheral circuit area, the main memory array. Is at least one memory cell having a source and a drain provided in the base of the semiconductor chip, a bit line electrically connected to the drain of the memory cell, and a source electrically connected to the memory cell A ground line, the additional memory array having at least an additional source and an additional drain provided in the base of the semiconductor chip.
Comprising at least one additional memory cell, an additional bit line electrically connected to an additional drain of the additional memory cell, and an additional ground line electrically connected to an additional source of the additional memory cell, and A non-volatile storage medium, wherein the additional memory array shares a common doping region with the main memory array, and the peripheral circuit region includes at least one decoder. 27. The decoder includes a main memory ground line decoder electrically connected to a ground line of the main memory array, and an additional memory ground line decoder electrically connected to an additional ground line of the additional memory array. 27. At least two signal transmission lines are provided, and both ends of each signal transmission line are electrically connected to the main memory ground line decoder and the additional memory ground line decoder. Non-volatile storage medium. 28. The non-volatile storage medium of claim 27, wherein the decoder further comprises a shared ground line decoder. 29. The non-volatile storage medium according to claim 26, wherein the shared doping region is a source at a position where the main memory array and the additional memory array are in contact with each other, and is also an additional source. . 30. The decoder comprises: a main memory bitline decoder electrically connected to a bitline of the main memory array; and an additional memory bitline decoder electrically connected to an additional bitline of the additional memory array. 27. The device according to claim 26, comprising at least two signal transmission lines, and both ends of each signal transmission line are electrically connected to the main memory bit line decoder and the additional memory bit line decoder. Non-volatile storage medium. 31. The non-volatile storage medium of claim 30, wherein the decoder further comprises a shared bit line decoder. 32. The nonvolatile memory according to claim 26, wherein the shared doping region serves as a drain at a position where the main memory array and the additional memory array are in contact with each other, and also serves as an additional drain. Medium.