JP2003198342A - Voltage comparison circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a voltage comparison circuit capable of increasing a noise resistance characteristics and achieving desired operations. <P>SOLUTION: A changing point detecting circuit 6 detects a level changing point of an output signal from a comparator 2, and a time comparison circuit 9 reduces a hysteresis width of the comparator 2 by switching a resistance value of a variable resistance circuit 5 when an elapsed time from the changing point of the output signal counted by a timer circuit 7 passes up to the time set by a time setting register 8. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage comparison circuit having a hysteresis characteristic, and particularly to a CD-
The present invention relates to a voltage comparison circuit that is used in a circuit that handles a wobble signal or an RF signal in R / RW signal processing, and that can reduce malfunction due to noise by changing the hysteresis characteristic according to the time zone from the change point of the signal.

[0002]

2. Description of the Related Art FIG. 10 is a circuit diagram showing an example of a voltage comparison circuit having a general hysteresis characteristic. Figure 10
In the voltage comparison circuit 100,
1. A reference voltage generation circuit 102 for generating and outputting a predetermined reference voltage Vr, a feedback resistor 103, and a resistor 104 for setting a hysteresis width.
In the voltage comparison circuit 100, when the input signal Si rises, the input voltage Vi becomes the reference voltage Vr and the hysteresis voltage V.
When it becomes higher than the voltage obtained by adding h, a high level signal is output, and when the input signal falls, it becomes low when the input voltage Vi becomes lower than the reference voltage Vr minus the hysteresis voltage Vh. Output level signal.

On the other hand, as a prior art relating to the characteristic improvement of a voltage comparison circuit for the purpose of improving the noise resistance characteristic, Japanese Patent Application Laid-Open No. HEI-1 is proposed.
Japanese Patent Application Laid-Open No. 1-248761 discloses that a dead time zone of a comparator is provided for a certain period of time. In Japanese Patent Laid-Open No. 11-340801, a hysteresis characteristic is selected depending on whether the input signal is rising or falling. Those that can be set selectively are disclosed.

[0004]

However, when a signal with a small amplitude is handled by the voltage comparison circuit, it is necessary to apply a large gain in processing the signal, and at that time, it is generated from the periphery of the LSI and the LSI itself. There is also a problem that the noise component that is also amplified. When such a signal with large noise is binarized into a digital signal by the voltage comparison circuit, the voltage comparison circuit may oscillate as shown in FIG. 11 due to the noise component. In addition, in order for the voltage comparison circuit to accurately perform voltage comparison on the input signal,
It was also not possible to set the hysteresis width of the voltage comparison circuit large. In FIG. 11, the waveform of a shows the input signal Si, and the waveform of b shows the waveform of the output signal of the comparator 101.

In FIG. 11, the input signal Si is 2.1V.
It is assumed that the input signal Si has noise on it. The voltage comparison circuit 10 of FIG.
At 0, the hysteresis width is fixed at 20 mV, for example, and thus it can be seen from FIG. 11 that the output signal of the comparator 101 oscillates when the input signal Si is around 2.1 V. This is because the noise component of the input signal Si sometimes exceeds the hysteresis width. However, if the hysteresis width is uniformly increased, the change point of the signal level of the output signal in the comparator 101 has a small hysteresis width. There is a problem that it will be slower than time.

On the other hand, the signal for voltage comparison in the voltage comparison circuit often has a certain width within the range of the frequency f. In such a case, the same applies to the output change of the voltage comparison circuit. The interval between the signal level change points in the signal output from the voltage comparison circuit is 1 / f. That is, the next change point of the signal level in the output signal of the voltage comparison circuit can be predicted to some extent.
For this reason, a method of making the voltage comparison circuit insensitive by setting the mask or threshold voltage to the power supply voltage VCC or the ground voltage GND during the period when the output signal from the voltage comparison circuit is considered to have no change point, etc. Was being considered.

However, if there is a time zone in which the voltage comparison circuit is insensitive as described above, the output signal of the voltage comparison circuit is There was a problem that the originally desired change point was missing and the effect appeared in the circuit in the subsequent stage.

The present invention has been made in order to solve the above-mentioned problems. The hysteresis width is increased in a time zone in which it is considered that there is no change point of the input signal, and near the change point of the input signal. It is an object of the present invention to obtain a voltage comparison circuit capable of improving a noise resistance characteristic and realizing a desired operation by returning the hysteresis width to a normal low state.

[0009]

A voltage comparison circuit according to the present invention compares a predetermined reference voltage with a voltage of an input signal,
A voltage comparing circuit that outputs a binary signal indicating the comparison result and has a hysteresis characteristic, compares the reference voltage with the voltage of the input signal, and outputs a binary signal indicating the comparison result. A comparison unit, a hysteresis width switching unit that switches the hysteresis width in the voltage comparison unit according to an input control signal, a change point detection unit that detects a change point of the output signal level of the voltage comparison unit, Each time the change point detection unit detects a change point, an elapsed time measurement unit that measures and sequentially outputs an elapsed time from the change point, a time setting unit in which a predetermined time is set, and the elapsed time measurement unit And a time comparison unit for switching the hysteresis width by outputting a predetermined control signal to the hysteresis width switching unit when the elapsed time from is equal to or longer than the predetermined time set in the time setting unit. Than it is.

Specifically, the hysteresis width switching unit is configured to switch so that the hysteresis width becomes small while a predetermined control signal is being input from the time comparison unit.

Further, there is provided a changing point cycle detecting section for detecting a cycle between the changing points of the output signal level in the voltage comparing section from the elapsed time output from the elapsed time measuring section, and the changing point cycle detecting section comprises: The time calculated by a predetermined method from the average value of each cycle between the detected change points may be updated and set in the time setting unit each time the change point detection unit detects the change point. .

The voltage comparison circuit according to the present invention is a voltage comparison circuit having a hysteresis characteristic, which compares a predetermined reference voltage with the voltage of an input signal and outputs a binary signal indicating the comparison result. , Comparing the reference voltage with the voltage of the input signal and outputting a binary signal indicating the comparison result, and switching the hysteresis width in the voltage comparison unit in accordance with the input control signal. Hysteresis width switching unit, change point detection unit that detects a change point of the output signal level of the voltage comparison unit, and each time the change point detection unit detects a change point, measures the elapsed time from the change point Then, the elapsed time measuring section that sequentially outputs, a plurality of time setting sections each having a different predetermined time set, and the predetermined time set in the corresponding time setting section from the elapsed time measuring section Na When, in which each and a plurality of time comparison unit to perform the switching of the hysteresis width by outputting a predetermined control signal to the hysteresis switch unit.

More specifically, the hysteresis width switching section responds to each control signal input from each time comparison section,
The hysteresis width is switched so as to be gradually reduced.

Further, each change point cycle detecting section for detecting a cycle between change points in the output signal level of the corresponding voltage comparing section from the elapsed time output from the elapsed time measuring section is provided. The detection unit may set the time calculated by a predetermined method from the average value of each cycle between the detected change points in each corresponding time setting unit.

On the other hand, a signal delay unit for delaying and outputting the output signal of the voltage comparison unit may be provided.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail based on the embodiments shown in the drawings. First embodiment. FIG. 1 is a block diagram showing an example of a voltage comparison circuit according to the first embodiment of the present invention.
The voltage comparison circuit 1 of FIG. 1 compares the voltage of the input signal Si input from the input terminal IN with a predetermined reference voltage Vr, and outputs a binary signal indicating the comparison result to an internal circuit (not shown). ) And output to the output terminal OUT via the buffer circuit 12 forming an I / O cell.

In FIG. 1, the voltage comparison circuit 1 includes a comparator 2, a reference voltage generation circuit 3 for generating and outputting a predetermined reference voltage Vr, a resistor 4 forming a feedback circuit for the comparator 2, and an input. And a variable resistance circuit 5 for adjusting the hysteresis width, which switches the resistance value in accordance with the generated control signal. Further, the voltage comparison circuit 1 includes a change point detection circuit 6 that detects a change point of the signal level in the output signal of the comparator 2, a timer circuit 7, a time setting register 8 in which predetermined time information is set, and a timer circuit. 7, a time comparison circuit 9 that compares the elapsed time information output from 7 with the time information set in the time setting register 8 and outputs the comparison result, and a delay circuit that delays and outputs the output signal of the comparator 2. 10 and 10. The comparator 2 is a voltage comparison unit, the variable resistance circuit 5 (strictly including the resistor 4) is a hysteresis width switching unit, the timer circuit 7 is an elapsed time measuring unit, and the time setting register 8 is a time setting unit. I am doing it.

The input signal Si is input to the non-inverting input terminal of the comparator 2 via the variable resistance circuit 5, and the resistor 4 is connected between the output terminal and the non-inverting input terminal of the comparator 2. The reference voltage Vr from the reference voltage generation circuit 3 is input to the inverting input terminal of the comparator 2, and the comparator 2 compares the voltage Vi input to the non-inverting input terminal with the reference voltage Vr. A binary signal corresponding to the comparison result is output. When the change point detection circuit 6 detects that the signal level of the output signal of the comparator 2 has changed, the change point detection circuit 6 outputs a predetermined change point detection signal Sa to the timer circuit 7.

On the other hand, while the output signal of the comparator 2 is used as the input signal of the change point detection circuit 6, the other internal circuits, the buffer circuit 12 and the like are provided with the delay circuit 10 including delay elements and the like. The point of change is intentionally delayed. By doing so, the resistance value is switched by the variable resistance circuit 5 earlier than the digital noise generated by the change in the output signal level of the comparator 2 itself, and the time zone in which the digital noise occurs A malfunction can be avoided by increasing the hysteresis width of the comparator 2 at.

Next, the timer circuit 7 is composed of a counter, and when the change point detection signal Sa is input, after resetting the count value of the counter indicating the elapsed time information to an initial value, for example, 0. , Start counting. The timer circuit 7 constantly outputs the count value to the time comparison circuit 9, and when the count value from the timer circuit 7 reaches the value stored in the time setting register 8, the time comparison circuit 9 outputs a predetermined control signal. The SC is output to the variable resistance circuit 5.
The variable resistance circuit 5 changes the resistance value according to the input control signal SC and changes the hysteresis width of the comparator 2.

FIG. 2 is a diagram showing a circuit example of the variable resistance circuit 5. In FIG. 2, the variable resistance circuit 5 includes a switch 15 and resistors 16 and 17, and
A series circuit of the resistor 5 and the resistor 16 and the resistor 17 are connected in parallel, and the parallel circuit is connected between the input terminal IN and the non-inverting input terminal of the comparator 2. Switch 15
Turns on and turns off, and turns off. For example, the resistance value of the resistor 16 is Ra and the resistance value of the resistor 17 is
When the resistance value of 9 is Ra, the hysteresis width of the comparator 2 is set to 10 by turning the switch 15 on or off.
It can be doubled.

In such a configuration, the comparator 2
Outputs a high level signal when the input voltage Vi is higher than the reference voltage Vr, and outputs a low level signal when the input voltage Vi is lower than the reference voltage Vr. Next, the change point detection circuit 6 detects whether the output signal of the comparator 2 has changed from low level to high level or from high level to low level.

When the change point detection circuit 6 detects the change point of the output signal of the comparator 2, it outputs a predetermined change point detection signal Sa to the timer circuit 7. Timer circuit 7
When the change point detection signal Sa is input, the counter resets the counter to 0 and then starts counting up.
In the timer circuit 7, the reference of the operation is a clock signal of a predetermined frequency or a clock signal which is in direct proportion to the input signal Si, and the time information including the set value serves as a reference. This is a value in units of clocks.

The time setting register 8 can arbitrarily set time information from an external CPU (not shown) or the like.
The timing of changing the hysteresis width of the comparator 2 is set. In the time comparison circuit 9, the timer circuit 7
The time information indicating the elapsed time T from the change in the output signal level of the comparator 2 output from the time information is compared with the time information indicating the time Ts set in the time setting register 8, and the elapsed time T is set to the set time Ts. Then, a predetermined control signal SC is output to the variable resistance circuit 5. When the control signal SC is input to the variable resistance circuit 5, the switch 15 is turned on to be in a conductive state, and the resistance 16 and the resistance 16 are connected in parallel. Therefore, in the case of FIG. 2, the resistance value of the variable resistance circuit 5 becomes 1/10, and the hysteresis width of the comparator 2 is 1
It becomes 0 times.

FIG. 3 is a diagram showing an operation example of the voltage comparison circuit 1 shown in FIGS. 1 and 2. The waveform of a shown by the solid line is the input signal Si, and the waveform of b shown by the solid line is the waveform. An output waveform of the comparator 2 is indicated by a one-dot chain line, and a waveform of c indicates a change in the hysteresis width of the comparator 2. In FIG. 3, the input signal Si is a sine wave centered on 2.1 V, noise is added to the input signal Si, and there are two hysteresis widths, 20 mV and 200 mV.

As can be seen from FIG. 3, when the output signal level of the comparator 2 changes, the hysteresis width is immediately switched to 200 mV, the noise resistance characteristic is improved, and the oscillation of the output signal of the comparator 2 is prevented. The elapsed time is counted by the timer circuit 7 from the output signal level change point of the comparator 2, and after a predetermined time elapses, the hysteresis width is returned to 20 mV to prepare for the next signal level change point. In this way, the hysteresis width is 20 mV
Compared with each waveform in the conventional voltage comparison circuit of FIG. 11 fixed to FIG. 11, the output signal of the comparator 2 does not oscillate, and the noise resistance characteristic is improved without delaying the change point of the signal level. I understand.

In the above description, the case where the time setting register 8 and the time comparison circuit 9 are provided one by one has been described as an example, but as shown in FIG. 4, the time setting register and the time comparison circuit 9 are provided. You may make it each provide a plurality. In addition, in FIG. 4, the case where three time setting registers and three time comparison circuits are provided is shown as an example, and the same components as those in FIG. Only the differences will be described. 4 is different from FIG. 1 in that three time setting registers 8a to 8c are used instead of the time setting register 8 in FIG. 1, and three time comparison circuits 9a to 9c are used in place of the time comparing circuit 9 in FIG. In addition to the above, the circuit configuration of the variable resistance circuit 5 in FIG. 1 is changed accordingly to form the variable resistance circuit 5a. In addition,
The variable resistance circuit 5a forms a hysteresis width switching unit, and the time setting registers 8a to 8c form a time setting unit.

The voltage comparison circuit 1 in FIG. 4 includes a comparator 2, a reference voltage generation circuit 3, a resistor 4, and a variable resistor for adjusting the hysteresis width, which changes the resistance value according to the input control signal. The circuit 5a, the change point detection circuit 6, the timer circuit 7, the time setting registers 8a to 8c in which predetermined time information is set, respectively, and the time setting register 8a corresponding to the elapsed time information output from the timer circuit 7. Time comparison circuits 9a to 9c that compare the time information set to 8c to output the comparison result, and a delay circuit 10.

The timer circuit 7 constantly outputs the count value to the time comparison circuits 9a to 9c, respectively, and the time comparison circuits 9a to 9c respectively correspond to the time setting registers 8a to 8c to which the count value from the timer circuit 7 corresponds. When the value stored in the variable resistance circuit 5a is reached, predetermined control signals SCa to SCc are output to the variable resistance circuit 5a, respectively. The variable resistance circuit 5a is
The resistance value is changed according to the input control signals SCa to SCc to change the hysteresis of the comparator 2.

FIG. 5 is a diagram showing a circuit example of the variable resistance circuit 5a. In FIG. 5, the variable resistance circuit 5a includes switches 21 to 23 and resistors 24 to 27,
A series circuit of a switch 21 and a resistor 25, a series circuit of a switch 22 and a resistor 26, a series circuit of a switch 23 and a resistor 27, and a resistor 24 are connected in parallel, and the parallel circuit includes an input terminal IN and a comparator 2. It is connected to the non-inverting input terminal of. The switches 21 to 23 are
When turned on, it becomes conductive, and when turned off, it becomes cutoff.

For example, the resistance values of the resistors 24 and 25 are 8 × R, the resistance value of the resistor 26 is 4 × R, the resistance value of the resistor 27 is 2 × R, and the switches 21, 22 and 2 are used.
By turning on the switches in the order of 3, 8R, 4R,
It is possible to select four resistance values of 2R and 1R.
Further, by sequentially turning on the switches in this way, the number of times the switches are turned on or off at the same time can be minimized, and the resistance value of the variable resistance circuit 5a can be prevented from being disturbed when the resistance value is changed. Comparator 2
There is an advantage that disturbance of the hysteresis width of can be prevented. When the resistance value of the variable resistance circuit 5a is set to 1R by selecting the resistance in the variable resistance circuit 5a as described above, the hysteresis width of the comparator 2 is 1 time, 2 times, 4 times at each time zone. , Can be changed eight times.

Here, the time setting register 8a has time information indicating the predetermined time T1, the time setting register 8b has time information indicating the predetermined time T2, and the time setting register 8c has time information indicating the predetermined time T3. These are respectively set, and the relationship between the predetermined times T1 to T3 is T1 <T2 <T3. In this case, first, the time comparison circuit 9a determines that the time information from the timer circuit 7 indicates the predetermined time T1.
The switch 21 is turned on to make it conductive. Next, when the time information from the timer circuit 7 indicates the predetermined time T2, the time comparison circuit 9b turns on the switch 22 to make it conductive. Next, when the time information from the timer circuit 7 indicates the predetermined time T3, the time comparison circuit 9c turns on the switch 23 to make it conductive.

FIG. 6 is a diagram showing an operation example of the voltage comparison circuit 1 shown in FIGS. 4 and 5, in which the waveform of a shown by the solid line is the input signal Si and the waveform of b shown by the solid line is. An output waveform of the comparator 2 is indicated by a one-dot chain line, and a waveform of c indicates a change in the hysteresis width of the comparator 2. In FIG. 6, the input signal Si is a sine wave centered on 2.1 V, noise is added to the input signal Si near the center value 2.1 V, and the hysteresis width is 50 mV.
There are four types of 0 mV, 200 mV, and 400 mV.

In FIG. 6, until the time information from the timer circuit 7 indicates the predetermined time T1, the switches 21 to 23 of the variable resistance circuit 5a are off and cut off, and the hysteresis width at this time is 400 mV. is there. Next, when the time information from the timer circuit 7 indicates the predetermined time T1, the time comparison circuit 9a turns on the switch 21 to bring it into a conductive state, so that the hysteresis width is 200 mV.
Fall to. Next, when the time information from the timer circuit 7 indicates the predetermined time T2, the time comparison circuit 9b further turns on the switch 22 to bring it into a conductive state, so that the hysteresis width is reduced to 100 mV.

Next, when the time information from the timer circuit 7 indicates the predetermined time T3, the time comparison circuit 9c further turns on the switch 23 to bring it into a conductive state, so that the hysteresis width is reduced to 50 mV. When the output signal level of the comparator 2 changes, the time information from the timer circuit 7 is reset to 0, so that the time comparison circuits 9a to 9c
Since the corresponding switches 21 to 23 are turned off to be in the cutoff state, the hysteresis width becomes 400 mV again,
The above operation is repeated. As described above, in FIG. 6, when compared with each waveform in the conventional voltage comparison circuit of FIG. 11 in which the hysteresis width is fixed, even when a large noise is present near the center value of the input signal Si,
It can be seen that the output signal of the comparator 2 does not oscillate and the noise resistance characteristic is improved without delaying the change point of the signal level.

As described above, the voltage comparison circuit according to the first embodiment increases the hysteresis width of the comparator 2 until a predetermined time elapses from the signal level change point of the output signal of the comparator 2, and the predetermined width. After the lapse of time, the hysteresis width of the comparator 2 is reduced. Therefore, the hysteresis width of the comparator 2 can be increased during the period in which the output signal level of the comparator 2 does not seem to change, and the period in which the output signal level of the comparator 2 seems to change is
The hysteresis width of the comparator 2 can be reduced, and the noise resistance characteristic can be improved without delaying the change point of the output signal level.

Second Embodiment. In the first embodiment, the time information indicating the predetermined time is set in advance in the time setting register. However, the cycle in which the output signal level of the comparator 2 changes is measured a predetermined number of times to calculate the average value. The time information indicating the calculated cycle may be updated and set in the period setting register, and such a configuration is the second embodiment of the present invention.

FIG. 7 is a block diagram showing an example of the voltage comparison circuit according to the second embodiment of the present invention. In addition,
7, the same components as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted and only the differences from FIG. 1 will be described. The difference between FIG. 7 and FIG. 1 is that the time setting register 8 of FIG. 1 is replaced with a time setting register 51 that can freely set time information, and the elapsed time information output from the timer circuit 7 is 0. A change-point cycle detection circuit 52 for detecting and storing a cycle to be reset to a predetermined number of times and storing it, and setting time information calculated by a predetermined method from an average value of each detected cycle in the period setting register 51. Therefore, the voltage comparison circuit 1 in FIG. 1 is replaced by the voltage comparison circuit 50.

The voltage comparison circuit 50 of FIG. 7 sets a comparator 2, a reference voltage generation circuit 3, a resistor 4, a variable resistance circuit 5, a change point detection circuit 6, a timer circuit 7, and time information. It has a time setting register 51 that can be set. Further, the voltage comparison circuit 50 of FIG. 7 detects and stores a predetermined number of cycles in which the elapsed time information output from the timer circuit 7 is reset, and stores the detected cycle, and calculates an average value of each detected cycle. A transition point period detection circuit 52 that sets time information calculated by a predetermined method from the average value in the time setting register 51, elapsed time information output from the timer circuit 7, and time information set in the time setting register 51. The delay circuit 10 is provided with a time comparison circuit 9 for comparing the control signals SC and the control signal SC indicating the comparison result.

When the change point detection circuit 6 detects a change point of the output signal of the comparator 2, it outputs a predetermined change point detection signal Sa to the timer circuit 7, the time setting register 51 and the change point period detection circuit 52. . When the change point detection signal Sa is input, the change point cycle detection circuit 52 shifts the built-in shift register, calculates the average value of each cycle stored in the shift register, and further determines a predetermined value from the average value. The time information calculated by the above method is always output to the time setting register 51. Time setting register 51
When the change point detection signal Sa is input, the time information output from the change point period detection circuit 52 is set.

The timer circuit 7 constantly outputs the count value indicating the elapsed time to the time comparison circuit 9 and the change point cycle detection circuit 52, respectively.
Detects and stores the interval at which the count value output from the timer circuit 7 is reset to the initial value, that is, the cycle in which the output signal level of the comparator 2 changes, and stores the average value of the cycle stored a predetermined number of times. Then, the time information calculated from the average value by a predetermined method is set in the time setting register 51. When the count value indicating the elapsed time information from the timer circuit 7 reaches the value stored in the time setting register 51, the time comparison circuit 9 outputs a predetermined control signal SC to the variable resistance circuit 5.

FIG. 8 is a block diagram showing an example of the internal configuration of the change point period detection circuit 52. In FIG. 8, the change point cycle detection circuit 52 stores the cycle in which the output signal level from the comparator 2 changes four times, and sets a value obtained by averaging the stored four cycles in the time setting register 51. The case is shown as an example. In FIG. 8, the change point cycle detection circuit 52 stores and outputs time information indicating an interval at which the count value output from the timer circuit 7 is reset to an initial value, that is, the count value output from the timer circuit 7. And four flip-flops FF1 to FF4 that form a shift register
.About.FF4, the arithmetic circuit 55 calculates the average value of the count values and outputs the time information calculated from the average value by a predetermined method to the time setting register 51.

Change point detection signal S from the change point detection circuit 6
When a is input, the flip-flop FF1 stores the count value input from the timer circuit 7, and the flip-flop FF2 stores the count value stored in the flip-flop FF1. Similarly, the flip-flop FF3 stores the count value stored in the flip-flop FF2, and the flip-flop FF4 stores the count value stored in the flip-flop FF3. In this way, the flip-flops FF1 to FF4 forming the shift register shift the stored count value. On the other hand, each count value stored in the flip-flops FF1 to FF4 is always output to the arithmetic circuit 55, and the arithmetic circuit 55 constantly outputs the time information calculated from each input count value to the time setting register 51. To do.

When the change point detection signal Sa from the change point detection circuit 6 is input, the time setting register 51 stores the time information from the arithmetic circuit 55 and sets the timing for changing the hysteresis width of the comparator 2. . In the time comparison circuit 9, time information indicating the elapsed time T from the change in the output signal level of the comparator 2 output from the timer circuit 7 and the time Ts set in the time setting register 8 are set.
When the elapsed time T reaches the set time Ts, a predetermined control signal SC is output to the variable resistance circuit 5. The diagram showing the operation example of the voltage comparison circuit 50 shown in FIG. 7 and FIG. 8 is similar to FIG. 3, and the output signal of the comparator 2 is compared with each waveform in the conventional voltage comparison circuit of FIG. Even when the oscillation does not occur and the frequency of the input signal Si changes, the noise resistance characteristic can be improved without delaying the change point of the signal level.

In the above description, the case where the time setting register 51 and the time comparison circuit 9 are provided one by one has been described as an example, but in the second embodiment as well, it is shown in FIG. As described above, a plurality of time setting registers and a plurality of time comparison circuits may be provided. Note that FIG. 9 shows an example in which three time setting registers and three time comparison circuits are provided. The same components as those in FIG. 3 or 7 are designated by the same reference numerals, and the description thereof will be omitted here. Only differences from FIG. 7 will be described.

The difference between FIG. 9 and FIG. 7 is that the time setting register 51 of FIG. 7 is replaced by three time setting registers 51a to 51c, and the change point period detection circuit 52 of FIG. The period detection circuits 52a to 52c have three time comparison circuits 9a instead of the time comparison circuit 9 of FIG.
.About.9c, and accordingly, the variable resistance circuit 5 of FIG. 7 is replaced with the variable resistance circuit 5a of FIG.

The voltage comparison circuit 50 in FIG. 9 includes a comparator 2, a reference voltage generation circuit 3, a resistor 4, a variable resistance circuit 5a, a change point detection circuit 6, and a timer circuit 7.
And a time setting register 51a to 51c in which predetermined time information is set, respectively, and a cycle in which the elapsed time information output from the timer circuit 7 is reset to 0 is detected and stored a predetermined number of times, and each detected cycle is detected. Change point cycle detection circuits 52a to 52c are provided for calculating the average value of the cycles and setting the time information calculated from the average value by a predetermined method in the corresponding time setting registers 51a to 51c. Further, the voltage comparison circuit 50 compares the elapsed time information output from the timer circuit 7 with the time information set in the corresponding time setting registers 51a to 51c and outputs the comparison result, and the time comparison circuits 9a to 9c. And a delay circuit 10.

When the change point detecting circuit 6 detects the change point of the output signal of the comparator 2, the timer circuit 7, the time setting registers 51a to 51c, and the change point cycle detecting circuit 52a.
The predetermined change point detection signal Sa is output to each of .about.52c. The change point period detection circuits 52a to 52c are the same as those shown in FIG.
The same circuit configuration as that of the change point cycle detection circuit 52 shown in FIG. 3 is formed, and when the change point detection signal Sa is input, the shift registers incorporated therein are shifted, and the average value of each cycle stored in the shift register is changed. And the time information calculated from the average value by a predetermined method is constantly output to the corresponding time setting registers 51a to 51c. When the change point detection signal Sa is input to the time setting registers 51a to 51c, the time information output from the corresponding change point period detection circuits 52a to 52c is set.

The timer circuit 7 constantly outputs the count value indicating the elapsed time to the time comparison circuits 9a to 9c and the change point cycle detection circuits 52a to 52c, respectively, and the change point cycle detection circuits 52a to 52c use the timer. The interval at which the count value output from the circuit 7 is reset to the initial value, that is, the cycle in which the output signal level from the comparator 2 changes is detected and stored, and the average value of each cycle stored a predetermined number of times is calculated. The time setting register 51 corresponding to the time information calculated by the predetermined method from the average value.
a to 51c, respectively.

When the count value indicating the elapsed time information from the timer circuit 7 reaches the value stored in the corresponding time setting register 51a to 51c, the time comparison circuits 9a to 9c output a predetermined control signal to the variable resistance circuit 5a. Output to. The time setting register 51a is set with time information indicating the predetermined time T1, the time setting register 51b is set with time information indicating the predetermined time T2, and the time setting register 51c is set with time information indicating the predetermined time T3. . A diagram showing an operation example of the voltage comparison circuit 50 shown in FIG. 9 is similar to FIG. 6, and when compared with each waveform in the conventional voltage comparison circuit of FIG. 11, a large noise is generated near the center value of the input signal Si. The noise-proof characteristic can be improved without delaying the change point of the signal level even when the output signal of the comparator 2 does not oscillate and the frequency of the input signal Si changes even when the input signal Si changes.

As described above, the voltage comparison circuit according to the second embodiment detects and stores the cycle in which the output signal level of the comparator 2 changes, as compared with the voltage comparison circuit according to the first embodiment. Then, a change point cycle detection circuit is provided which calculates the average value of the cycles stored a predetermined number of times and sets the time information calculated from the average value by a predetermined method in the corresponding time setting register. Therefore, the input signal Si
Even when the frequency changes, the same effect as that of the first embodiment can be obtained.

[0052]

As is apparent from the above description, according to the voltage comparison circuit of the present invention, when the elapsed time from the signal level change point in the output signal of the voltage comparison unit becomes a predetermined time or more, the voltage comparison unit The hysteresis width of is switched to be smaller, for example. From this, it is possible to increase the hysteresis width of the voltage comparison unit in the time zone in which the voltage comparison result is unlikely to change and decrease the hysteresis width of the voltage comparison unit in the time zone in which the voltage comparison result changes. Therefore, it is possible to obtain a characteristic having excellent noise resistance with a small hysteresis width, and it is possible to improve the noise resistance without delaying the change point of the output signal level.

Further, the time calculated by the predetermined method from the average value of each period between the changing points of the output signal level of the voltage comparing section is set every time the changing point of the output signal level of the voltage comparing section is detected. I updated it and set it. Therefore, even when the frequency of the input signal changes, the noise resistance characteristic can be improved without delaying the change point of the output signal level. For example, considering a wobble signal when CAV (constant speeds) control is performed in an optical disk device, the frequency gradually increases as the optical pickup moves from the inner circumference to the outer circumference. In such a case, the change in frequency is gradual, so the time setting of the change timing of the hysteresis width can be automatically updated based on the cycle of the immediately preceding change point, improving the noise resistance characteristics to the input signal. Can be made.

Further, according to the voltage comparison circuit of the present invention, the hysteresis width of the voltage comparison unit is switched so as to become smaller, for example, according to the elapsed time from the signal level change point in the output signal of the voltage comparison unit. . From this, it is possible to finely set the hysteresis width in each time zone. For example, when the time zone where a large amount of noise is generated is clear, the noise width can be improved by increasing the hysteresis width in that time zone. In addition, it is possible to reduce the hysteresis width in the time period when the voltage comparison result changes, and it is possible to obtain a characteristic having excellent noise resistance with a small hysteresis width, and the change point of the output signal level is Noise resistance can be improved without delay.

Further, each time calculated by a predetermined method from the average value of each period between the change points of the output signal level of the voltage comparison section is corresponded to each time when the change point of the output signal level of the voltage comparison section is detected. Each time setting unit to be updated is updated and set. Therefore, even when the frequency of the input signal changes, the noise resistance characteristic can be improved without delaying the change point of the output signal level. For example, in an optical disk device, CAV
Considering the wobble signal when (variable speed) control is performed, the frequency gradually increases as the optical pickup moves from the inner circumference to the outer circumference. In such a case, the change in frequency is gradual, so the time setting of the change timing of the hysteresis width can be automatically updated based on the cycle of the immediately preceding change point, improving the noise resistance characteristics to the input signal. Can be made.

On the other hand, by providing the signal delay section for delaying and outputting the output signal of the voltage comparison section, the signal to be output to the internal circuit or the external circuit at the timing of switching the hysteresis width by the hysteresis width switching section is provided. The signal level change point can be relatively delayed. Therefore, in a time zone in which digital noise is generated from the voltage comparison unit, switching can be performed so that the hysteresis width becomes large immediately before the time zone, and the noise resistance characteristic is improved even for a momentary large digital noise or the like. be able to.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a voltage comparison circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a circuit example of a variable resistance circuit 5 of FIG.

FIG. 3 is a diagram showing an operation example of the voltage comparison circuit 1 shown in FIGS. 1 and 2.

FIG. 4 is a block diagram showing another example of the voltage comparison circuit according to the first embodiment of the present invention.

5 is a diagram showing a circuit example of a variable resistance circuit 5a in FIG.

6 is a diagram showing an operation example of the voltage comparison circuit 1 shown in FIGS. 4 and 5. FIG.

FIG. 7 is a block diagram showing an example of a voltage comparison circuit according to a second embodiment of the present invention.

8 is a block diagram showing an internal configuration example of a change point period detection circuit 52 in FIG.

FIG. 9 is a block diagram showing another example of the voltage comparison circuit according to the second embodiment of the present invention.

FIG. 10 is a circuit diagram showing an example of a conventional voltage comparison circuit.

11 is a diagram showing an operation example of the voltage comparison circuit 100 shown in FIG.

[Explanation of symbols]

1, 50 Voltage comparison circuit 2 Comparator 3 Reference voltage generation circuit 4 Resistor 5, 5a Variable resistance circuit 6 Change point detection circuit 7 Timer circuit 8, 8a-8c, 51, 51a-51c Time setting register 9, 9a-9c Time comparison Circuit 10 Delay circuit 52, 52a to 52c Change point cycle detection circuit 55 Operation circuit FF1 to FF4 Flip flop

Claims (7)

[Claims] 1. A voltage comparison circuit having a hysteresis characteristic, which compares a predetermined reference voltage with the voltage of an input signal and outputs a binary signal indicating the comparison result, wherein the voltage of the reference voltage and the voltage of the input signal are And a voltage comparison unit that outputs a binary signal indicating the comparison result, a hysteresis width switching unit that switches the hysteresis width in the voltage comparison unit according to an input control signal, and the voltage A change point detection unit that detects a change point of the output signal level of the comparison unit, and an elapsed time measurement unit that measures and sequentially outputs the elapsed time from the change point each time the change point detection unit detects the change point. And a time setting section for setting a predetermined time, and when the elapsed time from the elapsed time measuring section reaches a predetermined time set for the time setting section, a predetermined control signal is sent to the hysteresis width switching section. Output A voltage comparison circuit comprising: a time comparison unit that switches the hysteresis width. 2. The voltage comparison circuit according to claim 1, wherein the hysteresis width switching unit performs switching so that the hysteresis width becomes small while a predetermined control signal is being input from the time comparison unit. 3. A change point period detection unit for detecting a period between change points of the output signal level in the voltage comparison unit from the elapsed time output from the elapsed time measurement unit, the change point period detection unit comprising: The time calculated by a predetermined method from the average value of each cycle between the detected change points is updated and set in the time setting unit each time the change point detection unit detects the change point. The voltage comparison circuit according to claim 1. 4. A voltage comparison circuit having a hysteresis characteristic, which compares a predetermined reference voltage with a voltage of an input signal and outputs a binary signal indicating the comparison result. And a voltage comparison unit that outputs a binary signal indicating the comparison result, a hysteresis width switching unit that switches the hysteresis width in the voltage comparison unit according to an input control signal, and the voltage A change point detection unit that detects a change point of the output signal level of the comparison unit, and an elapsed time measurement unit that measures and sequentially outputs the elapsed time from the change point each time the change point detection unit detects the change point. A plurality of time setting units each having a different predetermined time set, and when the predetermined time set in the corresponding time setting unit from the elapsed time measuring unit reaches the hysteresis width switching unit, And a plurality of time comparators that respectively output a predetermined control signal to switch the hysteresis width. 5. The voltage comparison circuit according to claim 4, wherein the hysteresis width switching unit switches the hysteresis width so as to gradually decrease in accordance with each control signal input from each time comparison unit. circuit. 6. A change point cycle detection unit for detecting a cycle between change points in the output signal level of the corresponding voltage comparison unit from the elapsed time output from the elapsed time measurement unit, and each change point cycle. 6. The voltage according to claim 4, wherein the detection unit sets the time calculated by a predetermined method from the average value of each cycle between the detected change points in each corresponding time setting unit. Comparison circuit. 7. A signal delay unit for delaying and outputting the output signal of the voltage comparison unit.
The voltage comparison circuit described in 2, 3, 4, 5 or 6.