JP2003187579A - Semiconductor storage device - Google Patents

Abstract

[PROBLEMS] To initialize a memory cell relatively easily,
S that can reduce the time required for initialization
Implement a RAM. SOLUTION: The power supply lines (L1, L2) of two inverters (INV1, INV2) constituting an SRAM memory cell (MC) whose input / output terminals are cross-coupled are provided separately and separately. A time lag is provided at the rise of the power supply voltage supplied to the power supply line.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a data setting technique for a memory cell of a static RAM (random access memory) and, more particularly, to a technique effectively used for initialization of a memory array.

[0002]

2. Description of the Related Art A static RAM (hereinafter referred to as SRAM) uses, as a memory cell, a flip-flop circuit including a pair of inverters whose input and output terminals are cross-coupled to each other. Since the initial state of the flip-flop circuit when the power is turned on is indefinite, it is unknown whether the stored data in the memory cell immediately after the power is turned on is "1" or "0". Therefore, depending on the system using the SRAM, it is necessary to perform the initialization process of writing the data "1" or "0" to all the memory cells in the SRAM when the power is turned on.

[0003]

In the conventional SRAM, since the initial state must be set by the data writing process, there is a problem that initialization takes time in a system that requires initialization of memory cells. . Further, in the conventional SRAM, even if a data abnormality is detected in a test for checking whether or not a memory cell normally operates, it is not easy to determine whether it is a write abnormality or a read abnormality. There wasn't. Therefore, it is difficult to narrow down the cause in the failure analysis, and there is a problem that it takes a long time to improve the production line start-up period and the production line to improve the yield.

An object of the present invention is to provide an SRAM capable of relatively easily initializing memory cells and shortening the time required for initialization. Another object of the present invention is to easily determine whether a memory cell error is caused by a write error or a read error, and narrow down the cause in failure analysis more easily than in the past. It is to provide an SRAM. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0005]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, the power supply lines of the two inverters, which have cross-coupled input / output terminals forming the memory cell of the SRAM, are separately provided and a time lag is provided at the rise of the power supply voltage supplied to each power supply line. It is the one.

According to the above-mentioned means, since the input terminal of the inverter whose power supply voltage has risen first is at the ground potential, the output, that is, the input of the other inverter becomes high level, and then the power supply voltage is applied to the other inverter. Since the output of the other inverter, that is, the input of the first inverter that rises first is set to the ground potential and the high level of the output is maintained by rising, the state of the memory cell composed of the flip-flop is uniquely determined.
Moreover, the state of this memory cell, that is, the initial storage data of the memory data can be determined by raising the power supply voltage of any inverter first. further,
By separating the power supply lines of the respective inverters for all the memory cells in the memory array, the states of all the memory cells can be set at the same time, so that the time required for initialization can be shortened. In addition, even after the power to the SRAM chip is turned on,
Temporarily lowering the voltage of one of the power supply lines of the separated memory cells clears all the data that had been held until then, and unifies the stored data of all memory cells to "1" or "0". It is possible to add a new function to the SRAM.

The initialization of the memory cell by turning on the power supply voltage with a time difference may be performed by separately providing a dedicated control terminal and inputting a signal to the control terminal, but it is already provided in the SRAM. It may be configured such that it is performed by combining the enable signal and the address strobe signal. As a result, a new function of data initialization can be added to the SRAM without increasing the number of external terminals.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of a suitable SRAM memory cell to which the present invention is applied. In FIG. 1, MC is a memory cell, WL is a word line, BL, / BL
Are complementary bit line pairs. The memory cell has two CMOS inverters INV whose input / output terminals are cross-coupled to each other.
1, a flip-flop circuit composed of INV2, an input / output node n1 of one inverter INV1 and a bit line BL
A switching MOSFET Qa for selection whose source and drain are connected to each other and whose gate is connected to a word line WL, and whose source and drain are connected to the input / output node n2 and bit line / BL of the other inverter INV2 and whose gate is a word line WL. Switch MOSFET Qb for selection connected to
It consists of and. Although the structure of the memory cell itself is the same as the conventional one, the memory cell MC of this embodiment is
The power supply terminals of the two inverters INV1 and INV2 are separated from each other, and are connected to the power supply lines L1 and L2 respectively arranged in the memory array. Although not apparent in the drawing, the power supply lines L1 and L2 are arranged as a power supply line common to all the memory cells in the memory array.

FIG. 2 shows the power supply voltage VDDA of the power supply lines L1 and L2 in the memory cell configured as described above.
And VDDB are raised in the order of VDDA → VDDB, and changes in the potentials Va and Vb of the nodes n1 and n2 in the memory cell are shown. When the power supply voltage rises in the order of VDDA → VDDB, the power supply of the inverter INV1 is first turned on with the input terminal being at the ground potential, so that the P-channel MOSFET is
When Qp1 is turned on, the potential of the node n1 rises to a high level (a level close to the power supply voltage VDDA). After that, when the other inverter INV2 is powered on, the input of the inverter INV2, that is, the output of the inverter INV1 has already been fixed to the high level, so that the N-channel MOSFET Qn2 is turned on and the potential Vb of the node n2 is turned on. Remains low level. As a result, the input of the inverter INV1 whose power supply first rises is set to the ground potential, so that the state of the memory cell is uniquely determined.

FIG. 3 shows an example of a circuit for controlling the rising of the power supply voltages VDDA and VDDB supplied to the memory cells by the power supply lines L1 and L2. In FIG. 3, reference numeral VD
The power supply control signal DL of the memory cell is indicated by C.
Y is a delay circuit that delays the power supply control signal VDC for a predetermined time, INV11 and INV12 are CMOS inverters that invert the power supply control signal VDC and its delay signal VDC ', DRV1 and DRV2 are inverters INV11 and IV1.
The power supply driver drives the power supply lines L1 and L2 by the output signal of the NV12. Power driver DR
Like the inverters INV11 and INV12, V1 and DRV2 are composed of MOSFET inverters, but the element sizes are inverters INV11 and INV.
Much larger than 12 is used. Instead of configuring the power source drivers DRV1 and DRV2 with inverters, it is possible to use only P-channel MOSFETs.

FIG. 4 shows an example of another circuit for controlling the power supply voltages VDDA and VDDB supplied to the memory cells by the power supply lines L1 and L2. The power supply control circuit of this embodiment is shown in FIG.
Of the power supply control signal VDC and the reset signal RES, for example, is added to the circuit of FIG. 2 to temporarily raise the power supply voltages VDDA and VDDB supplied to the memory cells and then one power supply voltage VDDA. It is the one that can temporarily shut down only.

FIG. 5 shows how the power supply voltages VDDA and VDDB and the potentials Va and Vb of the nodes N1 and n2 in the memory cell MC change when the power supply control circuit of this embodiment is applied. After the power supply voltages VDDA and VDDB are raised, when the reset signal RES is temporarily changed to the low level at timing t1 in FIG. 5, the driver DRV1 is turned off and the power supply line L1 is changed from the power supply voltage VDDA to the ground potential. GND
Is changed to. This lowers the potential Va of the node n1 in the memory cell MC, so that the inverter INV2
The potential Vb of the node n2, which is the output of, is changed from the low level to the high level. Then, even if the power supply voltage VDDA is again supplied to the power supply line L1, the potential of the node n1 does not return to the original VDDA and remains at the ground potential because the inverter INV1 has the N-channel MOSFET Qn1 turned on. To be done.

Further, if the reset signal RES is assumed after the power is turned on.
No matter what data is written by the write operation to the memory cell during the period T0 until the input of the reset signal RES, the memory cell keeps the potential Va of the node n1 at the low level by the input of the reset signal RES. The potential Vb of n2 is set to the high level state. Thus, in the SRAM to which this embodiment is applied,
The data in all memory cells in the memory array can be set to "1" or cleared to "0" at any time. Therefore, by using this function, it becomes easy to analyze the memory cell in which the abnormality is detected by the memory test. For example, when the data is read after writing the data in a certain memory cell and the data does not match the write data, the conventional SRAM could not discriminate between the write system abnormality and the read system abnormality.
In the SRAM to which the above embodiment is applied, the data read by the normal write and read operations and the data obtained by setting the data in the memory cell using the data setting function and then reading the data are described. It becomes possible to determine whether the abnormality is in the writing system or the reading system by comparing the above.

FIG. 6 shows the configuration of the entire SRAM chip to which the above embodiment is applied. In the figure, 10 is a plurality of memory cells MC arranged in a matrix and a plurality of word lines to which the selection terminals of the memory cells in the same row are connected, and a plurality of bit lines to which the input / output terminals of the memory cells in the same column are connected. And a memory array 11 having an address buffer 11 for fetching an address signal ADD input from the outside, and a decoder 12 for decoding a row address signal fetched in the address buffer to select a corresponding word line in the memory array 10. An address decoder, 13 is a Y decoder for decoding a column address signal fetched in an address buffer to select a corresponding bit line pair in the memory array 10, and 14 is a plurality of amplifiers for amplifying the potential difference of the selected bit line pair. A sense amplifier & column switch circuit comprising a sense amplifier circuit and a column switch, 5 data output buffer for outputting the read data amplified by the sense amplifier circuit outside the chip, 16 denotes a data input buffer for taking a write data input from the outside.

Further, in FIG. 6, 17 is a chip enable signal / chip-selection signal supplied from the outside as a chip select signal.
Write enable signal as CE and write control signal /
A control circuit for generating a control signal for an internal circuit based on WE and address strobe signals RAS and CAS, 18
Are power supply lines L1 and L arranged in the memory array 10.
Power supply voltage VDDA supplied to each memory cell via
It is a power supply control circuit having a configuration as shown in FIGS. 3 and 4 for controlling V DDB. The above-mentioned control signal VDC and reset signal RES for the power supply control circuit 18 are controlled by the control circuit 17 according to a combination of enable signals / CE, / WE and address strobe signals / RSA, / CAS.
Is generated and supplied in.

FIG. 7 shows a second embodiment of the SRAM according to the present invention. In the SRAM of this embodiment, two inverters INV that form a memory cell are used.
The power supply voltage of 1 and INV2 is made common, two word lines are provided instead, one (WL) is connected to the gate of the selection switch MOSFET Qa connected to the bit line BL, and the other (/ WL) is connected. It is connected to the gate of the selection switch MOSFET Qb connected to the bit line / BL. At the same time, the discharge MOSFETs Qd1 and Qd2 are respectively provided on the bit lines BL and / BL.
And write amplifiers W-AMP1 and W-AMP2 connected to the bit lines BL and / BL are P-channel M
The OSFET and the N-channel MOSFET are configured so that they can be controlled by different signals D, E; F, G, respectively. The discharge MOSFETs Qd1 and Qd2 are on / off controlled by a common signal C. Signal C above
G is generated and supplied by the control circuit 17.

Table 1 shows the relationship between the operation of the memory cell MC, the potentials of the word lines WL and / WL, and the potentials of the signals C to G. H means high level and L means low level.

[0018]

[Table 1]

When data "0" (or "1") is set in the memory cell MC, one word line WL is set to the high level and the other word line / WL is set to the low level, and signals D, E; F, G are set. Write amplifier W-AMP1, W-AM
Hold P2 in the output high impedance state, and
MOSF for discharge by setting the high level
ET Qd1 and Qd2 are turned on and bit line B
Lower L and / BL to ground potential. Then, since the selection switch MOSFET Qa of the memory cell is turned on and Qb is turned off, only the node n1 in the memory cell is connected to the bit line to lower the potential, and the memory cell outputs data “0” (or “1”). )) Is retained.

On the other hand, when setting data "1" (or "0") in the memory cell MC, the word line WL is set to low level and / WL is set to high level. Also, like the above,
Write amplifiers W-AMP1, W- with signals D, E; F, G
By holding the AMP2 in the output high impedance state and setting the signal C to the high level, the discharge MO
The SFETs Qd1 and Qd2 are turned on to lower the bit lines BL and / BL to the ground potential. Then, since the selection switch MOSFET Qa of the memory cell is turned off and Qb is turned on, only the node n2 in the memory cell is connected to the bit line to lower the potential, and the memory cell outputs data "1" (or "0"). )) Is retained.

Further, during a normal data write operation, the two word lines WL, / WL of the selected memory row are simultaneously set to the high level, and the word lines WL, / WL of the non-selected memory row are set.
Are all set to the low level, and the signal C is set to the low level to discharge MOSFET Qd.
1 and Qd2 are turned off. Also, write amplifier W
-AMP1 and W-AMP2 are controlled by signals D, E; F, and G so as to have complementary output states according to write data, and drive bit lines BL and / BL to opposite levels. To do.

Furthermore, during a normal data read operation,
The two word lines WL, / WL of the selected memory row are set to the high level, the word lines WL, / WL of the non-selected memory row are set to the low level, and the signal C is set to the low level to discharge the MOSFET Qd1. ，
Turn off Qd2. And write amplifier W-
The AMP1 and W-AMP2 are controlled by the signals D, E; F, G to be in the output high impedance state, and the sense amplifier SA outputs the signal read from the selected memory cell to the bit lines BL and / BL. Amplify.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in the embodiment of FIG. 7, the MOSFETs Qd1 and Qd2 for discharging are provided on the bit lines BL and / BL, respectively, but the MOSFETs for charging connected to the bit lines BL and / BL are provided. It is also possible to set the state by raising one of the internal nodes n1 and n2 to the power supply voltage VDD when setting the data of the memory cell. In addition, although the embodiment has shown that the memory cell is composed of the MOSFET, the present invention can be applied to the SRAM in which the memory cell is composed of the bipolar transistor.

Further, in the above embodiment, the SRAM
Power supply voltages V to be supplied to the memory cells in the chip
Although the power supply control circuit for controlling the rising and resetting of DDA and VDDB has been described, a power supply terminal for separately supplying each power supply voltage from the outside may be provided on the chip.

In the above description, the case where the invention made by the present inventor is mainly applied to the static RAM which is the field of application as the background has been described, but the present invention is not limited to this, and a flip-flop is used. In an LSI having a large number of signal latch flip-flops in a register or logic block, it can also be used to uniquely set the initial state of the register or flip-flop.

[0026]

The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, according to the present invention, the initialization of the memory cell can be performed relatively easily, the time required for the initialization can be shortened, and if the abnormality of the memory cell is detected, it is caused by the write abnormality. It is possible to easily determine whether it is due to an abnormality and narrow down the cause in failure analysis more easily than before.
The effect that a RAM can be realized is obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a memory cell of a static RAM to which the present invention is applied.

FIG. 2 is a time chart showing changes in signals when data is set in the memory cells of the static RAM according to the embodiment.

FIG. 3 is a circuit diagram showing a configuration example of a power supply control circuit that supplies a power supply voltage to a memory cell of an embodiment.

FIG. 4 is a circuit diagram showing a configuration example of a power supply control circuit capable of setting data in a memory cell of an embodiment.

5 is a time chart showing changes in signals when data is set by the power supply control circuit of the embodiment of FIG.

FIG. 6 is a block diagram showing a configuration example of an entire chip of a static RAM to which the present invention is applied.

FIG. 7 is a circuit configuration diagram of a memory array section showing another embodiment of the present invention.

[Explanation of symbols]

10 memory array 11 address buffer 12 X address decoder 13 Y address decoder 14 Sense amplifier & column switch circuit 15 data output buffer 16 data input buffer 17 Control circuit 18 Power supply control circuit MC memory cell WL word line SA sense amplifier BL, / BL bit line pair W-AMP light amplifier Qa, Qb selection switch MOSFET

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yoichiro Eto             5-22-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company Hitachi Cho-LS System             Within F term (reference) 5B015 HH05 JJ21 KA13 KA28 KB74                       RR00

Claims (5)

[Claims] 1. A memory cell comprising a pair of inverters whose input and output terminals are cross-coupled to each other, a plurality of word lines to which select terminals of memory cells in the same row are connected, and input and output terminals of memory cells in the same column. In a semiconductor memory device including a memory array having a plurality of bit line pairs connected to each other, a power supply line for individually supplying a power supply voltage to each of the two inverters forming the memory array is provided. The semiconductor memory device is configured such that the state of the memory cell is uniquely determined by raising the power supply voltage supplied by the device at different timings. 2. The semiconductor memory device according to claim 1, further comprising a power supply control circuit that controls rising of power supply voltages supplied by the power supply lines. 3. The power supply control circuit is configured such that data held in a memory cell can be uniquely set by temporarily lowering one of the power supply voltages. The semiconductor memory device described. 4. A memory cell comprising a pair of inverters whose input and output terminals are cross-coupled to each other and a pair of selection switch elements connected to the input terminals of the inverter, and one selection switch of one of the memory cells in the same row. A plurality of first word lines connected to the control terminals of the elements, a plurality of second word lines connected to the control terminals of the other selection switch elements of the memory cells on the same row, and the input of the memory cells on the same column. A memory array having a plurality of bit lines whose output terminals are connected via the selection switch element is provided, and one of the first word line and the second word line is set to a selection level, whereby A semiconductor memory device characterized in that the state of a memory cell is uniquely determined. 5. A switch means capable of applying a fixed potential to each of the bit lines is connected to each of the bit lines, and when one of the first word line and the second word line is set to a selection level, The switch means is turned on and a fixed potential is applied to each of the bit lines, and the fixed potential is turned on by the potential of the selection level of either the first word line or the second word line. 5. The semiconductor memory device according to claim 4, wherein the semiconductor memory device is configured to be transmitted to an input / output terminal of one of the inverters of the memory cell via a switching element for use.