JP2003163332A - Semiconductor device - Google Patents

Abstract

(57) Abstract: Provided is a semiconductor device which can be used as a multi-valued memory or a neuron element of a neuron computer and can hold multi-valued information, and a driving method thereof. A semiconductor device includes a control voltage supply unit.
A MOS transistor having a gate electrode 109, a drain region 103a and a source region 103b, and a dielectric capacitor 104 and a resistance element 10 interposed in parallel between the gate electrode 109 and the control voltage supply unit 110.
6. With this configuration, a voltage is applied to accumulate electric charges in the intermediate electrode and the gate electrode 109 of the dielectric capacitor 104, so that the threshold value of the MOS transistor can be changed. Therefore, the history of the input signal can be stored as a change in the drain current of the MOS transistor, and multi-value information can be held.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a driving method thereof, and more particularly to a semiconductor device which can be used in a neural network computer (neuron computer) or the like and can hold multivalued information, and a driving method thereof.

[0002]

2. Description of the Related Art With the progress of multimedia, demands for improving the performance of semiconductor devices are increasing. In order to process a large amount of digital information, for example, a CPU of a personal computer, which has a high-speed operation of 1 GHz or more, has been commercially available.

Semiconductor manufacturers have hitherto mainly responded to such demands for improving the performance of semiconductor devices by improving the performance of semiconductor devices by miniaturization process technology.

However, now that even physical limits have been pointed out for the miniaturization of semiconductor devices, the performance improvement of semiconductor devices by further miniaturization is
From the point of view of manufacturing costs, we are no longer expecting.

As a means for solving the above requirement, "1"
In addition to the conventional digital information processing technology that uses two-valued signals of 0 and “0” to perform arithmetic operations, the technology that multivalues information into three-valued and four-valued data and the multi-valued technology is applied. Computer technology (neuron computer) that can perform arithmetic processing that mimics the function of the brain of living things is being researched.

The brain of an organism is basically composed of nerve cells called neurons having an arithmetic function, and nerve fibers which play a role of wiring so as to transmit the arithmetic result to other neurons.

The neuron computer is composed of a large number of neuron parts made up of semiconductor elements corresponding to neurons, and a large number of synapse parts which transmit signals to the neuron parts and weight them. The combination of the neuron part and the synapse part is hereinafter called a neuron element.

When information signals having different "weights" from a plurality of preceding neuron elements are input to a certain neuron element, the information signals are added in this neuron element, and the sum of the information signals exceeds a threshold value. The neuron element "fires" and the signal is output to the next neuron element. By repeating this, information is processed.

Further, the process of learning by the brain of an organism is regarded as a process in which the weight in synaptic connection changes. That is, for various combinations of input signals, the weights are gradually modified so that a correct output can be obtained, and finally settled at an optimum value.

In order to construct a neural network having such a learning function, it is necessary to appropriately change the strength of each synaptic connection and store the changed value. Therefore, multi-valued technology is an essential technology for realizing a neuron computer.

The above-mentioned neuron computer is an example of application of multi-valued technology, but of course, research on multi-valued memory for stably storing multi-valued information has been actively conducted. As can be seen from these facts, the information multi-valued technique will be an extremely important technique in future semiconductor devices.

As an example of such multi-valued technique, polarization hysteresis of a ferroelectric substance is utilized to make three memory cells in one memory cell.
A conventional technique for storing information of a value or more is described in Japanese Patent Laid-Open No. 8-124378 "Ferroelectric Memory".

FIG. 49 is a sectional view of a conventional semiconductor device which functions as a multi-valued memory. As shown in the figure, the memory cell of the conventional semiconductor device has a silicon substrate 1107 and a well line BU embedded in the silicon substrate 1107.
L1 and the well line BUL2, the PZT film 1109 made of a ferroelectric material provided on the well line BUL1 and the well line BUL2, the word line WL1 provided on the PZT film 1109, the word line WL1 and the well Line B
The bit line BL1 is provided above the UL1 and the bit line BL2 is provided above the word line WL1 and the well line BUL2. Further, drains and sources (not shown) are provided in the well lines BUL1 and BUL2, respectively. The bit line BL1 is connected to the drain in the well line BUL1 via a bit contact (not shown), and the bit line BL2. Is connected to the drain in the well line BUL2 via the bit contact.

To write information, a voltage is applied to the word line WL1, the well line BUL1 and the well line BUL2 to PZ.
This is performed by changing the polarization of the T film 1109.

FIG. 50 shows each memory cell of the above-mentioned conventional example.
Voltage VGB applied to the gate electrode (= gate
Electrode potential-well potential) and magnitude of ferroelectric polarization
It is a graph which shows the relationship (hysteresis characteristic) with. strength
Since the dielectric has a hysteresis characteristic, the applied voltage
The polarization state changes depending on the history of the
The polarization state as indicated by 50 points A, B, and C remains.
It Saturation polarization of ferroelectric substance V = V₁After applying the voltage
When the pressure is unloaded, the polarization is in the state of point A, V = V ₂ Voltage
Unload the voltage after applying V = V₁After applying the voltage
-V₂When the voltage is applied and then the voltage is unloaded, the polarization
In the state of point C, V = -V₁Unload the voltage after applying the voltage
Then, the polarization becomes the state of point B.

FIG. 51 is a graph showing the relationship between the drain current I of the memory cell and the gate voltage VGB when the ferroelectric substance is in the state of points A, C and B, corresponding to FIG. In the same figure, the left curve corresponds to the point A, the center curve corresponds to the point C, and the right curve corresponds to the point B. In the state of point A, the ferroelectric substance is highly polarized, so that the threshold voltage VtA of the memory cell is smaller than the threshold voltage VtC in the state of unpolarized point C. Further, in the state of the point B, the ferroelectric substance is highly negatively polarized, so that the threshold voltage VtB of the memory cell is higher than the threshold voltage VtC in the state of the non-polarized point C. . As described above, by changing the ferroelectric substance into the three polarization states shown at the points A, C, and B, the threshold voltage of the memory cell can be controlled to three different types. Accordingly, ternary information can be stored in the memory cell. According to the above-mentioned conventional technology, it is possible to further multivalue by utilizing the polarization state between points A and C.

[0017]

However, the above-mentioned conventional example has a fundamental problem that it is difficult to accurately obtain the polarization state "C". In the prior art, it is stated that when an appropriate voltage is applied to weakly polarize the dielectric and then the voltage is unloaded, the polarization becomes close to zero. However, as is clear from FIG. Voltage Vc
Although it has a characteristic that it greatly changes in the vicinity, the absolute value of -V ₂ is inevitably close to Vc, and therefore its control is extremely difficult, and the value of V ₂ fluctuates slightly due to noise or the like. Therefore, the polarization value after unloading changes greatly. Further, the coercive voltage Vc also changes due to changes in the crystal state and film thickness of the ferroelectric substance in addition to such variations in the write voltage, and as a result, multi-value storage with high reliability and good reproducibility is obtained. It was extremely difficult to obtain stable characteristics. In the present specification, the coercive voltage refers to a voltage required to change the hysteresis of the ferroelectric substance significantly and change the charge distribution of the ferroelectric capacitor.

It is an object of the present invention to provide a semiconductor device which is highly reliable and capable of stably storing information and which can be used as a neuron element of a neuron computer, and a driving method thereof.

[0019]

A first semiconductor device of the present invention comprises a semiconductor substrate, a first upper electrode formed on the semiconductor substrate, a first dielectric layer, and a first lower electrode. And a second capacitor composed of a second upper electrode formed on the semiconductor substrate, a second dielectric layer, and a second lower electrode. In the semiconductor device having a portion and capable of holding information of three or more values, the first dielectric layer and the second dielectric layer have different coercive voltage values in hysteresis characteristics.

As a result, a metastable point is formed in the hysteresis curve of the entire capacitor, and three or more values of information can be stably stored even when the write voltage fluctuates.

During operation, the polarization direction of the first capacitor and the polarization direction of the second capacitor are the same, so that a hysteresis curve due to a difference in coercive voltage between the first capacitor and the second capacitor is displayed. It becomes possible to generate one or more metastable points at. As a result, it becomes possible to stably store information having three or more values.

Further, a transistor having a gate insulating film formed on the semiconductor substrate and a gate electrode made of a conductor film formed on the gate insulating film is further provided, and the first lower electrode and the transistor are provided. Since the second lower electrode is integrated with the gate electrode together, it is possible to reduce the number of manufacturing steps of the semiconductor device capable of stably storing the multivalued information. Manufacturing cost can be suppressed.

Further, the semiconductor device further includes a gate insulating film formed on the semiconductor substrate and a gate electrode formed of a conductive film formed on the gate insulating film, the first lower electrode and the second lower electrode. Since the electrode and the gate electrode are connected to each other, the voltage applied to the capacitor is transmitted to the gate electrode, and the drain current that flows when the gate voltage is applied changes depending on the state of the memory section. It can be stored stably.

In the first half of the process in which the polarization of each of the first capacitor and the second capacitor is from 0 to saturation, the rate of change of the polarization with respect to the change of the voltage is different, so that the hysteresis curve of the entire capacitor is A metastable point can be reliably formed. That is, the storage operation can be stably performed even when the write voltage fluctuates due to noise or the like.

Since both the first dielectric layer and the second dielectric layer have ferroelectric layers,
A remanent polarization after a voltage is applied to a capacitor can have a polarization state corresponding to multivalues, and thus a multivalued storage operation can be performed.

Since the first upper electrode and the second upper electrode are connected to each other, the write voltage can be applied through the same wiring.

Since the first dielectric layer is shared with the second dielectric layer, the storage section is different from the case where the first dielectric layer and the second dielectric layer are formed separately. Area can be reduced and the number of manufacturing steps can be reduced.

The materials of the members constituting the first dielectric layer and the second dielectric layer are the same, and the first dielectric layer is the same.
It may further have a paraelectric capacitor connected in parallel with the above capacitor and the second capacitor.

By further including the capacitor interposed between the second capacitor and the gate electrode, the apparent coercive voltage of the second capacitor can be changed and the degree of freedom in design can be increased. You can raise it further.

The coercive voltage of the capacitor can be changed also by making the areas of the first dielectric layer and the second dielectric layer different from each other.

Since the first dielectric layer and the second dielectric layer are made of different materials,
It is easy to form the first capacitor and the second capacitor so that the coercive voltages are different from each other.

By forming the first dielectric layer and the second dielectric layer to have different film thicknesses, the first capacitor and the second capacitor are formed to have different coercive voltages. be able to.

The value of (area of the first capacitor) / (area of the second capacitor), which is the ratio of the electrode areas of the first capacitor and the second capacitor, is 0. By being 2 or more and 2 or less, when the materials forming the first dielectric layer and the second dielectric layer are the same, the separability of the stored information is high and the ternary information is stably retained. You can

Particularly, the first capacitor and the second capacitor have a mutual electrode area ratio of 0.5 or more and 2 or more.
Due to the following, it is possible to realize a semiconductor device which has high separability of stored information and stably holds information of four or more values.

According to a second semiconductor device of the present invention, a control voltage supply section, a field effect transistor having a gate electrode having a function of accumulating charges, and the control voltage supply section and the gate electrode are parallel to each other. The multi-valued information can be held by having a capacitor element and a resistor element which are interposed between the two.

As a result, when a write voltage is applied to the resistance element, a current flows through the resistance element, so that charges are accumulated in the gate electrode and the threshold value of the field effect transistor can be changed. Further, since the field effect transistor has a plurality of states and the states are held for a certain period of time, multivalued information can be held. Further, since the information can be read according to the change of the drain current of the field effect transistor, it can be used not only as a multi-valued memory but also as an element for weighting signals in a neuron computer.

By injecting charges into the gate electrode from the control voltage supply section, it is possible to inject charges by a method different from that of the flash memory.

By functioning as an analog memory capable of continuously holding multi-valued information according to the amount of charge accumulated in the gate electrode, it can be used for various purposes such as weighting of a neuron computer as compared with a flash memory. Can be used.

Further, since the resistance element is made of a dielectric material, it is difficult for the charge accumulated in the gate electrode to leak. Therefore, as compared with the case where the resistance element is formed of non-doped silicon, the input The information provided can be retained for a longer period of time. Further, since the resistance element can be formed on the transistor, the cell area can be reduced.

The control voltage supply section serves as an upper electrode, the gate electrode of the field effect transistor is connected to an intermediate electrode, and the capacitive element includes the upper electrode, the intermediate electrode, the upper electrode and the intermediate electrode. A dielectric capacitor comprising a dielectric layer sandwiched between electrodes, wherein the resistance component of the dielectric layer functions as one of the resistance elements, so that, for example, the dielectric layer of the dielectric capacitor is a resistance element. In this case, the area of the device can be reduced as compared with the case where the resistance element and the dielectric layer are provided separately. The resistance value of the resistance element is
By changing according to the strength of the electric field applied to the resistance element, the amount of charge accumulated in the gate electrode can be adjusted.

Further, the resistance value of the resistance element takes a substantially constant value when the electric field strength applied to the resistance element is equal to or lower than a predetermined value, and decreases when the electric field strength exceeds the predetermined value. The device is driven by a plurality of methods, for example, when an electric field exceeding a predetermined value is applied to accumulate charges in the gate electrode in a short time, and when an electric field below a predetermined value is applied to accumulate charges over a relatively long time. It will be possible.

The passing current flowing through the resistance element increases substantially in direct proportion to the applied voltage when the absolute value of the voltage applied to both ends of the resistance element is equal to or less than a fixed value, and the absolute value of the applied voltage is the fixed value. By exhibiting the property of exponentially increasing when exceeding, it becomes possible to drive the device by a plurality of methods as described above.

Further, in the voltage range in which the passing current flowing through the resistance element increases substantially in direct proportion to the voltage, the passing current flowing per unit area of the resistance element is 100.
When it is [mA / cm ² ] or less, the written information or its history information can be retained for a certain period of time. The information holding time (return time) becomes longer as the passing current becomes smaller.

Since the capacitive element has a ferroelectric layer and at least one of the resistive elements is made of a ferroelectric material, the charge accumulation of the intermediate electrode and the gate electrode is possible depending on the polarization direction of the ferroelectric layer. Since the amount can be changed, the semiconductor device of the present invention can be used as a multi-valued memory capable of taking more values than in the case of using a capacitor having a paraelectric layer. It can also be used as a neuron element with extremely high degree of freedom in weighting.

By further including at least one resistance element provided separately from the above-mentioned capacitance element, it becomes possible to use materials having various characteristics for the resistance element, so that it is possible to more efficiently multivalue. It becomes easier to realize a semiconductor device that holds

The resistive element provided separately from the capacitive element is an oxide of an element selected from Ba, Sr, Ti, Zn, Fe and Cu, or 1 selected from SiC, Si and Se. With such a varistor, the electric charge is injected into the gate electrode in the voltage region where the resistance value of the resistance element is small, and the fine adjustment is performed in the voltage region where the resistance value is large.

The resistance element provided separately from the capacitance element may be a diode connected in parallel with each other and arranged in opposite directions.

A MIS transistor is further provided, and the above M
The on-resistance of the IS transistor may function as a resistance element provided separately from the capacitance element.

The resistance element provided separately from the capacitance element may be a resistance change element made of a resistance change material whose resistance value changes due to crystallinity.

Further, by being used as a synapse part of a neuron computer, it becomes possible to realize a high performance neuron computer.

Next, the driving method of the semiconductor device of the present invention is as follows.
A control voltage supply unit, a field effect transistor having a gate electrode having a function of accumulating charges, and a capacitive element and a resistance element interposed in parallel between the control voltage supply unit and the gate electrode. A method of driving a semiconductor device, wherein a write voltage is applied to both ends of the resistance element to change an amount of charge accumulated in the gate electrode through the resistance element, and a threshold voltage of the field effect transistor is changed. It includes (a) and a step (b) of reading information according to the change of the drain current of the field effect transistor.

By this method, the information written by applying the voltage to the capacitive element and the resistive element in step (a) is held for a certain period of time, and further, the drain current of the field effect transistor changes in step (b). Since multivalued information corresponding to the above can be read, the semiconductor device of the present invention can be driven as a multivalued memory. When used in a neuron computer, it can also be used as an element having a function of weighting input information.

Further, since the capacitance element has the dielectric layer, it is difficult for the charge accumulated in the gate electrode to leak. Therefore, for example, when the resistance element is made of non-doped silicon having a lower resistance value, The entered information can be retained for a longer period of time compared to.

In the step (a), if the absolute value of the write voltage applied to both ends of the resistance element is equal to or less than a fixed value, the passing current flowing through the resistance element increases in direct proportion to the write voltage, and the write voltage is increased. When the absolute value of the voltage exceeds the above-mentioned fixed value, the passing current increases exponentially with the increase of the write voltage, so that the writing of information is performed in a short time using the pulse voltage exceeding the fixed value. With the case
It is possible to selectively use the case where the voltage is applied below a certain value. Particularly when used as a neuron element, the learning operation can be executed by changing the threshold value of the field effect transistor by applying a voltage exceeding a certain value, and the memory operation can be reproduced with a relatively low voltage operation.

In step (a), when the absolute value of the write voltage is equal to or less than the constant value, the amount of charge accumulated in the gate electrode can be controlled by the length of time for applying the write voltage. it can. That is, multi-valued information can be written by a relatively simple method.

In step (a), when the absolute value of the write voltage is equal to or less than the constant value, the passing current per unit area flowing through the resistance element is 100 [mA / cm ² ] or less. It is possible to secure the recovery time of, that is, the information retention time above a certain level.

In the step (a), when the absolute value of the write voltage applied to both ends of the resistance element exceeds the fixed value, the pulse widths of the write voltage are made equal to each other, and the magnitude of the absolute value of the write voltage is set. Thus, the amount of charge accumulated in the gate electrode can be controlled. That is, multi-valued information can be written depending on the magnitude of the absolute value of the write voltage. In this case, the write time can be shortened, and the information can be stored in a short time.

In the step (a), when the absolute value of the write voltage applied to both ends of the resistance element exceeds the constant value, the charge amount accumulated in the gate electrode is roughly adjusted to obtain the write voltage. When the absolute value of is less than the above-mentioned fixed value, it is possible to efficiently write multi-valued information by finely adjusting the amount of charge accumulated in the gate electrode.

In the step (a), since the range of the write voltage applied to both ends of the resistance element is a positive range and a negative range in which absolute values are equal to each other, the case of applying the positive voltage and the case of applying the negative voltage. In and, since the drain current characteristics of the field effect transistors are different from each other, it becomes possible to hold more information in the semiconductor device than in the case where only a positive voltage is applied.

[0060]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a top view of a multi-valued memory according to the embodiment of the present invention. 2 is a sectional view taken along line II-II in FIG. 1, and FIG. 3 is a sectional view taken along line III-III in FIG. 1, FIG. 2, and FIG. 3, the same reference numerals are given to the same members. In FIG. 1, only the uppermost component is shown by a solid line. Further, in order to make the drawings easy to see, the reference numerals of the portions common to those of FIGS. 2 and 3 are also omitted.

As shown in FIG. 2, the multi-valued memory of the present embodiment has a p-type Si substrate 1 and a LOCOS on the Si substrate 1.
Element isolation film 5 made of silicon oxide formed by the method and a thickness of 3 nm made of silicon oxide formed on the active region of the Si substrate 1 partitioned by the element isolation film 5.
Gate insulating film 7, a gate electrode 9 made of polysilicon containing n-type impurities formed on the gate insulating film, and S
A plug wiring 13c formed on the side of the gate electrode 9 in the i-substrate 1 so as to be in contact with the element isolation film 5 and connecting the drain region 3a and the source region 3b containing n-type impurities, and the drain region 3a and the pad portion 15a. A plug wiring 13d connecting the source region 3b and the pad portion 15b, a first interlayer insulating film 11 filling the plug wiring 13c and the plug wiring 13d, and formed on the first interlayer insulating film 11. First made of 100 nm thick bismuth titanate (BIT)
On the first ferroelectric layer 16, the second ferroelectric layer 18 formed of BIT having a thickness of 400 nm on the first ferroelectric layer 16, and the second ferroelectric layer 18. The formed second interlayer insulating film 21 made of silicon oxide, the wiring 25c formed on the second interlayer insulating film 21, the first ferroelectric layer 16, and the second ferroelectric layer 18 And a wiring 25a that penetrates the second interlayer insulating film 21 and connects the pad portion 15a and the wiring 25c, the first ferroelectric layer 16, the second ferroelectric layer 18, and the second interlayer insulating film. And a wiring 25b penetrating through 21 and connected to the pad portion 15b. In addition,
In this embodiment, the gate length of the gate electrode 9 is 0.5 μm.
m, and the gate width is 5 μm.

As shown in FIG. 3, the multi-valued memory of this embodiment has a p-type Si substrate 1 and LO on the Si substrate 1.
An element isolation film 5 made of a silicon oxide film formed by the COS method, and a Si substrate 1 partitioned by the element isolation film 5.
A gate insulating film 7 made of silicon oxide and having a thickness of 3 nm formed on the active region, a gate electrode 9 made of polysilicon containing n-type impurities formed on the gate insulating film 7, a gate electrode 9 and A first interlayer insulating film 11 made of silicon oxide formed on the element isolation film 5 and Pt / TiN formed on the first interlayer insulating film 11 and having a size of 0.5 μm × 0.5 μm First intermediate electrode 14 of
a and P formed on the first interlayer insulating film 11 as well.
A second intermediate electrode 14b made of t / TiN and having a size of 0.5 μm × 0.5 μm, and a plug wiring penetrating the first interlayer insulating film 11 and connecting the gate electrode 9 and the first intermediate electrode 14a. 13a, a plug wiring 13b penetrating the first interlayer insulating film 11 and connecting the gate electrode 9 and the second intermediate electrode 14b, the first interlayer insulating film 11, the first intermediate electrode 14a, and the second intermediate electrode 14a. B formed on the intermediate electrode 14b of
First ferroelectric layer 16 made of IT and having a thickness of 100 nm
And the first intermediate electrode 14a on the first ferroelectric layer 16
And a first upper electrode 17 made of Pt / TiN and extending in parallel with each other and having a size of 0.5 μm × 0.5 μm.
And a second ferroelectric layer 18 made of BIT and having a thickness of 400 nm formed on the first ferroelectric layer 16, and a second intermediate electrode 14b on the second ferroelectric layer 18. The size of Pt / TiN that extends in parallel with and faces each other is 0.5μ
a second upper electrode 19 of m × 0.5 μm, a second interlayer insulating film 21 made of silicon oxide formed on the second ferroelectric layer 18, and a second ferroelectric layer 18. It penetrates through the second interlayer insulating film 21 and is connected to the first upper electrode 17, passes through the upper surface of the second interlayer insulating film 21, and then the second interlayer insulating film 21.
Wiring 25c penetrating the interlayer insulating film 21 and connected to the second upper electrode 19.

The ferroelectric capacitor composed of the first ferroelectric layer 16 and the first intermediate electrode 14a and the first upper electrode 17 that sandwich the first ferroelectric layer 16 is referred to as a capacitor MFM1, and the first ferroelectric layer 16 is used. A ferroelectric capacitor composed of the second intermediate electrode 14b and the second upper electrode 19 sandwiching the two layers of the second ferroelectric layer 18 and is called a capacitor MFM2. Further, the capacitors MFM1 and MFM2 are collectively referred to as capacitors MFMs.

FIG. 5 is an equivalent circuit diagram showing the multilevel memory of this embodiment.

As shown in the figure, the multilevel memory of this embodiment has a structure in which two ferroelectric capacitors are connected in parallel on the gate electrode of a MOS transistor.
In FIG. 5, the thickness of the ferroelectric layer of the capacitor MFM1 is 100 nm, and the size of the electrode is 0.5 μm × 0.
It is 5 μm. The thickness of the ferroelectric layer of the capacitor MFM2 is 500 nm, and the size of the electrode is 0.5 μm × 0.
It is 5 μm.

Next, FIGS. 4A to 4E are sectional views showing the manufacturing process of the multi-valued memory of this embodiment. This figure shows a cross section taken along line III-III in FIG. The method of manufacturing the multi-valued memory according to this embodiment will be described below with reference to FIG.

First, in the step shown in FIG. 4A, p-type S
Oxidation is performed on the i substrate 1 by the LOCOS method using silicon nitride (not shown) as a mask to form the element isolation film 5. Then, silicon nitride (not shown) is dissolved with heated phosphoric acid or the like. Then, the Si substrate 1 is thermally oxidized at 900 ° C., for example, to form a silicon oxide film having a thickness of 3 nm on the Si substrate 1, and this is used as the gate insulating film 7. afterwards,
A gate electrode 9 is formed by depositing phosphorus-doped polycrystalline silicon by the LPCVD method. Subsequently, the gate electrode 9 and the gate insulating film 7 are patterned by dry etching, and then boron ions are ion-implanted on both sides of the gate electrode 9 using the gate electrode 9 as a mask, and then heat treatment is performed at 900 ° C. for 30 minutes. By doing
The drain region 3a and the source region 3b shown in FIG. 2 are formed respectively. The MOS transistor manufactured in this step has a gate length of 0.5 μm and a gate width of 5 μm.

Next, in the step shown in FIG.
Silicon oxide (SiO ₂ ) is deposited on the substrate by the D method to form a first interlayer insulating film 11. Next, a contact window is formed by dry etching using a resist mask formed on the first interlayer insulating film 11, and then L
Polysilicon is deposited in the contact window by PCVD. Then, the plug wirings 13a, 13b, 13c and 13 are formed by planarizing the polysilicon by the CMP method.
to form d. Next, after depositing titanium nitride having a thickness of 20 nm on the first interlayer insulating film 11 by a sputtering method,
A 50 nm thick Pt layer is deposited by sputtering. Subsequently, a silicon oxide deposited on the Pt layer is patterned by a sputtering method to form a hard mask (not shown). Using this as a mask, the Pt / TiN layer is patterned by Ar milling to form a first intermediate electrode. 14a, second
Intermediate electrode 14b and pad portions 15a and 15b shown in FIG.
To form. After that, the hard mask made of silicon oxide is removed with diluted hydrofluoric acid or the like.

Next, in the step shown in FIG. 4C, a BIT having a thickness of 100 nm is deposited on the substrate by the sputtering method under the conditions of a substrate temperature of 550 ° C., an oxygen partial pressure of 20%, and an RF power of 100 W. To form the ferroelectric layer 16. After that, a Pt layer is deposited by the sputtering method, and Pt is deposited by Ar milling using a hard mask made of silicon oxide (not shown).
The layer is patterned to form the first upper electrode 17.
After that, the hard mask made of silicon oxide (not shown) is removed with diluted hydrofluoric acid or the like. In this embodiment, the dimensions of the first intermediate electrode 14a and the first upper electrode 17 are 0.5 μm × 0.5 μm.

Next, in the step shown in FIG. 4D, a BIT having a thickness of 400 nm is deposited on the substrate by the sputtering method under the conditions of a substrate temperature of 550 ° C., an oxygen partial pressure of 20%, and an RF power of 100 W. The ferroelectric layer 18 of is formed. Next, after depositing a Pt layer on the second ferroelectric layer 18 by a sputtering method, a hard mask made of silicon oxide (not shown)
Patterning the Pt layer by Ar milling using
The second upper electrode 19 is formed. Then, the hard mask (not shown) is removed with diluted hydrofluoric acid or the like. In addition,
In the present embodiment, the dimensions of the second intermediate electrode 14b and the second upper electrode 19 are 0.5 μm × 0.5 μm.

Next, in the step shown in FIG. 4E, a silicon oxide film is deposited on the substrate by plasma CVD using TEOS, and then planarized by the CMP method to form the second interlayer insulating film 21. Form. Then, the second interlayer insulating film 2 is formed using the resist mask formed on the second interlayer insulating film.
1 is dry-etched to form a contact window reaching the second upper electrode 19. On the other hand, the second interlayer insulating film 2 is formed using the resist mask formed on the second interlayer insulating film.
The first and second ferroelectric layers 18 are dry-etched to form a contact window reaching the first upper electrode 17.
When the etching selection ratio between the upper electrode 19 and the second ferroelectric layer 18 is sufficiently large, the second upper electrode 19
It is also possible to simultaneously form a contact window reaching the first contact electrode and a contact window reaching the first upper electrode 17. Next, after depositing an AlSiCu alloy in the contact window by a sputtering method, the AlSiCu alloy is dry-etched to form wirings 25a, 25b, 25c, respectively.

The multivalued memory of this embodiment is manufactured by the above method.

FIG. 6 is a diagram showing the voltage-polarization hysteresis characteristic (PV characteristic) of the capacitor MFM1. Note that this shows the hysteresis characteristic when only the capacitor MFM1 is connected to the power supply.

Referring to the figure, since the capacitor MFM1 has a thin film thickness of about 100 nm, the coercive voltage is small.
The polarization value (residual polarization) at a voltage of 0 V after applying a voltage of about 5 V or more reflects the characteristics of the material called BIT to be 4 μm.
It can be seen that about C / cm ² can be obtained.

On the other hand, FIG. 7 shows the PV of the capacitor MFM2.
It is a figure which shows a characteristic. As shown in FIG.
The ferroelectric material forming the FM2 has the same BIT as that of the capacitor MFM1, but the coercive voltage value is as high as about five times that of the capacitor MFM1 because the film thickness is 500 nm in total. However, since the value of the remanent polarization is peculiar to the material, it is about 4 μC / cm ² which is equivalent to that of the capacitor MFM1.

The driving method and the operation of the multilevel memory of this embodiment having the structure in which the two ferroelectric capacitors having different hysteresis characteristics are connected in parallel as described above will be described with reference to FIGS. .

FIG. 10 shows the voltage applied between the upper gate electrode and the lower electrode in the multilevel memory of this embodiment.
It is a figure showing effective polarization of two ferroelectric capacitors. As shown in the figure, since the capacitors used in the multi-valued memory of this embodiment are connected in parallel with each other, the polarization of the entire capacitor is just the capacitor MF.
The average value according to the area ratio of the polarization of M1 and the polarization of the capacitor MFM2 is shown.

FIG. 8 is a diagram for explaining the polarization hysteresis characteristic of the entire capacitor (capacitor MFMs) formed by connecting the capacitors MFM1 and MFM2 in parallel. In the figure, the average value of the polarization of the two capacitors shown by the broken line is the polarization of the capacitor MFMs. That is, the polarization of the capacitor MFMs is as shown in FIG.
The hysteresis characteristic is 0.

In the region x shown in FIG. 8, the capacitor MFM is
The polarization of 2 hardly changes with the change of the voltage V.
On the other hand, the polarization of the capacitor MFM1 sharply increases with respect to the change of the voltage V in the first half and becomes small in the latter half.
As a result, the combined value of the two changes sharply in the first half of the region x and becomes gentle in the second half of the region x. Further, in the region y, the polarization of the capacitor MFM2 largely changes with the change of the voltage V, but the polarization of the capacitor MFM1 hardly changes with the change of the voltage V. As a result, the combined value of both changes sharply in the first half of the region y, but changes more gently than when the capacitor MFM2 alone is used.

As described above, the multi-valued memory of this embodiment is
Since it has two ferroelectric capacitors having mutually different coercive voltages, it has a metastable point as shown by point C in FIG. 10, unlike the general hysteresis shape as shown in FIG.
Therefore, when the write voltage is around 4 V, the change in polarization with respect to the voltage change is gradual, and even if the write voltage fluctuates due to noise or the like, the change in polarization can be suppressed to a small level.

In order to obtain this effect, it is necessary that the region where the change in polarization becomes steep with respect to the change in voltage on the hysteresis curve is deviated, so the coercive voltages of the capacitors must be different from each other. is there. In particular, in the first half process of polarization from 0 to saturation, the metastable point can be reliably obtained by using two dielectric materials having different polarization change rates with respect to voltage changes. Similarly, when three or more capacitors are arranged in parallel, it is necessary that the difference in the coercive voltage of the capacitors be sufficiently different.

FIG. 9 is a diagram showing the P-V characteristic of the capacitor when the capacitor MFM1 and the capacitor MFM2 as well as the capacitor MFM3 having the same area as these capacitors are further added. The dashed line in the figure shows the PV characteristic of the entire capacitor. Since the coercive voltages of the capacitors are different from each other as in the case of two capacitors, a metastable point F can be further formed in the hysteresis curve. At this time, point C moves to point C '. As a result, at least four or more values can be recorded stably.

Next, a driving method for multivalued operation of the parallel ferroelectric capacitors in this embodiment will be described.

First, the line connecting the points A, S, C, D, and P in FIG. 10 represents the polarization of the capacitor when each voltage is applied. When the applied voltage is increased from -8 V, the polarization of the capacitor changes from the state at point A to the points S and C in the direction of the arrow. When a voltage of 8 V is applied, the polarization of the capacitor is saturated, and even if a voltage higher than this is applied, the polarization does not increase at the point D. Then, once the voltage applied to the capacitor is raised to 8V and then lowered, the polarization state of the capacitor goes to the point A through the point P, and returns to the state of the point A at -8V.

Now, the states of the capacitors MFM1 and MFM2 will be described. In the state of point A in which a voltage of -8V is applied to the capacitors, as can be seen from FIGS. 6 and 7, the capacitors MFM1 and MFM.
The polarization of FM2 is saturated with a negative charge. When the voltage applied to the capacitor is unloaded in this state, the applied voltage becomes 0 V, and the state at point S is reached. Since the areas of the capacitors MFM1 and MFM2 are the same, the polarization value of the capacitors MFMs is the same as the capacitors MF shown in FIGS.
It is the average value of M1 and capacitor MFM2 (Fig. 8
reference).

Next, when the applied voltage is raised to about 4 V from the state of point S, the polarization of the capacitor MFM1 is saturated with positive charge, and the capacitor MFM2 has positive charge but is not saturated. The polarization of the two capacitors is averaged,
The state becomes point C, which is a metastable point. In addition, in FIG.
A case where a voltage of 3.5 V is applied to the capacitor in consideration of the noise margin and the state becomes the state B is shown. continue,
When the applied voltage is unloaded, the polarization becomes the state Q of approximately 0 μC / cm ² .

Next, when the voltage applied to the capacitor is raised to 8 V, the capacitor is in the state of point D, and at this time, the polarizations of the capacitors MFM1 and MFM2 are both saturated with positive charges. After this, when the voltage is unloaded, the capacitor is at point P.

Next, the voltage applied to the capacitor is -8V.
Then, the capacitor returns to the state of point A.

As described above, the multi-valued memory of this embodiment is
For example, by applying three kinds of write voltages of -8V, 3.5V and 8V, it is possible to perform a stable storage operation against noise and the like.

FIG. 11 is a diagram showing the drain current when the gate voltage which is the read voltage is changed after writing at +8 V, +3.5 V and −8 V in the multilevel memory of this embodiment.

As shown in the figure, for example, when the read voltage is 2
In the range of up to 3 V, the current values flowing to the drain in each state are different from each other by one digit or more, which shows that the stored information can be stably read.

Next, writing at an intermediate point of the hysteresis curve where writing is apt to be unstable will be described by taking a case where the writing voltage at a voltage half the saturation voltage fluctuates by 10% as an example.

FIG. 12 is a diagram for explaining how the polarization value fluctuates when the write voltage fluctuates by 10% in the conventional multi-valued memory having a single ferroelectric capacitor. is there.

FIG. 13 is an enlarged view of the portion indicated by A in FIG.

From FIG. 12 and FIG. 13, in the method of the prior art, in order to obtain the polarization state on the way, there is no choice but to use the portion where the polarization changes sharply in the hysteresis curve.
For fluctuations of about 10% (see FIG. 13), 1.
Where to expect the polarization value of 7 .mu.C / cm ^2, the polarization value is understood to vary significantly between 1.4~2.0μC / cm ^2.

On the other hand, FIG. 14 is a diagram for explaining the fluctuation of the polarization value when the write voltage fluctuates in the multi-valued memory of this embodiment, as in FIGS. 12 and 13, and FIG.
5 is an enlarged view of the portion B shown in FIG.

It is understood from FIGS. 14 and 15 that the steepness of the polarization change with respect to the fluctuation of the write voltage is significantly improved in the multi-valued memory of this embodiment as compared with the prior art. For example, the original place expect polarization value of -0.15μC / cm ^2, the -0.1~-0.2μC / cm ² degree variation in the polarization value for ± 10% of the voltage fluctuation,
The fluctuation width is less than 0.6 μC / cm ^{2 of the} prior art.
It is significantly improved to 1 μC / cm ² or less. This is because the ferroelectric capacitors are connected in parallel and the mutual coercive voltages are changed, so that a metastable point occurs in the middle of the hysteresis.

These fluctuations in the write voltage (write field strength) can be caused by noise, fluctuations in the film thickness of the ferroelectric layer, fluctuations in the dielectric constant due to differences in crystallinity of the ferroelectric layers, and the like. However, the fluctuation of the write voltage of about ± 10% can be sufficiently considered under the practical condition.

Therefore, the structure of the multi-valued memory according to the present embodiment makes it possible to widen the process margin by suppressing the fluctuation of the polarization value, which is useful in practical device manufacturing.

16 and 17 both show the capacitor MF.
The ferroelectric film thickness of M1 is 100 nm and the capacitor MFM2 is
FIG. 3 is a diagram showing effective polarization values when the respective capacitor area ratios are changed when the ferroelectric film thickness is 1000 nm. 16 (a) to 16 (d) and FIG. 17 (a)
Points (D), (A), (B), and (E) in (d) indicate voltages for writing the positive maximum polarization, the negative maximum polarization, the positive intermediate polarization, and the negative intermediate polarization, respectively, and then unloading the voltage. The polarization values at that time are P, S, and
Q and R.

FIGS. 16A to 16D show the capacitor MF.
It is a figure which shows the effective polarization when the area of M2 is gradually increased with respect to the capacitor MFM1. As shown in the figure, as the area ratio of the capacitor MFM2 increases,
In the region passing the point B and the region passing the point E in the hysteresis curve, the polarization changes sharply with respect to the voltage change.

On the other hand, FIGS. 17A to 17D show the case where the area ratio of the capacitor MFM1 is increased. As shown in the figure, at this time, the change in polarization with respect to the voltage change in the region passing through the point B and the region passing through the point E in the hysteresis curve is gradual. From the above, the capacitors MFM1 and MFM2
As for the area ratio of, the larger the capacitor MFM1, the more the multi-valued memory which is more resistant to the fluctuation of the write voltage can be realized. However, as can be understood from FIG. 17D, when the area of the capacitor MFM1 becomes extremely large, the points P and Q, and the points S and R in the figure come close to each other, making it difficult to determine the data. . Therefore, in this embodiment, the area ratio of the capacitors MFM1 and MFM2 (area of MFM1 / area of MFM2) is 0.5 to 2
By setting the interval between the two, it is possible to realize a stable multi-valued operation with high separability of stored information.

However, when the effective polarization value is 0 μC / cm ² instead of the Q point and the R point, that is, when three types of polarization are used, the capacitor MFM1 and the capacitor MFM are used.
Even if the area ratio of 2 (area of MFM1 / area of MFM2) is approximately 0.2 to 2, good separability of stored information is maintained.

As described above, according to this embodiment, by connecting two or more ferroelectric capacitors having the same polarization direction but different coercive voltages to the gate electrode of the field effect transistor, it is possible to prevent a slight fluctuation in the write voltage. It is possible to realize a multi-valued memory with less fluctuation in drain current.

As a result, not only a highly integrated and stable semiconductor memory can be provided, but also a non-volatile transistor providing a plurality of resistance values can be applied to a neuron element which imitates a brain neuron.

Next, FIG. 18 is a sectional view showing a modified example of the multi-valued memory according to the embodiment of the present invention. Since this multi-valued memory has the same structure as the multi-valued memory of the present embodiment shown in FIG. 3 except for the second ferroelectric layer 18, the description of the structure will be omitted.

The multi-valued memory shown here uses a paraelectric material instead of the second ferroelectric layer 18 of the multi-valued memory of this embodiment shown in FIG.

For example, in the modification of this embodiment, the paraelectric layer 20 has a film thickness of 10 formed by the sputtering method.
0 nm tantalum oxide is used. The relative permittivity of the tantalum oxide layer is about 25 in this embodiment. In this case, the capacitance of the paraelectric layer is 1 of the capacitance of the ferroelectric layer.
Since it is about / 4, it is ⅕ of the voltage applied to MFM2.
Will be applied to the ferroelectric layer. For this reason, the apparent coercive voltage becomes five times, so that a metastable point can be provided until the polarization of the entire capacitor is saturated.

In this embodiment, in order to obtain ferroelectric capacitors having different coercive voltages, the thickness of the ferroelectric layer is 100 nm and 500 nm, or 100 nm and 100 nm.
Although it is set to 0 nm, by setting an arbitrary film thickness in addition to this,
The coercive voltage of the capacitor can be changed.

Further, even if ferroelectric materials of different materials are applied to the respective ferroelectric capacitors, the same effect as changing the film thickness of the ferroelectric layer can be obtained. For example, in the BIT of the present embodiment, the coercive electric field is about 20 kV / cm, but in PZT, the coercive electric field is about 40 kV / cm. Become.

In addition, the multi-valued memory of this embodiment is described especially for the case where two ferroelectric capacitors are provided. The ferroelectric capacitors having different coercive voltages are shown in FIG.
Even if three or more transistors are connected as shown in FIG. 5, the metastable points increase in the hysteresis as well, so that a more multi-valued ferroelectric gate memory can be realized.

In the multivalued memory of this embodiment,
The positive and negative polarities of the capacitor MFM1 and the capacitor MFM2 are the same, but they can be polarized in opposite directions.

(Second Embodiment) FIG. 19 is a sectional view showing the structure of a multilevel memory according to the second embodiment of the present invention. As shown in the figure, the multi-valued memory of this embodiment has p
Type Si substrate 1, an element isolation film (not shown) made of silicon oxide formed on the Si substrate 1, and the Si substrate 1
A gate insulating film made of silicon oxide formed above, a gate electrode / lower electrode 26 made of Pt / TiN formed on the gate insulating film, and a BIT formed on gate electrode / lower electrode 26 A first ferroelectric layer 27 having a thickness of 100 nm, a first upper electrode 29 formed on the first ferroelectric layer 27 and having a width not more than half the width of the gate electrode, The thickness formed on the ferroelectric layer 27 of No. 1 is less than half the width of the gate electrode, and the thickness is 400 nm.
Second ferroelectric layer 28 made of BIT, a second upper electrode 30 formed on the second ferroelectric layer 28, and a gate electrode / lower portion formed on the gate insulating film 7. Electrode 2
6, first ferroelectric layer 27, first upper electrode 29, second
Of the ferroelectric layer 28, the first upper electrode 29, and the second upper electrode 30, and an interlayer insulating film 31 filling the sides of the ferroelectric layer 28, and the first upper electrode 29 and the second upper electrode penetrating the interlayer insulating film. Thirty
And a plug wiring 32 connected to. Here, in the gate electrode / lower electrode 26, the gate electrode is integrated with the lower electrode of the capacitor.

In the present embodiment, the first upper electrode 2
9, a capacitor MFM1 including the first ferroelectric 27 and the lower electrode 26 and a second upper electrode 30, a second ferroelectric layer 28, a capacitor MFM2 including the first ferroelectric layer 26 and the lower electrode 26. The coercive voltages of are different from each other.
Therefore, a metastable point is formed in the hysteresis curve of the entire capacitor. Therefore, according to the multi-valued memory of the present embodiment, as in the multi-valued memory of the first embodiment, the stored information is highly separable and stable. It is possible to realize various multi-valued operations.

In the multivalued memory of this embodiment, since it is not necessary to form the intermediate electrode, the number of manufacturing steps can be reduced and the manufacturing cost can be suppressed as compared with the multivalued memory of the first embodiment. You can

Even if a paraelectric layer is used instead of the second ferroelectric layer 28 used in this embodiment, the capacitor M
The coercive voltages of the FM1 and the capacitor MFM2 may be formed to be different from each other.

(Third Embodiment) FIG. 20 is a circuit diagram showing a multilevel memory according to the third embodiment of the present invention. As shown in the figure, the multi-valued memory of this embodiment is connected in parallel to one selection transistor Tr1 whose gate is connected to the word line WL and whose drain is connected to the bit line BL, and the source of the selection transistor Tr1. And a capacitor MFM1 having a ferroelectric substance and a capacitor MFM2 having a ferroelectric substance. In the multi-valued memory of this embodiment, the coercive voltages of the capacitors MFM1 and MFM2 are different from each other.

The multi-valued memory of the present embodiment is a memory called FeRAM for reading information according to the amount of current flowing at the time of polarization reversal of the capacitor. At this time, in the multi-valued memory of this embodiment, as described in the first and second embodiments, a plurality of remanent polarization values can be stably obtained by connecting capacitors having different coercive voltages in parallel. It is possible. In the information read operation of the multi-valued memory according to the present embodiment, for example, a predetermined voltage, for example, 8V is held on the word line WL, and the voltage of the word line WL drops when the selection transistor Tr1 is turned on (conductive). T depending on the degree
Information is read by determining the amount of current flowing through r1. Here, since the amount of polarization reversal differs depending on the remanent polarization state of the ferroelectric capacitor, the amount of current flowing through Tr1 also differs. For example,
A large amount of current (absolute value) is detected in the order of points P, Q, and S in FIG. That is, multi-valued FeRAM
Can be realized.

Also with this structure, similar to the multi-valued memory of the first embodiment, it is possible to realize a stable multi-valued operation with high separability of stored information.

(Fourth Embodiment) FIG. 21 is an equivalent circuit diagram showing a multilevel memory according to the fourth embodiment of the present invention. The multi-valued memory according to the present embodiment has a configuration in which a capacitor 40 is inserted between the gate electrode 9 and the capacitor MFM2 of the multi-valued memory according to the first embodiment. That is, the multi-valued memory according to the present embodiment includes a MIS transistor, a capacitor MFM1 and a capacitor MFM2 that are connected in parallel to the gate electrode 9 of the MIS transistor and both have a ferroelectric substance, and the gate electrode 9 and the capacitor M.
And a capacitor 40 provided between FM2. 21, the same members as those in FIG. 5 are designated by the same reference numerals. The areas of the capacitors MFM1 and MIF2 and the thickness of the ferroelectric layer are the same as those in the first embodiment. The capacitor 40 is a capacitor having a paraelectric material, but may be a ferroelectric capacitor.

When a voltage is applied to the multi-valued memory of the first embodiment, the capacitors MFM1 and MFM2.
However, in the multi-valued memory of this embodiment, the sum of the voltages distributed to the capacitors MFM2 and 40 is equal to the voltage distributed to the capacitor MFM1.

Therefore, the voltage distributed to the capacitor MFM2 when the same voltage is applied to the multilevel memory is smaller than that of the capacitor MFM2 in the first embodiment, and the apparent coercive voltage is large. . The multi-valued memory according to this embodiment also includes the capacitors MFM1 and MFM.
The two coercive voltages are different and have a metastable point in their hysteresis loop. Therefore, the multi-valued memory of this embodiment can stably hold multi-valued data.

By inserting at least one capacitor between the ferroelectric capacitor and the gate electrode of the MIS transistor, the apparent coercive voltage can be arbitrarily adjusted, so that the degree of freedom in design is increased. be able to. In this embodiment, the capacitor MFM
1 shows an example in which the coercive voltage of the capacitor MFM2 is different from that of the capacitor MFM2.
Since the apparent coercive voltage of 2 changes, it is possible to realize a multi-valued memory that stably holds multi-valued even if the coercive voltages of two capacitors are the same. In addition, the multi-valued memory according to the present embodiment includes the capacitors MFM1 and MFM.
This is advantageous in that two ferroelectric layers can be formed at the same time.

In the present embodiment, the capacitor MFM2
Although an example in which one capacitor is inserted between the gate electrode 9 and the gate electrode 9 of the MIS transistor is shown, two or more capacitors may be inserted.

(Fifth Embodiment) A semiconductor device according to a fifth embodiment of the present invention will be described below with reference to the drawings.

FIG. 22 is an equivalent circuit diagram showing the semiconductor device of this embodiment. As can be seen from the figure, the semiconductor device of this embodiment includes a control voltage supply unit 110, a field effect transistor (hereinafter referred to as a MOS transistor), a gate electrode 109 of the MOS transistor, and a control voltage supply unit 110. It is characterized in that it has a dielectric capacitor 104 and a resistance element 106 which are interposed in parallel with each other.

Next, FIG. 23 is a top view of the semiconductor device of this embodiment, FIG. 24 is a sectional view taken along line XXIV-XXIV of FIG. 23, and FIG. 25 is taken along line XXV-XXV of FIG. A sectional view is shown. In FIG. 23, hatching is omitted for clarity, and only the uppermost component is shown by a solid line. Further, the same portions as those in FIGS. 24 and 25 are also partially omitted for easy understanding of the drawings. Further, also in FIGS. 24 and 25, a part of the components located behind the cut surface is omitted for the sake of easy viewing.

As shown in FIGS. 23, 24, and 25, the semiconductor device of this embodiment is provided, for example, on a P-type Si substrate 101 having an active region and on a surface of the Si substrate 101 facing the active region. The formed substrate electrode 108 (illustrated only in FIG. 22), the element isolation oxide film 105 surrounding the active region provided on the Si substrate 101, and the SiO ₂ provided on the Si substrate 101 with a thickness of 5 nm. Gate insulating film 107
And a gate electrode 109 made of polysilicon containing phosphorus provided on the gate insulating film 107, and the Si substrate 10.
1, the drain region 103a and the source region 103 including N-type impurities provided on both sides of the gate electrode 109.
b, a first interlayer insulating film 111 made of an insulator such as SiO ₂ provided on the Si substrate 101, and titanium nitride (TiN) having a thickness of 20 nm provided on the first interlayer insulating film 111. Film and a pad portion 115a, 115b made of a Pt film having a thickness of 50 nm and the intermediate electrode 114, and a plug wiring made of polysilicon that penetrates the first interlayer insulating film 111 and connects the gate electrode 109 and the intermediate electrode 114. 1
13a and the first interlayer insulating film 111, the drain region 103a, the pad portion 115a, and the source region 103b.
From plug wirings 113b and 113c made of polysilicon for connecting the pad and the pad portion 115b, respectively, and barium strontium titanate (hereinafter referred to as BST) having a thickness of 100 nm provided on the first interlayer insulating film 111. And the upper electrode 119 made of Pt and having a thickness of 50 nm provided on the dielectric layer 116.
A second interlayer insulating film 121 provided on the dielectric layer 116, a wire 125a made of a conductor such as an AlSiCu alloy, which penetrates the second interlayer insulating film 121 and reaches the upper electrode 119, Body layer 116 and second interlayer insulating film 12
Wirings 125b and 125c made of a conductor such as an AlSiCu alloy or the like and penetrating 1 to reach the pad portions 115a and 115b, respectively.

Further, the intermediate electrode 114 and the upper electrode 119.
The dimensions of both are 2.5 μm × 4 μm.
It is the same size as the MOS transistor having the 09.

In the semiconductor device of this embodiment, the dielectric layer 116 and the intermediate electrode 114 and the upper electrode 119 sandwiching the dielectric layer 116 form a capacitor, but the dielectric layer 116 simultaneously forms the resistance element 106 ( (See FIG. 22). The operation of the semiconductor device including this will be described in detail later.

Next, a method of manufacturing the semiconductor device of this embodiment will be described below with reference to FIG.

FIG. 26 is a sectional view taken along line XXV-XXV in FIG. 23, showing the manufacturing process of the semiconductor device of this embodiment.
Structures not shown or not shown in the XXV-XXV cross section of FIG. 26 will be described using the reference numerals used in the description of FIGS.

In the step shown in FIG. 26A, the substrate is oxidized by using a silicon nitride film (not shown) formed on the P type Si substrate 101 as a mask, and the element isolation oxide film 1 is formed.
05 is formed (LOCOS method). Next, the silicon nitride film is removed by using, for example, heated phosphoric acid, and the substrate is pyrooxidized at 900 ° C.
A SiO ₂ film made of iO ₂ is formed on the Si substrate 101. After that, polysilicon into which an n-type impurity such as phosphorus is introduced is deposited on the SiO ₂ film by the LPCVD method or the like, and then patterned by dry etching to form the gate insulating film 107 and the gate electrode 109. Then, by implanting a p-type impurity such as boron with the gate electrode 109 as a mask and performing a heat treatment at 900 ° C. for 30 minutes, the drain region 103a and the source region 103b are formed on both sides of the gate electrode 109 in the Si substrate 101.
To form. The MOS transistor manufactured by this process has a gate length of 1 μm and a gate width of 10 μm.

Next, in the step shown in FIG. 26B, SiO ₂ is deposited on the substrate by, for example, the LPCVD method to form the first interlayer insulating film 111. Then, a resist mask pattern (not shown) is formed on the first interlayer insulating film 111.
Then, the first interlayer insulating film 111 is dry-etched to form the gate electrode 109 and the drain region 1.
Contact windows reaching 03a and the source region 103b are formed respectively. Next, after depositing polysilicon on the substrate by the LPCVD method or the like, the substrate surface is flattened by the CMP method and the plug wiring 11 for filling each contact window is formed.
3a, 113b, 113c are formed respectively. next,
TiN is deposited on the first interlayer insulating film 111 by the sputtering method.
Is deposited to a thickness of 20 nm, and then Pt is deposited to a thickness of 50 nm by the same sputtering method. Then, S deposited by the sputtering method
Using a hard mask (not shown) formed by patterning the iO ₂ film, Pt / TiN is patterned by Ar milling to form the intermediate electrode 11 on the plug wiring 113a.
4, the pad portion 115a on the plug wiring 113b,
Pad portions 115b are formed on the plug wirings 113c, respectively. After that, the hard mask is removed with diluted hydrofluoric acid or the like.

Here, the TiN layer is formed in order to prevent Pt and polycrystalline silicon from forming silicide to increase resistance.

Next, in the step shown in FIG. 26C, the substrate temperature is 550 ° C., the oxygen partial pressure is 20%, and the RF
BST is deposited on the first interlayer insulating film 111 under the condition of power of 100 W to form a dielectric layer 116 having a thickness of 100 nm. Then, after Pt is deposited on the dielectric layer 116 by the sputtering method, the Pt layer deposited by Ar milling using a hard mask made of SiO _{2 (} not shown) is patterned, and the intermediate electrode 11 is sandwiched with the dielectric layer 116 in between.
The upper electrode 119 is formed at a position opposed to No. 4. After that, the hard mask is removed with diluted hydrofluoric acid or the like.

In this embodiment, the dimensions of the intermediate electrode 114 and the upper electrode 119 are 2.5 μm × 4 μm, and M
The size is the same as that of the OS transistor.

Next, in the step shown in FIG. 26D, TEOS is performed.
After depositing SiO ₂ by plasma CVD using (tetraethoxysilane), the second interlayer insulating film 121 is formed by planarizing by CMP. afterwards,
A contact window is formed by dry etching the second interlayer insulating film 121 and the dielectric layer 116 using a resist mask. Then, AlSi is formed by the sputtering method.
After depositing the Cu alloy on the substrate, dry etching is performed using a resist mask to remove the second interlayer insulating film 121.
Wiring 125a from the top to the upper electrode 119, pad portion 1
A wiring 125b reaching 15a and a wiring 125c reaching the pad portion 115b are formed. Note that the wiring 125a
Is connected to a control voltage supply unit 110 (not shown).

The semiconductor device shown in FIG. 22 is manufactured by the above method.

The semiconductor device of this embodiment has the structure shown by the equivalent circuit shown in FIG.
As shown in FIGS. 3 to 6, the intermediate electrode 114 and the upper electrode 119.
Thus, the dielectric capacitor 104 having the structure in which the dielectric layer 116 is sandwiched also operates as the electric resistance shown in FIG. That is, the dielectric capacitor 10 of FIG.
4 and the resistance element 106 are the same, and the electric resistance is the resistance component of the dielectric capacitor. Therefore, in the semiconductor device of the present embodiment, as compared with the case where the dielectric capacitor 104 and the resistance element 106 are provided separately, FIG.
The structure represented by the equivalent circuit shown in 2 is realized with a simpler configuration.

Next, the driving method and operation of the semiconductor device of this embodiment will be described below.

FIG. 27 shows a dielectric layer 116 made of BST.
FIG. 6 is a diagram showing characteristics of a passing current that passes through the dielectric layer 116 and flows between the intermediate electrode 114 and the upper electrode 119 when a voltage is applied to both electrodes of the dielectric capacitor 104 having a. As shown in the figure, the material BST has a characteristic that the resistance value is substantially constant while the electric field strength is small, so that a passing current value proportional to the voltage can be obtained. However, in FIG. 27, since the vertical axis is the log scale, the graph showing the characteristics is shown as a line-symmetrical curve in the positive and negative voltage ranges across 0V.

The driving method and operation of the semiconductor device of this embodiment having the dielectric layer 116 having such characteristics will be described below.

FIG. 28 is a drain current-applied voltage characteristic diagram for explaining the driving method and operation of the semiconductor device of this embodiment. The horizontal axis of the graph shown in FIG. 28 represents the voltage applied between the Si substrate 101 and the wiring 125a (hereinafter simply referred to as applied voltage), and the vertical axis represents the drain current flowing between the drain region 103a and the source region 103b. Are shown respectively. Note that when measuring the characteristics of the drain current-applied voltage in the semiconductor devices of the following embodiments including this embodiment, the evaluation is performed by applying 1 V between the drain region 103a and the source region 103b. ing.

In the semiconductor device of this embodiment, Si
The gate insulating film 1 is formed by the substrate 101 and the gate electrode 109.
MOS capacitor having a structure sandwiching 07 and the intermediate electrode 1
Since the dielectric capacitor 104 having the structure in which the dielectric layer 116 is sandwiched by the upper electrode 14 and the upper electrode 119 is connected in series, the applied voltage is distributed and applied to each capacitor.

For example, in the measurement of the semiconductor device of the present embodiment shown in FIG. 28, the applied voltage is in the range of -3V to + 3V, but when the maximum voltage of + 3V is applied, it is applied to the MOS and the dielectric capacitor, respectively. Is 2.2V and 0.
8V is distributed respectively. As shown in FIG. 27,
The dielectric capacitor has a very small leak current in the voltage range of −0.8 V or higher and 0.8 V or lower measured here.

As shown in FIG. 28, in the semiconductor device of this embodiment in the initial state, when the semiconductor device is operated at high speed with a pulse voltage having a high frequency of, for example, about 1 MHz, points A and O are obtained.
A characteristic of moving on a characteristic curve including (hereinafter, referred to as an A-O curve) is shown.

Although not shown in the A-O curve at about 0 V or less, the drain current in this region is a noise level, which is a current level sufficiently smaller than 10 ^-8 (A). Therefore, for example, when the applied voltage is 3 V, a drain current of about 1 × 10 ⁻³ (A) flows (see FIG. 28).
Point A), and then, when the applied voltage is set to 0 V, the drain current becomes a noise level (point O in FIG. 28). That is, when the semiconductor device of the present embodiment is operated at a high speed of about 1 MHz, the drain current increases in accordance with the applied voltage, and M
The same operation as the OS transistor is shown.

Next, when the state at point A in FIG. 28, that is, the state in which a voltage of +3 V is applied to the upper electrode 119 is maintained, electric charges are gradually accumulated in the intermediate electrode 114 due to the passing current of the dielectric layer 116. In this state, charges are also accumulated in the gate electrode 109 of the MOS transistor connected to the intermediate electrode, the threshold value of the MOS transistor changes, and the applied voltage-drain current characteristic of the semiconductor device also changes.

For example, when the applied voltage of +3 V is held for 100 seconds and then the voltage is applied to the upper electrode 119 at about 1 MHz, the characteristics change so as to draw a curve including points B and C in FIG. That is, it is possible to change the applied voltage-drain current characteristic (hereinafter referred to as VG-ID characteristic) of the MOS transistor by the product of the magnitude of the applied voltage and the holding time.

Since there is a difference of one digit or more in the drain current with respect to the applied voltage of +2 V and a five or more digits in the drain current with respect to the applied voltage of 0 V between the initial state and the state after holding for 100 seconds at +3 V, for example, this embodiment When the semiconductor device having the above-described structure is used as a memory, multivalued information can be read by detecting a drain current.

As described above, in the semiconductor device of this embodiment, the voltage within the range in which the resistance value of the dielectric capacitor 104 can be considered to be substantially constant is continuously applied to the upper electrode 119 for a long time, and this is used as write information in the initial stage. The drain current with respect to the applied voltage becomes larger than that in the state M
The characteristics of the OS transistor portion can be modulated. On the other hand, although not shown, by holding a negative voltage such as -3V, it is possible to modulate the characteristics of the MOS transistor portion so that the drain current with respect to the applied voltage becomes less likely to flow than in the initial state. .

As described above, according to the semiconductor device of the present embodiment, the storage operation can be performed by a driving method completely different from that of the conventional semiconductor device functioning as a multi-valued memory.

Since the semiconductor device of this embodiment changes its characteristics by reflecting the history of write information up to that point,
It can be applied not only as a multi-valued memory but also as a neuron element.

In the case of application to a neuron element, many semiconductor devices of this embodiment are connected to each other and the wiring 125
A weight signal is applied to a and an output signal from the preceding neuron element is applied to the drain region 103a. At this time, when the voltage applied to the wiring 125a is high and the pulse width thereof is long, current from the semiconductor device easily flows. The application to such a neuron element will be described in detail in later embodiments.

In the semiconductor device of this embodiment,
Hold the applied voltage of + 3V for 100 seconds, and
The characteristic curve of this semiconductor device gradually returns from the BC curve to the AO curve by, for example, grounding the wiring 125a after the state shown by the curve is reached, and the characteristic curve is about 100.
It returns to the characteristic shown by the A-O curve in a second.
This shows an operation reverse to the storage of the written information, and indicates that the information once written has a function of "forgetting" with the passage of time. Since the actual operation of the device is performed at a high speed such as 100 MHz, such a forgetting function is effective when a signal is not input for a long period of time. That is, the forgetting function effectively changes the less frequently used portion when the next learning operation is input, so that the element learning function can be improved.

In the semiconductor device of this embodiment, the amount of electric charge accumulated in the intermediate electrode 114 and the gate electrode 109 is adjusted depending on the time during which the voltage application is maintained, thereby controlling the ease of drain current flow. However, like the information writing speed, the forgetting speed can be adjusted by controlling the magnitude of the passing current in the voltage range in which the passing current changes in proportion to the voltage.

FIG. 29 shows the correlation between the passing current flowing through the dielectric capacitor 104 and the recovery time in the semiconductor device of this embodiment. Here, the recovery time is the time required from the application of the write voltage until the semiconductor device returns to the initial state (that is, the time until the information is forgotten).

From FIG. 29, it can be seen that within a voltage range where the resistance value of the dielectric layer 116 can be regarded as constant, the recovery time tends to become shorter as the passing current increases. This indicates that the charge accumulated in the intermediate electrode 114 and the gate electrode 109 is leaked as a passing current due to the write voltage.

Here, from the viewpoint of retaining stored information, the passing current when a voltage of 1 V is applied across the dielectric capacitor 104 is set to 100 (mA / cm ² ) or less, and the recovery time is set. By setting the holding time to 10 μsec or more, the modulation memory of the transistor is held sufficiently long with respect to the calculation time. It is sufficient that the passing current is sufficiently small with respect to the time for which the data is desired to be retained.

For example, in the semiconductor device of this embodiment, the graph of FIG. 27 shows that the passing current when 1 V is applied is about 10 ⁻⁸ (A / cm ² ), so the holding time is about 100 seconds as shown in FIG. is there.

As described above, the semiconductor device of this embodiment has the MOS
By adopting a configuration in which a dielectric capacitor and an electric resistance element are connected in parallel to the gate electrode of the transistor, it becomes possible to store the history of signals in a normal MOS transistor as a change in applied voltage-drain current characteristics. It is a thing.

In the semiconductor device of this embodiment, the dielectric capacitor 104 and the resistance element 106 are the same, so that the structure is simplified. Thereby, for example, the drain region 103a is used as a bit line and the wiring 125 is used.
If a is connected to a word line and the semiconductor device of this embodiment is used as a memory cell, a multi-valued memory with a small area can be manufactured. Further, even when the semiconductor device of this embodiment is used as a neuron element, there is an advantage that high integration can be achieved.

However, since the information once stored is lost after the recovery time elapses, the dielectric capacitor 10
4 and the resistance element 106 may be separately manufactured, and the resistance element may be made of a material through which a passing current is less likely to flow. This makes it possible to hold information for a longer time.

In the semiconductor device of this embodiment,
Although the case of using BST as the dielectric material has been described, any material that allows current to flow through the film can be substituted. As such a material, strontium titanate,
Titanium oxide, tantalum oxide, aluminum oxide, zirconium oxide, cerium oxide, gadolinium oxide, and lanthanum oxide are particularly effective.

Since the distribution ratio of the voltage applied to the upper electrode 119 between the dielectric capacitor and the MOS transistor is inversely proportional to the capacitance of the capacitor, it is necessary to change the dielectric material.
The voltage distributed to each element can be appropriately changed by changing the electrode area, changing the film thickness of the dielectric layer 116 or the gate insulating film, and the like.

Further, as the material of the gate insulating film of the MOS transistor, SiO ₂ was used in the present embodiment,
For example, another insulator or dielectric such as a silicon nitride film may be used. Further, not only MOS transistors but also field effect transistors can be used in the semiconductor device of this embodiment. This also applies to the subsequent embodiments.

In the semiconductor device of this embodiment, the writing time was set to 100 seconds under the condition of the applied voltage of +3 V, but this is an example of the writing time, and the charge accumulated in the intermediate electrode is saturated. Not necessarily. The time until the charge is saturated is a little longer, and this time also changes due to the design change of the device as described above. The writing voltage is not limited to + 3V as long as the resistance value of the dielectric layer 116 is within a certain range, but if the voltage is low, the time required for writing becomes longer.

In the semiconductor device of this embodiment, the resistance component of the dielectric layer 116 in the dielectric capacitor 104 also serves as the resistance element 106.
4 and the resistance element 106 may be provided separately from each other.
In that case, the area becomes large, but appropriate design conditions such as reducing the leak current from the resistance element 106 or shortening the time required for writing by making the constituent materials of the dielectric layer 116 and the resistance element 106 different from each other. It can be adjusted.

In the semiconductor device of this embodiment,
The charge accumulation on the intermediate electrode 114 is proportional to the product of the applied voltage and the applied time. Therefore, when applied to a neuron element, weighting is possible by changing the application time of the maximum voltage. Furthermore, once a signal is input, it is “forgotten” after the recovery time elapses if there is no subsequent input, so that neuron elements that are not used for computation and those that are not used are selected. The efficient calculation can be realized.

(Sixth Embodiment) Next, a sixth embodiment of the present invention will be described with reference to the drawings.

Here, with respect to the same semiconductor device of the fifth embodiment, a driving method different from that of the fifth embodiment will be described as a sixth embodiment. Therefore, only the driving method and operation of the semiconductor device will be described below.

FIG. 30 shows the same semiconductor device as that of the fifth embodiment shown in FIGS. 23 to 25, when a voltage is applied between both electrodes of the dielectric capacitor 104 having the dielectric layer 116 made of BST. FIG. 6 is a diagram showing characteristics of a passing current that passes through a dielectric layer 116 and flows between an intermediate electrode 114 and an upper electrode 119.

Generally, a perovskite type oxide such as BST has a substantially constant resistance value in the range where the electric field strength is small, but when the voltage is further increased, as shown in the characteristic curve of FIG. It has the characteristic that the passing current increases exponentially from around the point where it exceeds. Further, even when the applied voltage is in the negative range, it exhibits substantially symmetrical applied voltage-passing current characteristics across 0V.

The sudden increase in the passing current can be explained as a Schottky current. That is, there is a barrier height at the interface between the intermediate electrode 114 or the upper electrode 119 and the dielectric layer 116, and almost no current flows up to a certain electric field strength. However, when a certain electric field strength is exceeded, a current flows through this barrier. Such a current is called a Schottky current.

Next, a method of driving the semiconductor device of this embodiment using the characteristics of such a dielectric capacitor will be described.

FIG. 31 is a drain current-applied voltage characteristic diagram for explaining the driving method and operation of the semiconductor device of this embodiment. Here, the applied voltage refers to a voltage applied between the wiring 125a (or the upper electrode 119) and the substrate electrode 108.

In the semiconductor device of this embodiment, Si
The gate insulating film 10 is formed by the substrate 101 and the gate electrode 109.
Since a MOS capacitor having a structure sandwiching 7 and a dielectric capacitor having a structure sandwiching the dielectric layer 116 by the intermediate electrode 114 and the upper electrode 119 are connected in series, the applied voltage is applied to each capacitor. Will be distributed and applied. For example, when the applied voltage is + 2V, 1.5V and 0.5V are applied to the MOS capacitor and the dielectric capacitor, respectively, and when the applied voltage is + 8V, the MOS capacitor and the dielectric capacitor 104 are respectively 6. 0V and 2.0V are
It is distributed and applied. Note that, from FIG. 30, the dielectric capacitor 104 of the present embodiment, under the voltage of 0.5 V,
Operates as a resistance element with an almost constant resistance value, 2.0V
It can be seen that under the voltage of 1, the current increases exponentially with the increase of the voltage, and operates as a resistance element having a relatively small resistance.

In the method for driving the semiconductor device of this embodiment, the semiconductor device is operated by applying a voltage at, for example, about 50 kHz.

First, in the initial state, the applied voltage is ± 2
Within the range of V, the semiconductor device according to the present embodiment has the structure shown in FIG.
1 shows a characteristic of moving on a characteristic curve including a point D and a point O ′ of 1 (hereinafter referred to as a D-O ′ curve). It should be noted that although the D-O 'curve does not show approximately 0 V or less, the drain current in this region is a noise level and is 10 ^-8 (A).
It was a sufficiently smaller current level.

Here, for example, when 2V is applied, about 6 × 1
A drain current of 0 ^-4 flows (point D), and when 0 V is applied thereafter, the state returns to the state of point O where only a noise level current flows. Even if a voltage of 2 V or less is applied and then 0 V is applied, the drain current is almost at the noise level. That is, the semiconductor device of the present embodiment exhibits the same operation as that of the MOS transistor for the applied voltage of −2V to + 2V.

Next, when a high voltage of, for example, +8 V is applied, the passing current flowing through the dielectric layer 116 exponentially increases, so that charges are accumulated in the intermediate electrode 114 and the gate electrode 109 in a very short time. To be done. In this embodiment,
The operation is performed by setting the frequency of the applied pulse voltage to 50 kHz, but by applying a pulse voltage of, for example, +8 V and 20 μsec, the characteristics can be changed to a curve including points E and F in FIG. Is. That is, it is possible to change the VG-ID characteristics of the MOS transistor in a short time by increasing the applied voltage.
The time required for charge accumulation was 100 seconds in the driving method of the fifth embodiment, but it was 2 seconds in the driving method of the present embodiment.
It is greatly shortened to 0 μsec.

Here, the operation of the semiconductor device of this embodiment will be described in more detail. When a voltage pulse of + 8V is applied, the passing current flowing through the dielectric layer 116 exponentially increases, so that charges are rapidly accumulated in the intermediate electrode 114 and the gate electrode 109.

After that, when the applied voltage is returned to 0 V, FIG.
The characteristic changes to the position of point F, and the drain current changes. Next, when a voltage of +2 V is further applied to the upper electrode 119 from the state of the point F, the state of the point E is reached and the voltage becomes about 3 × 10 5.
^-3 (A) drain current flows, but apply voltage again to 0
When returning to V, the state of point F is restored. That is, the drain current-applied voltage characteristic of the semiconductor device does not change even if a low voltage pulse of about 0 to 2 V is applied after inputting a large voltage pulse. On the other hand, when a −2V negative voltage pulse is applied to the upper electrode 119 in the state of the point F, the state of the semiconductor device moves to the point G, and the drain current decreases by about one digit. After that, when the applied voltage is set to 0 V again, the state at the point H close to the point F is obtained, and the drain current is slightly smaller than that at the point F, but no large change in the drain current is observed.

According to the same principle, for example, the applied voltage is -8
It goes without saying that when V is applied, the drain current changes to an extremely small change in the scan of ± 2V.

As described above, in the method of driving the semiconductor device of this embodiment, information is written in the voltage range in which the passing current flowing through the dielectric capacitor 104 exponentially increases with respect to the increase of the applied voltage. When reading information, etc., within the voltage range in which the passing current is almost proportional to the applied voltage, M
It drives the OS transistor. By this method, the information writing time can be significantly shortened as compared with the semiconductor device driving method shown in the fifth embodiment.

According to the method of driving the semiconductor device of this embodiment, the history of writing information up to that time can be stored in the form of a change in element characteristics. Therefore, the semiconductor device of this embodiment is simply applied as a multi-valued memory. Instead, it can be applied as a neuron element. When it is used as a neuron element, the writing time of information can be significantly shortened as compared with the method of the fifth embodiment, so that the calculation speed can be greatly improved.

The semiconductor device driving method of this embodiment differs from that of the fifth embodiment in that the VG-ID characteristic of the MOS transistor is changed not by the length of the applied voltage pulse but by the magnitude of the absolute value of the applied voltage. The feature is that it can be done. That is, it is possible to modulate the VG-ID characteristic only by setting the input voltage pulse to be a constant cycle and setting the voltage value of the pulse.

In the method of driving the semiconductor device of this embodiment, the writing voltage is set to 8V, but writing may be performed at a higher voltage. Further, even if the voltage applied to the wiring 125a or the upper electrode 119 is, for example, 8 V or less, the capacitance is reduced by a method such as reducing the area of the dielectric capacitor or increasing the thickness of the dielectric layer. The write time can be shortened by increasing the voltage distributed to the capacitor.

Also in the semiconductor device driving method of this embodiment, the state of the semiconductor device returns to the initial state shown by the D-O 'curve in FIG. 31 with the passage of time, for example, by grounding the wiring 125a. That is, the semiconductor device of this embodiment also has a function of "forgetting" as described in the fifth embodiment.

In the method of driving the semiconductor device of this embodiment, from the viewpoint of retaining stored information, the passing current when a voltage of 1 V is applied across the dielectric capacitor 104 is 100 (mA / cm ² ). By setting as below and setting the recovery time to 10 μsec or more, the difference from the voltage pulse having a large absolute value is made clear. Since this is the same condition as the driving method of the fifth embodiment, in the present embodiment, the time required for the recovery is about 100 seconds.

(Seventh Embodiment) The semiconductor device according to the seventh embodiment of the present invention is different from the semiconductor device according to the sixth embodiment only in part of the structure and its driving method and operation. .

FIG. 32 is an equivalent circuit diagram showing the semiconductor device of this embodiment. As shown in the figure, the semiconductor device of this embodiment has a structure in which a ferroelectric capacitor 104a and a resistance element 106 are connected in parallel to a gate electrode 109 of a field effect transistor (hereinafter referred to as a MOS transistor). Is characterized by.

The semiconductor device of this embodiment has the fifth and sixth structures.
Although the structure is almost the same as that of the semiconductor device of the above embodiment, the semiconductor device of this embodiment uses the ferroelectric layer 131 made of a ferroelectric material instead of the dielectric layer 116. Of the embodiment of FIG.

That is, in the semiconductor device of this embodiment, the control voltage supply unit 110, the MOS transistor having the gate electrode 109, the drain region 103a, the source region 103b and the substrate electrode 108, the gate electrode 109 of the MOS transistor and the control unit. It has a ferroelectric capacitor 104a and a resistance element 106 that are provided in parallel with each other with the voltage supply unit 110. Further, the ferroelectric capacitor 104 a has an upper electrode 119, an intermediate electrode 114, and a thickness of 300 between the upper electrode 119 and the intermediate electrode 114.
nm ferroelectric layer 131 made of bismuth titanate (BIT). Further, in the semiconductor device of this embodiment, the ferroelectric layer 131 also functions as the resistance element 106. The source region 103b and the substrate electrode 108 are connected to each other.

Next, FIGS. 33A to 33D are cross-sectional views showing the manufacturing steps of the semiconductor device of this embodiment. In the figure, the same parts as those in FIG. 26 are designated by the same reference numerals.

First, in the step shown in FIG. 33A, the element isolation oxide film 105 is formed on the Si substrate 101 by the LOCOS method in the same procedure as in the fifth embodiment. Then
5 nm thick SiO ₂ on the substrate by pyrooxidation of the substrate
After forming the film, the polysilicon containing the n-type impurities is changed to Si.
The gate insulating film 107 and the gate electrode 109 are formed on the Si substrate 101 by depositing on the O ₂ film and patterning the SiO ₂ film and the polysilicon layer. Then, a p-type impurity such as boron is implanted to form the drain region 103a and the source region 103b on both sides of the gate electrode 109 in the Si substrate 101. In addition,
The MOS transistor manufactured by this step has a gate length of 1 μm and a gate width of 10 μm.

Next, in the step shown in FIG. 33B, the first step of forming SiO ₂ on the substrate is performed in the same procedure as in the fifth embodiment.
After forming the inter-layer insulation film 111, a contact window is formed by dry etching using a resist mask, and the contact window is filled with polysilicon to form plug wirings 113a, 113b, 113c made of polysilicon.
Are formed respectively. Next, the intermediate electrode 114 connected to the gate electrode 109 via the plug wiring 113a, the pad portion 115a connected to the drain region 103a via the plug wiring 113b, and the plug wiring 15b connected to the source region 103b via the plug wiring 113c are formed. Form each. The material of each member is the same as that of the fifth embodiment, but the size of the intermediate electrode is 1 μm × 2 μm, and its area is 1/5 of the area of the MOS transistor.

Next, in the step shown in FIG. 33C, BIT is deposited by a sputtering method under the conditions of a substrate temperature of 600 ° C., an oxygen partial pressure of 20%, and an RF power of 100 W, and a ferroelectric layer 131 having a thickness of 300 nm. Are formed on the substrate. After that, the upper electrode 119 is formed on the ferroelectric layer 131 at a position facing the intermediate electrode by the same procedure as in the fifth embodiment. The size of the upper electrode 119 is 1 μm which is the same as that of the intermediate electrode 114.
m × 2 μm, 1/5 of the area of MOS transistor
And

Next, in the step shown in FIG. 33D, the second interlayer insulating film 121 is formed on the ferroelectric layer 131 by the same procedure as in the semiconductor device of the first embodiment. Next, the wiring 12 from the second interlayer insulating film 121 to the upper electrode 119
5a and the pad portion 115 from above the second interlayer insulating film 121.
a and wirings 125b and 125c reaching the pad portion 115b
Are formed respectively.

The semiconductor device of the present embodiment manufactured by the above manufacturing method is the ferroelectric capacitor 1 shown in FIG.
04a and the resistance element 106 are the same thing, and the resistance element 106 is a resistance component of the ferroelectric capacitor 104a.

As a result, the structure shown in FIG. 32 can be realized in a relatively small area, and the ferroelectric capacitor 1
The number of manufacturing steps is smaller than that in the case of separately manufacturing 04a and the resistance element 106.

Next, the driving method and operation of the semiconductor device of this embodiment will be described below.

FIG. 34 (a) shows an equivalent circuit at the time of coarse adjustment for drastically changing the stored information in the semiconductor device of the present embodiment, and FIG. 34 (b) shows an equivalent circuit at the time of fine adjustment for minutely changing the stored information. Shows. Further, FIG. 35 is a diagram showing characteristics of a passing current when a voltage is applied to both ends of the ferroelectric capacitor 104a. Here, the passing current refers to a current that passes through the ferroelectric layer 131 and flows between the intermediate electrode 114 and the upper electrode 119.

In the present embodiment, the composition of the elements including BIT used as the ferroelectric material is ABO ₃
The oxide having a perovskite structure represented by the following is similar to BST used in the first and sixth embodiments, and has a resistance value that is negligible while the applied electric field strength is small, When the voltage is further increased, the passing current increases exponentially. From FIG. 35, also in the ferroelectric capacitor 104a of the present embodiment,
When a voltage higher than around 1.8 V is applied, the passing current increases exponentially. Further, when a negative voltage is applied, a symmetrical characteristic is shown across the axis of the applied voltage of 0V.

Therefore, as shown in FIG. 35, when the voltage distributed to the ferroelectric substance is within the voltage range of -2.3 V or less and +2.3 V or more during the coarse adjustment, the ferroelectric substance becomes the resistance element 1.
It also functions as 06, and the leak current I flows. The equivalent circuit at this time is, as shown in FIG. 34A, the ferroelectric capacitor 104 on the gate electrode 109 of the MOS transistor.
In this configuration, a and the resistance element 106 are connected in parallel.

On the other hand, the voltage distributed to the ferroelectric is -1.
In the fine adjustment voltage range of about 4 to +1.4 V, almost no current flows through the ferroelectric substance, and the ferroelectric substance is almost an insulator. The equivalent circuit at this time has a form in which only the ferroelectric capacitor 104a is connected to the gate electrode 109 of the MOS transistor, as shown in FIG.

In the semiconductor device of this embodiment, the MOS capacitor having a structure in which the gate insulating film 107 is sandwiched between the Si substrate 101 and the gate electrode 109, and the ferroelectric layer 131 is sandwiched between the intermediate electrode 114 and the upper electrode 119. Since the ferroelectric capacitor 104a having the recessed structure is connected in series, the applied voltage is distributed and applied to each capacitor. For example, in the semiconductor device of this embodiment, the applied voltage is +2
When V is applied to the entire device, 1.2V and 0.8V are applied to the MOS transistor and the ferroelectric capacitor 104a, respectively.
3.6V and 2.4V are distributed to the transistor and the ferroelectric capacitor 104a, respectively.

In the semiconductor device of this embodiment, the leak current can be increased and the potential of the floating gate can be greatly changed by setting the voltage distributed to the ferroelectric capacitor 104a within the voltage range during coarse adjustment. . Further, by setting the voltage distributed to the ferroelectric capacitor 104a in the fine adjustment voltage range, the leak current is reduced,
Data can be retained and the floating gate potential can be finely adjusted by changing the polarization of the ferroelectric substance.

FIG. 36 is a diagram showing an example of an actual voltage applying method based on the above findings. In this example, first, a voltage pulse of 2.5 V is applied to the ferroelectric in the period of 1 μsec. As a result, it is rapidly accumulated in the floating gate through the ferroelectric substance. At this time, the polarization of the ferroelectric substance is aligned in one direction.

Next, after 5 μsec, the period is 1 μse.
At c, a negative minute voltage is applied to the ferroelectric. At this time, the leak current from the ferroelectric substance is so small that it can be ignored, and the polarization of the ferroelectric substance is gradually inverted. As a result, the charge amount of the floating gate can be changed by a small amount.

In a general ferroelectric gate transistor, the charge amount of the floating electrode (gate electrode 109) can be changed only by the polarization value of the ferroelectric substance, but by using the driving method of this embodiment, it is very wide. The charge amount can be changed within the range. That is, the on-resistance value of the MOS transistor can be determined in a very wide range and in detail. This means that it functions as an analog memory capable of continuously holding multivalued information in accordance with the amount of charge accumulated in the floating electrode.

FIG. 37 is a characteristic diagram for explaining the operation of the semiconductor device of this embodiment in the initial state. In the figure, the horizontal axis represents the applied voltage and the vertical axis represents the drain current. The applied voltage here means a voltage applied between the wiring 125a (or the upper electrode 119) and the Si substrate 101.

As shown in FIG. 37, when a voltage is applied to the semiconductor device of this embodiment in the initial state within a range of ± 2 V, the VG-ID characteristic of the MOS transistor in the device causes counterclockwise hysteresis. It operates as a so-called ferroelectric gate transistor.

Therefore, even if the applied voltage is unloaded after the voltage of +2 V is applied to the semiconductor device, for example, the ferroelectric layer 1
The polarization of 31 induces charges in the intermediate electrode 114 to generate a potential. Therefore, even if the applied voltage is 0 V, about 2 μA
Drain current flows. On the other hand, conversely, if the applied voltage is unloaded after applying -2 V, the drain current will be extremely small this time (10 ^-8 A or less, not shown).
Here, the voltage between the source and the drain is 1V as in the fifth embodiment.

Next, when +6 V is applied to the semiconductor device of this embodiment, it becomes possible to set a different drain current value.

FIG. 38 is a diagram showing a drain current when a voltage pulse of 2V is repeatedly applied and unloaded to the semiconductor device of this embodiment after applying + 6V as a write voltage. The voltage pulse interval at this time is 20 μsec.

As shown in the figure, the present embodiment in the initial state
+ 6V is applied as a write voltage to the semiconductor device of the embodiment
Then, the voltage of 2.4V is distributed to the ferroelectric capacitor.
Therefore, the passing current increases exponentially and the charge is
By being accumulated in the pole 114 and the gate electrode 109,
Therefore, the drain current increases by more than two digits from the initial state. It
After that, even if the same + 2V voltage pulse is input,
Rain current is about 1 x 10 ^-3Almost no change from (A)
Shows the characteristics.

From this, it is understood that the semiconductor device of this embodiment can stably hold data by applying a high voltage write voltage.

Next, in FIG. 39, after applying +6 V,
FIG. 9 is a characteristic diagram of applied voltage-drain current in the semiconductor device of the present embodiment when the applied voltage is scanned in the range of 2V.

First, when a voltage of +6 V is applied to this semiconductor device and then the load is removed, the drain current has a value shown by point I in FIG.

Then, in this point I, the semiconductor device is
When a voltage of V is applied and the voltage is unloaded, the drain current follows the locus shown from point I to point J in FIG.
After unloading, the state returns to point I again. The state at point I corresponds to the state in which the voltage pulse shown in FIG. 38 is applied.

When a voltage of −2V is applied to the semiconductor device in the state of point I, the state shown in point K is reached, and the drain current is reduced to 1 × 10 ⁻⁵ (A) or less by about two digits. Then, when the voltage is unloaded, the state moves to the state of point L, and the drain current decreases by about one digit as compared with the state of point I before voltage application.

In the semiconductor device of the sixth embodiment, the structure shown in FIG.
There is no significant difference in the drain currents at points F and H, and this is the point that the semiconductor device of this embodiment is significantly different from the semiconductor devices of the fifth and sixth embodiments.

As a result, the semiconductor device of this embodiment can hold more data than the semiconductor devices of the fifth and sixth embodiments.

Next, when + 2V is applied to the semiconductor device in the state of point L in FIG. 39, the semiconductor device moves to the state of point M, and thereafter,
When the voltage is unloaded, the state shown at point N is reached. At this time, the drain current changes along a locus indicated by point L → point M → point N, and in the state of point N, a larger drain current than in the state of point L is obtained. In this way, it is possible to further modulate the drain current by a scan of a small applied voltage of ± 2V after a high applied voltage of + 6V.

On the other hand, a large negative voltage pulse can be input as the write voltage.

FIG. 40 is a diagram showing the drain current when a voltage of -6V is applied to the semiconductor device of this embodiment and then a voltage pulse of + 2V is applied to unload it. The pulse interval of the voltage pulse is 20 μsec.

From the figure, it can be seen that by applying a voltage of -6V to the semiconductor device of the present embodiment in the initial state, the drain current at 0V becomes four orders of magnitude lower than in the initial state. Also in this case, the change in drain current when the application of the voltage pulse of +2 V and the unloading are repeated is small.

Next, FIG. 41 is a diagram showing applied voltage-drain current characteristics of the semiconductor device of the present embodiment when the applied voltage is scanned within a range of ± 2 V after the input of a voltage pulse of -6 V. Although hysteresis is observed even in this state, the drain current in the 0 V applied state is maintained at an extremely low value regardless of which polarity voltage is applied. Thus, by applying a negative voltage, a small drain current that can be distinguished from the case of applying a positive voltage can be obtained.

As described above, in the semiconductor device of this embodiment, when the MOS transistor is driven in the voltage range (low voltage range) in which the resistance value of the resistance component of the ferroelectric capacitor 104a is substantially constant, It is possible to selectively use the case where writing is performed within a range in which the passing current exponentially increases by switching the applied voltage.

In the semiconductor device of this embodiment, the change in the applied voltage-drain current characteristic is caused by the accumulation of the charges passing through the ferroelectric layer 131 in the intermediate electrode 114.
Electric charges are also accumulated in the gate electrode 109 of the OS transistor, which is caused by a change in the VG-ID characteristic of the MOS transistor. Particularly, in the semiconductor device of this embodiment,
Since it is possible to change the charge storage amount of the intermediate electrode and the gate electrode 109 depending on the polarization direction of the ferroelectric capacitor 104a, it takes an extremely large value compared with the semiconductor devices of the fifth and sixth embodiments. Can be used as a multi-valued memory to obtain

Further, since the large modulation of the drain current by the large voltage pulse and the small modulation of the drain current by the small voltage pulse can be reflected respectively as the modulation of the drain current, the neuron element with extremely high degree of freedom of weighting can be obtained. Can also be applied.

In the semiconductor device of this embodiment as well, similar to the semiconductor devices of the fifth and sixth embodiments, the characteristic that the characteristics are returned to the initial state by grounding the wiring 125a and the like, and "forgetting" is performed. Have.

In the semiconductor device of this embodiment,
From the perspective of retaining stored information,
When a voltage of 1 V is applied to the end, the passing current is 100 (mA
/ Cm ² ) The recovery time is 10 μse
By setting c or more, the drain charge due to polarization of the ferroelectric substance
The difference with the pressure modulation is made clear. this
Is almost the same as the semiconductor device of the fifth embodiment shown in FIG.
It is the same tendency, and the time required for recovery is about 100 seconds.
Has become.

Further, similarly to the semiconductor device of the fifth embodiment, the ferroelectric layer 1 is also applied to the semiconductor device of the present embodiment.
31 and the resistance element 106 may be provided separately. In that case, for example, in order to extend the time for holding information, the ferroelectric material forming the resistance element 106 is changed to the ferroelectric layer 13.
It can be appropriately designed in accordance with the required conditions, such as making it harder for current to pass than the ferroelectric material constituting No. 1.

In addition, the ferroelectric layer 131 and the resistance element 106
When they are provided separately, a dielectric may be used as the material forming the resistance element 106.

In the semiconductor device driving method of this embodiment, the voltage region in which the resistance value of the ferroelectric layer is substantially constant and the voltage region in which the passing current exponentially increases with respect to the voltage are used separately. Although the method has been described, as in the fifth embodiment, the semiconductor device is driven only in the voltage region in which the resistance value of the ferroelectric layer is so small that it can be ignored, and the pulse width of the applied voltage is set to be longer than the recovery time. By setting it sufficiently short, it is possible to similarly change the amount of charge accumulated in the intermediate electrode 114 and the gate electrode 109.

In the semiconductor device of this embodiment, BIT was used as the material of the ferroelectric layer, but likewise, materials exhibiting ferroelectricity, such as lead titanate, lead zirconate titanate, and Any material such as strontium tantalate can be used as the material of the ferroelectric layer.

(Eighth Embodiment) In a semiconductor device according to an eighth embodiment of the present invention, the resistance element 106 in the seventh embodiment is replaced by a resistance element 150 which is a varistor made of zinc oxide (ZnO). It has been replaced. However, the resistance element 150 is provided separately from the ferroelectric substance.

FIG. 42A is a circuit diagram showing the semiconductor device of this embodiment, and FIG. 42B is a diagram showing varistor characteristics of the resistance element 150. The same members as those in FIG. 32 are designated by the same reference numerals.

As shown in FIG. 42 (b), ZnO, etc.
Some metal oxides have a property that the resistance value greatly changes depending on the applied voltage. In the case of the resistance element 150 of the present embodiment having an electrode area of 10 μm ^2, a resistance value of about 180 GΩ is exhibited in the voltage range of −1 V or more and +1 V or less, but when the absolute value of the voltage exceeds 1.5 V, the resistance value drastically decreases. To do.

From this, for example, -2V or less and 2V
By operating the above voltage range as the coarse adjustment voltage and operating the range of -1V to + 1V as the fine adjustment voltage, the same operation as that of the semiconductor device of the seventh embodiment becomes possible.

In addition, in the semiconductor device of this embodiment, the material of the resistance element 150 can be arbitrarily selected, so that the range of operating voltage can be freely set. For example, the resistance element 150 is applied at a voltage at which the polarization of the ferroelectric substance is saturated.
By setting the low resistance voltage of 1 to a little higher voltage, it is possible to execute the rough adjustment and fine adjustment operations with a lower drive voltage.

Next, FIG. 43 is a sectional view showing the structure of the semiconductor device of this embodiment.

As shown in the figure, the ferroelectric substance 131 and the resistance element 150 of this embodiment may be provided with the upper electrode and the lower electrode in common. Such a structure can be easily realized by using a known technique. For example, after depositing a ferroelectric substance on the entire surface of the lower electrode, a part of the ferroelectric substance is selectively etched, and ZnO is deposited on the lower electrode portion where the ferroelectric substance is removed. Although the example in which the ferroelectric and the resistance element are provided in contact with each other has been shown here, they may be provided separately from each other.

As the material for forming the resistance element,
In addition to ZnO, perovskite type oxides such as Ba _x Sr ₁ -x TiO ₃ , TiO ₂ -based oxides, Fe ₂ O ₃ -based oxides, C
A u ₂ O-based oxide or the like can be used. Further, in order to reduce the resistance of these metal oxides, it is possible to add Bi ₂ O ₃ or a rare earth element to the above metal oxides. Thereby, the resistivity and the rate of resistance change of the metal oxide material can be adjusted appropriately. Further, a PN junction of Si, a system in which Al is added to a SiC semiconductor, Se, or the like can also be used as the material of the resistance element.

In the semiconductor device of this embodiment, the multi-valued information is controlled so as to be favorably held by properly using the rough adjustment and the fine adjustment. However, the element provided in parallel with the ferroelectric is a resistor. Not limited to the element, any element or circuit capable of changing the charge injected into the floating gate by the applied voltage may be used.

(Ninth Embodiment) In a semiconductor device according to a ninth embodiment of the present invention, the resistance elements 106 of the seventh embodiment are connected in parallel to each other and arranged in opposite directions to each other. It is replaced with two diodes.

FIG. 44 is a circuit diagram showing the semiconductor device of this embodiment. The same members as those in FIG. 32 are designated by the same reference numerals.

As shown in the figure, in the semiconductor device of this embodiment, the ferroelectric capacitors 104 connected to the control voltage supply section 110, the MOS transistor, and the gate electrode 109 of the MOS transistor and provided in parallel with each other.
a, a diode 152, and a diode 154. Further, the diode 152 and the diode 154 are arranged in directions opposite to each other. That is, the diode 152 and the diode 154 are connected to the input section and the output section, respectively.

In the present embodiment, the diodes 152 and 154 are, for example, PN diodes or the like. A current flows through these diodes when a forward voltage higher than a predetermined value is applied, and almost no current flows when a current below a predetermined value is applied. Further, within the withstand voltage range, almost no current flows even if a reverse current is applied.

As shown in FIG. 44, by connecting two diodes opposite to each other in parallel, when the threshold value of the diode is tV, the voltage applied to the diode is between -tV and + tV. If so, almost no current flows, and when the absolute value of the voltage exceeds tV, current flows and charges flow into the floating gate.

Therefore, as in the third and eighth embodiments, when the absolute value of the distributed voltage is large, the coarse adjustment is performed, and when the absolute value of the distributed voltage is small, the fine adjustment is performed. Data can be stored.

In the semiconductor device of this embodiment, PN diodes are used as the diodes 152 and 154, but other diodes such as Schottky diodes may be used.

(Tenth Embodiment) In a semiconductor device according to a tenth embodiment of the present invention, the resistance element 106 in the seventh embodiment is replaced with a MIS transistor whose on / off is controlled by a control voltage Vr. It is a thing.

FIG. 45 is a circuit diagram showing the semiconductor device of this embodiment.

As shown in the figure, the semiconductor device of the present embodiment has a control voltage supply unit 110, a MOS transistor, a ferroelectric capacitor 104a connected to the gate electrode 109 of the MOS transistor, and a control voltage supply unit. 11
0 and the MIS transistor 156 provided between the gate electrode 109. The MIS transistor 156 is controlled by the control signal Vr.

According to the semiconductor device of the present embodiment, by appropriately controlling the on / off of the MIS transistor by an external control circuit or the like, the floating gate potential as described in the third to fifth embodiments can be obtained. Coarse and fine adjustments are possible. For example, when the absolute value of the voltage applied to the MIS transistor is equal to or larger than a predetermined value, the MIS transistor is turned on, and when the absolute value of the voltage applied to the MIS transistor is equal to or less than the set value, it is controlled to be off.

According to the semiconductor device of this embodiment, the MIS
Regardless of the structure of the transistor, it is possible to switch between the rough adjustment and the fine adjustment by appropriately changing the control voltage Vr, and thus it is possible to operate in an arbitrary voltage range.

In the semiconductor device of this embodiment,
A bipolar transistor can be used instead of the MIS transistor 156.

(Eleventh Embodiment) A semiconductor device according to an eleventh embodiment of the present invention is the resistance variable element 158 whose crystallinity is controlled by the resistance control signal Vw in the resistance element 106 of the seventh embodiment. Is replaced with.

FIG. 46 is a circuit diagram showing the semiconductor device of this embodiment.

As shown in the figure, in the semiconductor device of this embodiment, the ferroelectric capacitor provided between the control voltage supply unit 110, the MOS transistor, and the control voltage supply unit 110 and the gate electrode 109 of the MOS transistor. Body capacitor 1
04a, a resistance change element 158 provided between the control voltage supply unit 110 and the gate electrode 109 of the MOS transistor in parallel with the ferroelectric capacitor 104a. The resistance change element 158 is made of, for example, germanium (Ge), tellurium (Te), antimony (S).
It is composed of an alloy whose main component is the three elements of b),
Its crystallinity is controlled by the resistance control signal Vw.

The resistance change element 158 is in an amorphous state when the Vw is a high voltage pulse equal to or more than the set value, and the resistance value becomes large. After that, by decreasing the Vw pulse, the resistance value can be gradually decreased and adjusted to an arbitrary value. Therefore, when it is desired to accumulate charges in the floating gate, the Vw pulse is set to a low voltage and the voltage is supplied from the control voltage supply unit 110 in that state. Next, when the potential of the floating gate is finely adjusted or the data is held, the Vw pulse is set to a high voltage and a voltage in the fine adjustment voltage range shown in FIG. 35 is applied to the ferroelectric capacitor 104a. As a result, both the leak current from the ferroelectric substance and the leak current from the resistance change element can be reduced.
As described above, even by using the resistance change element, it is possible to realize a semiconductor device that can favorably hold multi-valued information.

A chalcogenide material other than Ge, Te, and Sb is preferably used as the material of the resistance change element 158 of this embodiment.

(Twelfth Embodiment) As a twelfth embodiment of the present invention, a neuron computer using the semiconductor device of the seventh embodiment as a neuron element will be described.

FIG. 48 is a diagram showing a model of the basic structure of the brain of a living organism. As shown in the same figure, the brain of an organism is a neuron 141a in the front stage and a neuron 141 in the rear stage, which are nerve cells having an arithmetic function.
b, 141c, nerve fibers 142a, 142b, 142c for transmitting the calculation result from the neuron, and synaptic connections 143a, 143b, 143c for weighting the signal transmitted by the nerve fiber and inputting to the neuron. There is.

For example, signals transmitted by a large number of nerve fibers including the nerve fiber 142a are transmitted through synaptic connections 143a.
Weights such as Wa, Wb, and Wc are applied by a large number of synaptic connections including, and input to the neuron 141a. The neuron 141a takes a linear sum of the input signal intensities, is activated when the total value exceeds a certain threshold value, and outputs a signal to the nerve fiber 142b. When a neuron is activated and outputs a signal, the neuron is said to "fire."

This output signal is branched into, for example, two parts, weighted by synaptic connections, and then input to the neurons 141b and 141c in the subsequent stage. The neurons 141b and 141c in the subsequent stage also take the linear sum of the input signals, and when the total value of these signals exceeds a certain threshold value, the neurons 141b and 141c are activated and output signals. This operation is repeated in a plurality of steps to output the calculation result.

The weight applied in the synapse connection is gradually corrected by learning so that the optimum calculation result is finally obtained.

The neuron computer is designed to substitute such a brain function with a semiconductor device.

FIG. 47 is a diagram showing an outline of the basic configuration of the neuron computer of this embodiment. In the figure, the same members as those of the semiconductor device of the seventh embodiment are designated by the same reference numerals as those shown in FIG.

First, as described above, the semiconductor device according to the seventh embodiment used in the neuron computer of this embodiment has the control voltage supply unit 110, the gate electrode 109, the drain region 103a, and the source region 103b.
MOS transistor Tr1 having a substrate electrode 108
1 and the gate electrode 10 of the MOS transistor Tr11
9 and the control voltage supply unit 110, the ferroelectric capacitor 104a and the resistance element 106 are provided in parallel with each other.

Next, as shown in FIG. 47, the neuron computer of the present embodiment has an electric resistance provided between the semiconductor device of the seventh embodiment and the ground and the source electrode of the MOS transistor Tr11. 133, a node N1 provided between the source electrode of the MOS transistor Tr11 and the electric resistance 133, a floating gate, a transistor Tr having a large number of input gates provided on the floating gate, and source and drain electrodes.
12 and an electric resistance 132 interposed between the source electrode of the transistor Tr12 and the voltage supply line Vdd. The source electrode of the transistor Tr12 is connected to ground. Further, the node N1 is connected to one of the input gates.

The semiconductor device according to the seventh embodiment,
The node N1 and the electric resistance 133 correspond to a synapse portion (a nerve fiber and a synapse connection) for transmitting and weighting signals in the brain of an organism, and a large number of synapse portions are neuron portions each including a transistor Tr12 and an electric resistance 132. (Neuron MOS). In the neuron computer of the present embodiment, the structure of the brain is imitated, and the combination of the synapse part and the neuron part connected to each other is taken as one layer, and for example, about four layers are superposed.

Next, regarding the signal transmission path, first, the output signal Ss1 from the preceding neuron section is input to the drain electrode of the MOS transistor Tr11, and the weight signal S ₁
Is input to the control voltage supply unit 110. Then, the drain signal value flowing from the MOS transistor Tr11 is changed by the weight signal S ₁ .

Next, the current signal output from the MOS transistor Tr11 is converted into a voltage signal by the electric resistance 133 and input to the input gate of the transistor Tr12. Signals from many other synapse parts are also input to the input gate of the transistor Tr12, and when the sum of the voltages of these input signals exceeds the threshold value of the transistor Tr12, the neuron “fires” and a signal is output from the neuron part. It Then, the output signal is transmitted to the synapse part of the next stage.

On the other hand, when the sum of the voltages of the input signals from the synapse part is smaller than the threshold value of the transistor Tr12,
No signal is output.

In the neuron computer of this embodiment, since the semiconductor device of the seventh embodiment, which has a simple structure and can hold multivalued information in the synapse portion, is used in the synapse portion, various signals can be obtained in a small area. Weight can be applied. As a result, it is possible to reduce the size of the neuron computer having a learning function, which is created by integrating the synapse part and the neuron part.

In the semiconductor device of the seventh embodiment, the MOS transistor Tr11 is changed by applying a low voltage of about ± 2V after changing the characteristics of the applied voltage-drain current at about 6V as already described. The drain current of can be finely changed. Therefore, in the neuron computer of the present embodiment, even if the weighted signal S ₁ has a relatively low voltage, it is possible to apply various levels of weighting corresponding thereto.

Further, the synapse portion of the neuron computer of this embodiment has a function of storing the history of the weight signal S ₁ and forgetting the history when it is not used for a long time.

In the neuron computer of this embodiment, the semiconductor device of the seventh embodiment having the ferroelectric capacitor in the synapse part is used, but instead of this, the fifth semiconductor device having the dielectric capacitor is used. You may use the semiconductor device of embodiment and the semiconductor device of 8th-11th embodiment.

[0285]

According to the semiconductor device of the present invention, by connecting the ferroelectric capacitors having different coercive voltages in parallel, the polarization of the capacitor is metastable in addition to the point that the polarization of the capacitor is saturated in the hysteresis of the capacitor. The point is obtained. As a result, it is possible to improve the separability of stored information, and to stabilize the voltage even when the write voltage fluctuates due to variations in the ferroelectric film thickness and differences in the crystallinity of the ferroelectric.
A polarization above the value can be obtained.

Further, according to the semiconductor device and the method of driving the same of the present invention, since the dielectric capacitor and the resistance element are provided in parallel between the gate electrode of the MOS transistor and the voltage supply portion, the voltage By applying an applied voltage to the supply portion, charges can be accumulated in the intermediate electrode and the gate electrode of the capacitor, and the voltage-drain current characteristic of the MOS transistor can be changed. Utilizing this fact, it is possible to realize a semiconductor device applicable not only as a multi-valued memory but also as a constituent element of a neuron element for weighting signals.

[Brief description of drawings]

FIG. 1 is a top view showing a multi-valued memory according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a II-II cross section of FIG. 1 in the multi-valued memory according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a III-III cross section of FIG. 1 in the multi-valued memory according to the first embodiment of the present invention.

4A to 4E are cross-sectional views showing a manufacturing process of the multi-valued memory according to the first embodiment of the present invention.

FIG. 5 is an equivalent circuit diagram showing a multi-valued memory according to the first embodiment of the present invention.

FIG. 6 is a diagram showing a voltage-polarization hysteresis characteristic (PV characteristic) of a capacitor MFM1.

FIG. 7 is a diagram showing a P-V characteristic of a capacitor MFM2.

FIG. 8 is a capacitor MFM1 and a capacitor MF.
It is a figure which shows the P-V characteristic of M2 and the P-V characteristic of the whole capacitor.

FIG. 9 is a diagram showing a P-V characteristic of the entire capacitor when three capacitors are used in the multilevel memory of the present invention.

FIG. 10 shows a voltage applied between an upper gate electrode and a lower electrode in the multilevel memory according to the first embodiment of the present invention,
It is a figure showing effective polarization of a ferroelectric capacitor.

FIG. 11 is a diagram for explaining gate voltage-drain current characteristics with respect to each write voltage of the multilevel memory according to the first embodiment of the present invention.

FIG. 12 is a diagram for explaining the correlation between the fluctuation of the write voltage and the fluctuation of the polarization value in the conventional multilevel memory.

FIG. 13 is an enlarged view of a portion indicated by A in FIG. 12 in the conventional multi-valued memory.

FIG. 14 is a diagram for explaining the correlation between the fluctuation of the write voltage and the fluctuation of the polarization value in the multi-valued memory according to the first embodiment of the present invention.

FIG. 15 is an enlarged view of a portion indicated by B in FIG. 14 in the multi-valued memory according to the first embodiment of the present invention.

16 (a) to 16 (d) are diagrams showing the area of the capacitor MFM2 in the multi-valued memory of the present invention.
It is a figure which shows the effective polarization when changing with respect to.

17 (a) to 17 (d) are diagrams showing the area of the capacitor MFM1 in the multi-valued memory of the present invention.
It is a figure which shows the effective polarization when changing with respect to.

FIG. 18 is a cross-sectional view showing a modified example of the multilevel memory according to the first embodiment of the present invention.

FIG. 19 is a cross-sectional view showing the structure of the multi-valued memory according to the second embodiment of the present invention.

FIG. 20 is a circuit diagram showing an outline of a multilevel memory according to a third embodiment of the present invention.

FIG. 21 is an equivalent circuit diagram showing a multilevel memory according to a fourth embodiment of the present invention.

FIG. 22 is an equivalent circuit diagram showing a semiconductor device according to a fifth embodiment of the present invention.

FIG. 23 is a top view showing a semiconductor device according to a fifth embodiment of the present invention.

24 is a cross-sectional view taken along line XXIV-XXIV shown in FIG. 22 of the semiconductor device according to the fifth embodiment of the present invention.

FIG. 25 is a sectional view taken along line XXV-XXV shown in FIG. 22 of the semiconductor device according to the fifth embodiment of the present invention.

26A to 26D are cross-sectional views showing the manufacturing process of the semiconductor device according to the fifth embodiment of the present invention.

FIG. 27 is a diagram showing applied voltage-pass current characteristics of a dielectric capacitor used in a semiconductor device according to a fifth embodiment of the present invention.

FIG. 28 is a diagram showing applied voltage-drain current characteristics of the semiconductor device according to the fifth embodiment of the present invention.

FIG. 29 is a correlation diagram between the passing current flowing through the dielectric capacitor and the recovery time in the semiconductor device according to the fifth embodiment of the present invention.

FIG. 30 is a diagram showing applied voltage-pass current characteristics of a dielectric capacitor in a method for driving a semiconductor device according to a sixth embodiment of the present invention.

FIG. 31 is a diagram showing applied voltage-drain current characteristics of the semiconductor device according to the sixth embodiment of the present invention.

FIG. 32 is an equivalent circuit diagram showing a semiconductor device according to a seventh embodiment of the present invention.

33 (a) to 33 (d) are views showing manufacturing steps of the semiconductor device according to the seventh embodiment of the present invention.

FIG. 34A is a diagram showing an equivalent circuit at the time of coarse adjustment in which the stored information is significantly changed in the semiconductor device of the present embodiment, and FIG. 34B is a view at the time of fine adjustment in which the stored information is finely changed. It is a figure which shows an equivalent circuit.

FIG. 35 is a diagram showing applied voltage-pass current characteristics of a ferroelectric capacitor used in a semiconductor device according to a seventh embodiment of the present invention.

FIG. 36 is a view of a semiconductor device according to a seventh embodiment,
It is a figure which shows an example of a voltage application method.

FIG. 37 is a diagram showing applied voltage-drain current characteristics in the initial state of the semiconductor device according to the seventh embodiment of the present invention.

FIG. 38 is a diagram showing a drain current when a pulse voltage is continuously applied after + 6V is applied in the semiconductor device according to the seventh embodiment of the present invention.

FIG. 39 is a diagram showing applied voltage-drain current characteristics when the applied voltage is scanned within a range of ± 2V after applying + 6V in the semiconductor device according to the seventh embodiment of the present invention.

FIG. 40 is a diagram showing a drain current when a pulse voltage is continuously applied after applying −6 V in the semiconductor device according to the seventh embodiment of the present invention.

FIG. 41 is a diagram showing applied voltage-drain current characteristics when the applied voltage was scanned within a range of ± 2 V after applying −6 V in the semiconductor device according to the seventh embodiment of the present invention.

42A is a circuit diagram showing a semiconductor device according to an eighth embodiment of the present invention, and FIG. 42B is a diagram showing varistor characteristics of a resistance element.

FIG. 43 is a cross-sectional view showing the structure of the semiconductor device according to the eighth embodiment.

FIG. 44 is a circuit diagram showing a semiconductor device according to a ninth embodiment of the present invention.

FIG. 45 is a circuit diagram showing a semiconductor device according to a tenth embodiment of the present invention.

FIG. 46 is a circuit diagram showing a semiconductor device according to an eleventh embodiment of the present invention.

FIG. 47 is a diagram showing an outline of a basic configuration of a neuron computer according to a twelfth embodiment of the present invention.

[Fig. 48] Fig. 48 is a diagram showing a model of the brain of an organism, in which the constitution of basic units is simplified.

FIG. 49 is a cross-sectional view of a conventional semiconductor device that functions as a multi-valued memory.

FIG. 50 is a diagram showing hysteresis characteristics of a conventional semiconductor device that functions as a multi-valued memory.

FIG. 51 is a graph showing a relationship between a gate voltage and a drain current of a memory cell of a conventional semiconductor device.

[Explanation of symbols]

1 substrate 3a drain region 3b source region 5 element isolation film 7 gate insulating film 9 gate electrode 11 first interlayer insulating films 13a, 13b, 13c, 13d plug wiring 14a first intermediate electrode 14b second intermediate electrode 15a, 15b Pad portion 16 First ferroelectric layer 17 First upper electrode 18 Second ferroelectric layer 19 Second upper electrode 20 Insulating layer 21 Second interlayer insulating films 25a, 25b, 25c Wiring 26 Gate electrode / Lower electrode 27 First ferroelectric layer 28 Second ferroelectric layer 29 First upper electrode 30 Second upper electrode 31 Interlayer insulating film 32 Plug wiring WL Word line BL bit line 101 Si substrate 103a Drain region 103b Source region 104 Dielectric capacitor 104a Ferroelectric capacitor 105 Element isolation oxide film 106 Resistive element 107 Gate insulating film 108 Electrode 109 Gate electrode 110 Control voltage supply section 111 First interlayer insulating films 113a, 113b, 113c Plug wiring 114 Intermediate electrodes 115a, 115b Pad section 116 Dielectric layer 119 Upper electrode 121 Second interlayer insulating films 125a, 125b, 125c Wiring 131 Ferroelectric layers 132, 133 Electric resistance Ss ₁ Output signal S ₁ from previous stage synapse Load signal Tr 11 MOS transistor Tr 12 Transistor N 1 node

[Procedure amendment]

[Submission date] December 25, 2002 (2002.12.
25)

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] Full text

[Correction method] Change

[Correction content]

[Document name] Statement

Title: Semiconductor device

[Claims]

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a driving method thereof, and more particularly to a semiconductor device which can be used in a neural network computer (neuron computer) or the like and can hold multivalued information, and a driving method thereof.

[0002]

2. Description of the Related Art With the progress of multimedia, demands for improving the performance of semiconductor devices are increasing. In order to process a large amount of digital information, for example, a CPU of a personal computer, which has a high-speed operation of 1 GHz or more, has been commercially available.

Semiconductor manufacturers have hitherto mainly responded to such demands for improving the performance of semiconductor devices by improving the performance of semiconductor devices by miniaturization process technology.

However, now that even physical limits have been pointed out for the miniaturization of semiconductor devices, the performance improvement of semiconductor devices by further miniaturization is
From the point of view of manufacturing costs, we are no longer expecting.

As a means for solving the above requirement, "1"
In addition to the conventional digital information processing technology that uses two-valued signals of 0 and “0” to perform arithmetic operations, the technology that multivalues information into three-valued and four-valued data and the multi-valued technology is applied. Computer technology (neuron computer) that can perform arithmetic processing that mimics the function of the brain of living things is being researched.

The brain of an organism is basically composed of nerve cells called neurons having an arithmetic function, and nerve fibers which play a role of wiring so as to transmit the arithmetic result to other neurons.

The neuron computer is composed of a large number of neuron parts made up of semiconductor elements corresponding to neurons, and a large number of synapse parts which transmit signals to the neuron parts and weight them. The combination of the neuron part and the synapse part is hereinafter called a neuron element.

When information signals having different "weights" from a plurality of preceding neuron elements are input to a certain neuron element, the information signals are added in this neuron element, and the sum of the information signals exceeds a threshold value. The neuron element "fires" and the signal is output to the next neuron element. By repeating this, information is processed.

Further, the process of learning by the brain of an organism is regarded as a process in which the weight in synaptic connection changes. That is, for various combinations of input signals, the weights are gradually modified so that a correct output can be obtained, and finally settled at an optimum value.

In order to construct a neural network having such a learning function, it is necessary to appropriately change the strength of each synaptic connection and store the changed value. Therefore, multi-valued technology is an essential technology for realizing a neuron computer.

The above-mentioned neuron computer is an example of application of multi-valued technology, but of course, research on multi-valued memory for stably storing multi-valued information has been actively conducted. As can be seen from these facts, the information multi-valued technique will be an extremely important technique in future semiconductor devices.

As an example of such multi-valued technique, polarization hysteresis of a ferroelectric substance is utilized to make three memory cells in one memory cell.
A conventional technique for storing information of a value or more is described in Japanese Patent Laid-Open No. 8-124378 "Ferroelectric Memory".

FIG. 49 is a sectional view of a conventional semiconductor device which functions as a multi-valued memory. As shown in the figure, the memory cell of the conventional semiconductor device has a silicon substrate 1107 and a well line BU embedded in the silicon substrate 1107.
L1 and the well line BUL2, the PZT film 1109 made of a ferroelectric material provided on the well line BUL1 and the well line BUL2, the word line WL1 provided on the PZT film 1109, the word line WL1 and the well Line B
The bit line BL1 is provided above the UL1 and the bit line BL2 is provided above the word line WL1 and the well line BUL2. Further, drains and sources (not shown) are provided in the well lines BUL1 and BUL2, respectively. The bit line BL1 is connected to the drain in the well line BUL1 via a bit contact (not shown), and the bit line BL2. Is connected to the drain in the well line BUL2 via the bit contact.

To write information, a voltage is applied to the word line WL1, the well line BUL1 and the well line BUL2 to PZ.
This is performed by changing the polarization of the T film 1109.

FIG. 50 shows each memory cell of the above-mentioned conventional example.
Voltage VGB applied to the gate electrode (= gate
Electrode potential-well potential) and magnitude of ferroelectric polarization
It is a graph which shows the relationship (hysteresis characteristic) with. strength
Since the dielectric has a hysteresis characteristic, the applied voltage
The polarization state changes depending on the history of the
The polarization state as indicated by 50 points A, B, and C remains.
It Saturation polarization of ferroelectric substance V = V₁After applying the voltage
When the pressure is unloaded, the polarization is in the state of point A, V = V ₂ Voltage
Unload the voltage after applying V = V₁After applying the voltage
-V₂When the voltage is applied and then the voltage is unloaded, the polarization
In the state of point C, V = -V₁Unload the voltage after applying the voltage
Then, the polarization becomes the state of point B.

FIG. 51 is a graph showing the relationship between the drain current I of the memory cell and the gate voltage VGB when the ferroelectric substance is in the state of points A, C and B, corresponding to FIG. In the same figure, the left curve corresponds to the point A, the center curve corresponds to the point C, and the right curve corresponds to the point B. In the state of point A, the ferroelectric substance is highly polarized, so that the threshold voltage VtA of the memory cell is smaller than the threshold voltage VtC in the state of unpolarized point C. Further, in the state of the point B, the ferroelectric substance is highly negatively polarized, so that the threshold voltage VtB of the memory cell is higher than the threshold voltage VtC in the state of the non-polarized point C. . As described above, by changing the ferroelectric substance into the three polarization states shown at the points A, C, and B, the threshold voltage of the memory cell can be controlled to three different types. Accordingly, ternary information can be stored in the memory cell. According to the above-mentioned conventional technology, it is possible to further multivalue by utilizing the polarization state between points A and C.

[0017]

However, the above-mentioned conventional example has a fundamental problem that it is difficult to accurately obtain the polarization state "C". In the prior art, it is stated that when an appropriate voltage is applied to weakly polarize the dielectric and then the voltage is unloaded, the polarization becomes close to zero. However, as is clear from FIG. Voltage Vc
Although it has a characteristic that it greatly changes in the vicinity, the absolute value of -V ₂ is inevitably close to Vc, and therefore its control is extremely difficult, and the value of V ₂ fluctuates slightly due to noise or the like. Therefore, the polarization value after unloading changes greatly. Further, the coercive voltage Vc also changes due to changes in the crystal state and film thickness of the ferroelectric substance in addition to such variations in the write voltage, and as a result, multi-value storage with high reliability and good reproducibility is obtained. It was extremely difficult to obtain stable characteristics. In the present specification, the coercive voltage refers to a voltage required to change the hysteresis of the ferroelectric substance significantly and change the charge distribution of the ferroelectric capacitor.

It is an object of the present invention to provide a semiconductor device which is highly reliable and capable of stably storing information and which can be used as a neuron element of a neuron computer, and a driving method thereof.

[0019]

A first semiconductor device of the present invention comprises a semiconductor substrate, a first upper electrode formed on the semiconductor substrate, a first dielectric layer, and a first lower electrode. And a second capacitor composed of a second upper electrode formed on the semiconductor substrate, a second dielectric layer, and a second lower electrode. In the semiconductor device having a portion and capable of holding information of three or more values, the first dielectric layer and the second dielectric layer have different coercive voltage values in hysteresis characteristics.

As a result, a metastable point is formed in the hysteresis curve of the entire capacitor, and three or more values of information can be stably stored even when the write voltage fluctuates.

During operation, the polarization direction of the first capacitor and the polarization direction of the second capacitor are the same, so that a hysteresis curve due to a difference in coercive voltage between the first capacitor and the second capacitor is displayed. It becomes possible to generate one or more metastable points at. As a result, it becomes possible to stably store information having three or more values.

Further, a transistor having a gate insulating film formed on the semiconductor substrate and a gate electrode made of a conductor film formed on the gate insulating film is further provided, and the first lower electrode and the transistor are provided. Since the second lower electrode is integrated with the gate electrode together, it is possible to reduce the number of manufacturing steps of the semiconductor device capable of stably storing the multivalued information. Manufacturing cost can be suppressed.

Further, the semiconductor device further includes a gate insulating film formed on the semiconductor substrate and a gate electrode formed of a conductive film formed on the gate insulating film, the first lower electrode and the second lower electrode. Since the electrode and the gate electrode are connected to each other, the voltage applied to the capacitor is transmitted to the gate electrode, and the drain current that flows when the gate voltage is applied changes depending on the state of the memory section. It can be stored stably.

In the first half of the process in which the polarization of each of the first capacitor and the second capacitor is from 0 to saturation, the rate of change of the polarization with respect to the change of the voltage is different, so that the hysteresis curve of the entire capacitor is A metastable point can be reliably formed. That is, the storage operation can be stably performed even when the write voltage fluctuates due to noise or the like.

Since both the first dielectric layer and the second dielectric layer have ferroelectric layers,
A remanent polarization after a voltage is applied to a capacitor can have a polarization state corresponding to multivalues, and thus a multivalued storage operation can be performed.

Since the first upper electrode and the second upper electrode are connected to each other, the write voltage can be applied through the same wiring.

Since the first dielectric layer is shared with the second dielectric layer, the storage section is different from the case where the first dielectric layer and the second dielectric layer are formed separately. Area can be reduced and the number of manufacturing steps can be reduced.

The materials of the members constituting the first dielectric layer and the second dielectric layer are the same, and the first dielectric layer is the same.
It may further have a paraelectric capacitor connected in parallel with the above capacitor and the second capacitor.

By further including the capacitor interposed between the second capacitor and the gate electrode, the apparent coercive voltage of the second capacitor can be changed and the degree of freedom in design can be increased. You can raise it further.

The coercive voltage of the capacitor can be changed also by making the areas of the first dielectric layer and the second dielectric layer different from each other.

Since the first dielectric layer and the second dielectric layer are made of different materials,
It is easy to form the first capacitor and the second capacitor so that the coercive voltages are different from each other.

By forming the first dielectric layer and the second dielectric layer to have different film thicknesses, the first capacitor and the second capacitor are formed to have different coercive voltages. be able to.

The value of (area of the first capacitor) / (area of the second capacitor), which is the ratio of the electrode areas of the first capacitor and the second capacitor, is 0. By being 2 or more and 2 or less, when the materials forming the first dielectric layer and the second dielectric layer are the same, the separability of the stored information is high and the ternary information is stably retained. You can

Particularly, the first capacitor and the second capacitor have a mutual electrode area ratio of 0.5 or more and 2 or more.
Due to the following, it is possible to realize a semiconductor device which has high separability of stored information and stably holds information of four or more values.

[0035]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a top view of a multi-valued memory according to the embodiment of the present invention. 2 is a sectional view taken along line II-II in FIG. 1, and FIG. 3 is a sectional view taken along line III-III in FIG. 1, FIG. 2, and FIG. 3, the same reference numerals are given to the same members. In FIG. 1, only the uppermost component is shown by a solid line. Further, in order to make the drawings easy to see, the reference numerals of the portions common to those of FIGS. 2 and 3 are also omitted.

As shown in FIG. 2, the multi-valued memory of the present embodiment has a p-type Si substrate 1 and a LOCOS on the Si substrate 1.
Element isolation film 5 made of silicon oxide formed by the method and a thickness of 3 nm made of silicon oxide formed on the active region of the Si substrate 1 partitioned by the element isolation film 5.
Gate insulating film 7, a gate electrode 9 made of polysilicon containing n-type impurities formed on the gate insulating film, and S
A plug wiring 13c formed on the side of the gate electrode 9 in the i-substrate 1 so as to be in contact with the element isolation film 5 and connecting the drain region 3a and the source region 3b containing n-type impurities, and the drain region 3a and the pad portion 15a. A plug wiring 13d connecting the source region 3b and the pad portion 15b, a first interlayer insulating film 11 filling the plug wiring 13c and the plug wiring 13d, and formed on the first interlayer insulating film 11. First made of 100 nm thick bismuth titanate (BIT)
On the first ferroelectric layer 16, the second ferroelectric layer 18 formed of BIT having a thickness of 400 nm on the first ferroelectric layer 16, and the second ferroelectric layer 18. The formed second interlayer insulating film 21 made of silicon oxide, the wiring 25c formed on the second interlayer insulating film 21, the first ferroelectric layer 16, and the second ferroelectric layer 18 And a wiring 25a that penetrates the second interlayer insulating film 21 and connects the pad portion 15a and the wiring 25c, the first ferroelectric layer 16, the second ferroelectric layer 18, and the second interlayer insulating film. And a wiring 25b penetrating through 21 and connected to the pad portion 15b. In addition,
In this embodiment, the gate length of the gate electrode 9 is 0.5 μm.
m, and the gate width is 5 μm.

Further, as shown in FIG. 3, the multi-valued memory of this embodiment has a p-type Si substrate 1 and a LO on the Si substrate 1.
An element isolation film 5 made of a silicon oxide film formed by the COS method, and a Si substrate 1 partitioned by the element isolation film 5.
A gate insulating film 7 made of silicon oxide and having a thickness of 3 nm formed on the active region, a gate electrode 9 made of polysilicon containing n-type impurities formed on the gate insulating film 7, a gate electrode 9 and A first interlayer insulating film 11 made of silicon oxide formed on the element isolation film 5 and Pt / TiN formed on the first interlayer insulating film 11 and having a size of 0.5 μm × 0.5 μm First intermediate electrode 14 of
a and P formed on the first interlayer insulating film 11 as well.
A second intermediate electrode 14b made of t / TiN and having a size of 0.5 μm × 0.5 μm, and a plug wiring penetrating the first interlayer insulating film 11 and connecting the gate electrode 9 and the first intermediate electrode 14a. 13a, a plug wiring 13b penetrating the first interlayer insulating film 11 and connecting the gate electrode 9 and the second intermediate electrode 14b, the first interlayer insulating film 11, the first intermediate electrode 14a, and the second intermediate electrode 14a. B formed on the intermediate electrode 14b of
First ferroelectric layer 16 made of IT and having a thickness of 100 nm
And the first intermediate electrode 14a on the first ferroelectric layer 16
And a first upper electrode 17 made of Pt / TiN and extending in parallel with each other and having a size of 0.5 μm × 0.5 μm.
And a second ferroelectric layer 18 made of BIT and having a thickness of 400 nm formed on the first ferroelectric layer 16, and a second intermediate electrode 14b on the second ferroelectric layer 18. The size of Pt / TiN that extends in parallel with and faces each other is 0.5μ
a second upper electrode 19 of m × 0.5 μm, a second interlayer insulating film 21 made of silicon oxide formed on the second ferroelectric layer 18, and a second ferroelectric layer 18. It penetrates through the second interlayer insulating film 21 and is connected to the first upper electrode 17, passes through the upper surface of the second interlayer insulating film 21, and then the second interlayer insulating film 21.
Wiring 25c penetrating the interlayer insulating film 21 and connected to the second upper electrode 19.

A ferroelectric capacitor composed of the first ferroelectric layer 16 and the first intermediate electrode 14a and the first upper electrode 17 which sandwich the first ferroelectric layer 16 is referred to as a capacitor MFM1, and the first ferroelectric layer 16 is used. A ferroelectric capacitor composed of the second intermediate electrode 14b and the second upper electrode 19 sandwiching the two layers of the second ferroelectric layer 18 and is called a capacitor MFM2. Further, the capacitors MFM1 and MFM2 are collectively referred to as capacitors MFMs.

FIG. 5 is an equivalent circuit diagram showing the multilevel memory of this embodiment.

As shown in the figure, the multi-valued memory of this embodiment has a structure in which two ferroelectric capacitors are connected in parallel on the gate electrode of a MOS transistor.
In FIG. 5, the thickness of the ferroelectric layer of the capacitor MFM1 is 100 nm, and the size of the electrode is 0.5 μm × 0.
It is 5 μm. The thickness of the ferroelectric layer of the capacitor MFM2 is 500 nm, and the size of the electrode is 0.5 μm × 0.
It is 5 μm.

Next, FIGS. 4A to 4E are cross-sectional views showing the manufacturing process of the multilevel memory of this embodiment. This figure shows a cross section taken along line III-III in FIG. The method of manufacturing the multi-valued memory according to this embodiment will be described below with reference to FIG.

First, in the step shown in FIG. 4A, p-type S
Oxidation is performed on the i substrate 1 by the LOCOS method using silicon nitride (not shown) as a mask to form the element isolation film 5. Then, silicon nitride (not shown) is dissolved with heated phosphoric acid or the like. Then, the Si substrate 1 is thermally oxidized at 900 ° C., for example, to form a silicon oxide film having a thickness of 3 nm on the Si substrate 1, and this is used as the gate insulating film 7. afterwards,
A gate electrode 9 is formed by depositing phosphorus-doped polycrystalline silicon by the LPCVD method. Subsequently, the gate electrode 9 and the gate insulating film 7 are patterned by dry etching, and then boron ions are ion-implanted on both sides of the gate electrode 9 using the gate electrode 9 as a mask, and then heat treatment is performed at 900 ° C. for 30 minutes. By doing
The drain region 3a and the source region 3b shown in FIG. 2 are formed respectively. The MOS transistor manufactured in this step has a gate length of 0.5 μm and a gate width of 5 μm.

Next, in the step shown in FIG.
Silicon oxide (SiO ₂ ) is deposited on the substrate by the D method to form a first interlayer insulating film 11. Next, a contact window is formed by dry etching using a resist mask formed on the first interlayer insulating film 11, and then L
Polysilicon is deposited in the contact window by PCVD. Then, the plug wirings 13a, 13b, 13c and 13 are formed by planarizing the polysilicon by the CMP method.
to form d. Next, after depositing titanium nitride having a thickness of 20 nm on the first interlayer insulating film 11 by a sputtering method,
A 50 nm thick Pt layer is deposited by sputtering. Subsequently, a silicon oxide deposited on the Pt layer is patterned by a sputtering method to form a hard mask (not shown). Using this as a mask, the Pt / TiN layer is patterned by Ar milling to form a first intermediate electrode. 14a, second
Intermediate electrode 14b and pad portions 15a and 15b shown in FIG.
To form. After that, the hard mask made of silicon oxide is removed with diluted hydrofluoric acid or the like.

Next, in the step shown in FIG. 4C, a BIT having a thickness of 100 nm is deposited on the substrate by a sputtering method under the conditions of a substrate temperature of 550 ° C., an oxygen partial pressure of 20%, and an RF power of 100 W. To form the ferroelectric layer 16. After that, a Pt layer is deposited by the sputtering method, and Pt is deposited by Ar milling using a hard mask made of silicon oxide (not shown).
The layer is patterned to form the first upper electrode 17.
After that, the hard mask made of silicon oxide (not shown) is removed with diluted hydrofluoric acid or the like. In this embodiment, the dimensions of the first intermediate electrode 14a and the first upper electrode 17 are 0.5 μm × 0.5 μm.

Next, in the step shown in FIG. 4D, a BIT having a thickness of 400 nm is deposited on the substrate by the sputtering method under the conditions of a substrate temperature of 550 ° C., an oxygen partial pressure of 20%, and an RF power of 100 W. The ferroelectric layer 18 of is formed. Next, after depositing a Pt layer on the second ferroelectric layer 18 by a sputtering method, a hard mask made of silicon oxide (not shown)
Patterning the Pt layer by Ar milling using
The second upper electrode 19 is formed. Then, the hard mask (not shown) is removed with diluted hydrofluoric acid or the like. In addition,
In the present embodiment, the dimensions of the second intermediate electrode 14b and the second upper electrode 19 are 0.5 μm × 0.5 μm.

Next, in the step shown in FIG. 4E, a silicon oxide film is deposited on the substrate by plasma CVD using TEOS, and then planarized by the CMP method to form the second interlayer insulating film 21. Form. Then, the second interlayer insulating film 2 is formed using the resist mask formed on the second interlayer insulating film.
1 is dry-etched to form a contact window reaching the second upper electrode 19. On the other hand, the second interlayer insulating film 2 is formed using the resist mask formed on the second interlayer insulating film.
The first and second ferroelectric layers 18 are dry-etched to form a contact window reaching the first upper electrode 17.
When the etching selection ratio between the upper electrode 19 and the second ferroelectric layer 18 is sufficiently large, the second upper electrode 19
It is also possible to simultaneously form a contact window reaching the first contact electrode and a contact window reaching the first upper electrode 17. Next, after depositing an AlSiCu alloy in the contact window by a sputtering method, the AlSiCu alloy is dry-etched to form wirings 25a, 25b, 25c, respectively.

The multi-valued memory of this embodiment is manufactured by the above method.

FIG. 6 is a diagram showing the voltage-polarization hysteresis characteristic (PV characteristic) of the capacitor MFM1. Note that this shows the hysteresis characteristic when only the capacitor MFM1 is connected to the power supply.

Referring to the figure, since the capacitor MFM1 has a thin film thickness of about 100 nm, the coercive voltage is small, but
The polarization value (residual polarization) at a voltage of 0 V after applying a voltage of about 5 V or more reflects the characteristics of the material called BIT to be 4 μm.
It can be seen that about C / cm ² can be obtained.

On the other hand, FIG. 7 shows the PV of the capacitor MFM2.
It is a figure which shows a characteristic. As shown in FIG.
The ferroelectric material forming the FM2 has the same BIT as that of the capacitor MFM1, but the coercive voltage value is as high as about five times that of the capacitor MFM1 because the film thickness is 500 nm in total. However, since the value of the remanent polarization is peculiar to the material, it is about 4 μC / cm ² which is equivalent to that of the capacitor MFM1.

The driving method and the operation of the multi-valued memory of this embodiment having the structure in which the two ferroelectric capacitors having different hysteresis characteristics are connected in parallel as described above will be described with reference to FIGS. .

FIG. 10 shows the voltage applied between the upper gate electrode and the lower electrode in the multi-valued memory of this embodiment.
It is a figure showing effective polarization of two ferroelectric capacitors. As shown in the figure, since the capacitors used in the multi-valued memory of this embodiment are connected in parallel with each other, the polarization of the entire capacitor is just the capacitor MF.
The average value according to the area ratio of the polarization of M1 and the polarization of the capacitor MFM2 is shown.

FIG. 8 is a diagram for explaining the polarization hysteresis characteristic of the entire capacitor (capacitor MFMs) formed by connecting the capacitors MFM1 and MFM2 in parallel. In the figure, the average value of the polarization of the two capacitors shown by the broken line is the polarization of the capacitor MFMs. That is, the polarization of the capacitor MFMs is as shown in FIG.
The hysteresis characteristic is 0.

In the region x shown in FIG. 8, the capacitor MFM is used.
The polarization of 2 hardly changes with the change of the voltage V.
On the other hand, the polarization of the capacitor MFM1 sharply increases with respect to the change of the voltage V in the first half and becomes small in the latter half.
As a result, the combined value of the two changes sharply in the first half of the region x and becomes gentle in the second half of the region x. Further, in the region y, the polarization of the capacitor MFM2 largely changes with the change of the voltage V, but the polarization of the capacitor MFM1 hardly changes with the change of the voltage V. As a result, the combined value of both changes sharply in the first half of the region y, but changes more gently than when the capacitor MFM2 alone is used.

As described above, the multi-valued memory of this embodiment is
Since it has two ferroelectric capacitors having mutually different coercive voltages, it has a metastable point as shown by point C in FIG. 10, unlike the general hysteresis shape as shown in FIG.
Therefore, when the write voltage is around 4 V, the change in polarization with respect to the voltage change is gradual, and even if the write voltage fluctuates due to noise or the like, the change in polarization can be suppressed to a small level.

In order to obtain this effect, it is necessary that the region where the change in polarization becomes steep with respect to the change in voltage on the hysteresis curve is deviated, so that the coercive voltages of the capacitors must be different from each other. is there. In particular, in the first half process of polarization from 0 to saturation, the metastable point can be reliably obtained by using two dielectric materials having different polarization change rates with respect to voltage changes. Similarly, when three or more capacitors are arranged in parallel, it is necessary that the difference in the coercive voltage of the capacitors be sufficiently different.

FIG. 9 is a diagram showing the P-V characteristic of the capacitor when the capacitor MFM1 and the capacitor MFM2 are additionally added with a capacitor MFM3 having an area equal to these capacitors. The dashed line in the figure shows the PV characteristic of the entire capacitor. Since the coercive voltages of the capacitors are different from each other as in the case of two capacitors, a metastable point F can be further formed in the hysteresis curve. At this time, point C moves to point C '. As a result, at least four or more values can be recorded stably.

Next, a driving method for multivalued operation of the parallel ferroelectric capacitors in this embodiment will be described.

First, the line connecting the points A, S, C, D and P in FIG. 10 represents the polarization of the capacitor when each voltage is applied. When the applied voltage is increased from -8 V, the polarization of the capacitor changes from the state at point A to the points S and C in the direction of the arrow. When a voltage of 8 V is applied, the polarization of the capacitor is saturated, and even if a voltage higher than this is applied, the polarization does not increase at the point D. Then, once the voltage applied to the capacitor is raised to 8V and then lowered, the polarization state of the capacitor goes to the point A through the point P, and returns to the state of the point A at -8V.

Now, the states of the capacitors MFM1 and MFM2 will be described. In the state of point A where a voltage of -8 V is applied to the capacitors, as can be seen from FIGS. 6 and 7, the capacitors MFM1 and MFM are shown.
The polarization of FM2 is saturated with a negative charge. When the voltage applied to the capacitor is unloaded in this state, the applied voltage becomes 0 V, and the state at point S is reached. Since the areas of the capacitors MFM1 and MFM2 are the same, the polarization value of the capacitors MFMs is the same as the capacitors MF shown in FIGS.
It is the average value of M1 and capacitor MFM2 (Fig. 8
reference).

Next, when the applied voltage is raised to about 4 V from the state of the point S, the polarization of the capacitor MFM1 is saturated with positive charge, and the capacitor MFM2 has a positive charge but is not saturated. The polarization of the two capacitors is averaged,
The state becomes point C, which is a metastable point. In addition, in FIG.
A case where a voltage of 3.5 V is applied to the capacitor in consideration of the noise margin and the state becomes the state B is shown. continue,
When the applied voltage is unloaded, the polarization becomes the state Q of approximately 0 μC / cm ² .

Next, when the voltage applied to the capacitor is raised to 8 V, the capacitor is in the state of point D, and at this time, the polarizations of the capacitors MFM1 and MFM2 are both saturated with positive charges. After this, when the voltage is unloaded, the capacitor is at point P.

Next, the voltage applied to the capacitor is -8V.
Then, the capacitor returns to the state of point A.

As described above, the multi-valued memory of this embodiment is
For example, by applying three kinds of write voltages of -8V, 3.5V and 8V, it is possible to perform a stable storage operation against noise and the like.

FIG. 11 is a diagram showing the drain current when the gate voltage which is the read voltage is changed after writing at +8 V, +3.5 V and −8 V in the multi-valued memory of this embodiment.

As shown in the figure, for example, when the read voltage is 2
In the range of up to 3 V, the current values flowing to the drain in each state are different from each other by one digit or more, which shows that the stored information can be stably read.

Next, writing at a point midway in the hysteresis curve where writing is apt to become unstable will be described by taking a case where the writing voltage at a voltage half the saturation voltage fluctuates by 10% as an example.

FIG. 12 is a diagram for explaining how the polarization value fluctuates when the write voltage fluctuates by 10% in the conventional multi-valued memory having a single ferroelectric capacitor. is there.

FIG. 13 is an enlarged view of the portion indicated by A in FIG.

From FIGS. 12 and 13, in the method of the prior art, in order to obtain the polarization state in the middle, there is no choice but to use the portion in which the polarization sharply changes in the hysteresis curve.
For fluctuations of about 10% (see FIG. 13), 1.
Where to expect the polarization value of 7 .mu.C / cm ^2, the polarization value is understood to vary significantly between 1.4~2.0μC / cm ^2.

On the other hand, FIG. 14 is a diagram for explaining the fluctuation of the polarization value when the write voltage fluctuates in the multi-valued memory of this embodiment, as in FIGS. 12 and 13, and FIG.
5 is an enlarged view of the portion B shown in FIG.

It is understood from FIGS. 14 and 15 that the steepness of the polarization change with respect to the fluctuation of the write voltage is significantly improved in the multi-valued memory of this embodiment as compared with the prior art. For example, the original place expect polarization value of -0.15μC / cm ^2, the -0.1~-0.2μC / cm ² degree variation in the polarization value for ± 10% of the voltage fluctuation,
The fluctuation width is less than 0.6 μC / cm ^{2 of the} prior art.
It is significantly improved to 1 μC / cm ² or less. This is because the ferroelectric capacitors are connected in parallel and the mutual coercive voltages are changed, so that a metastable point occurs in the middle of the hysteresis.

These fluctuations in the write voltage (write field strength) can be caused by noise, fluctuations in the film thickness of the ferroelectric layer, fluctuations in the dielectric constant due to the difference in crystallinity of the ferroelectric layer, and the like. However, the fluctuation of the write voltage of about ± 10% can be sufficiently considered under the practical condition.

Therefore, the structure of the multi-valued memory of the present embodiment makes it possible to widen the process margin by suppressing the fluctuation of the polarization value, and is useful in practical device manufacturing.

16 and 17 both show the capacitor MF.
The ferroelectric film thickness of M1 is 100 nm and the capacitor MFM2 is
FIG. 3 is a diagram showing effective polarization values when the respective capacitor area ratios are changed when the ferroelectric film thickness is 1000 nm. 16 (a) to 16 (d) and FIG. 17 (a)
Points (D), (A), (B), and (E) in (d) indicate voltages for writing the positive maximum polarization, the negative maximum polarization, the positive intermediate polarization, and the negative intermediate polarization, respectively, and then unloading the voltage. The polarization values at that time are P, S, and
Q and R.

16A to 16D show the capacitor MF.
It is a figure which shows the effective polarization when the area of M2 is gradually increased with respect to the capacitor MFM1. As shown in the figure, as the area ratio of the capacitor MFM2 increases,
In the region passing the point B and the region passing the point E in the hysteresis curve, the polarization changes sharply with respect to the voltage change.

On the other hand, FIGS. 17A to 17D show the case where the area ratio of the capacitor MFM1 is increased. As shown in the figure, at this time, the change in polarization with respect to the voltage change in the region passing through the point B and the region passing through the point E in the hysteresis curve is gradual. From the above, the capacitors MFM1 and MFM2
As for the area ratio of, the larger the capacitor MFM1, the more the multi-valued memory which is more resistant to the fluctuation of the write voltage can be realized. However, as can be understood from FIG. 17D, when the area of the capacitor MFM1 becomes extremely large, the points P and Q, and the points S and R in the figure come close to each other, making it difficult to determine the data. . Therefore, in this embodiment, the area ratio of the capacitors MFM1 and MFM2 (area of MFM1 / area of MFM2) is 0.5 to 2
By setting the interval between the two, it is possible to realize a stable multi-valued operation with high separability of stored information.

However, when the effective polarization value is 0 μC / cm ² instead of the Q point and the R point, that is, when three types of polarization are used, the capacitor MFM1 and the capacitor MFM are used.
Even if the area ratio of 2 (area of MFM1 / area of MFM2) is approximately 0.2 to 2, good separability of stored information is maintained.

As described above, according to the present embodiment, by connecting two or more ferroelectric capacitors having the same polarization direction but different coercive voltages to the gate electrode of the field effect transistor, it is possible to prevent some fluctuations in the write voltage. It is possible to realize a multi-valued memory with less fluctuation in drain current.

As a result, not only a highly integrated and stable semiconductor memory can be provided, but also a non-volatile transistor providing a plurality of resistance values can be applied to a neuron element which imitates a brain neuron.

Next, FIG. 18 is a sectional view showing a modified example of the multi-valued memory according to the embodiment of the present invention. Since this multi-valued memory has the same structure as the multi-valued memory of the present embodiment shown in FIG. 3 except for the second ferroelectric layer 18, the description of the structure will be omitted.

The multi-valued memory shown here uses a paraelectric material in place of the second ferroelectric layer 18 of the multi-valued memory of this embodiment shown in FIG.

For example, in the modification of this embodiment, the paraelectric layer 20 has a film thickness of 10 formed by the sputtering method.
0 nm tantalum oxide is used. The relative permittivity of the tantalum oxide layer is about 25 in this embodiment. In this case, the capacitance of the paraelectric layer is 1 of the capacitance of the ferroelectric layer.
Since it is about / 4, it is ⅕ of the voltage applied to MFM2.
Will be applied to the ferroelectric layer. For this reason, the apparent coercive voltage becomes five times, so that a metastable point can be provided until the polarization of the entire capacitor is saturated.

In this embodiment, in order to obtain ferroelectric capacitors having different coercive voltages, the thickness of the ferroelectric layer is 100 nm and 500 nm, or 100 nm and 100 nm.
Although it is set to 0 nm, by setting an arbitrary film thickness in addition to this,
The coercive voltage of the capacitor can be changed.

Further, even when the ferroelectrics made of different materials are applied to the respective ferroelectric capacitors, the same effect as changing the film thickness of the ferroelectric layer can be obtained. For example, in the BIT of the present embodiment, the coercive electric field is about 20 kV / cm, but in PZT, the coercive electric field is about 40 kV / cm. Become.

Further, as the multi-valued memory of this embodiment, the case where two ferroelectric capacitors are provided has been described, but the ferroelectric capacitors having different coercive voltages are shown in FIG.
Even if three or more transistors are connected as shown in FIG. 5, the metastable points increase in the hysteresis as well, so that a more multi-valued ferroelectric gate memory can be realized.

In the multivalued memory of this embodiment,
The positive and negative polarities of the capacitor MFM1 and the capacitor MFM2 are the same, but they can be polarized in opposite directions.

(Second Embodiment) FIG. 19 is a sectional view showing the structure of a multilevel memory according to the second embodiment of the present invention. As shown in the figure, the multi-valued memory of this embodiment has p
Type Si substrate 1, an element isolation film (not shown) made of silicon oxide formed on the Si substrate 1, and the Si substrate 1
A gate insulating film made of silicon oxide formed above, a gate electrode / lower electrode 26 made of Pt / TiN formed on the gate insulating film, and a BIT formed on gate electrode / lower electrode 26 A first ferroelectric layer 27 having a thickness of 100 nm, a first upper electrode 29 formed on the first ferroelectric layer 27 and having a width not more than half the width of the gate electrode, The thickness formed on the ferroelectric layer 27 of No. 1 is less than half the width of the gate electrode, and the thickness is 400 nm.
Second ferroelectric layer 28 made of BIT, a second upper electrode 30 formed on the second ferroelectric layer 28, and a gate electrode / lower portion formed on the gate insulating film 7. Electrode 2
6, first ferroelectric layer 27, first upper electrode 29, second
Of the ferroelectric layer 28, the first upper electrode 29, and the second upper electrode 30, and an interlayer insulating film 31 filling the sides of the ferroelectric layer 28, and the first upper electrode 29 and the second upper electrode penetrating the interlayer insulating film. Thirty
And a plug wiring 32 connected to. Here, in the gate electrode / lower electrode 26, the gate electrode is integrated with the lower electrode of the capacitor.

In this embodiment, the first upper electrode 2
9, a capacitor MFM1 including the first ferroelectric 27 and the lower electrode 26 and a second upper electrode 30, a second ferroelectric layer 28, a capacitor MFM2 including the first ferroelectric layer 26 and the lower electrode 26. The coercive voltages of are different from each other.
Therefore, a metastable point is formed in the hysteresis curve of the entire capacitor. Therefore, according to the multi-valued memory of the present embodiment, as in the multi-valued memory of the first embodiment, the stored information is highly separable and stable. It is possible to realize various multi-valued operations.

In the multi-valued memory of this embodiment, since it is not necessary to form the intermediate electrode, the number of manufacturing steps can be reduced and the manufacturing cost can be suppressed as compared with the multi-valued memory of the first embodiment. You can

Even if a paraelectric layer is used instead of the second ferroelectric layer 28 used in this embodiment, the capacitor M
The coercive voltages of the FM1 and the capacitor MFM2 may be formed to be different from each other.

(Third Embodiment) FIG. 20 is a circuit diagram showing a multilevel memory according to the third embodiment of the present invention. As shown in the figure, the multi-valued memory of this embodiment is connected in parallel to one selection transistor Tr1 whose gate is connected to the word line WL and whose drain is connected to the bit line BL, and the source of the selection transistor Tr1. And a capacitor MFM1 having a ferroelectric substance and a capacitor MFM2 having a ferroelectric substance. In the multi-valued memory of this embodiment, the coercive voltages of the capacitors MFM1 and MFM2 are different from each other.

The multi-valued memory of this embodiment is a memory called FeRAM for reading out information by the amount of current flowing when the polarization of the capacitor is inverted. At this time, in the multi-valued memory of this embodiment, as described in the first and second embodiments, a plurality of remanent polarization values can be stably obtained by connecting capacitors having different coercive voltages in parallel. It is possible. In the information read operation of the multi-valued memory according to the present embodiment, for example, a predetermined voltage, for example, 8V is held on the word line WL, and the voltage of the word line WL drops when the selection transistor Tr1 is turned on (conductive). T depending on the degree
Information is read by determining the amount of current flowing through r1. Here, since the amount of polarization reversal differs depending on the remanent polarization state of the ferroelectric capacitor, the amount of current flowing through Tr1 also differs. For example,
A large amount of current (absolute value) is detected in the order of points P, Q, and S in FIG. That is, multi-valued FeRAM
Can be realized.

With this structure as well, similar to the multi-valued memory of the first embodiment, it is possible to realize stable multi-valued operation with high separability of stored information.

(Fourth Embodiment) FIG. 21 is an equivalent circuit diagram showing a multilevel memory according to the fourth embodiment of the present invention. The multi-valued memory according to the present embodiment has a configuration in which a capacitor 40 is inserted between the gate electrode 9 and the capacitor MFM2 of the multi-valued memory according to the first embodiment. That is, the multi-valued memory according to the present embodiment includes a MIS transistor, a capacitor MFM1 and a capacitor MFM2 that are connected in parallel to the gate electrode 9 of the MIS transistor and both have a ferroelectric substance, and the gate electrode 9 and the capacitor M.
And a capacitor 40 provided between FM2. 21, the same members as those in FIG. 5 are designated by the same reference numerals. The areas of the capacitors MFM1 and MIF2 and the thickness of the ferroelectric layer are the same as those in the first embodiment. The capacitor 40 is a capacitor having a paraelectric material, but may be a ferroelectric capacitor.

When a voltage is applied to the multi-valued memory of the first embodiment, the capacitors MFM1 and MFM2
However, in the multi-valued memory of this embodiment, the sum of the voltages distributed to the capacitors MFM2 and 40 is equal to the voltage distributed to the capacitor MFM1.

Therefore, the voltage distributed to the capacitor MFM2 when the same voltage is applied to the multilevel memory is smaller than that of the capacitor MFM2 in the first embodiment, and the apparent coercive voltage is large. . The multi-valued memory according to this embodiment also includes the capacitors MFM1 and MFM.
The two coercive voltages are different and have a metastable point in their hysteresis loop. Therefore, the multi-valued memory of this embodiment can stably hold multi-valued data.

By inserting at least one capacitor between the ferroelectric capacitor and the gate electrode of the MIS transistor, the apparent coercive voltage can be adjusted arbitrarily, so that the degree of freedom in design is increased. be able to. In this embodiment, the capacitor MFM
1 shows an example in which the coercive voltage of the capacitor MFM2 is different from that of the capacitor MFM2.
Since the apparent coercive voltage of 2 changes, it is possible to realize a multi-valued memory that stably holds multi-valued even if the coercive voltages of two capacitors are the same. In addition, the multi-valued memory according to the present embodiment includes the capacitors MFM1 and MFM.
This is advantageous in that two ferroelectric layers can be formed at the same time.

In the present embodiment, the capacitor MFM2
Although an example in which one capacitor is inserted between the gate electrode 9 and the gate electrode 9 of the MIS transistor is shown, two or more capacitors may be inserted.

(Fifth Embodiment) A semiconductor device according to a fifth embodiment of the present invention will be described below with reference to the drawings.

FIG. 22 is an equivalent circuit diagram showing the semiconductor device of this embodiment. As can be seen from the figure, the semiconductor device of this embodiment includes a control voltage supply unit 110, a field effect transistor (hereinafter referred to as a MOS transistor), a gate electrode 109 of the MOS transistor, and a control voltage supply unit 110. It is characterized in that it has a dielectric capacitor 104 and a resistance element 106 which are interposed in parallel with each other.

Next, FIG. 23 is a top view of the semiconductor device of this embodiment, FIG. 24 is a sectional view taken along line XXIV-XXIV of FIG. 23, and FIG. 25 is taken along line XXV-XXV of FIG. A sectional view is shown. In FIG. 23, hatching is omitted for clarity, and only the uppermost component is shown by a solid line. Further, the same portions as those in FIGS. 24 and 25 are also partially omitted for easy understanding of the drawings. Further, also in FIGS. 24 and 25, a part of the components located behind the cut surface is omitted for the sake of easy viewing.

As shown in FIGS. 23, 24, and 25, the semiconductor device of this embodiment is provided, for example, on a P-type Si substrate 101 having an active region and on a surface of the Si substrate 101 facing the active region. The formed substrate electrode 108 (illustrated only in FIG. 22), the element isolation oxide film 105 surrounding the active region provided on the Si substrate 101, and the SiO ₂ provided on the Si substrate 101 with a thickness of 5 nm. Gate insulating film 107
And a gate electrode 109 made of polysilicon containing phosphorus provided on the gate insulating film 107, and the Si substrate 10.
1, the drain region 103a and the source region 103 including N-type impurities provided on both sides of the gate electrode 109.
b, a first interlayer insulating film 111 made of an insulator such as SiO ₂ provided on the Si substrate 101, and titanium nitride (TiN) having a thickness of 20 nm provided on the first interlayer insulating film 111. Film and a pad portion 115a, 115b made of a Pt film having a thickness of 50 nm and the intermediate electrode 114, and a plug wiring made of polysilicon that penetrates the first interlayer insulating film 111 and connects the gate electrode 109 and the intermediate electrode 114. 1
13a and the first interlayer insulating film 111, the drain region 103a, the pad portion 115a, and the source region 103b.
From plug wirings 113b and 113c made of polysilicon for connecting the pad and the pad portion 115b, respectively, and barium strontium titanate (hereinafter referred to as BST) having a thickness of 100 nm provided on the first interlayer insulating film 111. And the upper electrode 119 made of Pt and having a thickness of 50 nm provided on the dielectric layer 116.
A second interlayer insulating film 121 provided on the dielectric layer 116, a wire 125a made of a conductor such as an AlSiCu alloy, which penetrates the second interlayer insulating film 121 and reaches the upper electrode 119, Body layer 116 and second interlayer insulating film 12
Wirings 125b and 125c made of a conductor such as an AlSiCu alloy or the like and penetrating 1 to reach the pad portions 115a and 115b, respectively.

Also, the intermediate electrode 114 and the upper electrode 119.
The dimensions of both are 2.5 μm × 4 μm.
It is the same size as the MOS transistor having the 09.

In the semiconductor device of this embodiment, the dielectric layer 116 and the intermediate electrode 114 and the upper electrode 119 sandwiching the dielectric layer 116 form a capacitor, but the dielectric layer 116 simultaneously forms the resistance element 106 ( (See FIG. 22). The operation of the semiconductor device including this will be described in detail later.

Next, a method of manufacturing the semiconductor device of this embodiment will be described below with reference to FIG.

FIG. 26 is a sectional view taken along line XXV-XXV in FIG. 23, showing the manufacturing process of the semiconductor device of this embodiment.
Structures not shown or not shown in the XXV-XXV cross section of FIG. 26 will be described using the reference numerals used in the description of FIGS.

In the step shown in FIG. 26A, the substrate is oxidized by using a silicon nitride film (not shown) formed on the P-type Si substrate 101 as a mask, and the element isolation oxide film 1 is formed.
05 is formed (LOCOS method). Next, the silicon nitride film is removed by using, for example, heated phosphoric acid, and the substrate is pyrooxidized at 900 ° C.
A SiO ₂ film made of iO ₂ is formed on the Si substrate 101. After that, polysilicon into which an n-type impurity such as phosphorus is introduced is deposited on the SiO ₂ film by the LPCVD method or the like, and then patterned by dry etching to form the gate insulating film 107 and the gate electrode 109. Then, by implanting a p-type impurity such as boron with the gate electrode 109 as a mask and performing a heat treatment at 900 ° C. for 30 minutes, the drain region 103a and the source region 103b are formed on both sides of the gate electrode 109 in the Si substrate 101.
To form. The MOS transistor manufactured by this process has a gate length of 1 μm and a gate width of 10 μm.

Next, in the step shown in FIG. 26B, SiO ₂ is deposited on the substrate by, for example, the LPCVD method to form the first interlayer insulating film 111. Then, a resist mask pattern (not shown) is formed on the first interlayer insulating film 111.
Then, the first interlayer insulating film 111 is dry-etched to form the gate electrode 109 and the drain region 1.
Contact windows reaching 03a and the source region 103b are formed respectively. Next, after depositing polysilicon on the substrate by the LPCVD method or the like, the substrate surface is flattened by the CMP method and the plug wiring 11 for filling each contact window is formed.
3a, 113b, 113c are formed respectively. next,
TiN is deposited on the first interlayer insulating film 111 by the sputtering method.
Is deposited to a thickness of 20 nm, and then Pt is deposited to a thickness of 50 nm by the same sputtering method. Then, S deposited by the sputtering method
Using a hard mask (not shown) formed by patterning the iO ₂ film, Pt / TiN is patterned by Ar milling to form the intermediate electrode 11 on the plug wiring 113a.
4, the pad portion 115a on the plug wiring 113b,
Pad portions 115b are formed on the plug wirings 113c, respectively. After that, the hard mask is removed with diluted hydrofluoric acid or the like.

Here, the TiN layer is formed in order to prevent Pt and polycrystalline silicon from forming silicide to increase resistance.

Next, in the step shown in FIG. 26C, the substrate temperature is 550 ° C., the oxygen partial pressure is 20%, and the RF
BST is deposited on the first interlayer insulating film 111 under the condition of power of 100 W to form a dielectric layer 116 having a thickness of 100 nm. Then, after Pt is deposited on the dielectric layer 116 by the sputtering method, the Pt layer deposited by Ar milling using a hard mask made of SiO _{2 (} not shown) is patterned, and the intermediate electrode 11 is sandwiched with the dielectric layer 116 in between.
The upper electrode 119 is formed at a position opposed to No. 4. After that, the hard mask is removed with diluted hydrofluoric acid or the like.

In this embodiment, the dimensions of the intermediate electrode 114 and the upper electrode 119 are 2.5 μm × 4 μm, and M
The size is the same as that of the OS transistor.

Next, in the step shown in FIG. 26D, TEOS is performed.
After depositing SiO ₂ by plasma CVD using (tetraethoxysilane), the second interlayer insulating film 121 is formed by planarizing by CMP. afterwards,
A contact window is formed by dry etching the second interlayer insulating film 121 and the dielectric layer 116 using a resist mask. Then, AlSi is formed by the sputtering method.
After depositing the Cu alloy on the substrate, dry etching is performed using a resist mask to remove the second interlayer insulating film 121.
Wiring 125a from the top to the upper electrode 119, pad portion 1
A wiring 125b reaching 15a and a wiring 125c reaching the pad portion 115b are formed. Note that the wiring 125a
Is connected to a control voltage supply unit 110 (not shown).

The semiconductor device shown in FIG. 22 is manufactured by the above method.

The semiconductor device of this embodiment has the structure shown by the equivalent circuit shown in FIG.
As shown in FIGS. 3 to 6, the intermediate electrode 114 and the upper electrode 119.
Thus, the dielectric capacitor 104 having the structure in which the dielectric layer 116 is sandwiched also operates as the electric resistance shown in FIG. That is, the dielectric capacitor 10 of FIG.
4 and the resistance element 106 are the same, and the electric resistance is the resistance component of the dielectric capacitor. Therefore, in the semiconductor device of the present embodiment, as compared with the case where the dielectric capacitor 104 and the resistance element 106 are provided separately, FIG.
The structure represented by the equivalent circuit shown in 2 is realized with a simpler configuration.

Next, the driving method and operation of the semiconductor device of this embodiment will be described below.

FIG. 27 shows a dielectric layer 116 made of BST.
FIG. 6 is a diagram showing characteristics of a passing current that passes through the dielectric layer 116 and flows between the intermediate electrode 114 and the upper electrode 119 when a voltage is applied to both electrodes of the dielectric capacitor 104 having a. As shown in the figure, the material BST has a characteristic that the resistance value is substantially constant while the electric field strength is small, so that a passing current value proportional to the voltage can be obtained. However, in FIG. 27, since the vertical axis is the log scale, the graph showing the characteristics is shown as a line-symmetrical curve in the positive and negative voltage ranges across 0V.

The driving method and operation of the semiconductor device of this embodiment having the dielectric layer 116 having such characteristics will be described below.

FIG. 28 is a drain current-applied voltage characteristic diagram for explaining the driving method and operation of the semiconductor device of this embodiment. The horizontal axis of the graph shown in FIG. 28 represents the voltage applied between the Si substrate 101 and the wiring 125a (hereinafter simply referred to as applied voltage), and the vertical axis represents the drain current flowing between the drain region 103a and the source region 103b. Are shown respectively. Note that when measuring the characteristics of the drain current-applied voltage in the semiconductor devices of the following embodiments including this embodiment, the evaluation is performed by applying 1 V between the drain region 103a and the source region 103b. ing.

In the semiconductor device of this embodiment, Si
The gate insulating film 1 is formed by the substrate 101 and the gate electrode 109.
MOS capacitor having a structure sandwiching 07 and the intermediate electrode 1
Since the dielectric capacitor 104 having the structure in which the dielectric layer 116 is sandwiched by the upper electrode 14 and the upper electrode 119 is connected in series, the applied voltage is distributed and applied to each capacitor.

For example, in the measurement of the semiconductor device of the present embodiment shown in FIG. 28, the applied voltage is in the range of -3V to + 3V, but when the maximum voltage of + 3V is applied, the MOS and the dielectric capacitor are respectively applied. Is 2.2V and 0.
8V is distributed respectively. As shown in FIG. 27,
The dielectric capacitor has a very small leak current in the voltage range of −0.8 V or higher and 0.8 V or lower measured here.

As shown in FIG. 28, in the semiconductor device of this embodiment in the initial state, when the semiconductor device is operated at a high speed with a high frequency pulse voltage of, for example, about 1 MHz, points A and O are obtained.
A characteristic of moving on a characteristic curve including (hereinafter, referred to as an A-O curve) is shown.

Although not shown in the A-O curve at about 0 V or less, the drain current in this region was a noise level, which was a current level sufficiently smaller than 10 ^-8 (A). Therefore, for example, when the applied voltage is 3 V, a drain current of about 1 × 10 ⁻³ (A) flows (see FIG. 28).
Point A), and then, when the applied voltage is set to 0 V, the drain current becomes a noise level (point O in FIG. 28). That is, when the semiconductor device of the present embodiment is operated at a high speed of about 1 MHz, the drain current increases in accordance with the applied voltage, and M
The same operation as the OS transistor is shown.

Next, when the state at point A in FIG. 28, that is, the state in which a voltage of +3 V is applied to the upper electrode 119 is maintained, electric charges are gradually accumulated in the intermediate electrode 114 due to the passing current of the dielectric layer 116. In this state, charges are also accumulated in the gate electrode 109 of the MOS transistor connected to the intermediate electrode, the threshold value of the MOS transistor changes, and the applied voltage-drain current characteristic of the semiconductor device also changes.

For example, when the applied voltage of +3 V is held for 100 seconds and then the voltage is applied to the upper electrode 119 at about 1 MHz, the characteristics change so as to draw a curve including points B and C in FIG. That is, it is possible to change the applied voltage-drain current characteristic (hereinafter referred to as VG-ID characteristic) of the MOS transistor by the product of the magnitude of the applied voltage and the holding time.

Since there is a difference of 1 digit or more in the drain current with respect to the applied voltage of + 2V and a difference of 5 digits or more in the drain current with respect to the applied voltage of 0V between the initial state and the state after holding for 100 seconds at + 3V. When the semiconductor device having the above-described structure is used as a memory, multivalued information can be read by detecting a drain current.

As described above, in the semiconductor device of this embodiment, the voltage within the range in which the resistance value of the dielectric capacitor 104 can be considered to be substantially constant is continuously applied to the upper electrode 119 for a long time, and this is used as write information in the initial stage. The drain current with respect to the applied voltage becomes larger than that in the state M
The characteristics of the OS transistor portion can be modulated. On the other hand, although not shown, by holding a negative voltage such as -3V, it is possible to modulate the characteristics of the MOS transistor portion so that the drain current with respect to the applied voltage becomes less likely to flow than in the initial state. .

As described above, according to the semiconductor device of this embodiment, the storage operation can be performed by a driving method which is completely different from that of the conventional semiconductor device functioning as a multi-valued memory.

Further, since the semiconductor device of this embodiment changes its characteristics by reflecting the history of write information up to that time,
It can be applied not only as a multi-valued memory but also as a neuron element.

When applied to a neuron element, a large number of semiconductor devices of this embodiment are connected to each other and wiring 125
A weight signal is applied to a and an output signal from the preceding neuron element is applied to the drain region 103a. At this time, when the voltage applied to the wiring 125a is high and the pulse width thereof is long, current from the semiconductor device easily flows. The application to such a neuron element will be described in detail in later embodiments.

In the semiconductor device of this embodiment,
Hold the applied voltage of + 3V for 100 seconds, and
The characteristic curve of this semiconductor device gradually returns from the BC curve to the AO curve by, for example, grounding the wiring 125a after the state shown by the curve is reached, and the characteristic curve is about 100.
It returns to the characteristic shown by the A-O curve in a second.
This shows an operation reverse to the storage of the written information, and indicates that the information once written has a function of "forgetting" with the passage of time. Since the actual operation of the device is performed at a high speed such as 100 MHz, such a forgetting function is effective when a signal is not input for a long period of time. That is, the forgetting function effectively changes the less frequently used portion when the next learning operation is input, so that the element learning function can be improved.

In the semiconductor device of this embodiment, the amount of charge accumulated in the intermediate electrode 114 and the gate electrode 109 is adjusted depending on the time during which the voltage application is maintained, thereby controlling the ease of drain current flow. However, like the information writing speed, the forgetting speed can be adjusted by controlling the magnitude of the passing current in the voltage range in which the passing current changes in proportion to the voltage.

FIG. 29 shows the correlation between the passing current flowing through the dielectric capacitor 104 and the recovery time in the semiconductor device of this embodiment. Here, the recovery time is the time required from the application of the write voltage until the semiconductor device returns to the initial state (that is, the time until the information is forgotten).

From FIG. 29, it can be seen that within a voltage range where the resistance value of the dielectric layer 116 can be regarded as constant, the recovery time tends to become shorter as the passing current increases. This indicates that the charge accumulated in the intermediate electrode 114 and the gate electrode 109 is leaked as a passing current due to the write voltage.

Here, from the viewpoint of holding stored information, the passing current when a voltage of 1 V is applied across the dielectric capacitor 104 is set to 100 (mA / cm ² ) or less, and the recovery time is set. By setting the holding time to 10 μsec or more, the modulation memory of the transistor is held sufficiently long with respect to the calculation time. It is sufficient that the passing current is sufficiently small with respect to the time for which the data is desired to be retained.

For example, in the semiconductor device of this embodiment, the graph of FIG. 27 shows that the passing current when 1 V is applied is about 10 ⁻⁸ (A / cm ² ), so the holding time is about 100 seconds as shown in FIG. is there.

As described above, the semiconductor device of this embodiment has the MOS
By adopting a configuration in which a dielectric capacitor and an electric resistance element are connected in parallel to the gate electrode of the transistor, it becomes possible to store the history of signals in a normal MOS transistor as a change in applied voltage-drain current characteristics. It is a thing.

In the semiconductor device of this embodiment, the dielectric capacitor 104 and the resistance element 106 are the same, so that the structure is simplified. Thereby, for example, the drain region 103a is used as a bit line and the wiring 125 is used.
If a is connected to a word line and the semiconductor device of this embodiment is used as a memory cell, a multi-valued memory with a small area can be manufactured. Further, even when the semiconductor device of this embodiment is used as a neuron element, there is an advantage that high integration can be achieved.

However, since the information once stored is lost after the recovery time elapses, the dielectric capacitor 10
4 and the resistance element 106 may be separately manufactured, and the resistance element may be made of a material through which a passing current is less likely to flow. This makes it possible to hold information for a longer time.

In the semiconductor device of this embodiment,
Although the case of using BST as the dielectric material has been described, any material that allows current to flow through the film can be substituted. As such a material, strontium titanate,
Titanium oxide, tantalum oxide, aluminum oxide, zirconium oxide, cerium oxide, gadolinium oxide, and lanthanum oxide are particularly effective.

Since the distribution ratio of the voltage applied to the upper electrode 119 between the dielectric capacitor and the MOS transistor is inversely proportional to the capacitance of the capacitor, it is necessary to change the dielectric material.
The voltage distributed to each element can be appropriately changed by changing the electrode area, changing the film thickness of the dielectric layer 116 or the gate insulating film, and the like.

Further, as the material of the gate insulating film of the MOS transistor, SiO ₂ was used in the present embodiment,
For example, another insulator or dielectric such as a silicon nitride film may be used. Further, not only MOS transistors but also field effect transistors can be used in the semiconductor device of this embodiment. This also applies to the subsequent embodiments.

In the semiconductor device of this embodiment, the write time is set to 100 seconds under the condition of the applied voltage of + 3V, but this is an example of the write time, and the charge accumulated in the intermediate electrode is saturated. Not necessarily. The time until the charge is saturated is a little longer, and this time also changes due to the design change of the device as described above. The writing voltage is not limited to + 3V as long as the resistance value of the dielectric layer 116 is within a certain range, but if the voltage is low, the time required for writing becomes longer.

In the semiconductor device of this embodiment, the resistance component of the dielectric layer 116 in the dielectric capacitor 104 is also the resistance element 106.
4 and the resistance element 106 may be provided separately from each other.
In that case, the area becomes large, but appropriate design conditions such as reducing the leak current from the resistance element 106 or shortening the time required for writing by making the constituent materials of the dielectric layer 116 and the resistance element 106 different from each other. It can be adjusted.

In the semiconductor device of this embodiment,
The charge accumulation on the intermediate electrode 114 is proportional to the product of the applied voltage and the applied time. Therefore, when applied to a neuron element, weighting is possible by changing the application time of the maximum voltage. Furthermore, once a signal is input, it is “forgotten” after the recovery time elapses if there is no subsequent input, so that neuron elements that are not used for computation and those that are not used are selected. The efficient calculation can be realized.

(Sixth Embodiment) Next, a sixth embodiment of the present invention will be described with reference to the drawings.

Here, for the same semiconductor device of the fifth embodiment, a driving method different from that of the fifth embodiment will be described as a sixth embodiment. Therefore, only the driving method and operation of the semiconductor device will be described below.

FIG. 30 shows the same semiconductor device as that of the fifth embodiment shown in FIGS. 23 to 25, when a voltage is applied between both electrodes of a dielectric capacitor 104 having a dielectric layer 116 made of BST. FIG. 6 is a diagram showing characteristics of a passing current that passes through a dielectric layer 116 and flows between an intermediate electrode 114 and an upper electrode 119.

Generally, a perovskite type oxide such as BST has a substantially constant resistance value in the range where the electric field strength is small, but when the voltage is further increased, as shown in the characteristic curve of FIG. It has the characteristic that the passing current increases exponentially from around the point where it exceeds. Further, even when the applied voltage is in the negative range, it exhibits substantially symmetrical applied voltage-passing current characteristics across 0V.

This sudden increase in the passing current can be explained as a Schottky current. That is, there is a barrier height at the interface between the intermediate electrode 114 or the upper electrode 119 and the dielectric layer 116, and almost no current flows up to a certain electric field strength. However, when a certain electric field strength is exceeded, a current flows through this barrier. Such a current is called a Schottky current.

Next, a method of driving the semiconductor device of this embodiment using the characteristics of the dielectric capacitor will be described.

FIG. 31 is a drain current-applied voltage characteristic diagram for explaining the driving method and operation of the semiconductor device of this embodiment. Here, the applied voltage refers to a voltage applied between the wiring 125a (or the upper electrode 119) and the substrate electrode 108.

In the semiconductor device of this embodiment, Si
The gate insulating film 10 is formed by the substrate 101 and the gate electrode 109.
Since a MOS capacitor having a structure sandwiching 7 and a dielectric capacitor having a structure sandwiching the dielectric layer 116 by the intermediate electrode 114 and the upper electrode 119 are connected in series, the applied voltage is applied to each capacitor. Will be distributed and applied. For example, when the applied voltage is + 2V, 1.5V and 0.5V are applied to the MOS capacitor and the dielectric capacitor, respectively, and when the applied voltage is + 8V, the MOS capacitor and the dielectric capacitor 104 are respectively 6. 0V and 2.0V are
It is distributed and applied. Note that, from FIG. 30, the dielectric capacitor 104 of the present embodiment, under the voltage of 0.5 V,
Operates as a resistance element with an almost constant resistance value, 2.0V
It can be seen that under the voltage of 1, the current increases exponentially with the increase of the voltage, and operates as a resistance element having a relatively small resistance.

In the method of driving the semiconductor device of this embodiment, the semiconductor device is operated by applying a voltage at, for example, about 50 kHz.

First, in the initial state, the applied voltage is ± 2
Within the range of V, the semiconductor device according to the present embodiment has the structure shown in FIG.
1 shows a characteristic of moving on a characteristic curve including a point D and a point O ′ of 1 (hereinafter referred to as a D-O ′ curve). It should be noted that although the D-O 'curve does not show approximately 0 V or less, the drain current in this region is a noise level and is 10 ^-8 (A).
It was a sufficiently smaller current level.

Here, for example, when 2 V is applied, about 6 × 1
A drain current of 0 ^-4 flows (point D), and when 0 V is applied thereafter, the state returns to the state of point O where only a noise level current flows. Even if a voltage of 2 V or less is applied and then 0 V is applied, the drain current is almost at the noise level. That is, the semiconductor device of the present embodiment exhibits the same operation as that of the MOS transistor for the applied voltage of −2V to + 2V.

Next, when a high voltage of, for example, +8 V is applied, the passing current flowing through the dielectric layer 116 exponentially increases, so that charges are accumulated in the intermediate electrode 114 and the gate electrode 109 in a very short time. To be done. In this embodiment,
The operation is performed by setting the frequency of the applied pulse voltage to 50 kHz, but by applying a pulse voltage of, for example, +8 V and 20 μsec, the characteristics can be changed to a curve including points E and F in FIG. Is. That is, it is possible to change the VG-ID characteristics of the MOS transistor in a short time by increasing the applied voltage.
The time required for charge accumulation was 100 seconds in the driving method of the fifth embodiment, but it was 2 seconds in the driving method of the present embodiment.
It is greatly shortened to 0 μsec.

Now, the operation of the semiconductor device of this embodiment will be described in more detail. When a voltage pulse of + 8V is applied, the passing current flowing through the dielectric layer 116 exponentially increases, so that charges are rapidly accumulated in the intermediate electrode 114 and the gate electrode 109.

After that, when the applied voltage is returned to 0 V, FIG.
The characteristic changes to the position of point F, and the drain current changes. Next, when a voltage of +2 V is further applied to the upper electrode 119 from the state of the point F, the state of the point E is reached and the voltage becomes about 3 × 10 5.
^-3 (A) drain current flows, but apply voltage again to 0
When returning to V, the state of point F is restored. That is, the drain current-applied voltage characteristic of the semiconductor device does not change even if a low voltage pulse of about 0 to 2 V is applied after inputting a large voltage pulse. On the other hand, when a −2V negative voltage pulse is applied to the upper electrode 119 in the state of the point F, the state of the semiconductor device moves to the point G, and the drain current decreases by about one digit. After that, when the applied voltage is set to 0 V again, the state at the point H close to the point F is obtained, and the drain current is slightly smaller than that at the point F, but no large change in the drain current is observed.

According to the same principle, for example, the applied voltage is -8
It goes without saying that when V is applied, the drain current changes to an extremely small change in the scan of ± 2V.

As described above, in the method of driving the semiconductor device of this embodiment, information is written in the voltage range in which the passing current flowing through the dielectric capacitor 104 exponentially increases with respect to the increase of the applied voltage, When reading information, etc., within the voltage range where the passing current is almost proportional to the applied voltage,
It drives the OS transistor. By this method, the information writing time can be significantly shortened as compared with the semiconductor device driving method shown in the fifth embodiment.

According to the method of driving the semiconductor device of this embodiment, the history of writing information up to that time can be stored in the form of a change in element characteristics. Therefore, the semiconductor device of this embodiment is simply applied as a multi-valued memory. Instead, it can be applied as a neuron element. When it is used as a neuron element, the writing time of information can be significantly shortened as compared with the method of the fifth embodiment, so that the calculation speed can be greatly improved.

The semiconductor device driving method of this embodiment differs from that of the fifth embodiment in that the VG-ID characteristics of the MOS transistor are changed not by the length of the applied voltage pulse but by the magnitude of the absolute value of the applied voltage. The feature is that it can be done. That is, it is possible to modulate the VG-ID characteristic only by setting the input voltage pulse to be a constant cycle and setting the voltage value of the pulse.

In the method for driving the semiconductor device of this embodiment, the write voltage is set to 8V, but writing may be performed at a higher voltage. Further, even if the voltage applied to the wiring 125a or the upper electrode 119 is, for example, 8 V or less, the capacitance is reduced by a method such as reducing the area of the dielectric capacitor or increasing the thickness of the dielectric layer. The write time can be shortened by increasing the voltage distributed to the capacitor.

Also in the semiconductor device driving method of this embodiment, the state of the semiconductor device returns to the initial state shown by the D-O 'curve in FIG. 31 with the passage of time by grounding the wiring 125a, for example. That is, the semiconductor device of this embodiment also has a function of "forgetting" as described in the fifth embodiment.

In the method of driving the semiconductor device of this embodiment, from the viewpoint of retaining stored information, the passing current when a voltage of 1 V is applied across the dielectric capacitor 104 is 100 (mA / cm ² ). By setting as below and setting the recovery time to 10 μsec or more, the difference from the voltage pulse having a large absolute value is made clear. Since this is the same condition as the driving method of the fifth embodiment, in the present embodiment, the time required for the recovery is about 100 seconds.

(Seventh Embodiment) The semiconductor device according to the seventh embodiment of the present invention is different from the semiconductor device according to the sixth embodiment only in part of the structure and its driving method and operation. .

FIG. 32 is an equivalent circuit diagram showing the semiconductor device of this embodiment. As shown in the figure, the semiconductor device of this embodiment has a structure in which a ferroelectric capacitor 104a and a resistance element 106 are connected in parallel to a gate electrode 109 of a field effect transistor (hereinafter referred to as a MOS transistor). Is characterized by.

The semiconductor device of this embodiment has the fifth and sixth structures.
Although the structure is almost the same as that of the semiconductor device of the above embodiment, the semiconductor device of this embodiment uses the ferroelectric layer 131 made of a ferroelectric material instead of the dielectric layer 116. Of the embodiment of FIG.

That is, in the semiconductor device of this embodiment, the control voltage supply unit 110, the MOS transistor having the gate electrode 109, the drain region 103a, the source region 103b, and the substrate electrode 108, the gate electrode 109 of the MOS transistor, and the control transistor. It has a ferroelectric capacitor 104a and a resistance element 106 that are provided in parallel with each other with the voltage supply unit 110. Further, the ferroelectric capacitor 104 a has an upper electrode 119, an intermediate electrode 114, and a thickness of 300 between the upper electrode 119 and the intermediate electrode 114.
nm ferroelectric layer 131 made of bismuth titanate (BIT). Further, in the semiconductor device of this embodiment, the ferroelectric layer 131 also functions as the resistance element 106. The source region 103b and the substrate electrode 108 are connected to each other.

Next, FIGS. 33A to 33D are sectional views showing the manufacturing steps of the semiconductor device of this embodiment. In the figure, the same parts as those in FIG. 26 are designated by the same reference numerals.

First, in the step shown in FIG. 33A, the element isolation oxide film 105 is formed on the Si substrate 101 by the LOCOS method in the same procedure as in the fifth embodiment. Then
5 nm thick SiO ₂ on the substrate by pyrooxidation of the substrate
After forming the film, the polysilicon containing the n-type impurities is changed to Si.
The gate insulating film 107 and the gate electrode 109 are formed on the Si substrate 101 by depositing on the O ₂ film and patterning the SiO ₂ film and the polysilicon layer. Then, a p-type impurity such as boron is implanted to form the drain region 103a and the source region 103b on both sides of the gate electrode 109 in the Si substrate 101. In addition,
The MOS transistor manufactured by this step has a gate length of 1 μm and a gate width of 10 μm.

Next, in the step shown in FIG. 33B, the first step of forming SiO ₂ on the substrate is carried out in the same procedure as in the fifth embodiment.
After forming the inter-layer insulation film 111, a contact window is formed by dry etching using a resist mask, and the contact window is filled with polysilicon to form plug wirings 113a, 113b, 113c made of polysilicon.
Are formed respectively. Next, the intermediate electrode 114 connected to the gate electrode 109 via the plug wiring 113a, the pad portion 115a connected to the drain region 103a via the plug wiring 113b, and the plug wiring 15b connected to the source region 103b via the plug wiring 113c are formed. Form each. The material of each member is the same as that of the fifth embodiment, but the size of the intermediate electrode is 1 μm × 2 μm, and its area is 1/5 of the area of the MOS transistor.

Next, in the step shown in FIG. 33C, BIT is deposited by a sputtering method under the conditions of a substrate temperature of 600 ° C., an oxygen partial pressure of 20% and an RF power of 100 W, and a ferroelectric layer 131 having a thickness of 300 nm is formed. Are formed on the substrate. After that, the upper electrode 119 is formed on the ferroelectric layer 131 at a position facing the intermediate electrode by the same procedure as in the fifth embodiment. The size of the upper electrode 119 is 1 μm which is the same as that of the intermediate electrode 114.
m × 2 μm, 1/5 of the area of MOS transistor
And

Then, in the step shown in FIG. 33D, the second interlayer insulating film 121 is formed on the ferroelectric layer 131 by the same procedure as in the semiconductor device of the first embodiment. Next, the wiring 12 from the second interlayer insulating film 121 to the upper electrode 119
5a and the pad portion 115 from above the second interlayer insulating film 121.
a and wirings 125b and 125c reaching the pad portion 115b
Are formed respectively.

The semiconductor device of this embodiment manufactured by the above manufacturing method is the ferroelectric capacitor 1 shown in FIG.
04a and the resistance element 106 are the same thing, and the resistance element 106 is a resistance component of the ferroelectric capacitor 104a.

As a result, the structure shown in FIG. 32 can be realized in a relatively small area, and the ferroelectric capacitor 1
The number of manufacturing steps is smaller than that in the case of separately manufacturing 04a and the resistance element 106.

Next, the driving method and operation of the semiconductor device of this embodiment will be described below.

FIG. 34 (a) shows an equivalent circuit at the time of coarse adjustment in which the stored information is significantly changed in the semiconductor device of this embodiment, and FIG. 34 (b) shows an equivalent circuit at the time of fine adjustment in which the stored information is finely changed. Shows. Further, FIG. 35 is a diagram showing characteristics of a passing current when a voltage is applied to both ends of the ferroelectric capacitor 104a. Here, the passing current refers to a current that passes through the ferroelectric layer 131 and flows between the intermediate electrode 114 and the upper electrode 119.

In the present embodiment, the composition of the elements including BIT used as the ferroelectric material is ABO ₃
The oxide having a perovskite structure represented by the following is similar to BST used in the first and sixth embodiments, and has a resistance value that is negligible while the applied electric field strength is small, When the voltage is further increased, the passing current increases exponentially. From FIG. 35, also in the ferroelectric capacitor 104a of the present embodiment,
When a voltage higher than around 1.8 V is applied, the passing current increases exponentially. Further, when a negative voltage is applied, a symmetrical characteristic is shown across the axis of the applied voltage of 0V.

Therefore, as shown in FIG. 35, when the voltage distributed to the ferroelectric substance is within the voltage range of -2.3 V or less and +2.3 V or more during the rough adjustment time, the ferroelectric substance becomes the resistance element 1.
It also functions as 06, and the leak current I flows. The equivalent circuit at this time is, as shown in FIG. 34A, the ferroelectric capacitor 104 on the gate electrode 109 of the MOS transistor.
In this configuration, a and the resistance element 106 are connected in parallel.

On the other hand, the voltage distributed to the ferroelectric is -1.
In the fine adjustment voltage range of about 4 to +1.4 V, almost no current flows through the ferroelectric substance, and the ferroelectric substance is almost an insulator. The equivalent circuit at this time has a form in which only the ferroelectric capacitor 104a is connected to the gate electrode 109 of the MOS transistor, as shown in FIG.

In the semiconductor device of this embodiment, the MOS capacitor having a structure in which the gate insulating film 107 is sandwiched between the Si substrate 101 and the gate electrode 109, and the ferroelectric layer 131 is sandwiched between the intermediate electrode 114 and the upper electrode 119. Since the ferroelectric capacitor 104a having the recessed structure is connected in series, the applied voltage is distributed and applied to each capacitor. For example, in the semiconductor device of this embodiment, the applied voltage is +2
When V is applied to the entire device, 1.2V and 0.8V are applied to the MOS transistor and the ferroelectric capacitor 104a, respectively.
3.6V and 2.4V are distributed to the transistor and the ferroelectric capacitor 104a, respectively.

In the semiconductor device of this embodiment, the leak current can be increased and the potential of the floating gate can be greatly changed by setting the voltage distributed to the ferroelectric capacitor 104a within the voltage range during coarse adjustment. . Further, by setting the voltage distributed to the ferroelectric capacitor 104a in the fine adjustment voltage range, the leak current is reduced,
Data can be retained and the floating gate potential can be finely adjusted by changing the polarization of the ferroelectric substance.

FIG. 36 is a diagram showing an example of an actual voltage applying method based on the above findings. In this example, first, a voltage pulse of 2.5 V is applied to the ferroelectric in the period of 1 μsec. As a result, it is rapidly accumulated in the floating gate through the ferroelectric substance. At this time, the polarization of the ferroelectric substance is aligned in one direction.

Next, after 5 μsec, the period is 1 μse.
At c, a negative minute voltage is applied to the ferroelectric. At this time, the leak current from the ferroelectric substance is so small that it can be ignored, and the polarization of the ferroelectric substance is gradually inverted. As a result, the charge amount of the floating gate can be changed by a small amount.

In a general ferroelectric gate transistor, the charge amount of the floating electrode (gate electrode 109) can be changed only by the polarization value of the ferroelectric substance, but by using the driving method of this embodiment, it is very wide. The charge amount can be changed within the range. That is, the on-resistance value of the MOS transistor can be determined in a very wide range and in detail. This means that it functions as an analog memory capable of continuously holding multivalued information in accordance with the amount of charge accumulated in the floating electrode.

FIG. 37 is a characteristic diagram for explaining the operation of the semiconductor device of this embodiment in the initial state. In the figure, the horizontal axis represents the applied voltage and the vertical axis represents the drain current. The applied voltage here means a voltage applied between the wiring 125a (or the upper electrode 119) and the Si substrate 101.

As shown in FIG. 37, when a voltage is applied to the semiconductor device of this embodiment in the initial state within a range of ± 2 V, the VG-ID characteristic of the MOS transistor in the device causes counterclockwise hysteresis. It operates as a so-called ferroelectric gate transistor.

Therefore, for example, even if the applied voltage is unloaded after the + 2V voltage is applied to the semiconductor device, the ferroelectric layer 1
The polarization of 31 induces charges in the intermediate electrode 114 to generate a potential. Therefore, even if the applied voltage is 0 V, about 2 μA
Drain current flows. On the other hand, conversely, if the applied voltage is unloaded after applying -2 V, the drain current will be extremely small this time (10 ^-8 A or less, not shown).
Here, the voltage between the source and the drain is 1V as in the fifth embodiment.

Next, when +6 V is applied to the semiconductor device of this embodiment, it becomes possible to set a different drain current value.

FIG. 38 is a diagram showing a drain current when a voltage pulse of 2 V is repeatedly applied and unloaded to the semiconductor device of this embodiment after applying +6 V as a write voltage. The voltage pulse interval at this time is 20 μsec.

As shown in the figure, the present embodiment in the initial state
+ 6V is applied as a write voltage to the semiconductor device of the embodiment
Then, the voltage of 2.4V is distributed to the ferroelectric capacitor.
Therefore, the passing current increases exponentially and the charge is
By being accumulated in the pole 114 and the gate electrode 109,
Therefore, the drain current increases by more than two digits from the initial state. It
After that, even if the same + 2V voltage pulse is input,
Rain current is about 1 x 10 ^-3Almost no change from (A)
Shows the characteristics.

From this, it is understood that the semiconductor device of this embodiment can stably hold data by applying a high voltage write voltage.

Next, in FIG. 39, after applying +6 V,
FIG. 9 is a characteristic diagram of applied voltage-drain current in the semiconductor device of the present embodiment when the applied voltage is scanned in the range of 2V.

First, when a voltage of +6 V is applied to this semiconductor device and then the load is removed, the drain current has a value shown by point I in FIG.

Then, in this point I, the semiconductor device is
When a voltage of V is applied and the voltage is unloaded, the drain current follows the locus shown from point I to point J in FIG.
After unloading, the state returns to point I again. The state at point I corresponds to the state in which the voltage pulse shown in FIG. 38 is applied.

When a voltage of -2 V is applied to the semiconductor device in the state of point I, the state shown in point K is reached, and the drain current is reduced to 1 × 10 ^-5 (A) or less, which is about two digits. Then, when the voltage is unloaded, the state moves to the state of point L, and the drain current decreases by about one digit as compared with the state of point I before voltage application.

In the semiconductor device of the sixth embodiment, FIG.
There is no significant difference in the drain currents at points F and H, and this is the point that the semiconductor device of this embodiment is significantly different from the semiconductor devices of the fifth and sixth embodiments.

As a result, the semiconductor device of this embodiment can hold much more data than the semiconductor devices of the fifth and sixth embodiments.

Next, when + 2V is applied to the semiconductor device in the state of point L in FIG. 39, the semiconductor device moves to the state of point M, and thereafter,
When the voltage is unloaded, the state shown at point N is reached. At this time, the drain current changes along a locus indicated by point L → point M → point N, and in the state of point N, a larger drain current than in the state of point L is obtained. In this way, it is possible to further modulate the drain current by a scan of a small applied voltage of ± 2V after a high applied voltage of + 6V.

On the other hand, a large negative voltage pulse can be input as the write voltage.

FIG. 40 is a diagram showing the drain current when a voltage of -6V is applied to the semiconductor device of this embodiment and then a voltage pulse of + 2V is applied to unload it. The pulse interval of the voltage pulse is 20 μsec.

From the figure, it can be seen that by applying a voltage of -6V to the semiconductor device of this embodiment in the initial state, the drain current at 0V becomes four orders of magnitude lower than that in the initial state. Also in this case, the change in drain current when the application of the voltage pulse of +2 V and the unloading are repeated is small.

Next, FIG. 41 is a diagram showing applied voltage-drain current characteristics of the semiconductor device of the present embodiment when the applied voltage is scanned within a range of ± 2 V after the input of a voltage pulse of -6 V. Although hysteresis is observed even in this state, the drain current in the 0 V applied state is maintained at an extremely low value regardless of which polarity voltage is applied. Thus, by applying a negative voltage, a small drain current that can be distinguished from the case of applying a positive voltage can be obtained.

As described above, in the semiconductor device of this embodiment, when the MOS transistor is driven in the voltage range (low voltage range) where the resistance value of the resistance component of the ferroelectric capacitor 104a is substantially constant, It is possible to selectively use the case where writing is performed within a range in which the passing current exponentially increases by switching the applied voltage.

In the semiconductor device of this embodiment, the change in the applied voltage-drain current characteristic is caused by the accumulation of the charges passing through the ferroelectric layer 131 in the intermediate electrode 114.
Electric charges are also accumulated in the gate electrode 109 of the OS transistor, which is caused by a change in the VG-ID characteristic of the MOS transistor. Particularly, in the semiconductor device of this embodiment,
Since it is possible to change the charge storage amount of the intermediate electrode and the gate electrode 109 depending on the polarization direction of the ferroelectric capacitor 104a, it takes an extremely large value compared with the semiconductor devices of the fifth and sixth embodiments. Can be used as a multi-valued memory to obtain

Further, since the large modulation of the drain current by the large voltage pulse and the small modulation of the drain current by the small voltage pulse can be reflected as the modulation of the drain current, respectively, the neuron element with extremely high degree of freedom of weighting can be obtained. Can also be applied.

In the semiconductor device of this embodiment as well, similar to the semiconductor devices of the fifth and sixth embodiments, the characteristic of restoring the characteristic to the initial state by grounding the wiring 125a, etc., and "forgetting" Have.

In the semiconductor device of this embodiment,
From the perspective of retaining stored information,
When a voltage of 1 V is applied to the end, the passing current is 100 (mA
/ Cm ² ) The recovery time is 10 μse
By setting c or more, the drain charge due to polarization of the ferroelectric substance
The difference with the pressure modulation is made clear. this
Is almost the same as the semiconductor device of the fifth embodiment shown in FIG.
It is the same tendency, and the time required for recovery is about 100 seconds.
Has become.

Further, similarly to the semiconductor device of the fifth embodiment, the ferroelectric layer 1 is also applied to the semiconductor device of the present embodiment.
31 and the resistance element 106 may be provided separately. In that case, for example, in order to extend the time for holding information, the ferroelectric material forming the resistance element 106 is changed to the ferroelectric layer 13.
It can be appropriately designed in accordance with the required conditions, such as making it harder for current to pass than the ferroelectric material constituting No. 1.

In addition, the ferroelectric layer 131 and the resistance element 106
When they are provided separately, a dielectric may be used as the material forming the resistance element 106.

In the semiconductor device driving method of this embodiment, the voltage region in which the resistance value of the ferroelectric layer is substantially constant and the voltage region in which the passing current exponentially increases with respect to the voltage are used separately. Although the method has been described, as in the fifth embodiment, the semiconductor device is driven only in the voltage region in which the resistance value of the ferroelectric layer is so small that it can be ignored, and the pulse width of the applied voltage is set to be longer than the recovery time. By setting it sufficiently short, it is possible to similarly change the amount of charge accumulated in the intermediate electrode 114 and the gate electrode 109.

Although BIT was used as the material of the ferroelectric layer in the semiconductor device of this embodiment, lead titanate, lead zirconate titanate, and other materials exhibiting ferroelectricity are also used. Any material such as strontium tantalate can be used as the material of the ferroelectric layer.

(Eighth Embodiment) In a semiconductor device according to an eighth embodiment of the present invention, the resistance element 106 in the seventh embodiment is replaced with a resistance element 150 which is a varistor made of zinc oxide (ZnO). It has been replaced. However, the resistance element 150 is provided separately from the ferroelectric substance.

FIG. 42A is a circuit diagram showing the semiconductor device of this embodiment, and FIG. 42B is a diagram showing the varistor characteristic of the resistance element 150. The same members as those in FIG. 32 are designated by the same reference numerals.

As shown in FIG. 42 (b), ZnO, etc.
Some metal oxides have a property that the resistance value greatly changes depending on the applied voltage. In the case of the resistance element 150 of the present embodiment having an electrode area of 10 μm ^2, a resistance value of about 180 GΩ is exhibited in the voltage range of −1 V or more and +1 V or less, but when the absolute value of the voltage exceeds 1.5 V, the resistance value drastically decreases. To do.

From this, for example, -2V or less and 2V
By operating the above voltage range as the coarse adjustment voltage and operating the range of -1V to + 1V as the fine adjustment voltage, the same operation as that of the semiconductor device of the seventh embodiment becomes possible.

In addition, in the semiconductor device of this embodiment, the material of the resistance element 150 can be arbitrarily selected, so that the range of operating voltage can be freely set. For example, the resistance element 150 is applied at a voltage at which the polarization of the ferroelectric substance is saturated.
By setting the low resistance voltage of 1 to a little higher voltage, it is possible to execute the rough adjustment and fine adjustment operations with a lower drive voltage.

Next, FIG. 43 is a sectional view showing the structure of the semiconductor device of this embodiment.

As shown in the figure, the ferroelectric substance 131 and the resistance element 150 of this embodiment may be provided with the upper electrode and the lower electrode in common. Such a structure can be easily realized by using a known technique. For example, after depositing a ferroelectric substance on the entire surface of the lower electrode, a part of the ferroelectric substance is selectively etched, and ZnO is deposited on the lower electrode portion where the ferroelectric substance is removed. Although the example in which the ferroelectric and the resistance element are provided in contact with each other has been shown here, they may be provided separately from each other.

Incidentally, as the material for forming the resistance element,
In addition to ZnO, perovskite type oxides such as Ba _x Sr ₁ -x TiO ₃ , TiO ₂ -based oxides, Fe ₂ O ₃ -based oxides, C
A u ₂ O-based oxide or the like can be used. Further, in order to reduce the resistance of these metal oxides, it is possible to add Bi ₂ O ₃ or a rare earth element to the above metal oxides. Thereby, the resistivity and the rate of resistance change of the metal oxide material can be adjusted appropriately. Further, a PN junction of Si, a system in which Al is added to a SiC semiconductor, Se, or the like can also be used as the material of the resistance element.

In the semiconductor device of this embodiment, the multi-valued information is controlled so as to be favorably retained by properly using the rough adjustment time and the fine adjustment time. However, the element provided in parallel with the ferroelectric substance is a resistor. Not limited to the element, any element or circuit capable of changing the charge injected into the floating gate by the applied voltage may be used.

(Ninth Embodiment) In a semiconductor device according to a ninth embodiment of the present invention, the resistance elements 106 of the seventh embodiment are connected in parallel to each other and arranged in opposite directions to each other. It is replaced with two diodes.

FIG. 44 is a circuit diagram showing the semiconductor device of this embodiment. The same members as those in FIG. 32 are designated by the same reference numerals.

As shown in the figure, in the semiconductor device of this embodiment, the ferroelectric capacitors 104 connected to the control voltage supply section 110, the MOS transistor, and the gate electrode 109 of the MOS transistor and provided in parallel with each other.
a, a diode 152, and a diode 154. Further, the diode 152 and the diode 154 are arranged in directions opposite to each other. That is, the diode 152 and the diode 154 are connected to the input section and the output section, respectively.

In this embodiment, the diodes 152 and 154 are, for example, PN diodes or the like. A current flows through these diodes when a forward voltage higher than a predetermined value is applied, and almost no current flows when a current below a predetermined value is applied. Further, within the withstand voltage range, almost no current flows even if a reverse current is applied.

As shown in FIG. 44, by connecting two diodes opposite to each other in parallel, when the threshold voltage of the diode is tV, the voltage applied to the diode is between -tV and + tV. If so, almost no current flows, and when the absolute value of the voltage exceeds tV, current flows and charges flow into the floating gate.

Therefore, as in the third and eighth embodiments, the case where the absolute value of the distributed voltage is large is set as the coarse adjustment, and the case where the absolute value of the distributed voltage is small is set as the fine adjustment. Data can be stored.

In the semiconductor device of this embodiment, PN diodes are used as the diodes 152 and 154, but other diodes such as Schottky diodes may be used.

(Tenth Embodiment) In a semiconductor device according to a tenth embodiment of the present invention, the resistance element 106 in the seventh embodiment is replaced with a MIS transistor whose on / off is controlled by a control voltage Vr. It is a thing.

FIG. 45 is a circuit diagram showing the semiconductor device of this embodiment.

As shown in the figure, the semiconductor device according to the present embodiment has a control voltage supply unit 110, a MOS transistor, a ferroelectric capacitor 104a connected to the gate electrode 109 of the MOS transistor, and a control voltage supply unit. 11
0 and the MIS transistor 156 provided between the gate electrode 109. The MIS transistor 156 is controlled by the control signal Vr.

According to the semiconductor device of the present embodiment, by appropriately controlling the on / off of the MIS transistor by an external control circuit or the like, the floating gate potential as described in the third to fifth embodiments can be obtained. Coarse and fine adjustments are possible. For example, when the absolute value of the voltage applied to the MIS transistor is equal to or larger than a predetermined value, the MIS transistor is turned on, and when the absolute value of the voltage applied to the MIS transistor is equal to or less than the set value, it is controlled to be off.

According to the semiconductor device of this embodiment, the MIS
Regardless of the structure of the transistor, it is possible to switch between the rough adjustment and the fine adjustment by appropriately changing the control voltage Vr, and thus it is possible to operate in an arbitrary voltage range.

In the semiconductor device of this embodiment,
A bipolar transistor can be used instead of the MIS transistor 156.

(Eleventh Embodiment) A semiconductor device according to an eleventh embodiment of the present invention is the resistance variable element 158 whose crystallinity is controlled by the resistance control signal Vw in the resistance element 106 of the seventh embodiment. Is replaced with.

FIG. 46 is a circuit diagram showing the semiconductor device of this embodiment.

As shown in the figure, in the semiconductor device of this embodiment, the ferroelectric capacitor provided between the control voltage supply unit 110, the MOS transistor, and the control voltage supply unit 110 and the gate electrode 109 of the MOS transistor. Body capacitor 1
04a, a resistance change element 158 provided between the control voltage supply unit 110 and the gate electrode 109 of the MOS transistor in parallel with the ferroelectric capacitor 104a. The resistance change element 158 is made of, for example, germanium (Ge), tellurium (Te), antimony (S).
It is composed of an alloy whose main component is the three elements of b),
Its crystallinity is controlled by the resistance control signal Vw.

The resistance change element 158 becomes amorphous when Vw is a high voltage pulse equal to or higher than the set value, and the resistance value becomes large. After that, by decreasing the Vw pulse, the resistance value can be gradually decreased and adjusted to an arbitrary value. Therefore, when it is desired to accumulate charges in the floating gate, the Vw pulse is set to a low voltage and the voltage is supplied from the control voltage supply unit 110 in that state. Next, when the potential of the floating gate is finely adjusted or the data is held, the Vw pulse is set to a high voltage and a voltage in the fine adjustment voltage range shown in FIG. 35 is applied to the ferroelectric capacitor 104a. As a result, both the leak current from the ferroelectric substance and the leak current from the resistance change element can be reduced.
As described above, even by using the resistance change element, it is possible to realize a semiconductor device that can favorably hold multi-valued information.

A chalcogenide material other than Ge, Te, and Sb is preferably used as the material of the resistance change element 158 of this embodiment.

(Twelfth Embodiment) As a twelfth embodiment of the present invention, a neuron computer using the semiconductor device of the seventh embodiment as a neuron element will be described.

FIG. 48 is a diagram showing a model of the basic structure of the brain of a living organism. As shown in the same figure, the brain of an organism is a neuron 141a in the front stage and a neuron 141 in the rear stage, which are nerve cells having an arithmetic function.
b, 141c, nerve fibers 142a, 142b, 142c for transmitting the calculation result from the neuron, and synaptic connections 143a, 143b, 143c for weighting the signal transmitted by the nerve fiber and inputting to the neuron. There is.

For example, the signals transmitted by a large number of nerve fibers including the nerve fiber 142a are transmitted through the synapse connection 143a.
Weights such as Wa, Wb, and Wc are applied by a large number of synaptic connections including, and input to the neuron 141a. The neuron 141a takes a linear sum of the input signal intensities, is activated when the total value exceeds a certain threshold value, and outputs a signal to the nerve fiber 142b. When a neuron is activated and outputs a signal, the neuron is said to "fire."

This output signal is branched into, for example, two parts, weighted by synaptic connection, and then input to the neurons 141b and 141c in the subsequent stage. The neurons 141b and 141c in the subsequent stage also take the linear sum of the input signals, and when the total value of these signals exceeds a certain threshold value, the neurons 141b and 141c are activated and output signals. This operation is repeated in a plurality of steps to output the calculation result.

The weight applied in the synapse connection is gradually corrected by learning so that the optimum calculation result can be finally obtained.

The neuron computer is designed to substitute such a brain function with a semiconductor device.

FIG. 47 is a diagram showing an outline of the basic configuration of the neuron computer of this embodiment. In the figure, the same members as those of the semiconductor device of the seventh embodiment are designated by the same reference numerals as those shown in FIG.

First, as described above, the semiconductor device according to the seventh embodiment used in the neuron computer of this embodiment has the control voltage supply unit 110, the gate electrode 109, the drain region 103a, and the source region 103b.
MOS transistor Tr1 having a substrate electrode 108
1 and the gate electrode 10 of the MOS transistor Tr11
9 and the control voltage supply unit 110, the ferroelectric capacitor 104a and the resistance element 106 are provided in parallel with each other.

Next, as shown in FIG. 47, the neuron computer according to the present embodiment has an electric resistance provided between the semiconductor device according to the seventh embodiment and the ground and the source electrode of the MOS transistor Tr11. 133, a node N1 provided between the source electrode of the MOS transistor Tr11 and the electric resistance 133, a floating gate, a transistor Tr having a large number of input gates provided on the floating gate, and source and drain electrodes.
12 and an electric resistance 132 interposed between the source electrode of the transistor Tr12 and the voltage supply line Vdd. The source electrode of the transistor Tr12 is connected to ground. Further, the node N1 is connected to one of the input gates.

The semiconductor device according to the seventh embodiment,
The node N1 and the electric resistance 133 correspond to a synapse portion (a nerve fiber and a synapse connection) for transmitting and weighting signals in the brain of an organism, and a large number of synapse portions are neuron portions each including a transistor Tr12 and an electric resistance 132. (Neuron MOS). In the neuron computer of the present embodiment, the structure of the brain is imitated, and the combination of the synapse part and the neuron part connected to each other is taken as one layer, and for example, about four layers are superposed.

Next, regarding the signal transmission path, first, the output signal Ss1 from the preceding neuron section is input to the drain electrode of the MOS transistor Tr11, and the weight signal S ₁
Is input to the control voltage supply unit 110. Then, the drain signal value flowing from the MOS transistor Tr11 is changed by the weight signal S ₁ .

Next, the current signal output from the MOS transistor Tr11 is converted into a voltage signal by the electric resistance 133 and input to the input gate of the transistor Tr12. Signals from many other synapse parts are also input to the input gate of the transistor Tr12, and when the sum of the voltages of these input signals exceeds the threshold value of the transistor Tr12, the neuron “fires” and a signal is output from the neuron part. It Then, the output signal is transmitted to the synapse part of the next stage.

On the other hand, when the sum of the voltages of the input signals from the synapse part is smaller than the threshold value of the transistor Tr12,
No signal is output.

In the neuron computer of this embodiment, since the semiconductor device of the seventh embodiment capable of holding multivalued information in the synapse portion with a simple structure is used in the synapse portion, various signals can be obtained in a small area. Weight can be applied. As a result, it is possible to reduce the size of the neuron computer having a learning function, which is created by integrating the synapse part and the neuron part.

Further, in the semiconductor device of the seventh embodiment, the MOS transistor Tr11 is changed by applying a low voltage of about ± 2V after changing the characteristics of the applied voltage-drain current at about 6V as described above. The drain current of can be finely changed. Therefore, in the neuron computer of the present embodiment, even if the weighted signal S ₁ has a relatively low voltage, it is possible to apply various levels of weighting corresponding thereto.

Further, the synapse portion of the neuron computer of this embodiment has a function of storing the history of the weight signal S ₁ and forgetting the history when it is not used for a long time.

In the neuron computer of this embodiment, the semiconductor device of the seventh embodiment having the ferroelectric capacitor in the synapse portion is used, but instead of this, the fifth semiconductor device having the dielectric capacitor is used. You may use the semiconductor device of embodiment and the semiconductor device of 8th-11th embodiment.

[0260]

According to the semiconductor device of the present invention, by connecting the ferroelectric capacitors having different coercive voltages in parallel, the polarization of the capacitor is metastable in addition to the point that the polarization of the capacitor is saturated in the hysteresis of the capacitor. The point is obtained. As a result, it is possible to improve the separability of stored information, and to stabilize the voltage even when the write voltage fluctuates due to variations in the ferroelectric film thickness and differences in the crystallinity of the ferroelectric.
Ru can obtain the value or more polarization.

[0261] Using the fact of this, not the multi-level memory but also can be realized applicable semiconductor device as a component of a neuron element which performs weighted signal.

[Brief description of drawings]

FIG. 1 is a top view showing a multi-valued memory according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a II-II cross section of FIG. 1 in the multi-valued memory according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a III-III cross section of FIG. 1 in the multi-valued memory according to the first embodiment of the present invention.

4A to 4E are cross-sectional views showing a manufacturing process of the multi-valued memory according to the first embodiment of the present invention.

FIG. 5 is an equivalent circuit diagram showing a multi-valued memory according to the first embodiment of the present invention.

FIG. 6 is a diagram showing a voltage-polarization hysteresis characteristic (PV characteristic) of a capacitor MFM1.

FIG. 7 is a diagram showing a P-V characteristic of a capacitor MFM2.

FIG. 8 is a capacitor MFM1 and a capacitor MF.
It is a figure which shows the P-V characteristic of M2 and the P-V characteristic of the whole capacitor.

FIG. 9 is a diagram showing a P-V characteristic of the entire capacitor when three capacitors are used in the multilevel memory of the present invention.

FIG. 10 shows a voltage applied between an upper gate electrode and a lower electrode in the multilevel memory according to the first embodiment of the present invention,
It is a figure showing effective polarization of a ferroelectric capacitor.

FIG. 11 is a diagram for explaining gate voltage-drain current characteristics with respect to each write voltage of the multilevel memory according to the first embodiment of the present invention.

FIG. 12 is a diagram for explaining the correlation between the fluctuation of the write voltage and the fluctuation of the polarization value in the conventional multilevel memory.

FIG. 13 is an enlarged view of a portion indicated by A in FIG. 12 in the conventional multi-valued memory.

FIG. 14 is a diagram for explaining the correlation between the fluctuation of the write voltage and the fluctuation of the polarization value in the multi-valued memory according to the first embodiment of the present invention.

FIG. 15 is an enlarged view of a portion indicated by B in FIG. 14 in the multi-valued memory according to the first embodiment of the present invention.

16 (a) to 16 (d) are diagrams showing the area of the capacitor MFM2 in the multi-valued memory of the present invention.
It is a figure which shows the effective polarization when changing with respect to.

17 (a) to 17 (d) are diagrams showing the area of the capacitor MFM1 in the multi-valued memory of the present invention.
It is a figure which shows the effective polarization when changing with respect to.

FIG. 18 is a cross-sectional view showing a modified example of the multilevel memory according to the first embodiment of the present invention.

FIG. 19 is a cross-sectional view showing the structure of the multi-valued memory according to the second embodiment of the present invention.

FIG. 20 is a circuit diagram showing an outline of a multilevel memory according to a third embodiment of the present invention.

FIG. 21 is an equivalent circuit diagram showing a multilevel memory according to a fourth embodiment of the present invention.

FIG. 22 is an equivalent circuit diagram showing a semiconductor device according to a fifth embodiment of the present invention.

FIG. 23 is a top view showing a semiconductor device according to a fifth embodiment of the present invention.

24 is a cross-sectional view taken along line XXIV-XXIV shown in FIG. 22 of the semiconductor device according to the fifth embodiment of the present invention.

FIG. 25 is a sectional view taken along line XXV-XXV shown in FIG. 22 of the semiconductor device according to the fifth embodiment of the present invention.

26A to 26D are cross-sectional views showing the manufacturing process of the semiconductor device according to the fifth embodiment of the present invention.

FIG. 27 is a diagram showing applied voltage-pass current characteristics of a dielectric capacitor used in a semiconductor device according to a fifth embodiment of the present invention.

FIG. 28 is a diagram showing applied voltage-drain current characteristics of the semiconductor device according to the fifth embodiment of the present invention.

FIG. 29 is a correlation diagram between the passing current flowing through the dielectric capacitor and the recovery time in the semiconductor device according to the fifth embodiment of the present invention.

FIG. 30 is a diagram showing applied voltage-pass current characteristics of a dielectric capacitor in a method for driving a semiconductor device according to a sixth embodiment of the present invention.

FIG. 31 is a diagram showing applied voltage-drain current characteristics of the semiconductor device according to the sixth embodiment of the present invention.

FIG. 32 is an equivalent circuit diagram showing a semiconductor device according to a seventh embodiment of the present invention.

33 (a) to 33 (d) are views showing manufacturing steps of the semiconductor device according to the seventh embodiment of the present invention.

FIG. 34A is a diagram showing an equivalent circuit at the time of coarse adjustment in which the stored information is significantly changed in the semiconductor device of the present embodiment, and FIG. 34B is a view at the time of fine adjustment in which the stored information is finely changed. It is a figure which shows an equivalent circuit.

FIG. 35 is a diagram showing applied voltage-pass current characteristics of a ferroelectric capacitor used in a semiconductor device according to a seventh embodiment of the present invention.

FIG. 36 is a view of a semiconductor device according to a seventh embodiment,
It is a figure which shows an example of a voltage application method.

FIG. 37 is a diagram showing applied voltage-drain current characteristics in the initial state of the semiconductor device according to the seventh embodiment of the present invention.

FIG. 38 is a diagram showing a drain current when a pulse voltage is continuously applied after + 6V is applied in the semiconductor device according to the seventh embodiment of the present invention.

FIG. 39 is a diagram showing applied voltage-drain current characteristics when the applied voltage is scanned within a range of ± 2V after applying + 6V in the semiconductor device according to the seventh embodiment of the present invention.

FIG. 40 is a diagram showing a drain current when a pulse voltage is continuously applied after applying −6 V in the semiconductor device according to the seventh embodiment of the present invention.

FIG. 41 is a diagram showing applied voltage-drain current characteristics when the applied voltage was scanned within a range of ± 2 V after applying −6 V in the semiconductor device according to the seventh embodiment of the present invention.

42A is a circuit diagram showing a semiconductor device according to an eighth embodiment of the present invention, and FIG. 42B is a diagram showing varistor characteristics of a resistance element.

FIG. 43 is a cross-sectional view showing the structure of the semiconductor device according to the eighth embodiment.

FIG. 44 is a circuit diagram showing a semiconductor device according to a ninth embodiment of the present invention.

FIG. 45 is a circuit diagram showing a semiconductor device according to a tenth embodiment of the present invention.

FIG. 46 is a circuit diagram showing a semiconductor device according to an eleventh embodiment of the present invention.

FIG. 47 is a diagram showing an outline of a basic configuration of a neuron computer according to a twelfth embodiment of the present invention.

[Fig. 48] Fig. 48 is a diagram showing a model of the brain of an organism, in which the constitution of basic units is simplified.

FIG. 49 is a cross-sectional view of a conventional semiconductor device that functions as a multi-valued memory.

FIG. 50 is a diagram showing hysteresis characteristics of a conventional semiconductor device that functions as a multi-valued memory.

FIG. 51 is a graph showing a relationship between a gate voltage and a drain current of a memory cell of a conventional semiconductor device.

[Description of Reference Signs] 1 substrate 3a drain region 3b source region 5 element isolation film 7 gate insulating film 9 gate electrode 11 first interlayer insulating films 13a, 13b, 13c, 13d plug wiring 14a first intermediate electrode 14b second Intermediate electrodes 15a and 15b Pad portion 16 First ferroelectric layer 17 First upper electrode 18 Second ferroelectric layer 19 Second upper electrode 20 Insulating layer 21 Second interlayer insulating film 25a, 25b, 25c Wiring 26 Gate / Lower Electrode 27 First Ferroelectric Layer 28 Second Ferroelectric Layer 29 First Upper Electrode 30 Second Upper Electrode 31 Interlayer Insulating Film 32 Plug Wiring WL Word Line BL Bit Line 101 Si Substrate 103a Drain region 103b Source region 104 Dielectric capacitor 104a Ferroelectric capacitor 105 Element isolation oxide film 106 Resistor element 107 Gate Edge film 108 Substrate electrode 109 Gate electrode 110 Control voltage supply section 111 First interlayer insulating films 113a, 113b, 113c Plug wiring 114 Intermediate electrodes 115a, 115b Pad section 116 Dielectric layer 119 Upper electrode 121 Second interlayer insulating film 125a , 125b, 125c Wiring 131 Ferroelectric layer 132, 133 Electric resistance Ss ₁ Output signal S ₁ from previous stage synapse S ₁ Load signal Tr 11 MOS transistor Tr 12 Transistor N 1 node

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H03K 19/20 101 H01L 27/10 444Z (72) Inventor Kiyoyuki Morita 1006 Kadoma, Kadoma, Osaka Prefecture Matsushita F-term in Denki Sangyo Co., Ltd. (reference) 5F083 FR01 FR02 JA06 JA14 JA15 JA38 JA40 KA01 KA05 MA06 MA17 MA19 NA08 PR22 PR40 ZA21 5J042 AA10 BA13 CA07 CA20 DA00 DA06

Claims (40)

[Claims] 1. A semiconductor substrate, a first capacitor composed of a first upper electrode, a first dielectric layer, and a first lower electrode formed on the semiconductor substrate, and formed on the semiconductor substrate. And a storage unit configured by arranging a second upper electrode, a second dielectric layer, and a second capacitor composed of a second lower electrode, which can hold information of three values or more. A semiconductor device, wherein the first dielectric layer and the second dielectric layer have different coercive voltage values in hysteresis characteristics. 2. The semiconductor device according to claim 1, wherein the polarization direction of the first capacitor and the polarization direction of the second capacitor are the same during operation. 3. The semiconductor device according to claim 1, comprising a gate insulating film formed on the semiconductor substrate, and a gate electrode formed of a conductive film formed on the gate insulating film. The semiconductor device, further comprising: a first lower electrode and a second lower electrode both integrated with the gate electrode. 4. The semiconductor device according to claim 1, further comprising a gate insulating film formed on the semiconductor substrate and a gate electrode formed of a conductor film formed on the gate insulating film. A semiconductor device, wherein the first lower electrode and the second lower electrode are connected to the gate electrode, respectively. 5. The semiconductor device according to claim 1, wherein the voltage of the first capacitor and the second capacitor in the first half process until the polarization of each of the first capacitor and the second capacitor is saturated. A semiconductor device characterized in that the rate of change of polarization with respect to the change of the difference is different. 6. The semiconductor device according to claim 1, wherein the first dielectric layer and the second dielectric layer both have a ferroelectric layer. A semiconductor device characterized by the above. 7. The semiconductor device according to claim 1, wherein the first upper electrode and the second upper electrode are connected to each other. . 8. The semiconductor device according to claim 3, wherein the first dielectric layer is shared with the second dielectric layer. . 9. The semiconductor device according to claim 8, wherein materials of members forming the first dielectric layer and the second dielectric layer are the same, and the first capacitor and the second capacitor are the same. A semiconductor device further comprising a paraelectric capacitor connected in parallel with the second capacitor. 10. The semiconductor device according to claim 8, further comprising a capacitor interposed between the second capacitor and the gate electrode. 11. The semiconductor device according to claim 1, wherein the areas of the first dielectric layer and the second dielectric layer are different from each other. Semiconductor device. 12. The semiconductor device according to claim 1, wherein the first dielectric layer and the second dielectric layer are made of different materials. Characteristic semiconductor device. 13. The semiconductor device according to claim 1, wherein the film thickness of the first dielectric layer and the film thickness of the second dielectric layer are different from each other. Characteristic semiconductor device. 14. The semiconductor device according to claim 11, wherein the first capacitor and the second capacitor are a ratio of mutual electrode areas (area of the first capacitor) / (the first capacitor). The area of the capacitor 2) is 0.2
A semiconductor device having the number of 2 or more. 15. The semiconductor device according to claim 12, wherein a ratio of mutual electrode areas of the first capacitor and the second capacitor is 0.5 or more and 2 or less. . 16. The semiconductor device according to claim 1, wherein a MIS transistor connected to the first upper electrode and the second upper electrode, and a word line connected to a gate electrode of the MIS transistor. And a bit line connected to the MIS transistor. 17. A control voltage supply unit, a field effect transistor having a gate electrode having a function of accumulating charges, a capacitor element interposed in parallel between the control voltage supply unit and the gate electrode, and A semiconductor device having a resistance element and capable of holding multivalued information. 18. The semiconductor device according to claim 17, wherein the charge is injected into the gate electrode from the control voltage supply section. 19. The semiconductor device according to claim 17, which functions as an analog memory capable of continuously holding multi-valued information in accordance with the amount of charge accumulated in the gate electrode. Semiconductor device. 20. The semiconductor device according to claim 17, wherein the resistance element is made of a dielectric material. 21. The semiconductor device according to claim 17, wherein the control voltage supply section serves as an upper electrode, and the gate electrode of the field effect transistor is connected to an intermediate electrode. Wherein the capacitive element is a dielectric capacitor including the upper electrode, the intermediate electrode, and a dielectric layer sandwiched between the upper electrode and the intermediate electrode, and the resistance component of the dielectric layer is the resistance element of the resistive element. A semiconductor device, which functions as one. 22. The semiconductor device according to claim 20, wherein the resistance value of the resistance element changes according to the electric field strength applied to the resistance element. 23. The semiconductor device according to claim 20, wherein a resistance value of the resistance element has a substantially constant value when an electric field strength applied to the resistance element is a predetermined value or less. In particular, the semiconductor device is characterized in that it becomes low when the electric field strength exceeds the above-mentioned predetermined value. 24. The semiconductor device according to claim 20, wherein the passing current flowing through the resistance element is equal to or less than a certain absolute value of a voltage applied across the resistance element. A semiconductor device having a characteristic that the voltage increases substantially in direct proportion to an applied voltage and increases exponentially when the absolute value of the applied voltage exceeds the constant value. 25. The semiconductor device according to claim 24, wherein in the voltage range in which the passing current flowing through the resistance element increases substantially in direct proportion to the voltage, the passing current flowing per unit area of the resistance element is 100. wherein a is not more than [mA / cm ^2]. 26. The semiconductor device according to claim 20, wherein the capacitance element has a ferroelectric layer, and at least one of the resistance elements is made of a ferroelectric material. A semiconductor device characterized by the above. 27. The semiconductor device according to claim 21, further comprising at least one resistance element provided separately from the capacitance element. 28. The semiconductor device according to claim 27, wherein the resistive element provided separately from the capacitive element is Ba or S.
An oxide of an element selected from r, Ti, Zn, Fe, and Cu or 1 selected from SiC, Si, and Se
A semiconductor device characterized by being a varistor including two. 29. The semiconductor device according to claim 27, wherein the resistance element provided separately from the capacitance element is a diode connected in parallel to each other and arranged in opposite directions to each other. Semiconductor device. 30. The semiconductor device according to claim 27, further comprising an MIS transistor, wherein an on-resistance of the MIS transistor functions as a resistance element provided separately from the capacitance element. 31. The semiconductor device according to claim 27, wherein the resistance element provided separately from the capacitance element is a resistance change element made of a resistance change material whose resistance value changes according to crystallinity. Semiconductor device. 32. The semiconductor device according to claim 17, wherein the semiconductor device is used as a synapse unit of a neuron computer. 33. A control voltage supply unit, a field effect transistor having a gate electrode having a function of accumulating charges,
A driving method of a semiconductor device having a capacitive element and a resistive element interposed in parallel with each other between the control voltage supply section and the gate electrode, wherein a write voltage is applied to both ends of the resistive element. A step (a) of changing the amount of charge accumulated in the gate electrode through the resistance element to change the threshold voltage of the field effect transistor, and a step of reading information according to the change of the drain current of the field effect transistor ( b) A method for driving a semiconductor device including: 34. The method of driving a semiconductor device according to claim 33, wherein the capacitive element has a dielectric layer. 35. The method of driving a semiconductor device according to claim 34, wherein in step (a), if the absolute value of the write voltage applied to both ends of the resistance element is equal to or less than a constant value, The flowing current increases almost directly in proportion to the write voltage, and when the absolute value of the write voltage exceeds the above constant value, the passing current increases exponentially with the increase of the write voltage. Driving method for semiconductor device. 36. The method of driving a semiconductor device according to claim 35, wherein in step (a), when the absolute value of the write voltage is equal to or less than the constant value, the gate is applied depending on the length of time for applying the write voltage. A method for driving a semiconductor device, comprising controlling the amount of charge accumulated in an electrode. 37. The method of driving a semiconductor device according to claim 35 or 36, wherein in step (a), when the absolute value of the write voltage is equal to or less than the constant value, a passage per unit area flowing through the resistance element is performed. A method for driving a semiconductor device, wherein the current is 100 [mA / cm ² ] or less. 38. The method of driving a semiconductor device according to claim 35, wherein in step (a), when the absolute value of the write voltage applied to both ends of the resistance element exceeds the predetermined value, the write voltage A method of driving a semiconductor device, wherein the pulse widths are made equal to each other, and the amount of charges accumulated in the gate electrode is controlled by the magnitude of the absolute value of the write voltage. 39. The method of driving a semiconductor device according to claim 38, wherein in step (a), when the absolute value of the write voltage applied to both ends of the resistance element exceeds the certain value, the gate electrode is used. Driving of a semiconductor device characterized in that the amount of charge accumulated in the gate electrode is roughly adjusted, and the amount of charge accumulated in the gate electrode is finely adjusted when the absolute value of the write voltage is lower than the constant value. Method. 40. The method of driving a semiconductor device according to claim 33, wherein in the step (a), ranges of write voltages applied to both ends of the resistance element are mutually absolute values. A method for driving a semiconductor device, wherein the positive and negative ranges are equal.