JP2003158659A - Image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image pickup device the circuit scale of which can be reduced. SOLUTION: First and second CCD driver circuits 33a, 33b alternately extract first and second image signals Ya(t), Yb(t) at each prescribed time from the first and second CCD solid-state imaging elements 31a, 31b. A selection circuit 36 alternately capture the first and second image signals Ya(t), Yb(t) in a timing in response to an operation timing of the first and second CCD solid-state imaging elements and provide the output of an image signal Y(t). Thus, the output side of the selection circuit 36 substantially configures the composite state of the first and second image signals Ya(t), Yb(t).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention captures a plurality of subject images using a plurality of solid-state image pickup devices, synthesizes a plurality of series of image signals obtained thereby, and produces a plurality of reproduced images on a common display screen. The present invention relates to an image pickup device for displaying.

[0002]

2. Description of the Related Art In an image pickup apparatus such as a digital still camera, it is considered that a plurality of solid-state image pickup elements are mounted and images of different subjects are picked up at the same time. Such an image pickup device is configured to combine a plurality of series of image signals obtained from a plurality of solid-state image pickup devices and display a plurality of reproduced images on one display screen, for example. Figure 9
It is a block diagram showing an example of an imaging device carrying a plurality of solid-state imaging elements.

The image pickup device shown in FIG. 9 has two image pickup devices 20a and 20b corresponding to the respective subjects in order to pick up images of the two subjects, and the memory controller 9 outputs the respective outputs. Controlled.

The first image pickup device 20a includes a first CCD solid-state image pickup device 1a, a first booster circuit 2a, a first CCD driver circuit 3a, a first timing control circuit 4a, and a first timing control circuit 4a.
Analog signal processing circuit 5a, first A / D conversion circuit 6
a, a first digital signal processing circuit 7a, and a first memory 8a, which form a first imaging system. In the first CCD solid-state image sensor 1a, a plurality of light receiving pixels are arranged in a matrix, and information charges generated in response to an incident first subject image are accumulated in each light receiving pixel. Also, the first CCD
The solid-state imaging device 1a has a so-called vertical overflow drain structure that absorbs excess information charges generated in each light receiving pixel to the substrate side, and discharges information charges accumulated in each light receiving pixel to the substrate side. Is possible.

The first booster circuit 2a boosts an input power supply voltage V _D (not shown) to generate a boosted voltage,
To the CCD driver circuit 3a. The first CCD driver circuit 3a generates a plurality of clock pulses using the boosted voltage generated by the first booster circuit 2a and supplies the clock pulses to the first CCD solid-state image sensor 1a. The plurality of clock pulses are generated based on various timing signals supplied from the first timing control circuit 4a. As a result, the image signal Y (t) corresponding to the charge amount of the information charge accumulated in each light receiving pixel of the first CCD solid-state image pickup device 1a.
Are taken out from the first CCD solid-state image pickup device 1a on a pixel-by-pixel basis.

The first timing control circuit 4a is composed of a plurality of counters for counting the reference clock CK having a constant cycle, and divides the reference clock CK to divide the vertical synchronizing signal VD.
And a horizontal synchronizing signal HD. Then, various timing signals to be supplied to the first CCD driver circuit 1b are generated at the timings synchronized with the vertical synchronization signal VD and the horizontal synchronization signal HD. As a result, the image signal Y (t) for each line is output from the first CCD solid-state image sensor 1a at the timing synchronized with the horizontal synchronizing signal HD, and the image signal Y (t) for each line is synchronized with the vertical synchronizing signal VD. The image signal Y (t) is output.

The first analog signal processing circuit 5a has a first
Image signal Ya output from the CCD solid-state image sensor 1a
For (t), CDS (Correlated Double Sampling), AGC (Automatic Gain Contro)
l: Automatic gain control) and other analog signal processing. CD
In S, for the image signal in which the reset level and the signal level are repeated, the signal level is taken out after the reset level is clamped, and an image signal having a continuous signal level is generated. In the AGC, the image signal taken out by the CDS is integrated in one screen or in units of one vertical scanning period, and gain adjustment is performed so that the integrated data is contained within a predetermined range. The first A / D converter 6a outputs the first image signal Y output from the first analog signal processing circuit 5a.
The a (t) is standardized in synchronization with the output timing of the first CCD solid-state imaging device 1a, and the first image data Ya (n) of a digital signal is output.

The first digital signal processing circuit 7a has a first
The image data Ya (n) is subjected to processing such as color separation and matrix calculation to generate image data Y ′ (n) including luminance data and color difference data. In addition, the first digital signal processing circuit 7a includes an exposure control circuit and a white balance control circuit, and controls exposure of the first CCD solid-state image pickup device 1a to control the white balance of the image signal Y (t). Perform white balance correction processing to adjust. The first memory 8a is a frame memory, and stores the luminance data and the color difference data output from the first digital signal processing circuit 7a in one screen unit in response to a write instruction from the memory controller 9.

The second image pickup device 20b includes a second CCD solid-state image pickup device 1b, a second booster circuit 2b, a second CCD driver circuit 3b, a second timing control circuit 4b, and a second timing control circuit 4b.
Analog signal processing circuit 5b, second A / D conversion circuit 6
b, a second digital signal processing circuit 7b, and a second memory 8b, which form a second image pickup system. Each circuit forming the second image pickup device 20b has the same circuit structure as each circuit forming the first image pickup device 20a, and a second image signal output from the second CCD solid-state image pickup device 1b. The same process is performed for.

The memory controller 9 controls the read timing of the first and second image data from the first and second memories 8a and 8b, and the captured image captured by the first image capturing device 20a and the second captured image. The captured image captured by the image capturing device 20b is controlled to be reproduced on a single display screen. For example, as shown in FIG. 10A, the first captured image A and the second captured image captured by the first image capturing device 20a are divided into two areas vertically divided on a single display screen. When displaying the second captured image B captured by the device 20b, the first image data Ya (n) and the first image data Ya (n) corresponding to the first captured image A from the first and second memories 8a and 8b are displayed. The second image data Yb (n) corresponding to the second captured image B is taken out. After that, the two image data are combined so as to match the display form on the display screen. Further, as shown in FIG. 10B, when the first captured image A is mainly displayed on the display screen and the second captured image B is reduced and displayed in the lower left quarter area of the display screen, First memory 8
The first image data Y corresponding to the upper half of the display screen from a
a (n) is read out, and then the first and second memories 8a,
The first image data Ya (n) and the second image data Yb (n) corresponding to the lower half area of the display screen are read from 8b.
At this time, in order to display one screen in the area where the second captured image B is allocated on the display screen, the second memory 8
The image data for one screen read from is compressed into 1/4 data. Then, the first image data Ya (n) and the compressed second image data Yb (n) are combined to form the first captured image A and the second captured image B reduced to 1/4. And 1
Display on one display screen at the same time.

[0011]

An image pickup apparatus for picking up a plurality of subject images as described above by using a plurality of solid-state image pickup devices, and combining and displaying a plurality of picked-up images on a single display screen is as follows. A plurality of solid-state image pickup devices, a drive circuit, a timing control circuit, and a signal processing circuit are mounted, respectively, which causes a problem that the circuit scale becomes large and the power consumption also becomes large. Therefore, it is conceivable to share the circuits other than the solid-state image sensor to reduce the circuit scale of the image pickup apparatus, but there are many choices as to which of the circuits included in the image pickup apparatus should be shared. If a circuit to be shared is simply selected from the options, it may cause a problem such as deterioration of function. For example, when the drive system is shared, a plurality of solid-state image pickup devices cannot be driven simultaneously, and the frame rate of each solid-state image pickup device decreases.

Therefore, the present invention finds an optimum combination of an individually provided circuit and a common circuit in an image pickup apparatus using a plurality of solid-state image pickup elements, realizes reduction in circuit scale, and is efficient. An object is to provide an imaging device that can operate.

[0013]

The present invention has been made to solve the above-mentioned problems, and is characterized in that a plurality of light receiving pixels are arranged in a matrix and respond to a first subject image. A first solid-state image sensor for accumulating information charges generated in each light receiving pixel and a plurality of light receiving pixels are arranged in a matrix, and information charges generated in response to a second subject image are accumulated in each light receiving pixel. A second solid-state imaging device; a first drive circuit that transfers and outputs information charges accumulated in each light-receiving pixel of the first solid-state imaging device to obtain a first image signal; and the second solid-state imaging device A second drive circuit that transfers and outputs the information charges accumulated in each light receiving pixel of the device to obtain a second image signal, and the first and second solid-state imaging devices based on a reference clock having a constant period. Timing to determine the timing of vertical and horizontal scanning And a control circuit, said first and second
And a selection circuit for selectively outputting one of the first and second image signals in synchronization with the operation timing of the solid-state image sensor, and receiving the output from the selection circuit to generate a predetermined image signal. And a signal processing circuit, wherein the selection circuit alternately selects the first and second image signals at predetermined time intervals.

According to the present invention, the first and second image signals are fetched from the first and second solid-state image pickup devices into the selection circuit, and the first and second image signals are stored in the selection circuit for a predetermined time. They are alternately selected and output every time. As a result, the first and second image signals are substantially combined at the output side of the selection circuit. Therefore, the signal processing circuit after the selection circuit can be shared by the first and second solid-state imaging devices.

[0015]

FIG. 1 is a block diagram showing the configuration of a first embodiment of an image pickup apparatus of the present invention. This image pickup device is provided with two solid-state image pickup devices.
And second CCD solid-state imaging devices 31a and 31b, first and second booster circuits 32a and 33b, first and second CCs.
D driver circuits 33a and 33b, timing control circuit 3
4, first and second clamp circuits 35a and 35b, a selection circuit 36, an analog signal processing circuit 37, an A / D conversion circuit 38, and a digital signal processing circuit 39.

The first CCD solid-state image pickup device 31a is, for example, a frame transfer type solid-state image pickup device as shown in FIG. 2, and includes a plurality of vertical shift registers 1v continuous from the image pickup unit to the storage unit, and a plurality of these vertical shift registers. It is composed of a horizontal shift register 1h arranged on the output side of the shift register 1v and an output section 1d arranged on the output side of the horizontal shift register 1h. In the imaging unit, the vertical shift register 1v is electrically separated to form a plurality of light receiving pixels, and information charges generated by receiving the first subject image are accumulated in each light receiving pixel. Further, in the image pickup unit, a part of the columns of the vertical shift registers are shielded from light, so-called OPB (Opti
cal black) area is set. The information charge accumulated in each light receiving pixel of the image pickup section is transferred at high speed to the accumulation section by the frame transfer clock φa (f) and the vertical transfer clock φa (v). The information charges output to the storage unit are temporarily stored in the storage unit, and the vertical transfer clock φ
The data is transferred to the horizontal shift register 1h by a (v) in 1-line units, and transferred from the horizontal shift register 1h to the output section 1d side in 1-pixel units by the horizontal transfer clock φh. The information charge output to the output unit 1d is converted into a voltage value according to the charge amount by being accumulated in the capacitor for each pixel, and output as the image signal Ya (t). At this time, in the output section 1d, the information charge accumulated in the capacitor is discharged to the drain in response to the reset clock φr synchronized with the horizontal transfer clock φh. Further, the first CCD solid-state image pickup device 1a has a so-called vertical overflow drain structure for absorbing an excessive electric charge generated in the image pickup unit to the substrate side, and the information charge accumulated in the image pickup unit is transferred to the substrate clock φa. (b)
It is possible to discharge to the substrate side. The second CCD solid-state imaging device 31b has a plurality of light-receiving pixels arranged in a matrix, like the first CCD solid-state imaging device 31a.
Information charges generated in response to the second subject image are accumulated in each light receiving pixel, and a second image signal Yb (t) corresponding to the accumulated information charges is output. The second CCD solid-state imaging device 31b is set so that the driving conditions such as the operating voltage and the frequency of the driving clock are equal to those of the first CCD solid-state imaging device 31b.

The first booster circuit 32a is arranged corresponding to the first CCD solid-state image pickup device 31a and boosts the input power supply voltage V _D (not shown) to generate a boosted voltage. To the CCD driver circuit 33a. The second booster circuit 33b is arranged corresponding to the second CCD solid-state imaging device 31b, and similarly to the first booster circuit 32a, the boosted voltage obtained by boosting the power supply voltage V _D is applied to the second CCD. It is supplied to the driver circuit 33b.

The first CCD driver circuit 33a receives the first frame transfer clock φa (f), the first vertical transfer clock φa (v), and the first vertical transfer clock φa (v) based on the timing signal supplied from the timing control circuit 34. Horizontal transfer clock φa (h),
The first reset clock φa (r) and the first substrate clock φa (b) are generated and supplied to the first CCD solid-state imaging device 31a. The second CCD driver circuit 33b receives the second frame transfer clock φb (f), the second vertical transfer clock φb (v), and the second horizontal transfer clock based on the timing signal supplied from the timing control circuit 34. φb (h), second
Reset clock φb (r) and second substrate clock φb
(b) is generated and supplied to the second CCD solid-state image sensor 33b. These first and second CCD driver circuits 33
a and 33b are the first and second CCD solid-state imaging devices 31.
The first and second solid-state image pickup devices 31a and 31b can be simultaneously driven, because they are arranged corresponding to the respective a and 31b.

The timing control circuit 34 includes a plurality of counters 34a for counting the reference clock CK having a constant cycle.
And a decoder 34b for decoding the output of this counter
It is possible to generate a plurality of various timing signals by changing the setting value of the decoder 34b. The timing control circuit 34 is commonly arranged for the first and second CCD driver circuits 33a and 33b.

Further, the timing control circuit 34 receives one of a plurality of setting data corresponding to each of a plurality of display modes set as shown in FIG. Decoder 34b
The setting value of is changed. As a result, the supply start timing and rising timing of each clock pulse are changed. For example, in the case of FIG. 3B, the setting data corresponding to this is given to the decoder 34b, the phase of the clock pulse supplied to the first CCD driver circuit 33a and the clock pulse supplied to the second CCD driver circuit 33b. Each clock pulse is generated so as to be out of phase with.
These clock pulses are then applied to the first and second CCs.
It is supplied to the D solid-state image pickup devices 31a and 31b, and is controlled so that the first image signal Ya (t) and the second image signal Yb (t) are output in a time division manner.

The register 40 stores a plurality of setting data associated with each of a plurality of display modes, and a display mode switching signal MOD provided from the outside.
Upon receiving E, the setting data corresponding to the display mode designated by E is output to the timing control circuit 34.
As a result, the timing of starting supply of each clock pulse or the timing of rising is changed according to the designated display mode.

The first clamp circuit 35a has a first CC
It is arranged corresponding to the D solid-state image pickup device 31a, clamps the first image signal Ya (t), and supplies it to the selection circuit 36.
Of the second CCD solid-state image sensor 3
1b, and the second image signal Yb (t) is clamped and supplied to the selection circuit 36. These first and second
The clamp circuits 35a and 35b have the same clamp level, and the first and second image signals Ya
The black levels of (t) and Yb (t) are fixed to the same voltage level and then output.

The selection circuit 36 has two input terminals 36a,
36b and one output terminal 36c, and takes in the first and second image signals Ya (t), Yb (t) output from the first and second clamp circuits 35a, 35b, Image signal Y is selected by selecting one of these signals.
Output as (t). The selection circuit 36 operates according to the timing signal supplied from the timing control circuit 34, and the input terminal 36a and the output terminal 36a during the period in which the first image signal Ya (t) is output from the first CCD solid-state imaging device 31a. 36c is connected to the second CCD solid-state image sensor 31b
The input terminal 36b and the output terminal 36c are connected during the period in which the second image signal Yb (t) is being output. That is, the selection circuit 36 includes the first and second CCD solid-state imaging devices 31a,
The two series of image signals output from 31b in a time division manner are selectively taken in according to these output timings and output, so that the output side thereof is substantially combined into one series of image signals.

The analog signal processing circuit 37 includes a selection circuit 3
The image signal Y (t) output from 6 is taken in, CDS,
The image signal Y ′ (t) is output by performing signal processing such as AGC. The A / D conversion circuit 38 converts the image signal Y ′ (t) subjected to the analog signal processing into a digital signal and outputs it as image data Y (n). The digital signal processing circuit 39 is
The image data Y (n) is subjected to processing such as color separation and matrix calculation to generate image data including brightness data and color difference data. Further, the digital signal processing circuit 39 is
An exposure control circuit, a white balance control circuit, and an integration circuit are built in, the image data is integrated in a predetermined period unit, and exposure control and white balance correction are performed based on the integrated value. In the analog signal processing circuit 37, the A / D conversion circuit 38, and the digital signal processing circuit 39, the first and second image signals Ya (t) and Yb (t) are controlled by the timing control circuit 34. Signal processing is performed separately in time division.

As described above, the first and second CCD solid-state image pickup devices 31a and 31b are used with respect to the first and second CCDs.
The driver circuits 33a and 33b, the first and second clamp circuits 35a and 35b are individually provided, and the analog signal processing circuit 37, the A / D conversion circuit 38, and the digital signal processing circuit 39 are shared, thereby reducing the function. It is possible to reduce the circuit scale of the imaging device while preventing it. That is, while simultaneously driving the two CCD solid-state image pickup devices 31a and 31b, the output timings of the first and second image signals are set in a time-division manner, and the selection circuit 36 is operated in accordance with the output timings, thereby The switching operation of two image signals is efficiently performed. By sharing the analog signal processing circuit 37, the A / D conversion circuit 38, and the digital signal processing circuit 39 subsequent to the selection circuit 36, the circuit scale of the image pickup apparatus can be effectively reduced. Furthermore, the first and second CCD solid-state imaging devices 31a,
The timing control circuit 34 is commonly provided for 31b, which enables further downsizing of the circuit scale.

Further, in the image pickup apparatus of the present invention, two C
Two clamp circuits 35a and 35b are individually provided for the CD solid-state image pickup devices 31a and 31b. For this reason,
Even if there is a level difference between the black levels of the first and second image signals Ya (t) and Yb (t) due to manufacturing variations in the two CCD solid-state image pickup devices 31a and 31b, after the level difference is corrected, It can be supplied to the selection circuit 36. As a result, it is possible to suppress the variation in the contrast of the two picked-up images obtained from the two CCD solid-state image pickup devices 31a and 31b and prevent the two picked-up images from having different image qualities.

FIG. 4 is a timing diagram illustrating the operation of FIG. Here, the first captured image A is mainly displayed from among the plurality of display modes shown in FIG.
When the second captured image B is displayed in the / 4 area (see FIG.
(A)) will be described as an example. In the following description, the first and second CCD solid-state image pickup devices 31a and 31b.
It is assumed that the image pickup unit of is composed of 12 lines.

At timings t0 to t1, the first frame transfer clock φa (f) and the first vertical transfer clock φa (v) are clocked within the blanking period of the vertical synchronization signal VD, and the first CCD is clocked. Information charges for one screen accumulated in the image pickup section of the solid-state image pickup device 31a are transferred to the storage section and output. At subsequent timings t1 to t2, the second frame transfer clock φb (f) and the second vertical transfer clock φb (v) are clocked and accumulated in the image pickup unit of the second CCD solid-state image pickup device 31b. Information charges for the screen are transferred and output to the storage unit. Here, the reason why the frame shift timing is shifted between the first CCD solid-state imaging device 31a and the second CCD solid-state imaging device 31b is to reduce the peak value of the inrush current at the start of the frame shift.
That is, in the frame shift, the information charges accumulated in the image pickup unit are transferred to the storage unit at high speed and output, so that an excessive rush current flows at the start of the frame shift. So two CCs
The peak value of the inrush current is kept low by not simultaneously starting the frame shift in the D solid-state image pickup device.

Subsequently, at timing t3, the first vertical transfer clock φa (v) begins to be clocked at the timing synchronized with the horizontal synchronizing signal HD, and is output to the storage section of the first CCD solid-state image pickup device 31a. Information charges for one screen are sequentially transferred and output to the horizontal transfer unit in units of one line, and the information charges output to the horizontal transfer unit are sequentially output as image signals Ya (t). This is continued until the timing t5, and the image signals for 6 lines corresponding to the upper half area of one screen are output. During this period, the second CCD
The power supply to the driver circuit 33b is stopped, and the second vertical transfer clock φb (v) is fixed to the low level.
This allows the second CCD solid-state image sensor 31b to
The image signal Yb (t) is not output.

At timing t4, the first substrate clock φa (b) is raised, and the information charges accumulated in the image pickup section of the first CCD solid-state image pickup device 31a are discharged to the substrate side. Then, the information charges are accumulated in the image pickup unit in the period La until the next frame shift timing. Further, at the timing t6, the second substrate clock φb (b) is raised, and information charges are accumulated in the image pickup section of the second CCD solid-state image pickup device 31b during the period Lb until the next frame shift timing.

At the timing t5, when the output of the image signals for 6 lines from the first CCD solid-state image pickup device 31a is completed, the cycle of the first vertical transfer clock φa (v) becomes 2
Doubled, and the clocking of the second vertical transfer clock φb (v) is started in the same cycle. The first and second vertical transfer clocks φa (v) and φb (v) have timings t5 to t5.
Clocking is performed for t7, and the second image signal Yb (b) is output from the first CCD solid-state imaging device 31a.
In this period, as shown in FIG. 4, the first and second vertical transfer clocks φa (v) and φb (v) are set to rise alternately, and as a result, the first and second CCD solid-state imaging From the elements 31a and 31b, the first and second image signals Ya
(t) and Yb (t) are alternately output for each line. At this time, since the display area of the second image signal Yb (t) is set to a half area in the vertical direction, one screen of 12 lines is thinned out every other line. It is output in 6 lines. Further, at timings t5 to t7,
In response to the output timing of the first and second image signals Ya (t) and Yb (t), each image signal is selectively taken out by the selection circuit 36 and output as the image signal Y (t). .
In this way, by controlling the output timing of the first and second image signals Y (t) and operating the selection circuit 36 in accordance with the output timing, the image signals are output in the order according to the designated display mode. Can be taken out.

FIG. 5 shows selection of the first and second image signals Ya (t) and Yb (t) output from the first and second CCD solid-state image pickup devices 31a and 31b at the timings shown in FIG. 9 is a timing chart showing the states of the image signal Y (t) output from the circuit 36 and the image data D (n) output from the digital signal processing circuit 39. FIG.

As described with reference to FIG. 4, the first image signal Ya (t) is continuously output in units of one line up to the sixth line. Then, from the 7th line, the second image signal Yb (t) is output alternately at different timings. The output of the second image signal Yb (t) is started after the output of the first image signal Ya (t) for 6 lines is completed.

Image signal Y output from the selection circuit 36
In (t), the 6th line is the 6th line of the first image signal Ya (t), and the 7th and subsequent lines are the first image signal Ya (t) and the second image signal Yb (t). It is assigned alternately in units of one line. That is, in the period until the first image signal Ya (t) is output up to the 6th line, the first C
The CD solid-state imaging device 31a side is selected, and up to the 6th line of the first image signal Ya (t) is selected as it is and output as the image signal Y (t). After that,
The selection circuit 36 alternately selects the first CCD solid-state imaging device 31a side and the second CCD solid-state imaging device 31b side,
After the signal of the first line of the second image signal Yb (t),
Image signal Ya (t) on the 7th line, followed by the second image signal Yb (t) on the 3rd line, and so on.
The first and second image signals Ya (t) and Yb (t) are alternately assigned and output as the image signal Y (t). As a result,
From the seventh line onward of the image signal Y (t), the first image signal Ya (t) and the second image signal Yb (t) are substantially combined.

In the image data D (n) output from the digital signal processing circuit 39, up to the 6th line of the image signal Y (t) corresponding to the 6th line of the first image signal Ya (t) is sequentially. The signal is processed and output. After the 7th line,
The image data corresponding to one line of the second image signal Yb (t) is compressed by the compression circuit incorporated in the digital signal processing circuit 39 into half the data of one line. In addition to this,
From the 7th line onward, the image data corresponding to one line of the first image signal Ya (t) does not reach the display area 1
The data in the first half of the line is removed. Then, the compressed image data and the data obtained by extracting only the latter half of one line are combined into one line of image data D (n). For example, the data of the 7th line of the image data D (n) is the data obtained by compressing the image data generated from the 1st line of the second image signal Yb (t) into half of the 1st line and the 1st line.
The image data Ya (t) is generated by synthesizing the latter half of one line of the image data generated from the seventh line with the extracted data. As a result, the first captured image A captured by the first CCD solid-state image sensor 31a is displayed on the display screen.
The second CCD solid-state image sensor 31 in the lower left quarter area of the
The second captured image B captured in b is reduced and displayed, and the two captured images are displayed simultaneously.

Thus, the first image signal Ya (t) and the second image signal Ya (t)
It is possible to switch the display mode of the reproduced image on the display screen by switching the output with the image signal Yb (t) of, and performing the compression process and the combining process according to the output. That is, the first and second image signals Ya according to the respective display areas.
By controlling the output of each image signal of (t) and Yb (t), it is possible to generate image data according to the designated display mode without using the frame memory. For example, in FIG.
As shown in (b), the first and second captured images A and B are provided in each of the areas divided in half in the vertical direction of the display screen.
To display the first and second image signals Ya (t), Yb
It suffices to drive the first and second CCD solid-state image pickup devices 31a and 31b so as to alternately output (t). Also, FIG.
When only one of the first captured image A and the second captured image B is displayed as shown in (c) and (d), the first CCD is displayed in accordance with the desired image. Solid-state image sensor 31a or second CCD solid-state image sensor 3
It suffices to drive either one of 1b.

FIG. 6 is a block diagram showing the configuration of the digital signal processing circuit 39. Digital signal processing circuit 39
Is a line memory 41, first and second integrator circuits 42,
43, an exposure control circuit 44, an RGB process circuit 45, third and fourth integrating circuits 46 and 47, and a white balance control circuit 48.

The line memory 41 includes an A / D conversion circuit 38.
The image data Y (n) output from is stored in an appropriate number of lines per line, held for one horizontal scanning period, and then output to the first and second integration circuits 42 and 43. The first and second integrator circuits 42 take in the image data Y (n) output from the line memory 41 and integrate, for example, in a period corresponding to the central region of one screen. The first and second integration circuits 42 and 43 operate by receiving the first and second integration control signals W1 and W2 supplied from the timing control circuit 34, and operate with the first and second integration control signals. The integration period is controlled by W1 and W2. The first and second integration control signals W1 and W2 are the first and second image signals Ya (t) and Yb.
FIG. 7 shows the case where the data generated according to the output timing of (t) or the output order, for example, the data output from the line memory 41 is the data generated from the first image signal Ya (t). Thus, the first integration control signal W1 is raised to the high level corresponding to the period in which the data is output. As a result, in the first integration circuit 42 that receives the first integration control signal W1, the integration processing of the image data generated from the first image signal Ya (t) is performed. On the contrary, when the data output from the line memory 41 is the data generated from the second image signal Yb (t), the second integration control signal W2 is high corresponding to the period in which the data is output. After being raised to the level, the second integration circuit 43 performs integration processing of the image data generated from the second image signal Yb (t). That is, the first and second integrating circuits 42 and 43
Corresponds to each of the first and second image signals Ya (t) and Yb (t). The integral of the image data corresponding to the first image signal Ya (t) and the second image signal Yb The integration of the image data corresponding to (t) can be performed independently.

The exposure control circuit 44 is arranged commonly to the first and second integrator circuits 42 and 43, and the first and second integrator circuits 42 and 43 are based on the outputs from these two integrator circuits 42 and 43.
The CCD solid-state image pickup devices 31a and 31b are independently controlled in a time-division manner. That is, based on the integration data output from the first integration circuit 42, the first CC
The integration time of the D solid-state image sensor 31a is expanded / contracted, and the second integration circuit 43 outputs the second data based on the integration data output from the second integration circuit 43.
The expansion / contraction of the storage time of the CCD solid-state image sensor 31b is controlled. For example, when controlling the exposure state of the first CCD solid-state imaging device 31a, if the integrated value of the image data generated from the first image signal Ya (t) becomes larger than the appropriate range, the first CCD solid-state imaging device The timing control circuit 33 is instructed to shorten the accumulation time of 31a. On the contrary, when the integrated value becomes smaller than the appropriate range, an instruction is given to extend the accumulation time, and the first CCD solid-state image sensor 31 is always operated.
Feedback control is performed so that the exposure state of a is appropriate.

The RGB process circuit 45 uses the image data Y
Image data D (n) including luminance data and color difference data is obtained by subjecting (n) to processing such as color separation and matrix calculation.
To generate. For example, in the color separation processing, the image data Y is generated according to the color arrangement of the color filters attached to the image pickup units of the first and second CCD solid-state image pickup devices 31a and 31b.
(n) is assigned to a plurality of color component data R (n), G (n), B
generates (n). In the matrix calculation process, the distributed color component data are combined to generate luminance data, and the color difference data is generated by subtracting the luminance data from each color component data. Further, the RGB process circuit 45 has a compression circuit and a synthesizing circuit built therein, and performs compression processing on specific image data as necessary, and
The image data obtained from the first CCD solid-state imaging device 31a and the image data obtained from the second CCD solid-state imaging device 31b are combined.

The third and fourth integrator circuits 46 and 47 have R
Color component data R output from the GB process circuit 45
(n), G (n), and B (n) are fetched and integrated for each color component data in units of one screen to several screens, for example. The third and fourth integrator circuits 46 and 47 generate the third and third integrators corresponding to the output timings of the first and second image signals Ya (t) and Yb (t) or the output order. It operates by receiving the integration control signals W3 and W4 of 4 and integrates the color component data R (n), G (n) and B (n) generated from the first image signal Ya (t) and the second Color component data R generated from the image signal Yb (t)
(n), G (n), and B (n) are integrated independently.

The white balance control circuit 48 is arranged commonly to the third and fourth integrating circuits 46 and 47,
Based on the integrated data output from these two integrating circuits 46 and 47, the first and second image signals Ya (t) and Yb (t
), The white balance of the image data generated is corrected independently by time division. In the white balance correction, for example, when correcting the white balance of the image data generated from the first image signal Ya (t), the color component data R (n) output from the third integrating circuit 46 is used. , G (n) and B (n) are compared with each other, and the color component signals R (n) and B (n) are multiplied by a unique coefficient so that these integrated values may coincide with each other.

In this way, the first and second image signals Ya
A plurality of integrator circuits are provided corresponding to (t) and Yb (t), respectively, and the integrator circuits perform integration processing according to the output timings of the first and second image signals Ya (t) and Yb (t). By doing
The image data generated from the first and second image signals Ya (t) and Yb (t) can be independently integrated. Furthermore, an exposure control circuit 4 is provided for these integration circuits.
4 or the configuration in which the white balance control circuit 48 is commonly provided, the increase in the circuit scale of the digital signal processing circuit 39 is minimized.

Next, a second embodiment of the present invention will be described. FIG. 8 is a block diagram showing the second embodiment of the present invention. The second embodiment is different from the first embodiment in that the first CCD solid-state image pickup device 31a and the second CCD solid-state image pickup device 33a share the booster circuit 51 and the clamp circuit 35 is shared. Selection circuit 5 in the previous stage
2 is arranged to unify the signal processing series after the clamp circuit 35.

The booster circuit 51 comprises a booster 51a and an output selector 51b. The booster 51a boosts an input power supply voltage to generate a boosted voltage, and the output selector 51b.
Switches the supply destination of the output of the booster 51b in accordance with the operation timing of the first CCD solid-state imaging device 31a and the second CCD solid-state imaging device 33a. And the first CCD
When driving the solid-state imaging device 31a, the booster circuit 51
Is the boosted voltage generated by the booster unit 51a,
Solid-state image sensor 31a and first CCD driver circuit 32
a, and when driving the second CCD solid-state imaging device 31b, the boosted voltage is output to the second CCD solid-state imaging device 33a.
And to the second CCD driver circuit 32b. still,
The switching operation by the output selection unit 51b is controlled by the timing signal from the timing control circuit 34, and is synchronized with the switching operation of the digital signal processing circuit 39.

The selection circuit 52 comprises first and second transistors 52a and 52b and a resistance element 52c. The first and second transistors 52a and 52b are respectively the first
Corresponding to the CCD solid-state image pickup device 31a and the second CCD solid-state image pickup device 31b, and is connected in series with the resistance element 52c between the power supply voltage V _D and the ground point. The first and second transistors 52a and 52b are composed of, for example, bipolar transistors, and receive the outputs of the first and second CCD solid-state imaging devices 31a and 31b at their base terminals, respectively. Therefore, in the selection circuit 52, the image signal from the CCD solid-state image pickup device in operation among the first and second CCD solid-state image pickup devices 31a and 31b is subjected to impedance conversion and the image signal Y ( t)
Output as.

In such a configuration, for example, when the first CCD solid-state image pickup device 31a is driven, the output selection section 51b selects the first CCD driver circuit 32a side, and the boosted voltage is set to the first CCD driver circuit. 32a. Then, when the first CCD solid-state image pickup device 31a is driven and the first image signal Ya (t) is taken in by the selection circuit 52, the first transistor 52a is activated and the first image signal Ya (t). Is the clamp circuit 35 as the image signal Y (t).
Is output to. On the contrary, the second CCD solid-state imaging device 31b
Drive the second CCD driver circuit 32
The boosted voltage is supplied to the b side, the second transistor 52b is activated, and the second image signal Yb (t) is output as the image signal Y (t).

According to this second embodiment, two CCs
Although there is a constraint that the D solid-state image pickup device cannot be simultaneously driven, the circuit configuration can be simplified as compared with the first embodiment, and the circuit scale can be greatly reduced as compared with the conventional configuration. Can be planned. Also, two C
Since only one booster circuit is operated for driving the CD solid-state imaging device, it is possible to reduce power consumption, which is particularly effective for a battery-driven imaging device.

The embodiments of the present invention have been described above with reference to FIGS. In the first embodiment, two CCs
For the D solid-state image pickup device, a configuration in which a timing control circuit and a signal processing sequence after the analog signal processing circuit are shared is illustrated, and in the second embodiment, a configuration in which a booster circuit and a clamp circuit are further shared is illustrated. However, the present invention is
It is not limited to this. For example, in addition to the configuration of the first embodiment, only the booster circuit may be shared, or conversely, only the clamp circuit may be shared. That is, it is possible to selectively combine and use the shared circuit and the separately provided circuit according to the imaging conditions.

Further, in the present invention, since the timing control circuit is common to the first and second CCD solid-state image pickup devices, the driving conditions of the two CCD solid-state image pickup devices are set equal. It is not necessary that the two CCD solid-state image pickup devices have exactly the same configuration. For example, if the driving conditions are the same, CCD solid-state imaging devices for color imaging or monochrome imaging may be used in combination, or CCD solid-state imaging devices having different device structures may be used. However, when a CCD solid-state image pickup device for color image pickup and monochrome image pickup is used in combination, a signal processing circuit that can handle both color image pickup and monochrome image pickup is applied.

Further, in the exposure control and the white balance control of the digital signal processing, a configuration in which a plurality of integrating circuits are provided in association with two CCD solid-state image pickup devices is illustrated, but the present invention is not limited to this. is not. For example, the 1st and 2nd CCDs in 1 line unit or 1 screen unit
Two CCDs that alternately drive the solid-state image sensor
When the operation of the solid-state image pickup device is frequently switched, it is desirable to separately provide an integrating circuit in association with each CCD solid-state image pickup device, but it is necessary to switch the operation of two CCD solid-state image pickup devices in units of a plurality of screens. In this case, the integration circuit may be shared by the two CCD solid-state image pickup devices.

The case where the first and second CCD solid-state image pickup devices are of the frame transfer type has been described as an example, but the present invention is not limited to this.
It is also suitable for an image pickup apparatus using a frame interline type solid-state image pickup element including a storage unit capable of temporarily holding information charges for the screen.

[0053]

According to the present invention, the output timings of the image signals from the two CCD solid-state image pickup devices are set in time division, and the selection circuit is operated in accordance with the output timings. As a result, the switching operation of the two image signals can be efficiently performed, and the circuit scale as the image pickup apparatus can be reduced to the maximum while preventing the adverse effect of the function deterioration.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of an image pickup apparatus of the present invention.

FIG. 2 is a plan view showing a configuration of a solid-state image sensor.

FIG. 3 is a schematic diagram showing an example of a display mode.

FIG. 4 is a timing diagram illustrating the operation of FIG.

FIG. 5 is a timing chart showing states of first and second image signals Ya (t), Yb (t), image signal Y (t), and image data D (n).

FIG. 6 is a block diagram showing a configuration of a digital signal processing circuit.

FIG. 7 is a timing diagram illustrating first and second integration control signals.

FIG. 8 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of a conventional image pickup apparatus.

FIG. 10 is a schematic diagram showing an example of a display mode.

[Explanation of symbols]

1a, 31a: first CCD solid-state image sensor 1b, 31b: Second CCD solid-state image sensor 2a, 32a: first booster circuit 2b, 33b: second booster circuit 3a, 33a: first CCD driver circuit 3b, 33b: second CCD driver circuit 4a: First timing control circuit 4b: Second timing control circuit 5a: First analog signal processing circuit 5b: second analog signal processing circuit 6a: First A / D converter 6b: second A / D converter 7a: First digital signal processing circuit 7b: second digital signal processing circuit 8a: first memory 8b: second memory 9: Memory controller 34: Timing control circuit 35: Clamp circuit 35a: First clamp circuit 35b: Second clamp circuit 36: Selection circuit 37: Analog signal processing circuit 38: A / D conversion circuit 39: Digital signal processing circuit 41: Line memory 42: First integrating circuit 43: Second integrating circuit 44: Exposure control circuit 45: RGB process circuit 46: Third integrating circuit 47: Fourth integrating circuit 48: White balance control circuit 51: Boost circuit 51a: Booster 51b: Output selection section 52: Selection circuit 52a: first transistor 52b: second transistor 52c: resistance element

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H04N 9/73 H04N 9/73 AF term (reference) 5C022 AA13 AB03 AB61 AB68 5C024 BX01 CY41 GY03 HX09 HX31 HX58 5C065 AA03 BB02 DD06 GG08 GG24 GG26 5C066 AA01 CA03 EA14 EA19 ED01 ED09 KA09 KE05 KM02

Claims (7)

[Claims] 1. A plurality of light-receiving pixels are arranged in a matrix, a first solid-state image sensor for accumulating information charges generated in response to a first subject image in each light-receiving pixel, and a plurality of light-receiving pixels are arranged in a matrix. , A second solid-state image sensor for accumulating information charges generated in response to a second subject image in each light-receiving pixel, and transferring and outputting information charges accumulated in each light-receiving pixel of the first solid-state image sensor. And a second drive circuit for obtaining and outputting a second image signal by transferring and outputting the information charges accumulated in each light receiving pixel of the second solid-state image sensor. , The first and second based on a reference clock of a constant period
A timing control circuit for deciding vertical scanning and horizontal scanning timings of the solid-state image sensor, and one of the first and second image signals in synchronization with the operation timing of the first and second solid-state image sensors. And a signal processing circuit that receives an output from the selection circuit to generate a predetermined image signal, and the selection circuit alternately includes the first and An image pickup apparatus characterized by selecting a second image signal. 2. The image pickup apparatus according to claim 1, wherein a first clamp circuit that clamps the first image signal and supplies the first image signal to the selection circuit, and a second clamp circuit that clamps the second image signal to perform the selection. A second clamp circuit supplied to the circuit, wherein the first and second clamp circuits have the same clamp level. 3. The image pickup device according to claim 1, further comprising a clamp circuit that clamps an output of the selection circuit and supplies the output to the signal processing circuit. 4. The image pickup device according to claim 1, wherein a first boosted voltage generated by boosting an input voltage is supplied to the first drive circuit. An image pickup apparatus further comprising: a booster circuit; and a second booster circuit that supplies a second boosted voltage generated by boosting an input voltage to the second drive circuit. 5. The image pickup device according to claim 1, further comprising a booster circuit that boosts an input voltage to generate a boosted voltage, the booster circuit increasing the boosted voltage. A boosting unit for generating, and an output selecting unit for selectively outputting one of the first and second drive circuits in synchronization with the operation timing of the first and second solid-state imaging devices with the boosted voltage. An imaging device comprising: 6. The image pickup device according to claim 1, wherein the signal processing circuit captures the first and second image signals, respectively, and integrates the first and second image signals in a predetermined period unit. An exposure control circuit that independently controls the exposure states of the first and second solid-state imaging devices based on the outputs of the first and second integration circuits, respectively. apparatus. 7. The image pickup device according to claim 6, wherein the signal processing circuit includes third and fourth integrating circuits that respectively take in the first and second image signals and integrate them in a predetermined period unit. And a white balance control circuit that independently corrects the white balance of the first and second image signals based on the outputs of the third and fourth integrator circuits, respectively. Imaging device.