JP2003158190A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily manufacture a semiconductor device with high reliability by forming a lower electrode of an MIM capacitor element at the same time with a wiring layer and then eliminating a leak current between an upper electrode and the lower electrode. SOLUTION: The MIM capacitor element is obtained by forming a 1st metal film 11, a reflection preventive film 12, an insulating film 13, and a 2nd metal film 14 one after another on a semiconductor substrate, patterning the 2nd metal film 14 and insulating film 13 and then patterning the 1st metal film 11 by using the reflection preventive film 12 to form a wiring layer 11a, and forming a pattern of a reflection preventive film (dielectric film lower-layer part) 12b and a 1st metal film (lower electrode) 11b below a pattern of the 2nd metal film (upper electrode) 14 and an insulating film (dielectric upper-layer part) 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor integrated circuit device having a capacitive element having a metal-insulating film-metal (MIM) structure.

[0002]

2. Description of the Related Art FIG. 6 shows a capacitive element having an MIM structure (hereinafter referred to as
FIG. 11 is a cross-sectional view showing the structure of a conventional semiconductor device including a MIM capacitor). For the sake of convenience, the illustration of the lower layer portion below the MIM capacitor is omitted. In the figure, 1a and 1b are made of a first metal film formed on a semiconductor substrate (not shown) in which transistors and the like are formed. Particularly, 1a is a wiring layer, 1b is a lower electrode of a MIM capacitor, and 2b. Is a dielectric film of the MIM capacitor formed on the lower electrode 1b, and 3 is an M film formed on the dielectric film 2.
The upper electrodes of the IM capacitor, 4 are sidewalls formed on the side walls of the dielectric film 2 and the upper electrode 3, and 5a are formed on the wiring layer 1a, and serve as an antireflection film in the photolithography process for forming the wiring layer 1a. The P-SiON film (plasma silicon oxynitride film) 5b to be used covers the MIM capacitor (upper electrode 3 / dielectric film 2 / lower electrode 1b).
A P-SiON film formed simultaneously with the antireflection film 5a, 6 is an interlayer insulating film, and 7a, 7b and 7c are wiring layers 1 respectively.
a, a connection hole provided in the interlayer insulating film 6 so as to reach the lower electrode 1b and the upper electrode 3.

A conventional method of manufacturing a semiconductor device having such a structure will be described below with reference to FIGS. First, as shown in FIG. 7, a first metal film 1, a dielectric film 2, a second metal film 3 serving as an upper electrode, an etching protection film are formed on a semiconductor substrate (not shown) in which elements such as transistors are formed. 8 is sequentially formed (FIG. 7A), and the etching protection film 8 and the second metal film 3 are sequentially etched using a resist mask to pattern the upper electrode (second metal film) 3 (FIG. 7A). 7 (b)). Next, as shown in FIG. 8, a film 9 for forming the sidewalls 4 is formed on the entire surface (see FIG.
(A)) The dielectric film 2 under the upper electrode 3 is patterned by the entire surface etch back by anisotropic etching, and the sidewalls 4 are formed on the side walls of the dielectric film 2 and the upper electrode 3. The etching protection film 8 on the upper electrode 3 prevents the upper electrode 3 from being thinned by etching in the etching for forming the sidewall 4 (FIG. 8B).

Next, as shown in FIG. 9, the wiring layer 1 is formed on the entire surface.
The P-SiON film 5 serving as an antireflection film for forming a is formed by the plasma CVD method, and the P-SiON film 5 and the first metal film 1 are formed by using the resist mask formed by the photoengraving process. The wiring layer 1a and the lower electrode 1b are patterned by etching, and the wiring layer 1a having a P-SiON film (antireflection film) 5a formed on its surface and PS
MIM capacitor (upper electrode 3 covered with iON film 5b
/ Dielectric film 2 / lower electrode 1b) is obtained. Next, the interlayer insulating film 6 is deposited on the entire surface, and the wiring layer 1 is formed on the interlayer insulating film 6.
Connection holes 7a, 7b and 7c are formed so as to reach a, the lower electrode 1b and the upper electrode 3, respectively (see FIG. 6).
After this, the wiring layer 1a, via the connection holes 7a, 7b, 7c,
An electrode and an upper wiring layer (not shown) respectively connected to the lower electrode 1b and the upper electrode 3 are formed, and a predetermined process is performed to complete the semiconductor device.

As described above, the conventional semiconductor device has the MI
The lower electrode 1b of the M capacitor is made of the metal film 1 forming the wiring layer 1a, and when the P-SiON film (antireflection film) 5a for forming the wiring layer 1a is formed on the wiring layer 1a,
A P-SiON film 5b covering the MIM capacitor is formed over the upper electrode 3 and the lower electrode 1b. This P-
The SiON film 5 (5a, 5b) is a film that has a low reflectance and is used as an antireflection film during photolithography during pattern formation of a fine wiring layer or the like that requires dimensional accuracy.
Although it has high resistance, it has some conductivity. Therefore, in the MIM capacitor, by forming the sidewall 4, the length of the P-SiON film 5b formed over the upper electrode 3 and the lower electrode 1b is increased,
The resistance of the P-SiON film 5b is increased to reduce the leak current flowing between the upper electrode 3 and the lower electrode 1b of the MIM capacitor as much as possible.

[0006]

The conventional semiconductor device is
Due to the above-mentioned structure, the P-SiON film 5b having a slight conductivity is formed over the upper electrode 3 and the lower electrode 1b of the MIM capacitor. This P-
Although the length dimension of the SiON film 5b was increased by forming the sidewall 4, the leak current flowing between the upper electrode 3 and the lower electrode 1b was suppressed, but it could not be completely eliminated. In addition, the manufacturing method is complicated because the sidewalls 4 are formed, and it is necessary to form the etching protection film 8 in order to prevent the film thickness of the upper electrode 3 from being reduced by etching when the sidewalls 4 are formed. It becomes complicated. Upper electrode 3 of this MIM capacitor
Is thinner than a normal wiring from the viewpoint of flatness, and there is a concern that it may penetrate due to over-etching even when the connection hole 7c is formed on the upper electrode 3. Was difficult to form. Further, as a measure for preventing such over-etching, there is a method of forming an etching stopper film in a desired region, but the manufacturing method becomes more complicated by increasing the number of steps and the number of masks. Furthermore, P-Si is formed on the upper electrode 3.
Although the ON film 5b is formed, since it is a thin film formed to prevent reflection, it does not function as an etching stopper.

The present invention has been made in order to solve the above-mentioned problems, and in an MIM capacitor composed of a metal film in which a lower electrode and a wiring layer are simultaneously formed, an upper electrode and An object of the present invention is to easily realize a highly reliable semiconductor device with zero leakage current between the lower electrode and the lower electrode. It is another object of the present invention to stably and reliably form a connection hole on the upper electrode of the MIM capacitor and to form a reliable and favorable contact between the upper electrode and the upper layer wiring.

[0008]

[Means for Solving the Problems] Claim 1 according to the present invention
The semiconductor device described above is a capacitive element including, on a semiconductor substrate, a lower electrode made of a first metal film and an upper electrode made of a second metal film formed on the lower electrode via a dielectric film; A device structure comprising a wiring layer made of the first metal film, wherein an antireflection film for forming the wiring layer is provided on the first metal film, and the antireflection film is provided in the capacitive element. It is used for the dielectric film.

A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein the antireflection film is a P-SiON.
The dielectric film has a laminated structure of the antireflection film and the insulating film formed thereon, which is made of a film (plasma silicon oxynitride film).

A semiconductor device according to a third aspect of the present invention is the semiconductor device according to the first or second aspect, wherein an interlayer insulating film formed over the entire surface of the capacitor element and the wiring layer, and an upper electrode and a lower electrode of the capacitor element. And a connection hole provided in the interlayer insulating film so as to reach each of the wiring layers, and the insulating film having etching selectivity with the interlayer insulating film is provided only on the surface of the upper electrode.

According to a fourth aspect of the present invention, in the third aspect, the insulating film provided on the surface of the upper electrode of the capacitor is a film made of the same material as the antireflection film.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein when forming a connection hole in an interlayer insulating film,
Using the resist mask, the insulating film on the surface of the upper electrode is used as an etching stopper to etch the interlayer insulating film so as to expose the insulating film and the antireflection film on the lower electrode and the wiring layer, respectively. The connection hole is formed, and then the insulating film and the antireflection film at the bottom of the connection hole are removed by etching.

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device, the first metal film, the antireflection film, the insulating film and the second metal film are sequentially formed on the semiconductor substrate.
And the second step of sequentially etching and patterning the second metal film and the insulating film using a resist mask, and a resist mask formed by pattern transfer using the antireflection film. The antireflection film and the first metal film are sequentially etched to form a wiring layer, and a capacitor element including the first metal film under the pattern of the second metal film and the insulating film is formed. And a third step of forming a lower electrode and forming a dielectric film including the antireflection film and the insulating film on the lower electrode.

According to a seventh aspect of the present invention, in the method of manufacturing a semiconductor device according to the sixth aspect, the thickness of the antireflection film formed in the first step is the insulating film in the second step. The etching thickness of the antireflection film due to overetching at the time of etching is set by adding in advance to the thickness used for the antireflection function in the third step.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1. Embodiment 1 of the present invention will be described below with reference to the drawings. 1 is a cross-sectional view showing a structure of a semiconductor device including a capacitive element (MIM capacitor) having an MIM structure according to a first embodiment of the present invention. For the sake of convenience, the illustration of the lower layer portion below the MIM capacitor is omitted. In the figure, 11
Reference numerals a and 11b are made of a first metal film formed on a semiconductor substrate (not shown) in which elements such as transistors are formed. In particular, 11a is a wiring layer, 11b is a lower electrode of the MIM capacitor, and 12a is a wiring layer. A P-SiON film (plasma silicon oxynitride film) formed on 11a and used as an antireflection film in the photolithography process for forming the wiring layer 11a,
12b is formed on the lower electrode 11a at the same time as the P-SiON film 12a and forms a lower layer of the dielectric film of the MIM capacitor, and P is formed on the P-SiON film 12b. An insulating film made of, for example, a SiO ₂ film forming an upper layer portion of the body film, 14 is an upper electrode of the MIM capacitor formed on the insulating film 13, 1
5 is formed on the upper electrode 14, a P-SiON film as an insulating film serving as an etching stopper when forming a connection hole described later on the upper electrode 14, 16 is an interlayer insulating film, 17
Reference numerals a, 17b, and 17c are connection holes provided in the interlayer insulating film 16 so as to reach the wiring layer 11a, the lower electrode 11b, and the upper electrode 14, respectively.

A method of manufacturing the semiconductor device having the above structure will be described below with reference to FIGS. 2, 3 and 4 are cross-sectional views showing the first, second and third steps of the method for manufacturing a semiconductor device according to the first embodiment of the present invention, respectively. First, a first metal film 11 is formed on a semiconductor substrate (not shown) on which elements such as transistors are formed (FIG. 2A), and subsequently, antireflection for forming a wiring layer 11a is formed on the entire surface. P-SiON film 1 as a film
2 is formed into a film with a film thickness of, for example, about 55 nm by the plasma CVD method (FIG. 2 (b)), and further, for example, SiO 2
_The insulating film 13 composed of _two films is formed with a film thickness of, for example, about 15 nm, and the second metal film 14 serving as the upper electrode is formed with, for example, about 0.
After the film is formed with a film thickness of 1 μm, a P-SiON film 15 as an insulating film serving as an etching stopper is then formed with a film thickness of, for example, about 0.11 μm (FIG. 2C).

Next, using a resist mask, P-SiO
The N film 15, the second metal film 14 and the insulating film 13 are sequentially etched and patterned. When the insulating film 13 is etched, it is etched by, for example, 100% over etching. Since the insulating film 13 made of this SiO ₂ film has an etching selection ratio of about 3 to the underlying P-SiON film 12, the P-SiON film 12 is thinned by over-etching at a film thickness of about 5 nm (see FIG. 3). ). The film loss due to this over-etching is a desired film thickness (about 50 nm) as an antireflection film when the P-SiON film 12 is formed.
Is added in advance to form a film (see FIG. 2B). Next, the P-SiON film 12 is used as an antireflection film and the resist mask formed by the photolithography process is used to remove the P-SiON film.
By etching the ON film 12 and the first metal film 11,
Wiring layer 11a having P-SiON film 12a formed on the surface
Patterning the P-SiON film 15 / second
A lower electrode 11b having a P-SiON film 12b formed on the surface thereof is patterned as a lower layer of the metal film 14 / insulating film 13 pattern. As a result, a film composed of the P-SiON film 12b and the insulating film 13 thereon is formed on the upper and lower electrodes 14,
An MIM capacitor having a dielectric film sandwiched between 11b is formed (FIG. 4).

Next, an interlayer insulating film 16 is formed on the entire surface by, for example, 0.
The interlayer insulating film 16 is deposited with a film thickness of 7 μm, and a predetermined region of the interlayer insulating film 16 is opened by etching to form connection holes 17 on the wiring layer 11a, the lower electrode 11b and the upper electrode 14, respectively.
a, 17b, 17c are formed. At this time, the upper electrode 1
4 has a thickness (about 0.
1 μm), and the film thickness variation is ± 0.1 μ
When the thickness is m, the thickness becomes 0.5 μm. On the other hand, the connection hole 17
Since the interlayer insulating film 16 for forming a, 17b, and 17c is over-etched in consideration of the variation in the film thickness of the interlayer insulating film 16, the etching is performed with a film thickness of about 0.8 μm. Therefore, on the upper electrode 14, about 0.3 μ
However, the P-SiON film 15 having an etching selection ratio to the interlayer insulating film 16 of about 3 has a thickness of 0.
Since the film is formed with a film thickness of 1 μm or more (about 0.11 μm), the P-SiON film 15 remains at the bottom of the connection hole 17c. Further, P-SiON films 12a and 12b are also formed on the wiring layer 11a and the lower electrode 11b, and exposed at the bottoms of the connection holes 17a and 17b, respectively (FIG. 5).

Next, the etching conditions are changed, and additional etching for forming the connection holes 17a, 17b, 17c is further performed, and P- at the bottom of the connection holes 17a, 17b, 17c is formed.
The SiON films 12a, 12b, 15 are removed to form the connection hole 1
7a, 17b and 17c are wiring layers 11a and lower electrodes 11b
And on the upper electrode 14 (see FIG. 1). Thereafter, electrodes and upper wiring layers (not shown) respectively connected to the wiring layer 11a, the lower electrode 11b, and the upper electrode 15 through the connection holes 17a, 17b, 17c, and an upper wiring layer (not shown) are formed, and a predetermined process is applied to the semiconductor device. To complete.

In this embodiment, since the P-SiON film 12 serving as an antireflection film for forming the wiring layer 11a is used as the dielectric film of the MIM capacitor, the P-SiON film 5 is covered over the entire MIM capacitor. The etching stopper (P-SiON film) 15 for opening the connection hole 17c, which could not be easily formed by the conventional one formed, can be easily formed only on the upper electrode 14. Therefore, the connection hole 17c can be stably and reliably formed on the upper electrode 14 of the MIM capacitor, and a highly reliable and good contact between the upper electrode 14 and the upper wiring can be obtained. In addition, P-SiO
An insulating film 13 having a good insulating property is formed on the N film 12b,
Since the dielectric film is composed of the insulating film 13 / P-SiON film 12b, even if the P-SiON film 12b has some conductivity, the leak current flowing between the upper electrode 14 and the lower electrode 11b is completely eliminated. A semiconductor device that can be eliminated and has improved electrical characteristics and reliability can be obtained. Further, unlike the conventional case, it is not necessary to form the sidewall 4 which complicates the manufacturing process, and the above effect can be realized by a simple manufacturing method.

In the above embodiment, the upper electrode 14
First, the upper etching stopper (P-SiON film) 15 is formed.
Since the film is made of the same material as the P-SiON film 12 formed on the metal film 11 of FIG.
During the additional etching for forming c, the connection holes 17a, 1
7b, 17c P-SiON films 12a, 12b, 1 at the bottom
5 can be easily removed at the same time to form the connection holes 17a, 17b, 17
c is the wiring layer 11a, the lower electrode 11b, and the upper electrode 14
You can reach the top reliably.

Although the dielectric film of the MIM capacitor has a two-layer structure of the insulating film 13 / P-SiON film 12b,
An insulating film made of two or more different materials may be formed on the P-SiON film 12b to form a laminated film having three or more layers. Furthermore, if it is a film that functions as an antireflection film and has a good insulating property, the antireflection film of the wiring layer 11a can be formed only by the MIM.
It may be used for the dielectric film of the capacitor, and the manufacturing method becomes much easier.

[0023]

As described above, in the semiconductor device according to the first aspect of the present invention, the lower electrode made of the first metal film and the first electrode formed on the lower electrode via the dielectric film are provided. 2 is a device configuration including a capacitive element formed of an upper electrode formed of a metal film, and a wiring layer formed of the first metal film, for forming the wiring layer on the first metal film. Since the antireflection film of 1) is provided and the antireflection film is used as the dielectric film of the capacitive element, a highly reliable semiconductor device can be obtained by an easy manufacturing method.

A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein the antireflection film is P-SiON.
Since the dielectric film is made of a film (plasma silicon oxynitride film) and the dielectric film has a laminated structure of the antireflection film and the insulating film formed thereon, the leak between the upper and lower electrodes of the capacitive element can be easily performed. It is possible to obtain a highly reliable semiconductor device that can reduce the current to zero.

A semiconductor device according to a third aspect of the present invention is the semiconductor device according to the first or second aspect, wherein an interlayer insulating film formed on the entire surface of the capacitance element and the wiring layer, and an upper electrode and a lower electrode of the capacitance element. And a connecting hole provided in the interlayer insulating film so as to reach each of the wiring layers, and the insulating film having etching selectivity with the interlayer insulating film is provided only on the surface of the upper electrode. Stable and reliable formation is possible, and a highly reliable and good contact with the upper wiring can be obtained.

According to a fourth aspect of the present invention, in the third aspect, the insulating film provided on the surface of the upper electrode of the capacitor is a film made of the same material as the antireflection film. The formation of the connection hole is easy, and it is possible to reach the base with high reliability.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein when forming a connection hole in an interlayer insulating film,
Using the resist mask, the insulating film on the surface of the upper electrode is used as an etching stopper to etch the interlayer insulating film so as to expose the insulating film and the antireflection film on the lower electrode and the wiring layer, respectively. Since the connection hole is formed and then the insulating film and the antireflection film at the bottom of the connection hole are removed by etching, the connection hole can be stably and reliably formed, and the reliability with the upper layer wiring is high. Contact can be easily obtained.

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device, the first metal film, the antireflection film, the insulating film and the second metal film are sequentially formed on the semiconductor substrate.
And the second step of sequentially etching and patterning the second metal film and the insulating film using a resist mask, and a resist mask formed by pattern transfer using the antireflection film. The antireflection film and the first metal film are sequentially etched to form a wiring layer, and a capacitor element including the first metal film under the pattern of the second metal film and the insulating film is formed. The third step of forming a lower electrode and forming a dielectric film composed of the antireflection film and the insulating film on the lower electrode has the effect of reducing the leak current between the upper and lower electrodes of the capacitive element to zero. A highly reliable semiconductor device can be obtained easily and surely.

According to a seventh aspect of the present invention, in the method of manufacturing a semiconductor device according to the sixth aspect, the thickness of the antireflection film formed in the first step is the insulating film in the second step. Since the etching thickness of the antireflection film due to overetching at the time of etching is set in advance by adding to the thickness used for the antireflection function in the third step, the antireflection film of the capacitive element can be formed without impairing its function. A highly reliable semiconductor device that can be used as a dielectric film can be obtained.

[Brief description of drawings]

FIG. 1 is a sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a first step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a sectional view showing a second step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a sectional view showing a third step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a cross sectional view showing a step in the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view showing the structure of a conventional semiconductor device.

FIG. 7 is a cross-sectional view showing a step in a conventional method for manufacturing a semiconductor device.

FIG. 8 is a cross-sectional view showing a step in a conventional method for manufacturing a semiconductor device.

FIG. 9 is a cross-sectional view showing a step in the conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

11 first metal film, 11a wiring layer, 11b lower electrode, 12, 12a, 12b P-SiON film (antireflection film), 13 insulating film, 14 upper electrode (second metal film), 15 as insulating film P-SiON film (etching stopper film), 16 interlayer insulating film, 17a, 17b,
17c Connection hole.

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5F004 DB00 DB03 EA22 EA23 EB01                       EB02 EB08                 5F033 MM15 QQ04 QQ08 QQ09 QQ10                       QQ21 QQ25 QQ35 QQ37 QQ39                       RR04 RR08 SS15 TT02 VV10                       XX00                 5F038 AC05 AC09 AC15 AC16 AC18                       EZ15 EZ20

Claims (7)

[Claims] 1. A capacitive element including a lower electrode made of a first metal film and an upper electrode made of a second metal film formed on the semiconductor substrate via a dielectric film,
In a semiconductor device having a wiring layer made of the first metal film, an antireflection film for forming the wiring layer is provided on the first metal film, and the antireflection film is used as the dielectric layer of the capacitive element. A semiconductor device characterized by being used as a body film. 2. The antireflection film is made of a P-SiON film (plasma silicon oxynitride film), and the dielectric film has a laminated structure of the antireflection film and an insulating film formed thereon. The semiconductor device according to claim 1. 3. An interlayer insulating film formed over the entire surface of the capacitor and the wiring layer, and a connection provided in the interlayer insulating film so as to reach the upper electrode, the lower electrode of the capacitor and the wiring layer, respectively. 3. The semiconductor device according to claim 1, further comprising a hole, wherein the insulating film having etching selectivity with the interlayer insulating film is provided only on the surface of the upper electrode. 4. The semiconductor device according to claim 3, wherein the insulating film provided on the surface of the upper electrode of the capacitive element is a film made of the same material as the antireflection film. 5. An antireflection coating on the insulating film, the lower electrode and the wiring layer using a resist mask when forming a connection hole in an interlayer insulating film and using the insulating film on the surface of the upper electrode as an etching stopper. 4. The interlayer insulating film is etched to expose the film and the connection hole, so that the connection hole is formed, and then the insulating film and the antireflection film at the bottom of the connection hole are removed by etching. Alternatively, the method for manufacturing a semiconductor device according to the item 4 above. 6. A first step of sequentially forming a first metal film, an antireflection film, an insulating film and a second metal film on a semiconductor substrate, and a resist of the second metal film and the insulating film. Second patterning using a mask for sequential etching and patterning
And the resist mask formed by pattern transfer using the antireflection film, the antireflection film and the first metal film are sequentially etched to form a wiring layer, and the second film is formed. A lower electrode of the capacitive element made of the first metal film is formed under the pattern of the metal film and the insulating film, and a dielectric film made of the antireflection film and the insulating film is formed on the lower electrode. 3. The method of manufacturing a semiconductor device according to claim 2, further comprising the step 3). 7. The film thickness of the antireflection film formed in the first step is the etching thickness of the antireflection film due to overetching during the etching of the insulating film in the second step,
7. The method for manufacturing a semiconductor device according to claim 6, wherein the thickness used for the antireflection function is added in advance and set in the third step.